[AHDL]
Type=Synthesis
Handle=394748
Project=c:\my_designs\biosa\MotherBoard\external_sram_fifo\external_sram_fifo.adf
AHDLPath=C:\Program Files\Aldec\Active-HDL 7.2
[Synplify]
Path=C:/Libero/Synplify/Synplify_85F/BIN
[Design.Input]
OutputPath=c:\my_designs\biosa\MotherBoard\external_sram_fifo\synthesis
TargetPath=c:/my_designs/biosa/MotherBoard/external_sram_fifo/synthesis
LogFile=c:/my_designs/biosa/MotherBoard/external_sram_fifo/log/synthesize.htm
AddSystemLibraryDeclaration=0
SynplifyTool=MV_SYNPLIFY8_ACTEL
supportedOpt-maxfan=1
supportedOpt-maxfin=-
supportedOpt-optimizepercent=-
supportedOpt-maxterms=-
supportedOpt-reportpath=1
supportedOpt-forcegsr=0
supportedOpt-opcond=1
supportedOpt-fixgatedclocks=-
supportedOpt-disableio=1
supportedOpt-usedisabledreset=0
supportedOpt-hardlimitfanout=1
supportedOpt-maplogic=-
supportedOpt-performcliquing=-
supportedOpt-softlcells=-
supportedOpt-updatemodels=0
supportedOpt-vermode=-
supportedOpt-modular=-
supportedOpt-Pipeline=-
supportedOpt-Retiming=0
Mode=GUI
OverrideExistingProject=1
[GUI]
AutoClose=0
[Engine.Reports.Output]
Path=c:/my_designs/biosa/MotherBoard/external_sram_fifo/synthesis/asynchronous_fifo
Files=asynchronous_fifo.srr
Names={Synthesis Log}
[toplevel.Input.Data]
ALLOW_DUPLICATE_MODULES=0
VERILOG_LANGUAGE=Verilog 2001
ANNOTATED_PROPERTIES_FOR_ANALYST=0
USE_CLOCK_PERIOD_FOR_UNCONSTRAINED_IO=0
WRITE_VENDOR_CONSTRAINT_FILE=1
PUSH_TRISTATES=1
SYNTHESIS_ONOFF_IMPLEMENTED_AS_TRANSLATE_ONOFF=0
TopLevel=asynchronous_fifo
isVhdlEntity=1
VerilogMap=0
VHDLMap=1
Clock=1
OBTAIN_MAX_FREQENCY=0
FanoutLimit=12
FaninLimit=20
OptimizePercent=0
MaxTerms=16
ReportPath=4000
SymbolicFSMCompiler=1
DefaultEnumEncoding=default
ResourceSharing=1
ForceGSRUsage=auto
OpCond=Default
FixGatedClocks=0
InsertIOPads=1
UseResetPin=1
HardLimitFanout=0
MapLogic=1
PerformCliquing=1
SoftLcells=1
UpdateModels=0
VerMode=0
Modular=0
ResultFormat=EDIF
Retiming=0
Pipeline=1
[Design.PartSelector]
XFamily=Actel PA
XDevice=APA600FG484
XSpeed=STD
Target=PA
Part=APA600
[toplevel.Input.Files]
0=vhdl|external_sram_fifo|c:/my_designs/biosa/MotherBoard/external_sram_fifo/src/dual_port_memory.vhd
1=vhdl|external_sram_fifo|c:/my_designs/biosa/MotherBoard/external_sram_fifo/src/asynchronous_fifo.vhd
[Engine.Command]
Command=SYNTHESIZE
[TopLevel.Output.Data]
result=0
hdl_file=c:/my_designs/biosa/MotherBoard/external_sram_fifo/synthesis/asynchronous_fifo.vhm
netlist_file=c:/my_designs/biosa/MotherBoard/external_sram_fifo/synthesis/asynchronous_fifo.edf
top_level=asynchronous_fifo
proj_dir=c:/my_designs/biosa/MotherBoard/external_sram_fifo/synthesis/asynchronous_fifo
[Engine.Synthesis.Output]
ErrFile=c:/my_designs/biosa/MotherBoard/external_sram_fifo/synthesis/analyze.err
ErrorCode=0
Result=OK
Errors=0
Warning=0
LastError=Synthesis succeeded.