-------------------------------------------------------------------------------
--
-- Title       : No Title
-- Design      : fifo
-- Author      : Wayne Radochonski
-- Company     : MBARI
--
-------------------------------------------------------------------------------
--
-- File        : c:\My_Designs\MotherBoard\fifo\compile\fifo.vhd
-- Generated   : Wed Feb 14 05:27:06 2007
-- From        : c:\My_Designs\MotherBoard\fifo\src\fifo.bde
-- By          : Bde2Vhdl ver. 2.6
--
-------------------------------------------------------------------------------
--
-- Description : 
--
-------------------------------------------------------------------------------
-- Design unit header --
library IEEE;
use IEEE.std_logic_1164.all;


-- other libraries declarations
-- synopsys translate_off 
library APA;
use IEEE.VITAL_Timing.all;
-- synopsys translate_on 

entity fifo is 
end fifo;

architecture fifo of fifo is

---- Component declarations -----

component pll
-- synopsys translate_off
  generic(
       DELAY_TIME : TIME := 2.9500000000000002 ns;
       InstancePath : STRING := "*";
       MsgOn : BOOLEAN := True;
       TimingChecksOn : BOOLEAN := True;
       Xon : BOOLEAN := False;
       tipd_C : VitalDelayArrayType01(26 downto 0) := (others => (0.0 ns,0.0 ns));
       tipd_CLK : VitalDelayType01 := (0.0 ns,0.0 ns);
       tipd_CLKA : VitalDelayType01 := (0.0 ns,0.0 ns);
       tipd_DLYA : VitalDelayArrayType01(1 downto 0) := (others => (0.0 ns,0.0 ns));
       tipd_DLYB : VitalDelayArrayType01(1 downto 0) := (others => (0.0 ns,0.0 ns));
       tipd_EXTFB : VitalDelayType01 := (0.0 ns,0.0 ns)
  );
-- synopsys translate_on
  port (
       C : in STD_LOGIC_VECTOR(26 downto 0);
       CLK : in std_ulogic;
       CLKA : in std_ulogic;
       DLYA : in STD_LOGIC_VECTOR(1 downto 0);
       DLYB : in STD_LOGIC_VECTOR(1 downto 0);
       EXTFB : in std_ulogic;
       GLA : out std_ulogic;
       GLB : out std_ulogic;
       LOCK : out std_ulogic
  );
end component;

----     Constants     -----
constant DANGLING_INPUT_CONSTANT : STD_LOGIC := 'Z';

---- Declaration for Dangling input ----
signal Dangling_Input_Signal : STD_LOGIC;
signal Dangling_Input_Signal_STD_ULOGIC : std_ulogic;

---- Configuration specifications for declared components 

-- synopsys translate_off
for U1 : pll use entity APA.pll;
-- synopsys translate_on

begin

----  Component instantiations  ----

U1 : pll
  port map(
       C(0) => Dangling_Input_Signal,
       C(1) => Dangling_Input_Signal,
       C(2) => Dangling_Input_Signal,
       C(3) => Dangling_Input_Signal,
       C(4) => Dangling_Input_Signal,
       C(5) => Dangling_Input_Signal,
       C(6) => Dangling_Input_Signal,
       C(7) => Dangling_Input_Signal,
       C(8) => Dangling_Input_Signal,
       C(9) => Dangling_Input_Signal,
       C(10) => Dangling_Input_Signal,
       C(11) => Dangling_Input_Signal,
       C(12) => Dangling_Input_Signal,
       C(13) => Dangling_Input_Signal,
       C(14) => Dangling_Input_Signal,
       C(15) => Dangling_Input_Signal,
       C(16) => Dangling_Input_Signal,
       C(17) => Dangling_Input_Signal,
       C(18) => Dangling_Input_Signal,
       C(19) => Dangling_Input_Signal,
       C(20) => Dangling_Input_Signal,
       C(21) => Dangling_Input_Signal,
       C(22) => Dangling_Input_Signal,
       C(23) => Dangling_Input_Signal,
       C(24) => Dangling_Input_Signal,
       C(25) => Dangling_Input_Signal,
       C(26) => Dangling_Input_Signal,
       CLK => Dangling_Input_Signal_STD_ULOGIC,
       CLKA => Dangling_Input_Signal_STD_ULOGIC,
       DLYA(0) => Dangling_Input_Signal,
       DLYA(1) => Dangling_Input_Signal,
       DLYB(0) => Dangling_Input_Signal,
       DLYB(1) => Dangling_Input_Signal,
       EXTFB => Dangling_Input_Signal_STD_ULOGIC
  );


---- Dangling input signal assignment ----

Dangling_Input_Signal <= DANGLING_INPUT_CONSTANT;

end fifo;