***************************************************************************
                               Status Report
***************************************************************************

Product: Designer
Release: v7.1
Version: 7.1.0.14
File Name: c:\my_designs\biosa\fifo\implement\counter.adb
Design Name: counter  Design State: layout

***** Device Data **************************************************

Family: PA  Die: APA600  Package: 456 BGA
Speed: STD  Voltage: 2.5

Restrict JTAG Pins: YES

Junction Temperature Range:   COM
Voltage Range:   COM

***** Import Variables *********************************************

Source File(s) Imported on Wed Oct 11 14:31:38 2006:
        c:\my_designs\biosa\fifo\synthesis\counter\counter.edf


***** CAE Variables ************************************************

Back Annotation File: ./counter.sdf;Wed Oct 11 14:33:00 2006;37630


***** Bitstream Variables ******************************************

Bitstream File: N/A
     Lock Mode: OFF


***** Compile Variables ********************************************

Netlist PIN properties overwrite existing properties: 0

Compile Output:


gfimporter V6.3.1 - 07/19/05 

Design: c:\my_designs\biosa\fifo\implement\counter.dtfStarted: Wed Oct 11 14:31:52 2006



Parameters on the command line:



   c:\my_designs\biosa\fifo\implement\counter.dtf

   -constraints        c:\my_designs\biosa\fifo\implement\counter.dtf\master.gcf

   -family             apa

   -format             EDIF

   -part               APA600

   -package            APA600-BG456

   -source             ./counter.adl

   -topcell            counter

   -temp               0:25:70

   -voltage            2.30:2.50:2.70

   -process            Worst

   -jtag               Extended

   -auto_ram_support   

   -ngt_tdpr_support   

   -mem_region_support 

   -reportfanout       20



Info: [no_load]:

        The following nets have no load:



VCC

GND



Info: [removed_pwr_gnd_cells]:

        Removed 2 power/ground cells from the design.



The list of high fanout nets arranged by fanout:

Fanout  Type            Driver                         Name

----------------------------------------------------------------------

   20   SET/RESET_NET   reset_pad/MUXTILE              reset_c

   20   CLK_NET         clock_pad/MUXTILE              clock_c

    5   INT_NET         cnt_counter_3_I_86             cnt.counter_3.DWACT_ADD_CI_0_g_array_3[0]

    4   INT_NET         counter[16]                    counter_c[16]

    4   INT_NET         counter[4]                     counter_c[4]

    4   INT_NET         cnt_counter_3_I_108            cnt.counter_3.DWACT_ADD_CI_0_g_array_2[0]

    4   INT_NET         counter[12]                    counter_c[12]

    4   INT_NET         counter[14]                    counter_c[14]

    4   INT_NET         counter[8]                     counter_c[8]

    4   INT_NET         counter[6]                     counter_c[6]

    4   INT_NET         counter[10]                    counter_c[10]

    4   INT_NET         counter[2]                     counter_c[2]

    3   INT_NET         cnt_counter_3_I_113            cnt.counter_3.DWACT_ADD_CI_0_g_array_4[0]

    3   INT_NET         counter[18]                    counter_c[18]

    3   INT_NET         counter[17]                    counter_c[17]

    3   INT_NET         cnt_counter_3_I_94             cnt.counter_3.DWACT_ADD_CI_0_g_array_10[0]

    3   INT_NET         counter[1]                     counter_c[1]

    3   INT_NET         counter[5]                     counter_c[5]

    3   INT_NET         counter[0]                     counter_c[0]

    3   INT_NET         counter[3]                     counter_c[3]



The list of high fanout nets bypassing the buffers and invertors:

Fanout  Type            Driver                         Name

----------------------------------------------------------------------

   20   SET/RESET_NET   reset_pad/MUXTILE              reset_c

   20   CLK_NET         clock_pad/MUXTILE              clock_c

    5   INT_NET         cnt_counter_3_I_86             cnt.counter_3.DWACT_ADD_CI_0_g_array_3[0]

    4   INT_NET         counter[16]                    counter_c[16]

    4   INT_NET         counter[4]                     counter_c[4]

    4   INT_NET         cnt_counter_3_I_108            cnt.counter_3.DWACT_ADD_CI_0_g_array_2[0]

    4   INT_NET         counter[12]                    counter_c[12]

    4   INT_NET         counter[14]                    counter_c[14]

    4   INT_NET         counter[8]                     counter_c[8]

    4   INT_NET         counter[6]                     counter_c[6]

    4   INT_NET         counter[10]                    counter_c[10]

    4   INT_NET         counter[2]                     counter_c[2]

    3   INT_NET         cnt_counter_3_I_113            cnt.counter_3.DWACT_ADD_CI_0_g_array_4[0]

    3   INT_NET         counter[18]                    counter_c[18]

    3   INT_NET         counter[17]                    counter_c[17]

    3   INT_NET         cnt_counter_3_I_94             cnt.counter_3.DWACT_ADD_CI_0_g_array_10[0]

    3   INT_NET         counter[1]                     counter_c[1]

    3   INT_NET         counter[5]                     counter_c[5]

    3   INT_NET         counter[0]                     counter_c[0]

    3   INT_NET         counter[3]                     counter_c[3]

Info: [too_few_globals]:

        Too few global nets could be promoted. 

        Total:2. Available global resources:4.

        The fanout required for promotion was set to 32.



The following nets are assigned to global resources:



Fanout  Name                       Reason for being global

--------------------------------------------------------------

   20   reset_c                    output of a global IO cell GL33/MUXTILE

   20   clock_c                    output of a global IO cell GL33/MUXTILE



Netlist Optimization Summary

============================



Unnecessary block removal:



  dangling net drivers:      0

               buffers:      0

             inverters:      0



Constant propagation block removal (by block type):



                  AND :      0

                  NAND:      0

                  OR  :      0

                  NOR :      0

                  XOR :      0

                  XNOR:      0

                  MUX :      0

                  AOI :      0

                  OA  :      0

                  

                  Total      0



  Total blocks removed:      0





Design Difficulty Constants: 234 - 2.5

    71.13 percent Connectivity Fanout <= 3

    100.00 percent Connectivity Fanout <= 6

    100.00 percent Connectivity Fanout <= 12

    100.00 percent Connectivity Fanout <= 28

    100.00 percent Connectivity Fanout <= 44

    100.00 percent Connectivity Fanout <= 80



Importer Summary

===============

Part-Package: APA600-BG456 

        Core Slots:        21504

        RAM/FIFO Slots:       56

        I/O Slots:           356    (Globals: 4)   (PLLs: 2)



Core Cells:         71  -->  Usage: 0.3 percent

RAM/FIFO Cells:      0  -->  Usage: 0.0 percent

IOs:                23  -->  Usage: 6.5 percent

PLLs:                0  -->  Usage: 0.0 percent



Constraints processed:

IO constraints:           0

Path constraints:         0

Placement constraints:    0

Net constraints:          0





I/O  Cells:                   Core cells:

                                          | Instances |  Gates |  Tiles

Input. IOs:         1           ----------|-----------|--------|-------

Bidir  IOs:         0      Logic          |     51    |     91 |     51

Output IOs:        20      Storage        |     20    |    160 |     20

Global IOs:         2      RAM/FIFO       |      0    |      0 |      0

Internal Global:    0                     |           |        |

-----------------------         ----------|-----------|--------|-------

Total  IOs:        23        Total        |     71    |    251 |     71



    



Nets           | Count  | Average Fanout | Max. Fanout

---------------|--------|----------------|------------

Global         |     2  |        20.0    |          20

External       |    21  |         3.3    |           4

Internal       |    51  |         1.4    |           5

---------------|--------|----------------|------------

Total          |    74  |         2.5    |          20





gfimporter completed successfully.



Design: c:\my_designs\biosa\fifo\implement\counter.dtf

Finished: Wed Oct 11 14:31:54 2006

Information messages reported: 1

Total CPU Time:     00:00:01            Total Elapsed Time: 00:00:02

                        o - o - o - o - o - o





***** Layout Variables *********************************************

Mode: TIMING_DRIVEN
Incremental Placement: OFF
Incremental Route: OFF


Layout Output:

desqdplacer V6_2_0.0 - 5/16/05
Design: c:\my_designs\biosa\fifo\implement\counterStarted: Wed Oct 11 14:31:56 2006

Initial IO placement.
IO & RAM improvement.
Core placement.
Core improvement.

Runtimes: IO Placement         = 0 seconds
          RAM Placement        = 0 seconds
          IO & RAM Improvement = 0 seconds
          Core Placement       = 0 seconds
          Core Improvement     = 0 seconds


desqdplacer completed successfully.

Design: c:\my_designs\biosa\fifo\implement\counter
Finished: Wed Oct 11 14:31:56 2006
Total CPU Time:     00:00:00            Total Elapsed Time: 00:00:00
                        o - o - o - o - o - o



gfblrouter V5_0_7.0 - 07/17/03 

Design: counter                         Started: Wed Oct 11 14:32:02 2006



Parameters on the command line:



   c:\my_designs\biosa\fifo\implement\counter.dtf

   -family             apa

   -part               APA600

   -package            APA600-BG456

   -time               

   -schedule           2 2 25 29

   -noRouteRamClock    



 Initial routing.

Initial routing...

        Pass 0: Shorts = 0. Open nets = 74.

        Pass 0: Shorts = 0. Open nets = 34.

        Pass 0: Shorts = 0. Open nets = 33.

        Pass 0: Shorts = 0. Open nets = 32.

        Pass 0: Shorts = 0. Open nets = 30.

        Pass 0: Shorts = 0. Open nets = 29.

        Pass 0: Shorts = 0. Open nets = 28.

        Pass 0: Shorts = 0. Open nets = 27.

        Pass 0: Shorts = 0. Open nets = 26.

        Pass 0: Shorts = 0. Open nets = 24.

        Pass 0: Shorts = 0. Open nets = 23.

        Pass 0: Shorts = 0. Open nets = 22.

        Pass 0: Shorts = 0. Open nets = 21.

        Pass 0: Shorts = 0. Open nets = 20.

        Pass 0: Shorts = 0. Open nets = 18.

        Pass 0: Shorts = 0. Open nets = 17.

        Pass 0: Shorts = 0. Open nets = 16.

        Pass 0: Shorts = 0. Open nets = 15.

        Pass 0: Shorts = 0. Open nets = 14.

        Pass 0: Shorts = 0. Open nets = 12.

        Pass 0: Shorts = 0. Open nets = 11.

        Pass 0: Shorts = 0. Open nets = 10.

        Pass 0: Shorts = 0. Open nets = 9.

        Pass 0: Shorts = 0. Open nets = 7.

        Pass 0: Shorts = 0. Open nets = 6.

        Pass 0: Shorts = 0. Open nets = 5.

        Pass 0: Shorts = 0. Open nets = 4.

        Pass 0: Shorts = 0. Open nets = 3.

        Pass 0: Shorts = 0. Open nets = 2.

        Pass 0: Shorts = 0. Open nets = 1.

        Pass 0: Shorts = 0. Open nets = 0.

After pass 0: Shorts = 0. Open nets = 0.



 Iterative improvement.

        Pass 1: Shorts = 0. Open nets = 0.

Loads already balanced.



gfblrouter completed successfully.



Design: counter                         

Finished: Wed Oct 11 14:32:15 2006

Total CPU Time:     00:00:12            Total Elapsed Time: 00:00:13

                        o - o - o - o - o - o




Global Usage Report:
===================

The following nets have been routed to a global resource:

    Fanout            Name
    ----------------------
    20                Net   : clock_c
                      Driver: clock_pad/MUXTILE
    20                Net   : reset_c
                      Driver: reset_pad/MUXTILE





