Timing Report Max Delay Analysis

Timer Version 2.0
Actel Corporation - Actel Designer Software Release v7.1 (Version 7.1.0.14)
Copyright (c) 1989-2006
Date: Wed Oct 11 14:33:02 2006


Design: counter
Family: PA
Die: APA600
Package: 456 BGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis


-----------------------------------------------------
SUMMARY

Clock Domain:               clock
Period (ns):                14.414
Frequency (MHz):            69.377
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        13.417
External Hold (ns):         -0.591
Min Clock-To-Out (ns):      2.541
Max Clock-To-Out (ns):      8.491

Input to Output:
Min Delay (ns):
Max Delay (ns):

END SUMMARY
-----------------------------------------------------

Clock Domain clock

SET Register to Register

Path 1
  From:                        counter[5]:CLK
  To:                          counter[15]:D
  Delay (ns):                  13.647
  Slack (ns):
  Arrival (ns):                15.789
  Required (ns):
  Setup (ns):                  0.766
  Minimum Period (ns):         14.414

Path 2
  From:                        counter[4]:CLK
  To:                          counter[15]:D
  Delay (ns):                  13.504
  Slack (ns):
  Arrival (ns):                15.638
  Required (ns):
  Setup (ns):                  0.766
  Minimum Period (ns):         14.263

Path 3
  From:                        counter[7]:CLK
  To:                          counter[15]:D
  Delay (ns):                  13.093
  Slack (ns):
  Arrival (ns):                15.235
  Required (ns):
  Setup (ns):                  0.766
  Minimum Period (ns):         13.860

Path 4
  From:                        counter[6]:CLK
  To:                          counter[15]:D
  Delay (ns):                  12.948
  Slack (ns):
  Arrival (ns):                15.083
  Required (ns):
  Setup (ns):                  0.766
  Minimum Period (ns):         13.708

Path 5
  From:                        counter[5]:CLK
  To:                          counter[14]:D
  Delay (ns):                  12.888
  Slack (ns):
  Arrival (ns):                15.030
  Required (ns):
  Setup (ns):                  0.766
  Minimum Period (ns):         13.662


Expanded Path 1
  From: counter[5]:CLK
  To: counter[15]:D
  data required time                             N/C
  data arrival time                          -   15.789
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        clock
               +     2.142          clock network
  2.142                        counter[5]:CLK (r)
               +     0.814          cell: ADLIB:DFFC
  2.956                        counter[5]:Q (f)
               +     0.333          net: counter_c[5]
  3.289                        cnt_counter_3_I_124:B (f)
               +     0.727          cell: ADLIB:AND2
  4.016                        cnt_counter_3_I_124:Y (f)
               +     1.110          net: cnt_counter_3_DWACT_ADD_CI_0_pog_array_1_1[0]
  5.126                        cnt_counter_3_I_120:A (f)
               +     0.725          cell: ADLIB:AND2
  5.851                        cnt_counter_3_I_120:Y (f)
               +     1.955          net: cnt_counter_3_DWACT_ADD_CI_0_pog_array_2[0]
  7.806                        cnt_counter_3_I_86:B (f)
               +     0.739          cell: ADLIB:AND2
  8.545                        cnt_counter_3_I_86:Y (f)
               +     2.425          net: cnt_counter_3_DWACT_ADD_CI_0_g_array_3[0]
  10.970                       cnt_counter_3_I_94:A (f)
               +     0.603          cell: ADLIB:AND2
  11.573                       cnt_counter_3_I_94:Y (f)
               +     1.501          net: cnt_counter_3_DWACT_ADD_CI_0_g_array_10[0]
  13.074                       cnt_counter_3_I_102:A (f)
               +     0.734          cell: ADLIB:AND2
  13.808                       cnt_counter_3_I_102:Y (f)
               +     0.357          net: cnt_counter_3_DWACT_ADD_CI_0_g_array_11_2[0]
  14.165                       cnt_counter_3_I_105:A (f)
               +     0.450          cell: ADLIB:AND2
  14.615                       cnt_counter_3_I_105:Y (f)
               +     0.272          net: cnt_counter_3_DWACT_ADD_CI_0_g_array_12_6[0]
  14.887                       cnt_counter_3_I_64:B (f)
               +     0.592          cell: ADLIB:XOR2
  15.479                       cnt_counter_3_I_64:Y (f)
               +     0.310          net: cnt_counter_3[15]
  15.789                       counter[15]:D (f)
                                    
  15.789                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          clock
               +     2.141          clock network
  N/C                          counter[15]:CLK (r)
               -     0.766          Library setup: ADLIB:DFFC
  N/C                          counter[15]:D


END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        enable
  To:                          counter[15]:D
  Delay (ns):                  14.792
  Slack (ns):
  Arrival (ns):                14.792
  Required (ns):
  Setup (ns):                  0.766
  External Setup (ns):         13.417

Path 2
  From:                        enable
  To:                          counter[14]:D
  Delay (ns):                  14.033
  Slack (ns):
  Arrival (ns):                14.033
  Required (ns):
  Setup (ns):                  0.766
  External Setup (ns):         12.665

Path 3
  From:                        enable
  To:                          counter[19]:D
  Delay (ns):                  13.953
  Slack (ns):
  Arrival (ns):                13.953
  Required (ns):
  Setup (ns):                  0.766
  External Setup (ns):         12.580

Path 4
  From:                        enable
  To:                          counter[18]:D
  Delay (ns):                  13.226
  Slack (ns):
  Arrival (ns):                13.226
  Required (ns):
  Setup (ns):                  0.766
  External Setup (ns):         11.853

Path 5
  From:                        enable
  To:                          counter[13]:D
  Delay (ns):                  12.949
  Slack (ns):
  Arrival (ns):                12.949
  Required (ns):
  Setup (ns):                  0.766
  External Setup (ns):         11.581


Expanded Path 1
  From: enable
  To: counter[15]:D
  data required time                             N/C
  data arrival time                          -   14.792
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        enable (f)
               +     0.000          net: enable
  0.000                        enable_pad:PAD (f)
               +     0.596          cell: ADLIB:IB33
  0.596                        enable_pad:Y (f)
               +     2.577          net: enable_c
  3.173                        cnt_counter_3_I_1:B (f)
               +     0.740          cell: ADLIB:AND2
  3.913                        cnt_counter_3_I_1:Y (f)
               +     0.338          net: cnt_counter_3_DWACT_ADD_CI_0_TMP[0]
  4.251                        cnt_counter_3_I_89:A (f)
               +     0.444          cell: ADLIB:AND2
  4.695                        cnt_counter_3_I_89:Y (f)
               +     0.278          net: cnt_counter_3_DWACT_ADD_CI_0_g_array_1[0]
  4.973                        cnt_counter_3_I_108:A (f)
               +     0.424          cell: ADLIB:AND2
  5.397                        cnt_counter_3_I_108:Y (f)
               +     1.654          net: cnt_counter_3_DWACT_ADD_CI_0_g_array_2[0]
  7.051                        cnt_counter_3_I_86:A (f)
               +     0.497          cell: ADLIB:AND2
  7.548                        cnt_counter_3_I_86:Y (f)
               +     2.425          net: cnt_counter_3_DWACT_ADD_CI_0_g_array_3[0]
  9.973                        cnt_counter_3_I_94:A (f)
               +     0.603          cell: ADLIB:AND2
  10.576                       cnt_counter_3_I_94:Y (f)
               +     1.501          net: cnt_counter_3_DWACT_ADD_CI_0_g_array_10[0]
  12.077                       cnt_counter_3_I_102:A (f)
               +     0.734          cell: ADLIB:AND2
  12.811                       cnt_counter_3_I_102:Y (f)
               +     0.357          net: cnt_counter_3_DWACT_ADD_CI_0_g_array_11_2[0]
  13.168                       cnt_counter_3_I_105:A (f)
               +     0.450          cell: ADLIB:AND2
  13.618                       cnt_counter_3_I_105:Y (f)
               +     0.272          net: cnt_counter_3_DWACT_ADD_CI_0_g_array_12_6[0]
  13.890                       cnt_counter_3_I_64:B (f)
               +     0.592          cell: ADLIB:XOR2
  14.482                       cnt_counter_3_I_64:Y (f)
               +     0.310          net: cnt_counter_3[15]
  14.792                       counter[15]:D (f)
                                    
  14.792                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          clock
               +     2.141          clock network
  N/C                          counter[15]:CLK (r)
               -     0.766          Library setup: ADLIB:DFFC
  N/C                          counter[15]:D


END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        counter[7]:CLK
  To:                          count[7]
  Delay (ns):                  6.349
  Slack (ns):
  Arrival (ns):                8.491
  Required (ns):
  Clock to Out (ns):           8.491

Path 2
  From:                        counter[10]:CLK
  To:                          count[10]
  Delay (ns):                  6.301
  Slack (ns):
  Arrival (ns):                8.440
  Required (ns):
  Clock to Out (ns):           8.440

Path 3
  From:                        counter[11]:CLK
  To:                          count[11]
  Delay (ns):                  6.141
  Slack (ns):
  Arrival (ns):                8.280
  Required (ns):
  Clock to Out (ns):           8.280

Path 4
  From:                        counter[13]:CLK
  To:                          count[13]
  Delay (ns):                  5.869
  Slack (ns):
  Arrival (ns):                8.003
  Required (ns):
  Clock to Out (ns):           8.003

Path 5
  From:                        counter[12]:CLK
  To:                          count[12]
  Delay (ns):                  5.521
  Slack (ns):
  Arrival (ns):                7.663
  Required (ns):
  Clock to Out (ns):           7.663


Expanded Path 1
  From: counter[7]:CLK
  To: count[7]
  data required time                             N/C
  data arrival time                          -   8.491
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        clock
               +     2.142          clock network
  2.142                        counter[7]:CLK (r)
               +     0.814          cell: ADLIB:DFFC
  2.956                        counter[7]:Q (f)
               +     3.382          net: counter_c[7]
  6.338                        count_pad[7]:A (f)
               +     2.153          cell: ADLIB:OB33PH
  8.491                        count_pad[7]:PAD (f)
               +     0.000          net: count[7]
  8.491                        count[7] (f)
                                    
  8.491                        data arrival time
  ________________________________________________________
  Data required time calculation


END SET Clock to Output

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

