library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity address_multiplexer is
	 port(
		 clock 		: in 	std_logic;
		 reset 		: in 	std_logic;	
		 read		: in	std_logic;
		 write		: in	std_logic;		
		 address 	: out 	std_logic_vector(19 downto 0)
	 );
end address_multiplexer;

architecture synthesis of address_multiplexer is	  
	component counter					   
		 port(
			 clock 	: in 	std_logic;
			 reset 	: in 	std_logic;
			 enable : in 	std_logic;
			 count 	: out 	std_logic_vector(19 downto 0)
		 );
	end component;		   
	
	signal read_address		: std_logic_vector(19 downto 0);
	signal write_address 	: std_logic_vector(19 downto 0);  
	signal memory_address 	: std_logic_vector(19 downto 0);
begin  
	
	read_address_counter : counter
	  port map(
	  	clock	=> clock,
	  	reset	=> reset,
		enable	=> read,
		count	=> read_address
	  );	
	  
	write_address_counter : counter
	  port map(
	  	clock	=> clock,
	  	reset	=> reset,
		enable	=> write,
		count	=> write_address
	  );  
	  
	addr_mux : process (clock, reset)
	begin						
		if reset = '1' then
			memory_address <= (others => '0');
		elsif rising_edge(clock) then  
			if write = '1' then
				memory_address <= write_address;
			else
				memory_address <= read_address;
			end if;
		end if;
	end process addr_mux;

end synthesis;