library ieee;
use ieee.std_logic_1164.all;		  
use ieee.std_logic_unsigned.all;

entity counter is
	 port(
		 clock 	: in 	std_logic;
		 reset 	: in 	std_logic;
		 enable : in 	std_logic;
		 count 	: out 	std_logic_vector(19 downto 0)
	 );
end counter;

architecture synthesis of counter is	   
	signal counter	: std_logic_vector(19 downto 0);
begin

	cnt : process(clock, reset)
	begin					
		if (reset = '1') then  
			counter <= (others => '0');
		elsif rising_edge(clock) then
			if (enable = '1') then
				counter <= counter + 1;
			end if;			   
		end if;
	end process cnt;
	
	count <= counter;

end synthesis;