1              		.file	"ks8695px.cpp"
   9              	.Ltext0:
  10              		.section	.text._ZN11BUS_CONTROL10regAddressENS_9RegistersE,"axG",%progbits,_ZN11BUS_CONTROL10regAd
  11              		.align	2
  12              		.weak	_ZN11BUS_CONTROL10regAddressENS_9RegistersE
  14              	_ZN11BUS_CONTROL10regAddressENS_9RegistersE:
  15              	.LFB2:
  16              		.file 1 "bus_control_register.h"
   1:bus_control_register.h **** #ifndef __BUS_CONTROL_REGISTER_H__
   2:bus_control_register.h **** #define __BUS_CONTROL_REGISTER_H__
   3:bus_control_register.h **** 
   4:bus_control_register.h **** #include <stdint.h>
   5:bus_control_register.h **** #include "platform.h"
   6:bus_control_register.h **** 
   7:bus_control_register.h **** namespace BUS_CONTROL
   8:bus_control_register.h **** {
   9:bus_control_register.h **** 	static const uint32_t BaseAddress = (KS8695PX_IO_BASE + KS8695PX_BUS_CONTROL_OFFSET);
  10:bus_control_register.h **** 	
  11:bus_control_register.h **** 	enum Registers
  12:bus_control_register.h **** 	{
  13:bus_control_register.h **** 		CLKCON	= 0x0004		// 0x00	- System Clock and Bus Control Register (rw)
  14:bus_control_register.h **** 	};
  15:bus_control_register.h **** 	
  16:bus_control_register.h **** 	inline volatile uint32_t *regAddress(Registers reg)
  17              	args = 0, pretend = 0, frame = 4
  18              		@ frame_needed = 1, uses_anonymous_args = 0
  19              		mov	ip, sp
  20 0000 0DC0A0E1 	.LCFI0:
  21              		stmfd	sp!, {fp, ip, lr, pc}
  22 0004 00D82DE9 	.LCFI1:
  23              		sub	fp, ip, #4
  24 0008 04B04CE2 	.LCFI2:
  25              		sub	sp, sp, #4
  26 000c 04D04DE2 	.LCFI3:
  27              		str	r0, [fp, #-16]
  28 0010 10000BE5 		.loc 1 18 0
  17:bus_control_register.h **** 	{
  18:bus_control_register.h **** 	    return reinterpret_cast<volatile uint32_t*>(BaseAddress + reg);
  29              	, #-16]
  30 0014 10301BE5 		add	r3, r3, #66846720
  31 0018 FF3783E2 		add	r3, r3, #196608
  32 001c 033883E2 		.loc 1 19 0
  19:bus_control_register.h **** 	}
  33              		r0, r3
  34 0020 0300A0E1 		ldmfd	sp, {r3, fp, sp, pc}
  35 0024 08A89DE8 	.LFE2:
  37              		.section	.text._ZN11BUS_CONTROL8regWriteENS_9RegistersEm,"axG",%progbits,_ZN11BUS_CONTROL8regWrite
  38              		.align	2
  39              		.weak	_ZN11BUS_CONTROL8regWriteENS_9RegistersEm
  41              	_ZN11BUS_CONTROL8regWriteENS_9RegistersEm:
  42              	.LFB4:
  43              		.loc 1 26 0
  20:bus_control_register.h **** 	
  21:bus_control_register.h **** 	inline uint32_t regRead(Registers reg)
  22:bus_control_register.h **** 	{
  23:bus_control_register.h **** 	    return *regAddress(reg);
  24:bus_control_register.h **** 	}
  25:bus_control_register.h **** 	
  26:bus_control_register.h **** 	inline void regWrite(Registers reg, uint32_t value)
  44              	, pretend = 0, frame = 8
  45              		@ frame_needed = 1, uses_anonymous_args = 0
  46              		mov	ip, sp
  47 0000 0DC0A0E1 	.LCFI4:
  48              		stmfd	sp!, {fp, ip, lr, pc}
  49 0004 00D82DE9 	.LCFI5:
  50              		sub	fp, ip, #4
  51 0008 04B04CE2 	.LCFI6:
  52              		sub	sp, sp, #8
  53 000c 08D04DE2 	.LCFI7:
  54              		str	r0, [fp, #-16]
  55 0010 10000BE5 		str	r1, [fp, #-20]
  56 0014 14100BE5 		.loc 1 28 0
  27:bus_control_register.h **** 	{
  28:bus_control_register.h **** 	    *regAddress(reg) = value;
  57              	 #-16]
  58 0018 10001BE5 		ldr	r3, .L5
  59 001c 18309FE5 		mov	lr, pc
  60 0020 0FE0A0E1 		bx	r3
  61 0024 13FF2FE1 		mov	r2, r0
  62 0028 0020A0E1 		ldr	r3, [fp, #-20]
  63 002c 14301BE5 		str	r3, [r2, #0]
  64 0030 003082E5 		.loc 1 29 0
  29:bus_control_register.h **** 	}
  65              	 fp, #12
  66 0034 0CD04BE2 		ldmfd	sp, {fp, sp, pc}
  67 0038 00A89DE8 	.L6:
  68              		.align	2
  69              	.L5:
  70              		.word	_ZN11BUS_CONTROL10regAddressENS_9RegistersE
  71 003c 00000000 	.LFE4:
  73              		.section	.text._ZN11EXTERNAL_IO10regAddressENS_9RegistersE,"axG",%progbits,_ZN11EXTERNAL_IO10regAd
  74              		.align	2
  75              		.weak	_ZN11EXTERNAL_IO10regAddressENS_9RegistersE
  77              	_ZN11EXTERNAL_IO10regAddressENS_9RegistersE:
  78              	.LFB7:
  79              		.file 2 "external_io_registers.h"
  80              		.loc 2 47 0
   1:external_io_registers.h **** #ifndef __EXTERNAL_IO_REGISTERS_H__
   2:external_io_registers.h **** #define __EXTERNAL_IO_REGISTERS_H__
   3:external_io_registers.h **** 
   4:external_io_registers.h **** #include <stdint.h>
   5:external_io_registers.h **** #include "platform.h"
   6:external_io_registers.h **** #include "register_bitops.h"
   7:external_io_registers.h **** 
   8:external_io_registers.h **** namespace EXTERNAL_IO
   9:external_io_registers.h **** {
  10:external_io_registers.h **** 	static const uint32_t BaseAddress = (KS8695PX_IO_BASE + KS8695PX_EXTERNAL_IO_OFFSET);
  11:external_io_registers.h **** 	
  12:external_io_registers.h **** 	enum Registers
  13:external_io_registers.h **** 	{
  14:external_io_registers.h **** 		EXTACON0	= 0x0000,		// 0x00	- External IO Access Control Register 0(rw)
  15:external_io_registers.h **** 		EXTACON1	= 0x0004,		// 0x04 - External IO Access Control Register 1(rw)
  16:external_io_registers.h **** 		EXTACON2	= 0x0008,		// 0x08 - External IO Access Control Register 2(rw)
  17:external_io_registers.h **** 		ROMCON0		= 0x0010,		// 0x10 - ROM/SRAM/Flash Control Register 0(rw)
  18:external_io_registers.h **** 		ROMCON1		= 0x0014,		// 0x14 - ROM/SRAM/Flash Control Register 1(rw)		
  19:external_io_registers.h **** 		ERGCON		= 0x0020,		// 0x20 - External IO General Control Register(rw)
  20:external_io_registers.h **** 		SDCON0		= 0x0030,		// 0x30 - SDRAM Control Register 0(rw)		
  21:external_io_registers.h **** 		SDCON1		= 0x0034,		// 0x34 - SDRAM Control Register 1(rw)	
  22:external_io_registers.h **** 		SDGCON		= 0x0038,		// 0x38 - SDRAM General Control Register(rw)	
  23:external_io_registers.h **** 		SDBCON		= 0x003C,		// 0x38 - SDRAM Buffer Control Register(rw)			
  24:external_io_registers.h **** 		REFTIM		= 0x0040		// 0x40 - SDRAM Refersh Timer Register(rw)
  25:external_io_registers.h **** 	};
  26:external_io_registers.h **** 	
  27:external_io_registers.h **** 	enum EXTACON_BITS
  28:external_io_registers.h **** 	{
  29:external_io_registers.h **** 		LAST_ADDRESS					= REGISTER_BIT_DEFINITION(31, 22),
  30:external_io_registers.h **** 		BASE_ADDRESS					= REGISTER_BIT_DEFINITION(21, 12),
  31:external_io_registers.h **** 		TIME_OE_OR_WE_IS_ASSERTED		= REGISTER_BIT_DEFINITION(11,  9),	
  32:external_io_registers.h **** 		CS_HOLD_TIME_AFTER_OE_OR_WE		= REGISTER_BIT_DEFINITION( 8,  6),		
  33:external_io_registers.h **** 		ADDRESS_SETUP_TIME_BEFORE_CS	= REGISTER_BIT_DEFINITION( 5,  3),
  34:external_io_registers.h **** 		CS_SETUP_TIME_BEFORE_OE_OR_WE	= REGISTER_BIT_DEFINITION( 2,  0)				
  35:external_io_registers.h **** 	};
  36:external_io_registers.h **** 	
  37:external_io_registers.h **** 	enum ERGCON_BITS
  38:external_io_registers.h **** 	{
  39:external_io_registers.h **** 		BUS_CLOCK_MULTIPLIER			= REGISTER_BIT_DEFINITION(29, 28),
  40:external_io_registers.h **** 		BUS_WIDTH_FOR_EXTERNAL_BANK_2	= REGISTER_BIT_DEFINITION(21, 20),
  41:external_io_registers.h **** 		BUS_WIDTH_FOR_EXTERNAL_BANK_1	= REGISTER_BIT_DEFINITION(19, 18),		
  42:external_io_registers.h **** 		BUS_WIDTH_FOR_EXTERNAL_BANK_0	= REGISTER_BIT_DEFINITION(17, 16),
  43:external_io_registers.h **** 		BUS_WIDTH_FOR_FLASH_BANK_1		= REGISTER_BIT_DEFINITION( 3,  2),
  44:external_io_registers.h **** 		BUS_WIDTH_FOR_FLASH_BANK_0		= REGISTER_BIT_DEFINITION( 1,  0)				
  45:external_io_registers.h **** 	};
  46:external_io_registers.h **** 	
  47:external_io_registers.h **** 	inline volatile uint32_t *regAddress(Registers reg)
  81              	tend = 0, frame = 4
  82              		@ frame_needed = 1, uses_anonymous_args = 0
  83              		mov	ip, sp
  84 0000 0DC0A0E1 	.LCFI8:
  85              		stmfd	sp!, {fp, ip, lr, pc}
  86 0004 00D82DE9 	.LCFI9:
  87              		sub	fp, ip, #4
  88 0008 04B04CE2 	.LCFI10:
  89              		sub	sp, sp, #4
  90 000c 04D04DE2 	.LCFI11:
  91              		str	r0, [fp, #-16]
  92 0010 10000BE5 		.loc 2 49 0
  48:external_io_registers.h **** 	{
  49:external_io_registers.h **** 	    return reinterpret_cast<volatile uint32_t*>(BaseAddress + reg);
  93              	, #-16]
  94 0014 10301BE5 		add	r3, r3, #66846720
  95 0018 FF3783E2 		add	r3, r3, #212992
  96 001c 0D3983E2 		.loc 2 50 0
  50:external_io_registers.h **** 	}
  97              		r0, r3
  98 0020 0300A0E1 		ldmfd	sp, {r3, fp, sp, pc}
  99 0024 08A89DE8 	.LFE7:
 101              		.section	.text._ZN6TIMERS10regAddressENS_9RegistersE,"axG",%progbits,_ZN6TIMERS10regAddressENS_9Re
 102              		.align	2
 103              		.weak	_ZN6TIMERS10regAddressENS_9RegistersE
 105              	_ZN6TIMERS10regAddressENS_9RegistersE:
 106              	.LFB10:
 107              		.file 3 "timer_registers.h"
 108              		.loc 3 20 0
   1:timer_registers.h **** #ifndef __TIMER_REGISTERS_H__
   2:timer_registers.h **** #define __TIMER_REGISTERS_H__
   3:timer_registers.h **** 
   4:timer_registers.h **** #include <stdint.h>
   5:timer_registers.h **** #include "platform.h"
   6:timer_registers.h **** 
   7:timer_registers.h **** namespace TIMERS
   8:timer_registers.h **** {
   9:timer_registers.h **** 	static const uint32_t BaseAddress = (KS8695PX_IO_BASE + KS8695PX_TIMER_OFFSET);
  10:timer_registers.h **** 	
  11:timer_registers.h **** 	enum Registers
  12:timer_registers.h **** 	{
  13:timer_registers.h **** 		TMCON	= 0x0000,	// 0x00	- Timer Control Register (rw)
  14:timer_registers.h **** 		T1TC	= 0x0004,	// 0x04	- Timer 1 Timeout Count Register (rw)
  15:timer_registers.h **** 		T0TC	= 0x0008,	// 0x08	- Timer 0 Timeout Count Register (rw)
  16:timer_registers.h **** 		T1PD	= 0x000C,	// 0x0c	- Timer 1 Pulse Count Register (rw)
  17:timer_registers.h **** 		T0PD	= 0x0010	// 0x10	- Timer 0 Pulse Count Register (rw)
  18:timer_registers.h **** 	};
  19:timer_registers.h **** 	
  20:timer_registers.h **** 	inline volatile uint32_t *regAddress(Registers reg)
 109              	 pretend = 0, frame = 4
 110              		@ frame_needed = 1, uses_anonymous_args = 0
 111              		mov	ip, sp
 112 0000 0DC0A0E1 	.LCFI12:
 113              		stmfd	sp!, {fp, ip, lr, pc}
 114 0004 00D82DE9 	.LCFI13:
 115              		sub	fp, ip, #4
 116 0008 04B04CE2 	.LCFI14:
 117              		sub	sp, sp, #4
 118 000c 04D04DE2 	.LCFI15:
 119              		str	r0, [fp, #-16]
 120 0010 10000BE5 		.loc 3 22 0
  21:timer_registers.h **** 	{
  22:timer_registers.h **** 	    return reinterpret_cast<volatile uint32_t*>(BaseAddress + reg);
 121              	, #-16]
 122 0014 10301BE5 		add	r3, r3, #66846720
 123 0018 FF3783E2 		add	r3, r3, #254976
 124 001c F93B83E2 		.loc 3 23 0
  23:timer_registers.h **** 	}
 125              		r0, r3
 126 0020 0300A0E1 		ldmfd	sp, {r3, fp, sp, pc}
 127 0024 08A89DE8 	.LFE10:
 129              		.section	.text._ZN6TIMERS7regReadENS_9RegistersE,"axG",%progbits,_ZN6TIMERS7regReadENS_9RegistersE
 130              		.align	2
 131              		.weak	_ZN6TIMERS7regReadENS_9RegistersE
 133              	_ZN6TIMERS7regReadENS_9RegistersE:
 134              	.LFB11:
 135              		.loc 3 25 0
  24:timer_registers.h **** 	
  25:timer_registers.h **** 	inline uint32_t regRead(Registers reg)
 136              	, pretend = 0, frame = 4
 137              		@ frame_needed = 1, uses_anonymous_args = 0
 138              		mov	ip, sp
 139 0000 0DC0A0E1 	.LCFI16:
 140              		stmfd	sp!, {fp, ip, lr, pc}
 141 0004 00D82DE9 	.LCFI17:
 142              		sub	fp, ip, #4
 143 0008 04B04CE2 	.LCFI18:
 144              		sub	sp, sp, #4
 145 000c 04D04DE2 	.LCFI19:
 146              		str	r0, [fp, #-16]
 147 0010 10000BE5 		.loc 3 27 0
  26:timer_registers.h **** 	{
  27:timer_registers.h **** 	    return *regAddress(reg);
 148              	, #-16]
 149 0014 10001BE5 		ldr	r3, .L13
 150 0018 14309FE5 		mov	lr, pc
 151 001c 0FE0A0E1 		bx	r3
 152 0020 13FF2FE1 		mov	r3, r0
 153 0024 0030A0E1 		ldr	r3, [r3, #0]
 154 0028 003093E5 		.loc 3 28 0
  28:timer_registers.h **** 	}
 155              	, r3
 156 002c 0300A0E1 		ldmfd	sp, {r3, fp, sp, pc}
 157 0030 08A89DE8 	.L14:
 158              		.align	2
 159              	.L13:
 160              		.word	_ZN6TIMERS10regAddressENS_9RegistersE
 161 0034 00000000 	.LFE11:
 163              		.section	.text._ZN6TIMERS8regWriteENS_9RegistersEm,"axG",%progbits,_ZN6TIMERS8regWriteENS_9Registe
 164              		.align	2
 165              		.weak	_ZN6TIMERS8regWriteENS_9RegistersEm
 167              	_ZN6TIMERS8regWriteENS_9RegistersEm:
 168              	.LFB12:
 169              		.loc 3 30 0
  29:timer_registers.h **** 	
  30:timer_registers.h **** 	inline void regWrite(Registers reg, uint32_t value)
 170              	etend = 0, frame = 8
 171              		@ frame_needed = 1, uses_anonymous_args = 0
 172              		mov	ip, sp
 173 0000 0DC0A0E1 	.LCFI20:
 174              		stmfd	sp!, {fp, ip, lr, pc}
 175 0004 00D82DE9 	.LCFI21:
 176              		sub	fp, ip, #4
 177 0008 04B04CE2 	.LCFI22:
 178              		sub	sp, sp, #8
 179 000c 08D04DE2 	.LCFI23:
 180              		str	r0, [fp, #-16]
 181 0010 10000BE5 		str	r1, [fp, #-20]
 182 0014 14100BE5 		.loc 3 32 0
  31:timer_registers.h **** 	{
  32:timer_registers.h **** 	    *regAddress(reg) = value;
 183              	 #-16]
 184 0018 10001BE5 		ldr	r3, .L17
 185 001c 18309FE5 		mov	lr, pc
 186 0020 0FE0A0E1 		bx	r3
 187 0024 13FF2FE1 		mov	r2, r0
 188 0028 0020A0E1 		ldr	r3, [fp, #-20]
 189 002c 14301BE5 		str	r3, [r2, #0]
 190 0030 003082E5 		.loc 3 33 0
  33:timer_registers.h **** 	}
 191              	 fp, #12
 192 0034 0CD04BE2 		ldmfd	sp, {fp, sp, pc}
 193 0038 00A89DE8 	.L18:
 194              		.align	2
 195              	.L17:
 196              		.word	_ZN6TIMERS10regAddressENS_9RegistersE
 197 003c 00000000 	.LFE12:
 199              		.text
 200              		.align	2
 201              		.global	_ZN3CPU19SetSystemClockSpeedE11CLOCK_SPEED
 203              	_ZN3CPU19SetSystemClockSpeedE11CLOCK_SPEED:
 204              	.LFB13:
 205              		.file 4 "ks8695px.cpp"
 206              		.loc 4 12 0
   1:ks8695px.cpp  **** #include "ks8695px.h"
   2:ks8695px.cpp  **** #include "bus_control_register.h"
   3:ks8695px.cpp  **** #include "external_io_registers.h"
   4:ks8695px.cpp  **** #include "watchdog.h"
   5:ks8695px.cpp  **** #include "timer_registers.h"
   6:ks8695px.cpp  **** 
   7:ks8695px.cpp  **** const uint32_t	MMU_Mask		=	0x00000001;
   8:ks8695px.cpp  **** const uint32_t	DCacheMask		=	0x00000004;
   9:ks8695px.cpp  **** const uint32_t	ICacheMask		=	0x00001000;
  10:ks8695px.cpp  **** const uint32_t	FCSEMask		=	0xC0000000;
  11:ks8695px.cpp  **** 
  12:ks8695px.cpp  **** void CPU::SetSystemClockSpeed(CLOCK_SPEED speed)
 207              	tend = 0, frame = 4
 208              		@ frame_needed = 1, uses_anonymous_args = 0
 209              		mov	ip, sp
 210 0000 0DC0A0E1 	.LCFI24:
 211              		stmfd	sp!, {fp, ip, lr, pc}
 212 0004 00D82DE9 	.LCFI25:
 213              		sub	fp, ip, #4
 214 0008 04B04CE2 	.LCFI26:
 215              		sub	sp, sp, #4
 216 000c 04D04DE2 	.LCFI27:
 217              		str	r0, [fp, #-16]
 218 0010 10000BE5 		.loc 4 14 0
  13:ks8695px.cpp  **** {
  14:ks8695px.cpp  **** 	regWrite(BUS_CONTROL::CLKCON, static_cast<uint32_t>(speed));
 219              	, #-16]
 220 0014 10301BE5 		mov	r0, #4
 221 0018 0400A0E3 		mov	r1, r3
 222 001c 0310A0E1 		ldr	r3, .L21
 223 0020 08309FE5 		mov	lr, pc
 224 0024 0FE0A0E1 		bx	r3
 225 0028 13FF2FE1 		.loc 4 15 0
  15:ks8695px.cpp  **** }
 226              	sp, {r3, fp, sp, pc}
 227 002c 08A89DE8 	.L22:
 228              		.align	2
 229              	.L21:
 230              		.word	_ZN11BUS_CONTROL8regWriteENS_9RegistersEm
 231 0030 00000000 	.LFE13:
 233              		.align	2
 234              		.global	_ZN3CPU5ResetEv
 236              	_ZN3CPU5ResetEv:
 237              	.LFB14:
 238              		.loc 4 17 0
  16:ks8695px.cpp  **** 
  17:ks8695px.cpp  **** void CPU::Reset(void)
 239              	pretend = 0, frame = 4
 240              		@ frame_needed = 1, uses_anonymous_args = 0
 241              		mov	ip, sp
 242 0034 0DC0A0E1 	.LCFI28:
 243              		stmfd	sp!, {fp, ip, lr, pc}
 244 0038 00D82DE9 	.LCFI29:
 245              		sub	fp, ip, #4
 246 003c 04B04CE2 	.LCFI30:
 247              		sub	sp, sp, #4
 248 0040 04D04DE2 	.LCFI31:
 249              	.LBB2:
 250              		.loc 4 19 0
  18:ks8695px.cpp  **** {
  19:ks8695px.cpp  **** 	const uint32_t Timer_0_Enable	= (1 << 0);
 251              		str	r3, [fp, #-16]
 252 0044 0130A0E3 		.loc 4 21 0
 253 0048 10300BE5 		mov	r0, #8
  20:ks8695px.cpp  **** 	
  21:ks8695px.cpp  **** 	regWrite(TIMERS::T0TC, 0x1FF);
 254              	r	r1, .L26
 255 004c 0800A0E3 		ldr	r3, .L26+4
 256 0050 4C109FE5 		mov	lr, pc
 257 0054 4C309FE5 		bx	r3
 258 0058 0FE0A0E1 		.loc 4 22 0
 259 005c 13FF2FE1 		mov	r0, #16
  22:ks8695px.cpp  **** 	regWrite(TIMERS::T0PD, 0);
 260              	1, #0
 261 0060 1000A0E3 		ldr	r3, .L26+4
 262 0064 0010A0E3 		mov	lr, pc
 263 0068 38309FE5 		bx	r3
 264 006c 0FE0A0E1 		.loc 4 23 0
 265 0070 13FF2FE1 		mov	r0, #0
  23:ks8695px.cpp  **** 	regWrite(TIMERS::TMCON, (regRead(TIMERS::TMCON) |  Timer_0_Enable));
 266              	3, .L26+8
 267 0074 0000A0E3 		mov	lr, pc
 268 0078 2C309FE5 		bx	r3
 269 007c 0FE0A0E1 		mov	r3, r0
 270 0080 13FF2FE1 		orr	r3, r3, #1
 271 0084 0030A0E1 		mov	r0, #0
 272 0088 013083E3 		mov	r1, r3
 273 008c 0000A0E3 		ldr	r3, .L26+4
 274 0090 0310A0E1 		mov	lr, pc
 275 0094 0C309FE5 		bx	r3
 276 0098 0FE0A0E1 	.L24:
 277 009c 13FF2FE1 		.loc 4 25 0
 278              		b	.L24
  24:ks8695px.cpp  **** 	// Wait until watchdog resets CPU
  25:ks8695px.cpp  **** 	for (;;) ;
 279              		2
 280 00a0 FEFFFFEA 	.L26:
 281              		.word	511
 282              		.word	_ZN6TIMERS8regWriteENS_9RegistersEm
 283              		.word	_ZN6TIMERS7regReadENS_9RegistersE
 284 00a4 FF010000 	.LBE2:
 285 00a8 00000000 	.LFE14:
 287              		.align	2
 288              		.global	_ZN3CPU26setCoprocessorRegisterBitsEm
 290              	_ZN3CPU26setCoprocessorRegisterBitsEm:
 291              	.LFB26:
 292              		.loc 4 131 0
 293              		@ args = 0, pretend = 0, frame = 8
 294              		@ frame_needed = 1, uses_anonymous_args = 0
  26:ks8695px.cpp  **** }
  27:ks8695px.cpp  ****                   
  28:ks8695px.cpp  **** void CPU::InitializeChipSelectZero(uint32_t 	baseAddress, 
  29:ks8695px.cpp  **** 							       uint32_t 	size,
  30:ks8695px.cpp  **** 							  	   BUS_WIDTH  	width,
  31:ks8695px.cpp  ****                               	   CYCLES 		time_OE_or_WE_Asserted,
  32:ks8695px.cpp  **** 							  	   CYCLES 		addressHoldTimeAfter_CS_Negated, 
  33:ks8695px.cpp  **** 							       CYCLES 		addressSetupTimeBefore_CS_Asserted,
  34:ks8695px.cpp  **** 						           CYCLES 		addressSetupTimeBefore_OE_or_WE_Asserted)
  35:ks8695px.cpp  **** {
  36:ks8695px.cpp  **** 	bitWrite(EXTERNAL_IO::ERGCON, 	EXTERNAL_IO::BUS_WIDTH_FOR_EXTERNAL_BANK_0, width);
  37:ks8695px.cpp  **** 	bitWrite(EXTERNAL_IO::EXTACON0, EXTERNAL_IO::LAST_ADDRESS, ((baseAddress + size - 1) >> 16));
  38:ks8695px.cpp  **** 	bitWrite(EXTERNAL_IO::EXTACON0, EXTERNAL_IO::BASE_ADDRESS, (baseAddress >> 16));
  39:ks8695px.cpp  **** 	bitWrite(EXTERNAL_IO::EXTACON0, EXTERNAL_IO::TIME_OE_OR_WE_IS_ASSERTED, 
  40:ks8695px.cpp  **** 	           time_OE_or_WE_Asserted);
  41:ks8695px.cpp  **** 	bitWrite(EXTERNAL_IO::EXTACON0, EXTERNAL_IO::CS_HOLD_TIME_AFTER_OE_OR_WE, 
  42:ks8695px.cpp  **** 	           addressHoldTimeAfter_CS_Negated);
  43:ks8695px.cpp  **** 	bitWrite(EXTERNAL_IO::EXTACON0, EXTERNAL_IO::ADDRESS_SETUP_TIME_BEFORE_CS, 
  44:ks8695px.cpp  **** 	           addressSetupTimeBefore_CS_Asserted );
  45:ks8695px.cpp  **** 	bitWrite(EXTERNAL_IO::EXTACON0, EXTERNAL_IO::CS_SETUP_TIME_BEFORE_OE_OR_WE, 
  46:ks8695px.cpp  **** 	           addressSetupTimeBefore_OE_or_WE_Asserted );
  47:ks8695px.cpp  **** }
  48:ks8695px.cpp  **** 
  49:ks8695px.cpp  **** void CPU::InitializeChipSelectOne(uint32_t 		baseAddress, 
  50:ks8695px.cpp  **** 							      uint32_t 		size,
  51:ks8695px.cpp  **** 							  	  BUS_WIDTH  	width,
  52:ks8695px.cpp  ****                               	  CYCLES 		time_OE_or_WE_Asserted,
  53:ks8695px.cpp  **** 							  	  CYCLES 		addressHoldTimeAfter_CS_Negated, 
  54:ks8695px.cpp  **** 							      CYCLES 		addressSetupTimeBefore_CS_Asserted,
  55:ks8695px.cpp  **** 						          CYCLES 		addressSetupTimeBefore_OE_or_WE_Asserted)
  56:ks8695px.cpp  **** {
  57:ks8695px.cpp  **** 	bitWrite(EXTERNAL_IO::ERGCON,   EXTERNAL_IO::BUS_WIDTH_FOR_EXTERNAL_BANK_1, width);
  58:ks8695px.cpp  **** 	bitWrite(EXTERNAL_IO::EXTACON1, EXTERNAL_IO::LAST_ADDRESS, ((baseAddress + size - 1) >> 16));
  59:ks8695px.cpp  **** 	bitWrite(EXTERNAL_IO::EXTACON1, EXTERNAL_IO::BASE_ADDRESS, (baseAddress >> 16));
  60:ks8695px.cpp  **** 	bitWrite(EXTERNAL_IO::EXTACON1, EXTERNAL_IO::TIME_OE_OR_WE_IS_ASSERTED, 
  61:ks8695px.cpp  **** 	           time_OE_or_WE_Asserted);
  62:ks8695px.cpp  **** 	bitWrite(EXTERNAL_IO::EXTACON1, EXTERNAL_IO::CS_HOLD_TIME_AFTER_OE_OR_WE, 
  63:ks8695px.cpp  **** 	           addressHoldTimeAfter_CS_Negated);
  64:ks8695px.cpp  **** 	bitWrite(EXTERNAL_IO::EXTACON1, EXTERNAL_IO::ADDRESS_SETUP_TIME_BEFORE_CS, 
  65:ks8695px.cpp  **** 	           addressSetupTimeBefore_CS_Asserted );
  66:ks8695px.cpp  **** 	bitWrite(EXTERNAL_IO::EXTACON1, EXTERNAL_IO::CS_SETUP_TIME_BEFORE_OE_OR_WE, 
  67:ks8695px.cpp  **** 	           addressSetupTimeBefore_OE_or_WE_Asserted );
  68:ks8695px.cpp  **** }
  69:ks8695px.cpp  **** 
  70:ks8695px.cpp  **** void CPU::InitializeChipSelectTwo(uint32_t 		baseAddress, 
  71:ks8695px.cpp  **** 							      uint32_t 		size,
  72:ks8695px.cpp  **** 							  	  BUS_WIDTH  	width,
  73:ks8695px.cpp  ****                               	  CYCLES 		time_OE_or_WE_Asserted,
  74:ks8695px.cpp  **** 							  	  CYCLES 		addressHoldTimeAfter_CS_Negated, 
  75:ks8695px.cpp  **** 							      CYCLES 		addressSetupTimeBefore_CS_Asserted,
  76:ks8695px.cpp  **** 						          CYCLES 		addressSetupTimeBefore_OE_or_WE_Asserted)
  77:ks8695px.cpp  **** {
  78:ks8695px.cpp  **** 	bitWrite(EXTERNAL_IO::ERGCON, 	EXTERNAL_IO::BUS_WIDTH_FOR_EXTERNAL_BANK_2, width);
  79:ks8695px.cpp  **** 	bitWrite(EXTERNAL_IO::EXTACON2, EXTERNAL_IO::LAST_ADDRESS, ((baseAddress + size - 1) >> 16));
  80:ks8695px.cpp  **** 	bitWrite(EXTERNAL_IO::EXTACON2, EXTERNAL_IO::BASE_ADDRESS,  (baseAddress >> 16));
  81:ks8695px.cpp  **** 	bitWrite(EXTERNAL_IO::EXTACON2, EXTERNAL_IO::TIME_OE_OR_WE_IS_ASSERTED, 
  82:ks8695px.cpp  **** 	           time_OE_or_WE_Asserted);
  83:ks8695px.cpp  **** 	bitWrite(EXTERNAL_IO::EXTACON2, EXTERNAL_IO::CS_HOLD_TIME_AFTER_OE_OR_WE, 
  84:ks8695px.cpp  **** 	           addressHoldTimeAfter_CS_Negated);
  85:ks8695px.cpp  **** 	bitWrite(EXTERNAL_IO::EXTACON2, EXTERNAL_IO::ADDRESS_SETUP_TIME_BEFORE_CS, 
  86:ks8695px.cpp  **** 	           addressSetupTimeBefore_CS_Asserted );
  87:ks8695px.cpp  **** 	bitWrite(EXTERNAL_IO::EXTACON2, EXTERNAL_IO::CS_SETUP_TIME_BEFORE_OE_OR_WE, 
  88:ks8695px.cpp  **** 	           addressSetupTimeBefore_OE_or_WE_Asserted );
  89:ks8695px.cpp  **** }
  90:ks8695px.cpp  **** 
  91:ks8695px.cpp  **** void CPU::EnableMMU(void)
  92:ks8695px.cpp  **** {
  93:ks8695px.cpp  **** 	setCoprocessorRegisterBits(MMU_Mask);
  94:ks8695px.cpp  **** }
  95:ks8695px.cpp  **** 
  96:ks8695px.cpp  **** void CPU::EnableICache(void)
  97:ks8695px.cpp  **** {
  98:ks8695px.cpp  **** 	setCoprocessorRegisterBits(ICacheMask);
  99:ks8695px.cpp  **** }
 100:ks8695px.cpp  **** 
 101:ks8695px.cpp  **** void CPU::EnableDCache(void)
 102:ks8695px.cpp  **** {
 103:ks8695px.cpp  **** 	setCoprocessorRegisterBits(DCacheMask);
 104:ks8695px.cpp  **** }
 105:ks8695px.cpp  **** 
 106:ks8695px.cpp  **** void CPU::EnableFastContextSwitch(void)
 107:ks8695px.cpp  **** {
 108:ks8695px.cpp  **** 	setCoprocessorRegisterBits(FCSEMask);
 109:ks8695px.cpp  **** }
 110:ks8695px.cpp  **** 
 111:ks8695px.cpp  **** void CPU::DisableMMU(void)
 112:ks8695px.cpp  **** {
 113:ks8695px.cpp  **** 	clearCoprocessorRegisterBits(MMU_Mask);
 114:ks8695px.cpp  **** }
 115:ks8695px.cpp  **** 
 116:ks8695px.cpp  **** void CPU::DisableICache(void)
 117:ks8695px.cpp  **** {
 118:ks8695px.cpp  **** 	clearCoprocessorRegisterBits(ICacheMask);
 119:ks8695px.cpp  **** }
 120:ks8695px.cpp  **** 
 121:ks8695px.cpp  **** void CPU::DisableDCache(void)
 122:ks8695px.cpp  **** {
 123:ks8695px.cpp  **** 	clearCoprocessorRegisterBits(DCacheMask);
 124:ks8695px.cpp  **** }
 125:ks8695px.cpp  **** 
 126:ks8695px.cpp  **** void CPU::DisableFastContextSwitch(void)
 127:ks8695px.cpp  **** {
 128:ks8695px.cpp  **** 	clearCoprocessorRegisterBits(FCSEMask);
 129:ks8695px.cpp  **** }
 130:ks8695px.cpp  **** 
 131:ks8695px.cpp  **** void CPU::setCoprocessorRegisterBits(uint32_t mask)
 295              	I32:
 296              		stmfd	sp!, {fp, ip, lr, pc}
 297              	.LCFI33:
 298 00b0 0DC0A0E1 		sub	fp, ip, #4
 299              	.LCFI34:
 300 00b4 00D82DE9 		sub	sp, sp, #8
 301              	.LCFI35:
 302 00b8 04B04CE2 		str	r0, [fp, #-20]
 303              	.LBB3:
 304 00bc 08D04DE2 		.loc 4 136 0
 305              		  MRC      p15, 0, r0, c1, c0 ,0
 306 00c0 14000BE5 		str	r3, [fp, #-16]
 307              		.loc 4 138 0
 132:ks8695px.cpp  **** {	
 133:ks8695px.cpp  **** 	uint32_t c1format;
 134:ks8695px.cpp  ****    	asm volatile ("  MRC      p15, 0, r0, c1, c0 ,0"
 135:ks8695px.cpp  ****    	              : "=r"(c1format)
 136:ks8695px.cpp  ****    	              );
 308              	 #-16]
 309 00c4 100F11EE 		ldr	r3, [fp, #-20]
 310 00c8 10300BE5 		orr	r3, r2, r3
 137:ks8695px.cpp  ****    	              
 138:ks8695px.cpp  ****    	c1format = c1format | mask;
 311              	r	r3, [fp, #-16]
 312 00cc 10201BE5 		.loc 4 143 0
 313 00d0 14301BE5 		ldr	r3, [fp, #-16]
 314 00d4 033082E1 		  MCR      p15, 0, r0, c1, c0 ,0
 315 00d8 10300BE5 	.LBE3:
 139:ks8695px.cpp  ****    	
 140:ks8695px.cpp  **** 	asm volatile ("  MCR      p15, 0, r0, c1, c0 ,0"
 141:ks8695px.cpp  ****             	  :
 142:ks8695px.cpp  ****                   : "r" (c1format)
 143:ks8695px.cpp  ****                   );
 316              	 4 144 0
 317 00dc 10301BE5 		sub	sp, fp, #12
 318 00e0 100F01EE 		ldmfd	sp, {fp, sp, pc}
 319              	.LFE26:
 144:ks8695px.cpp  **** }
 320              	ze	_ZN3CPU26setCoprocessorRegisterBitsEm, .-_ZN3CPU26setCoprocessorRegisterBitsEm
 321 00e4 0CD04BE2 		.align	2
 322 00e8 00A89DE8 		.global	_ZN3CPU23EnableFastContextSwitchEv
 324              	_ZN3CPU23EnableFastContextSwitchEv:
 325              	.LFB21:
 326              		.loc 4 106 0
 327              		@ args = 0, pretend = 0, frame = 0
 328              		@ frame_needed = 1, uses_anonymous_args = 0
 329              		mov	ip, sp
 330              	.LCFI36:
 331              		stmfd	sp!, {fp, ip, lr, pc}
 332              	.LCFI37:
 333 00ec 0DC0A0E1 		sub	fp, ip, #4
 334              	.LCFI38:
 335 00f0 00D82DE9 		.loc 4 108 0
 336              		mov	r0, #-1073741824
 337 00f4 04B04CE2 		bl	_ZN3CPU26setCoprocessorRegisterBitsEm
 338              		.loc 4 109 0
 339              		ldmfd	sp, {fp, sp, pc}
 340 00f8 0301A0E3 	.LFE21:
 342              		.align	2
 343 0100 00A89DE8 		.global	_ZN3CPU12EnableDCacheEv
 345              	_ZN3CPU12EnableDCacheEv:
 346              	.LFB20:
 347              		.loc 4 101 0
 348              		@ args = 0, pretend = 0, frame = 0
 349              		@ frame_needed = 1, uses_anonymous_args = 0
 350              		mov	ip, sp
 351              	.LCFI39:
 352              		stmfd	sp!, {fp, ip, lr, pc}
 353              	.LCFI40:
 354 0104 0DC0A0E1 		sub	fp, ip, #4
 355              	.LCFI41:
 356 0108 00D82DE9 		.loc 4 103 0
 357              		mov	r0, #4
 358 010c 04B04CE2 		bl	_ZN3CPU26setCoprocessorRegisterBitsEm
 359              		.loc 4 104 0
 360              		ldmfd	sp, {fp, sp, pc}
 361 0110 0400A0E3 	.LFE20:
 363              		.align	2
 364 0118 00A89DE8 		.global	_ZN3CPU12EnableICacheEv
 366              	_ZN3CPU12EnableICacheEv:
 367              	.LFB19:
 368              		.loc 4 96 0
 369              		@ args = 0, pretend = 0, frame = 0
 370              		@ frame_needed = 1, uses_anonymous_args = 0
 371              		mov	ip, sp
 372              	.LCFI42:
 373              		stmfd	sp!, {fp, ip, lr, pc}
 374              	.LCFI43:
 375 011c 0DC0A0E1 		sub	fp, ip, #4
 376              	.LCFI44:
 377 0120 00D82DE9 		.loc 4 98 0
 378              		mov	r0, #4096
 379 0124 04B04CE2 		bl	_ZN3CPU26setCoprocessorRegisterBitsEm
 380              		.loc 4 99 0
 381              		ldmfd	sp, {fp, sp, pc}
 382 0128 010AA0E3 	.LFE19:
 384              		.align	2
 385 0130 00A89DE8 		.global	_ZN3CPU9EnableMMUEv
 387              	_ZN3CPU9EnableMMUEv:
 388              	.LFB18:
 389              		.loc 4 91 0
 390              		@ args = 0, pretend = 0, frame = 0
 391              		@ frame_needed = 1, uses_anonymous_args = 0
 392              		mov	ip, sp
 393              	.LCFI45:
 394              		stmfd	sp!, {fp, ip, lr, pc}
 395              	.LCFI46:
 396 0134 0DC0A0E1 		sub	fp, ip, #4
 397              	.LCFI47:
 398 0138 00D82DE9 		.loc 4 93 0
 399              		mov	r0, #1
 400 013c 04B04CE2 		bl	_ZN3CPU26setCoprocessorRegisterBitsEm
 401              		.loc 4 94 0
 402              		ldmfd	sp, {fp, sp, pc}
 403 0140 0100A0E3 	.LFE18:
 405              		.align	2
 406 0148 00A89DE8 		.global	_ZN3CPU28clearCoprocessorRegisterBitsEm
 408              	_ZN3CPU28clearCoprocessorRegisterBitsEm:
 409              	.LFB27:
 410              		.loc 4 146 0
 411              		@ args = 0, pretend = 0, frame = 8
 412              		@ frame_needed = 1, uses_anonymous_args = 0
 413              		mov	ip, sp
 145:ks8695px.cpp  **** 
 146:ks8695px.cpp  **** void CPU::clearCoprocessorRegisterBits(uint32_t mask)
 414              	1:
 415              		str	r0, [fp, #-20]
 416              	.LBB4:
 417 014c 0DC0A0E1 		.loc 4 151 0
 418              		  MRC      p15, 0, r0 , c1, c0 ,0
 419 0150 00D82DE9 		str	r3, [fp, #-16]
 420              		.loc 4 152 0
 421 0154 04B04CE2 		ldr	r3, [fp, #-20]
 422              		mvn	r2, r3
 423 0158 08D04DE2 		ldr	r3, [fp, #-16]
 424              		and	r3, r3, r2
 425 015c 14000BE5 		str	r3, [fp, #-16]
 426              		.loc 4 157 0
 147:ks8695px.cpp  **** {	
 148:ks8695px.cpp  **** 	uint32_t c1format;
 149:ks8695px.cpp  ****    	asm volatile ("  MRC      p15, 0, r0 , c1, c0 ,0"
 150:ks8695px.cpp  ****    	              : "=r"(c1format)
 151:ks8695px.cpp  ****    	              );
 427              	 #-16]
 428 0160 100F11EE 		  MCR      p15, 0, r0, c1, c0 ,0
 429 0164 10300BE5 	.LBE4:
 152:ks8695px.cpp  ****    	c1format = c1format & ~mask;
 430              	oc 4 158 0
 431 0168 14301BE5 		sub	sp, fp, #12
 432 016c 0320E0E1 		ldmfd	sp, {fp, sp, pc}
 433 0170 10301BE5 	.LFE27:
 435 0178 10300BE5 		.align	2
 153:ks8695px.cpp  ****    	
 154:ks8695px.cpp  **** 	asm volatile ("  MCR      p15, 0, r0, c1, c0 ,0"
 155:ks8695px.cpp  ****             	  :
 156:ks8695px.cpp  ****             	  : "r" (c1format)
 157:ks8695px.cpp  ****             	  );
 436              	al	_ZN3CPU24DisableFastContextSwitchEv
 438 0180 100F01EE 	_ZN3CPU24DisableFastContextSwitchEv:
 439              	.LFB25:
 158:ks8695px.cpp  **** }
 440              	c 4 126 0
 441 0184 0CD04BE2 		@ args = 0, pretend = 0, frame = 0
 442 0188 00A89DE8 		@ frame_needed = 1, uses_anonymous_args = 0
 443              		mov	ip, sp
 444              	.LCFI52:
 445              		stmfd	sp!, {fp, ip, lr, pc}
 446              	.LCFI53:
 447              		sub	fp, ip, #4
 448              	.LCFI54:
 449              		.loc 4 128 0
 450              		mov	r0, #-1073741824
 451              		bl	_ZN3CPU28clearCoprocessorRegisterBitsEm
 452              		.loc 4 129 0
 453 018c 0DC0A0E1 		ldmfd	sp, {fp, sp, pc}
 454              	.LFE25:
 456              		.align	2
 457 0194 04B04CE2 		.global	_ZN3CPU13DisableDCacheEv
 459              	_ZN3CPU13DisableDCacheEv:
 460 0198 0301A0E3 	.LFB24:
 461 019c FEFFFFEB 		.loc 4 121 0
 462              		@ args = 0, pretend = 0, frame = 0
 463 01a0 00A89DE8 		@ frame_needed = 1, uses_anonymous_args = 0
 464              		mov	ip, sp
 465              	.LCFI55:
 466              		stmfd	sp!, {fp, ip, lr, pc}
 467              	.LCFI56:
 468              		sub	fp, ip, #4
 469              	.LCFI57:
 470              		.loc 4 123 0
 471              		mov	r0, #4
 472              		bl	_ZN3CPU28clearCoprocessorRegisterBitsEm
 473              		.loc 4 124 0
 474 01a4 0DC0A0E1 		ldmfd	sp, {fp, sp, pc}
 475              	.LFE24:
 477              		.align	2
 478 01ac 04B04CE2 		.global	_ZN3CPU13DisableICacheEv
 480              	_ZN3CPU13DisableICacheEv:
 481 01b0 0400A0E3 	.LFB23:
 482 01b4 FEFFFFEB 		.loc 4 116 0
 483              		@ args = 0, pretend = 0, frame = 0
 484 01b8 00A89DE8 		@ frame_needed = 1, uses_anonymous_args = 0
 485              		mov	ip, sp
 486              	.LCFI58:
 487              		stmfd	sp!, {fp, ip, lr, pc}
 488              	.LCFI59:
 489              		sub	fp, ip, #4
 490              	.LCFI60:
 491              		.loc 4 118 0
 492              		mov	r0, #4096
 493              		bl	_ZN3CPU28clearCoprocessorRegisterBitsEm
 494              		.loc 4 119 0
 495 01bc 0DC0A0E1 		ldmfd	sp, {fp, sp, pc}
 496              	.LFE23:
 498              		.align	2
 499 01c4 04B04CE2 		.global	_ZN3CPU10DisableMMUEv
 501              	_ZN3CPU10DisableMMUEv:
 502 01c8 010AA0E3 	.LFB22:
 503 01cc FEFFFFEB 		.loc 4 111 0
 504              		@ args = 0, pretend = 0, frame = 0
 505 01d0 00A89DE8 		@ frame_needed = 1, uses_anonymous_args = 0
 506              		mov	ip, sp
 507              	.LCFI61:
 508              		stmfd	sp!, {fp, ip, lr, pc}
 509              	.LCFI62:
 510              		sub	fp, ip, #4
 511              	.LCFI63:
 512              		.loc 4 113 0
 513              		mov	r0, #1
 514              		bl	_ZN3CPU28clearCoprocessorRegisterBitsEm
 515              		.loc 4 114 0
 516 01d4 0DC0A0E1 		ldmfd	sp, {fp, sp, pc}
 517              	.LFE22:
 519              		.section	.text._Z8bitWriteIN11EXTERNAL_IO9RegistersEEvT_mm,"axG",%progbits,_Z8bitWriteIN11EXTERNAL
 520 01dc 04B04CE2 		.align	2
 521              		.weak	_Z8bitWriteIN11EXTERNAL_IO9RegistersEEvT_mm
 523 01e0 0100A0E3 	_Z8bitWriteIN11EXTERNAL_IO9RegistersEEvT_mm:
 524 01e4 FEFFFFEB 	.LFB28:
 525              		.file 5 "register_bitops.h"
 526 01e8 00A89DE8 		.loc 5 20 0
 527              		@ args = 0, pretend = 0, frame = 24
 528              		@ frame_needed = 1, uses_anonymous_args = 0
 529              		mov	ip, sp
 530              	.LCFI64:
 531              		stmfd	sp!, {fp, ip, lr, pc}
 532              	.LCFI65:
 533              		sub	fp, ip, #4
 534              	.LCFI66:
 535              		sub	sp, sp, #24
   1:register_bitops.h **** #ifndef __REGISTER_BITOPS_H__
   2:register_bitops.h **** #define __REGISTER_BITOPS_H__
   3:register_bitops.h **** 
   4:register_bitops.h **** #include <stdlib.h>
   5:register_bitops.h **** 
   6:register_bitops.h **** #define REGISTER_BIT_DEFINITION(end, start) ((start << 16) | (end - start + 1))
   7:register_bitops.h **** 
   8:register_bitops.h **** template <typename RegType>
   9:register_bitops.h **** uint32_t bitRead(RegType reg, uint32_t bits)
  10:register_bitops.h **** {
  11:register_bitops.h **** 	uint32_t regval = *regAddress(reg);
  12:register_bitops.h **** 	const uint32_t width = bits & 0xff;
  13:register_bitops.h **** 	const uint32_t bitno = bits >> 16;
  14:register_bitops.h **** 	regval >>= bitno;
  15:register_bitops.h **** 	regval &= ((1 << width) - 1);
  16:register_bitops.h **** 	return regval;
  17:register_bitops.h **** }
  18:register_bitops.h **** 
  19:register_bitops.h **** template <typename RegType>
  20:register_bitops.h **** void bitWrite(RegType reg, uint32_t bits, uint32_t value)
 536              	, [fp, #-28]
 537              		ldr	r3, .L50
 538              		mov	lr, pc
 539 0000 0DC0A0E1 		bx	r3
 540              		mov	r3, r0
 541 0004 00D82DE9 		ldr	r3, [r3, #0]
 542              		str	r3, [fp, #-24]
 543 0008 04B04CE2 		.loc 5 23 0
 544              		ldr	r3, [fp, #-32]
 545 000c 18D04DE2 		and	r3, r3, #255
 546              		str	r3, [fp, #-20]
 547 0010 1C000BE5 		.loc 5 24 0
 548 0014 20100BE5 		ldr	r3, [fp, #-32]
 549 0018 24200BE5 		mov	r3, r3, lsr #16
 550              		str	r3, [fp, #-16]
  21:register_bitops.h **** {
  22:register_bitops.h **** 	uint32_t regval = *regAddress(reg);
 551              	dr	r2, [fp, #-20]
 552 001c 1C001BE5 		mov	r3, #1
 553 0020 90309FE5 		mov	r3, r3, asl r2
 554 0024 0FE0A0E1 		sub	r2, r3, #1
 555 0028 13FF2FE1 		ldr	r3, [fp, #-16]
 556 002c 0030A0E1 		mov	r3, r2, asl r3
 557 0030 003093E5 		mvn	r3, r3
 558 0034 18300BE5 		mov	r2, r3
  23:register_bitops.h **** 	const uint32_t width = bits & 0xff;
 559              	 [fp, #-24]
 560 0038 20301BE5 		and	r3, r3, r2
 561 003c FF3003E2 		str	r3, [fp, #-24]
 562 0040 14300BE5 		.loc 5 26 0
  24:register_bitops.h **** 	const uint32_t bitno = bits >> 16;
 563              		r2, [fp, #-16]
 564 0044 20301BE5 		ldr	r3, [fp, #-36]
 565 0048 2338A0E1 		mov	r2, r3, asl r2
 566 004c 10300BE5 		ldr	r3, [fp, #-24]
  25:register_bitops.h **** 	regval &= ~(((1 << width) - 1) << bitno);
 567              		r3, r3, r2
 568 0050 14201BE5 		str	r3, [fp, #-24]
 569 0054 0130A0E3 		.loc 5 27 0
 570 0058 1332A0E1 		ldr	r0, [fp, #-28]
 571 005c 012043E2 		ldr	r3, .L50
 572 0060 10301BE5 		mov	lr, pc
 573 0064 1233A0E1 		bx	r3
 574 0068 0330E0E1 		mov	r2, r0
 575 006c 0320A0E1 		ldr	r3, [fp, #-24]
 576 0070 18301BE5 		str	r3, [r2, #0]
 577 0074 023003E0 	.LBE5:
 578 0078 18300BE5 		sub	sp, fp, #12
  26:register_bitops.h **** 	regval |= value << bitno;
 579              	fp, sp, pc}
 580 007c 10201BE5 	.L51:
 581 0080 24301BE5 		.align	2
 582 0084 1322A0E1 	.L50:
 583 0088 18301BE5 		.word	_ZN11EXTERNAL_IO10regAddressENS_9RegistersE
 584 008c 023083E1 	.LFE28:
  27:register_bitops.h **** 	*regAddress(reg) = regval;
 586              		.align	2
 587 0094 1C001BE5 		.global	_ZN3CPU23InitializeChipSelectTwoEmm9BUS_WIDTH6CYCLESS1_S1_S1_
 589 009c 0FE0A0E1 	_ZN3CPU23InitializeChipSelectTwoEmm9BUS_WIDTH6CYCLESS1_S1_S1_:
 590 00a0 13FF2FE1 	.LFB17:
 591 00a4 0020A0E1 		.loc 4 76 0
 592 00a8 18301BE5 		@ args = 12, pretend = 0, frame = 16
 593 00ac 003082E5 		@ frame_needed = 1, uses_anonymous_args = 0
 594              		mov	ip, sp
 595 00b0 0CD04BE2 	.LCFI68:
 596 00b4 00A89DE8 		stmfd	sp!, {fp, ip, lr, pc}
 597              	.LCFI69:
 598              		sub	fp, ip, #4
 599              	.LCFI70:
 600 00b8 00000000 		sub	sp, sp, #16
 601              	.LCFI71:
 602              		str	r0, [fp, #-16]
 603              		str	r1, [fp, #-20]
 604              		str	r2, [fp, #-24]
 605              		str	r3, [fp, #-28]
 606              		.loc 4 78 0
 607              		ldr	r3, [fp, #-24]
 608              		mov	r0, #32
 609              		ldr	r1, .L54
 610              		mov	r2, r3
 611              		ldr	r3, .L54+4
 612 01ec 0DC0A0E1 		mov	lr, pc
 613              		bx	r3
 614 01f0 00D82DE9 		.loc 4 79 0
 615              		ldr	r2, [fp, #-16]
 616 01f4 04B04CE2 		ldr	r3, [fp, #-20]
 617              		add	r3, r2, r3
 618 01f8 10D04DE2 		sub	r3, r3, #1
 619              		mov	r3, r3, lsr #16
 620 01fc 10000BE5 		mov	r0, #8
 621 0200 14100BE5 		ldr	r1, .L54+8
 622 0204 18200BE5 		mov	r2, r3
 623 0208 1C300BE5 		ldr	r3, .L54+4
 624              		mov	lr, pc
 625 020c 18301BE5 		bx	r3
 626 0210 2000A0E3 		.loc 4 80 0
 627 0214 D0109FE5 		ldr	r3, [fp, #-16]
 628 0218 0320A0E1 		mov	r3, r3, lsr #16
 629 021c CC309FE5 		mov	r0, #8
 630 0220 0FE0A0E1 		ldr	r1, .L54+12
 631 0224 13FF2FE1 		mov	r2, r3
 632              		ldr	r3, .L54+4
 633 0228 10201BE5 		mov	lr, pc
 634 022c 14301BE5 		bx	r3
 635 0230 033082E0 		.loc 4 82 0
 636 0234 013043E2 		ldr	r3, [fp, #-28]
 637 0238 2338A0E1 		mov	r0, #8
 638 023c 0800A0E3 		ldr	r1, .L54+16
 639 0240 AC109FE5 		mov	r2, r3
 640 0244 0320A0E1 		ldr	r3, .L54+4
 641 0248 A0309FE5 		mov	lr, pc
 642 024c 0FE0A0E1 		bx	r3
 643 0250 13FF2FE1 		.loc 4 84 0
 644              		ldr	r3, [fp, #4]
 645 0254 10301BE5 		mov	r0, #8
 646 0258 2338A0E1 		ldr	r1, .L54+20
 647 025c 0800A0E3 		mov	r2, r3
 648 0260 90109FE5 		ldr	r3, .L54+4
 649 0264 0320A0E1 		mov	lr, pc
 650 0268 80309FE5 		bx	r3
 651 026c 0FE0A0E1 		.loc 4 86 0
 652 0270 13FF2FE1 		ldr	r3, [fp, #8]
 653              		mov	r0, #8
 654 0274 1C301BE5 		ldr	r1, .L54+24
 655 0278 0800A0E3 		mov	r2, r3
 656 027c 78109FE5 		ldr	r3, .L54+4
 657 0280 0320A0E1 		mov	lr, pc
 658 0284 64309FE5 		bx	r3
 659 0288 0FE0A0E1 		.loc 4 88 0
 660 028c 13FF2FE1 		ldr	r3, [fp, #12]
 661              		mov	r0, #8
 662 0290 04309BE5 		mov	r1, #3
 663 0294 0800A0E3 		mov	r2, r3
 664 0298 60109FE5 		ldr	r3, .L54+4
 665 029c 0320A0E1 		mov	lr, pc
 666 02a0 48309FE5 		bx	r3
 667 02a4 0FE0A0E1 		.loc 4 89 0
 668 02a8 13FF2FE1 		sub	sp, fp, #12
 669              		ldmfd	sp, {fp, sp, pc}
 670 02ac 08309BE5 	.L55:
 671 02b0 0800A0E3 		.align	2
 672 02b4 48109FE5 	.L54:
 673 02b8 0320A0E1 		.word	1310722
 674 02bc 2C309FE5 		.word	_Z8bitWriteIN11EXTERNAL_IO9RegistersEEvT_mm
 675 02c0 0FE0A0E1 		.word	1441802
 676 02c4 13FF2FE1 		.word	786442
 677              		.word	589827
 678 02c8 0C309BE5 		.word	393219
 679 02cc 0800A0E3 		.word	196611
 680 02d0 0310A0E3 	.LFE17:
 682 02d8 10309FE5 		.align	2
 683 02dc 0FE0A0E1 		.global	_ZN3CPU23InitializeChipSelectOneEmm9BUS_WIDTH6CYCLESS1_S1_S1_
 685              	_ZN3CPU23InitializeChipSelectOneEmm9BUS_WIDTH6CYCLESS1_S1_S1_:
 686 02e4 0CD04BE2 	.LFB16:
 687 02e8 00A89DE8 		.loc 4 55 0
 688              		@ args = 12, pretend = 0, frame = 16
 689              		@ frame_needed = 1, uses_anonymous_args = 0
 690              		mov	ip, sp
 691 02ec 02001400 	.LCFI72:
 692 02f0 00000000 		stmfd	sp!, {fp, ip, lr, pc}
 693 02f4 0A001600 	.LCFI73:
 694 02f8 0A000C00 		sub	fp, ip, #4
 695 02fc 03000900 	.LCFI74:
 696 0300 03000600 		sub	sp, sp, #16
 697 0304 03000300 	.LCFI75:
 698              		str	r0, [fp, #-16]
 699              		str	r1, [fp, #-20]
 700              		str	r2, [fp, #-24]
 701              		str	r3, [fp, #-28]
 702              		.loc 4 57 0
 703              		ldr	r3, [fp, #-24]
 704              		mov	r0, #32
 705              		ldr	r1, .L58
 706              		mov	r2, r3
 707              		ldr	r3, .L58+4
 708 0308 0DC0A0E1 		mov	lr, pc
 709              		bx	r3
 710 030c 00D82DE9 		.loc 4 58 0
 711              		ldr	r2, [fp, #-16]
 712 0310 04B04CE2 		ldr	r3, [fp, #-20]
 713              		add	r3, r2, r3
 714 0314 10D04DE2 		sub	r3, r3, #1
 715              		mov	r3, r3, lsr #16
 716 0318 10000BE5 		mov	r0, #4
 717 031c 14100BE5 		ldr	r1, .L58+8
 718 0320 18200BE5 		mov	r2, r3
 719 0324 1C300BE5 		ldr	r3, .L58+4
 720              		mov	lr, pc
 721 0328 18301BE5 		bx	r3
 722 032c 2000A0E3 		.loc 4 59 0
 723 0330 D0109FE5 		ldr	r3, [fp, #-16]
 724 0334 0320A0E1 		mov	r3, r3, lsr #16
 725 0338 CC309FE5 		mov	r0, #4
 726 033c 0FE0A0E1 		ldr	r1, .L58+12
 727 0340 13FF2FE1 		mov	r2, r3
 728              		ldr	r3, .L58+4
 729 0344 10201BE5 		mov	lr, pc
 730 0348 14301BE5 		bx	r3
 731 034c 033082E0 		.loc 4 61 0
 732 0350 013043E2 		ldr	r3, [fp, #-28]
 733 0354 2338A0E1 		mov	r0, #4
 734 0358 0400A0E3 		ldr	r1, .L58+16
 735 035c AC109FE5 		mov	r2, r3
 736 0360 0320A0E1 		ldr	r3, .L58+4
 737 0364 A0309FE5 		mov	lr, pc
 738 0368 0FE0A0E1 		bx	r3
 739 036c 13FF2FE1 		.loc 4 63 0
 740              		ldr	r3, [fp, #4]
 741 0370 10301BE5 		mov	r0, #4
 742 0374 2338A0E1 		ldr	r1, .L58+20
 743 0378 0400A0E3 		mov	r2, r3
 744 037c 90109FE5 		ldr	r3, .L58+4
 745 0380 0320A0E1 		mov	lr, pc
 746 0384 80309FE5 		bx	r3
 747 0388 0FE0A0E1 		.loc 4 65 0
 748 038c 13FF2FE1 		ldr	r3, [fp, #8]
 749              		mov	r0, #4
 750 0390 1C301BE5 		ldr	r1, .L58+24
 751 0394 0400A0E3 		mov	r2, r3
 752 0398 78109FE5 		ldr	r3, .L58+4
 753 039c 0320A0E1 		mov	lr, pc
 754 03a0 64309FE5 		bx	r3
 755 03a4 0FE0A0E1 		.loc 4 67 0
 756 03a8 13FF2FE1 		ldr	r3, [fp, #12]
 757              		mov	r0, #4
 758 03ac 04309BE5 		mov	r1, #3
 759 03b0 0400A0E3 		mov	r2, r3
 760 03b4 60109FE5 		ldr	r3, .L58+4
 761 03b8 0320A0E1 		mov	lr, pc
 762 03bc 48309FE5 		bx	r3
 763 03c0 0FE0A0E1 		.loc 4 68 0
 764 03c4 13FF2FE1 		sub	sp, fp, #12
 765              		ldmfd	sp, {fp, sp, pc}
 766 03c8 08309BE5 	.L59:
 767 03cc 0400A0E3 		.align	2
 768 03d0 48109FE5 	.L58:
 769 03d4 0320A0E1 		.word	1179650
 770 03d8 2C309FE5 		.word	_Z8bitWriteIN11EXTERNAL_IO9RegistersEEvT_mm
 771 03dc 0FE0A0E1 		.word	1441802
 772 03e0 13FF2FE1 		.word	786442
 773              		.word	589827
 774 03e4 0C309BE5 		.word	393219
 775 03e8 0400A0E3 		.word	196611
 776 03ec 0310A0E3 	.LFE16:
 778 03f4 10309FE5 		.align	2
 779 03f8 0FE0A0E1 		.global	_ZN3CPU24InitializeChipSelectZeroEmm9BUS_WIDTH6CYCLESS1_S1_S1_
 781              	_ZN3CPU24InitializeChipSelectZeroEmm9BUS_WIDTH6CYCLESS1_S1_S1_:
 782 0400 0CD04BE2 	.LFB15:
 783 0404 00A89DE8 		.loc 4 34 0
 784              		@ args = 12, pretend = 0, frame = 16
 785              		@ frame_needed = 1, uses_anonymous_args = 0
 786              		mov	ip, sp
 787 0408 02001200 	.LCFI76:
 788 040c 00000000 		stmfd	sp!, {fp, ip, lr, pc}
 789 0410 0A001600 	.LCFI77:
 790 0414 0A000C00 		sub	fp, ip, #4
 791 0418 03000900 	.LCFI78:
 792 041c 03000600 		sub	sp, sp, #16
 793 0420 03000300 	.LCFI79:
 794              		str	r0, [fp, #-16]
 795              		str	r1, [fp, #-20]
 796              		str	r2, [fp, #-24]
 797              		str	r3, [fp, #-28]
 798              		.loc 4 36 0
 799              		ldr	r3, [fp, #-24]
 800              		mov	r0, #32
 801              		ldr	r1, .L62
 802              		mov	r2, r3
 803              		ldr	r3, .L62+4
 804 0424 0DC0A0E1 		mov	lr, pc
 805              		bx	r3
 806 0428 00D82DE9 		.loc 4 37 0
 807              		ldr	r2, [fp, #-16]
 808 042c 04B04CE2 		ldr	r3, [fp, #-20]
 809              		add	r3, r2, r3
 810 0430 10D04DE2 		sub	r3, r3, #1
 811              		mov	r3, r3, lsr #16
 812 0434 10000BE5 		mov	r0, #0
 813 0438 14100BE5 		ldr	r1, .L62+8
 814 043c 18200BE5 		mov	r2, r3
 815 0440 1C300BE5 		ldr	r3, .L62+4
 816              		mov	lr, pc
 817 0444 18301BE5 		bx	r3
 818 0448 2000A0E3 		.loc 4 38 0
 819 044c D0109FE5 		ldr	r3, [fp, #-16]
 820 0450 0320A0E1 		mov	r3, r3, lsr #16
 821 0454 CC309FE5 		mov	r0, #0
 822 0458 0FE0A0E1 		ldr	r1, .L62+12
 823 045c 13FF2FE1 		mov	r2, r3
 824              		ldr	r3, .L62+4
 825 0460 10201BE5 		mov	lr, pc
 826 0464 14301BE5 		bx	r3
 827 0468 033082E0 		.loc 4 40 0
 828 046c 013043E2 		ldr	r3, [fp, #-28]
 829 0470 2338A0E1 		mov	r0, #0
 830 0474 0000A0E3 		ldr	r1, .L62+16
 831 0478 AC109FE5 		mov	r2, r3
 832 047c 0320A0E1 		ldr	r3, .L62+4
 833 0480 A0309FE5 		mov	lr, pc
 834 0484 0FE0A0E1 		bx	r3
 835 0488 13FF2FE1 		.loc 4 42 0
 836              		ldr	r3, [fp, #4]
 837 048c 10301BE5 		mov	r0, #0
 838 0490 2338A0E1 		ldr	r1, .L62+20
 839 0494 0000A0E3 		mov	r2, r3
 840 0498 90109FE5 		ldr	r3, .L62+4
 841 049c 0320A0E1 		mov	lr, pc
 842 04a0 80309FE5 		bx	r3
 843 04a4 0FE0A0E1 		.loc 4 44 0
 844 04a8 13FF2FE1 		ldr	r3, [fp, #8]
 845              		mov	r0, #0
 846 04ac 1C301BE5 		ldr	r1, .L62+24
 847 04b0 0000A0E3 		mov	r2, r3
 848 04b4 78109FE5 		ldr	r3, .L62+4
 849 04b8 0320A0E1 		mov	lr, pc
 850 04bc 64309FE5 		bx	r3
 851 04c0 0FE0A0E1 		.loc 4 46 0
 852 04c4 13FF2FE1 		ldr	r3, [fp, #12]
 853              		mov	r0, #0
 854 04c8 04309BE5 		mov	r1, #3
 855 04cc 0000A0E3 		mov	r2, r3
 856 04d0 60109FE5 		ldr	r3, .L62+4
 857 04d4 0320A0E1 		mov	lr, pc
 858 04d8 48309FE5 		bx	r3
 859 04dc 0FE0A0E1 		.loc 4 47 0
 860 04e0 13FF2FE1 		sub	sp, fp, #12
 861              		ldmfd	sp, {fp, sp, pc}
 862 04e4 08309BE5 	.L63:
 863 04e8 0000A0E3 		.align	2
 864 04ec 48109FE5 	.L62:
 865 04f0 0320A0E1 		.word	1048578
 866 04f4 2C309FE5 		.word	_Z8bitWriteIN11EXTERNAL_IO9RegistersEEvT_mm
 867 04f8 0FE0A0E1 		.word	1441802
 868 04fc 13FF2FE1 		.word	786442
 869              		.word	589827
 870 0500 0C309BE5 		.word	393219
 871 0504 0000A0E3 		.word	196611
 872 0508 0310A0E3 	.LFE15:
 874 0510 10309FE5 		.section	.debug_frame,"",%progbits
 875 0514 0FE0A0E1 	.Lframe0:
 876 0518 13FF2FE1 		.4byte	.LECIE0-.LSCIE0
 877              	.LSCIE0:
 878 051c 0CD04BE2 		.4byte	0xffffffff
 879 0520 00A89DE8 		.byte	0x1
 880              		.ascii	"\000"
 881              		.uleb128 0x1
 882              		.sleb128 -4
 883 0524 02001000 		.byte	0xe
 884 0528 00000000 		.byte	0xc
 885 052c 0A001600 		.uleb128 0xd
 886 0530 0A000C00 		.uleb128 0x0
 887 0534 03000900 		.align	2
 888 0538 03000600 	.LECIE0:
 889 053c 03000300 	.LSFDE0:
 890              		.4byte	.LEFDE0-.LASFDE0
 891              	.LASFDE0:
 1462              		.4byte	0x0
DEFINED SYMBOLS
                            *ABS*:00000000 ks8695px.cpp
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:14     .text._ZN11BUS_CONTROL10regAddressENS_9RegistersE:00000000 _ZN11BUS_CONTROL10regAddressENS_9RegistersE
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:20     .text._ZN11BUS_CONTROL10regAddressENS_9RegistersE:00000000 $a
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:42     .text._ZN11BUS_CONTROL8regWriteENS_9RegistersEm:00000000 _ZN11BUS_CONTROL8regWriteENS_9RegistersEm
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:47     .text._ZN11BUS_CONTROL8regWriteENS_9RegistersEm:00000000 $a
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:71     .text._ZN11BUS_CONTROL8regWriteENS_9RegistersEm:0000003c $d
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:78     .text._ZN11EXTERNAL_IO10regAddressENS_9RegistersE:00000000 _ZN11EXTERNAL_IO10regAddressENS_9RegistersE
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:84     .text._ZN11EXTERNAL_IO10regAddressENS_9RegistersE:00000000 $a
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:106    .text._ZN6TIMERS10regAddressENS_9RegistersE:00000000 _ZN6TIMERS10regAddressENS_9RegistersE
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:112    .text._ZN6TIMERS10regAddressENS_9RegistersE:00000000 $a
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:134    .text._ZN6TIMERS7regReadENS_9RegistersE:00000000 _ZN6TIMERS7regReadENS_9RegistersE
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:139    .text._ZN6TIMERS7regReadENS_9RegistersE:00000000 $a
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:161    .text._ZN6TIMERS7regReadENS_9RegistersE:00000034 $d
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:168    .text._ZN6TIMERS8regWriteENS_9RegistersEm:00000000 _ZN6TIMERS8regWriteENS_9RegistersEm
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:173    .text._ZN6TIMERS8regWriteENS_9RegistersEm:00000000 $a
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:197    .text._ZN6TIMERS8regWriteENS_9RegistersEm:0000003c $d
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:204    .text:00000000 _ZN3CPU19SetSystemClockSpeedE11CLOCK_SPEED
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:210    .text:00000000 $a
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:231    .text:00000030 $d
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:237    .text:00000034 _ZN3CPU5ResetEv
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:242    .text:00000034 $a
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:284    .text:000000a4 $d
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:293    .text:000000b0 _ZN3CPU26setCoprocessorRegisterBitsEm
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:298    .text:000000b0 $a
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:328    .text:000000ec _ZN3CPU23EnableFastContextSwitchEv
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:349    .text:00000104 _ZN3CPU12EnableDCacheEv
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:370    .text:0000011c _ZN3CPU12EnableICacheEv
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:391    .text:00000134 _ZN3CPU9EnableMMUEv
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:412    .text:0000014c _ZN3CPU28clearCoprocessorRegisterBitsEm
C:\DOCUME~1\RAWA~1.LAG\LOCALS~1\Temp/ccCUgaaa.s:448    .text:0000018c _ZN3CPU24DisableFastContextSwitchEv
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