test.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .text         00001628  00000000  00000000  00008000  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  1 .bss          001008d8  00001628  00001628  00009628  2**0
                  ALLOC
  2 .comment      0000007e  00000000  00000000  00009628  2**0
                  CONTENTS, READONLY
  3 .debug_aranges 00000210  00000000  00000000  000096a8  2**3
                  CONTENTS, READONLY, DEBUGGING
  4 .debug_pubnames 0000073d  00000000  00000000  000098b8  2**0
                  CONTENTS, READONLY, DEBUGGING
  5 .debug_info   00004d0d  00000000  00000000  00009ff5  2**0
                  CONTENTS, READONLY, DEBUGGING
  6 .debug_abbrev 00000ad8  00000000  00000000  0000ed02  2**0
                  CONTENTS, READONLY, DEBUGGING
  7 .debug_line   00000950  00000000  00000000  0000f7da  2**0
                  CONTENTS, READONLY, DEBUGGING
  8 .debug_frame  000009c0  00000000  00000000  0001012c  2**2
                  CONTENTS, READONLY, DEBUGGING
  9 .debug_str    000001f7  00000000  00000000  00010aec  2**0
                  CONTENTS, READONLY, DEBUGGING
 10 .debug_loc    00000bfa  00000000  00000000  00010ce3  2**0
                  CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:

00000000 <Vectors>:

// Runtime Interrupt Vectors
// -------------------------
Vectors:
        b     _start                    // reset - _start
       0:	ea000012 	b	50 <_start>
        ldr   pc, _undf
       4:	e59ff014 	ldr	pc, [pc, #20]	; 20 <_undf>
        ldr   pc, _swi
       8:	e59ff014 	ldr	pc, [pc, #20]	; 24 <_swi>
        ldr   pc, _pabt
       c:	e59ff014 	ldr	pc, [pc, #20]	; 28 <_pabt>
        ldr   pc, _dabt
      10:	e59ff014 	ldr	pc, [pc, #20]	; 2c <_dabt>
        nop    
      14:	e1a00000 	nop			(mov r0,r0)
        ldr   pc, _irq	 
      18:	e59ff010 	ldr	pc, [pc, #16]	; 30 <_irq>
        ldr   pc, _fiq
      1c:	e59ff010 	ldr	pc, [pc, #16]	; 34 <_fiq>

00000020 <_undf>:
      20:	00000038 	andeq	r0, r0, r8, lsr r0

00000024 <_swi>:
      24:	0000003c 	andeq	r0, r0, ip, lsr r0

00000028 <_pabt>:
      28:	00000040 	andeq	r0, r0, r0, asr #32

0000002c <_dabt>:
      2c:	00000044 	andeq	r0, r0, r4, asr #32

00000030 <_irq>:
      30:	0000004c 	andeq	r0, r0, ip, asr #32

00000034 <_fiq>:
      34:	00000048 	andeq	r0, r0, r8, asr #32

00000038 <__undf>:
        
// Use this group for development
_undf:  .word __undf                    // undefined
_swi:   .word __swi                     // SWI
_pabt:  .word __pabt                    // program abort
_dabt:  .word __dabt                    // data abort
_irq:   .word __irq                     // IRQ
_fiq:   .word __fiq                     // FIQ

__undf: b     .                         // undefined
      38:	eafffffe 	b	38 <__undf>

0000003c <__swi>:
__swi:  b     .                         // SWI
      3c:	eafffffe 	b	3c <__swi>

00000040 <__pabt>:
__pabt: b     .                         // program abort
      40:	eafffffe 	b	40 <__pabt>

00000044 <__dabt>:
__dabt: b     .                         // data abort
      44:	eafffffe 	b	44 <__dabt>

00000048 <__fiq>:
__fiq:  b     .                         // FIQ
      48:	eafffffe 	b	48 <__fiq>

0000004c <__irq>:
__irq:  b     .                         // enter InterruptHandler
      4c:	eafffffe 	b	4c <__irq>

00000050 <_start>:


        .size _boot, . - _boot
        .endfunc


// Setup the operating mode & stack.
// ---------------------------------
        .global _start
        .func   _start

_start:

  //*****************************************************************************
  // Disable MMU and caches
  //*****************************************************************************/
        mov r0, #0
      50:	e3a00000 	mov	r0, #0	; 0x0
        mcr p15, 0, r0, c7, c7, 0    // Invalidate ICache and DCache 
      54:	ee070f17 	mcr	15, 0, r0, cr7, cr7, {0}
        mcr p15, 0, r0, c7, c10, 4   // Drain write buffer 
      58:	ee070f9a 	mcr	15, 0, r0, cr7, cr10, {4}
        mcr p15, 0, r0, c8, c7, 0    // Invalidate I & D TLBs 
      5c:	ee080f17 	mcr	15, 0, r0, cr8, cr7, {0}
        mrc p15, 0, r0, c1, c0, 0    // Read MMU control register 
      60:	ee110f10 	mrc	15, 0, r0, cr1, cr0, {0}
        bic r0, r0, #0x00001000      // Disable ICache 
      64:	e3c00a01 	bic	r0, r0, #4096	; 0x1000
        bic r0, r0, #0x00000007      // Disable DCache, MMU and alignment fault 
      68:	e3c00007 	bic	r0, r0, #7	; 0x7
#ifdef __BIG_ENDIAN
        orr r0, r0, #0x00000080      // Set B bit
#else
        bic r0, r0, #0x00000080      // Clear B bit
      6c:	e3c00080 	bic	r0, r0, #128	; 0x80
#endif
        mcr p15, 0, r0, c1, c0, 0    // Write MMU control register
      70:	ee010f10 	mcr	15, 0, r0, cr1, cr0, {0}


// Initialize Interrupt System
// - Set stack location for each mode
// - Leave in System Mode with Interrupts Disabled    
   		msr   CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT   /* Undefined Instruction Mode */     
      74:	e321f0db 	msr	CPSR_c, #219	; 0xdb
   		ldr   sp, =__stack_und_end
      78:	e59fd080 	ldr	sp, [pc, #128]	; 100 <ABT_STACK_SIZE>
   
   		msr   CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT   /* Abort Mode */
      7c:	e321f0d7 	msr	CPSR_c, #215	; 0xd7
   		ldr   sp, =__stack_abt_end
      80:	e59fd07c 	ldr	sp, [pc, #124]	; 104 <ABT_STACK_SIZE+0x4>
   
   		msr   CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT     /* FIQ Mode */   
      84:	e321f0d1 	msr	CPSR_c, #209	; 0xd1
   		ldr   sp, =__stack_fiq_end
      88:	e59fd078 	ldr	sp, [pc, #120]	; 108 <ABT_STACK_SIZE+0x8>
   
   		msr   CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT     /* IRQ Mode */   
      8c:	e321f0d2 	msr	CPSR_c, #210	; 0xd2
   		ldr   sp, =__stack_irq_end
      90:	e59fd074 	ldr	sp, [pc, #116]	; 10c <ABT_STACK_SIZE+0xc>
   
   		msr   CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT     /* Supervisor Mode */
      94:	e321f0d3 	msr	CPSR_c, #211	; 0xd3
   		ldr   sp, =__stack_svc_end
      98:	e59fd070 	ldr	sp, [pc, #112]	; 110 <ABT_STACK_SIZE+0x10>

// Copy initialized data to its execution address in RAM
// -----------------------------------------------------
#ifdef ROM_RUN
        ldr   r1,=_etext                // -> ROM data start
        ldr   r2,=_data                 // -> data start
        ldr   r3,=_edata                // -> end of data
1:      cmp   r2,r3                     // check if data to move
        ldrlo r0,[r1],#4                // copy it
        strlo r0,[r2],#4
        blo   1b                        // loop until done
#endif
// Clear .bss
// ----------
        mov   r0,#0                     // get a zero
      9c:	e3a00000 	mov	r0, #0	; 0x0
        ldr   r1,=__bss_start__         // -> bss start
      a0:	e59f106c 	ldr	r1, [pc, #108]	; 114 <ABT_STACK_SIZE+0x14>
        ldr   r2,=__bss_end__           // -> bss end
      a4:	e59f206c 	ldr	r2, [pc, #108]	; 118 <ABT_STACK_SIZE+0x18>
2:      cmp   r1,r2                     // check if data to clear
      a8:	e1510002 	cmp	r1, r2
        strlo r0,[r1],#4                // clear 4 bytes
      ac:	34810004 	strcc	r0, [r1], #4
        blo   2b                        // loop until done
      b0:	3afffffc 	bcc	a8 <I_BIT+0x28>
		
	  	ldr   r0, =__ctors_start__
      b4:	e59f0060 	ldr	r0, [pc, #96]	; 11c <ABT_STACK_SIZE+0x1c>
	  	ldr   r1, =__ctors_end__
      b8:	e59f1060 	ldr	r1, [pc, #96]	; 120 <ABT_STACK_SIZE+0x20>

000000bc <ctor_loop>:
ctor_loop:
        cmp   r0, r1
      bc:	e1500001 	cmp	r0, r1
        beq   ctor_end
      c0:	0a000005 	beq	dc <ctor_end>
	  	ldr   r2, [r0], #4
      c4:	e4902004 	ldr	r2, [r0], #4
	  	stmfd sp!, {r0-r1}
      c8:	e92d0003 	stmdb	sp!, {r0, r1}
	  	mov   lr, pc
      cc:	e1a0e00f 	mov	lr, pc
	  	mov   pc, r2
      d0:	e1a0f002 	mov	pc, r2
	  	ldm   sp!, {r0-r1}
      d4:	e8bd0003 	ldmia	sp!, {r0, r1}
	  	b 	  ctor_loop
      d8:	eafffff7 	b	bc <ctor_loop>

000000dc <ctor_end>:
ctor_end:

// Call main program: main(0)
// --------------------------
        mov   r0,#0                     // no arguments (argc = 0)
      dc:	e3a00000 	mov	r0, #0	; 0x0
        mov   r1,r0
      e0:	e1a01000 	mov	r1, r0
        mov   r2,r0
      e4:	e1a02000 	mov	r2, r0
        mov   fp,r0                     // null frame pointer
      e8:	e1a0b000 	mov	fp, r0
        mov   r7,r0                     // null frame pointer for thumb
      ec:	e1a07000 	mov	r7, r0
        ldr   r10,=main
      f0:	e59fa02c 	ldr	sl, [pc, #44]	; 124 <ABT_STACK_SIZE+0x24>
        mov   lr,pc
      f4:	e1a0e00f 	mov	lr, pc
        bx    r10                       // enter main()
      f8:	e12fff1a 	bx	sl

000000fc <_reset>:

/* "global object"-dtors are never called and it should not be 
   needed since there is no OS to exit to. */
  
        .endfunc

        .global _reset
        .func   _reset
_reset:
        b     .                         // loop until reset
      fc:	eafffffe 	b	fc <_reset>
     100:	00001b00 	andeq	r1, r0, r0, lsl #22
     104:	00001a00 	andeq	r1, r0, r0, lsl #20
     108:	00001800 	andeq	r1, r0, r0, lsl #16
     10c:	00001900 	andeq	r1, r0, r0, lsl #18
     110:	00001f00 	andeq	r1, r0, r0, lsl #30
     114:	00001628 	andeq	r1, r0, r8, lsr #12
     118:	00001628 	andeq	r1, r0, r8, lsr #12
     11c:	00001628 	andeq	r1, r0, r8, lsr #12
     120:	00001628 	andeq	r1, r0, r8, lsr #12
     124:	00000174 	andeq	r0, r0, r4, ror r1

00000128 <SetupTimersEnableInterrupts()>:
#include "timer.h"
#include "interrupt.h"
#include "ks8695px.h"

void SetupTimersEnableInterrupts(void)
     128:	e1a0c00d 	mov	ip, sp
     12c:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     130:	e24cb004 	sub	fp, ip, #4	; 0x4
{
	Interrupt::Initialize();
     134:	eb000187 	bl	758 <Interrupt::Initialize()>
	Interrupt::SetTimersInterruptPriority(Level_14_Priority, LowestPriority);
     138:	e3a0000e 	mov	r0, #14	; 0xe
     13c:	e3a01000 	mov	r1, #0	; 0x0
     140:	eb0001b3 	bl	814 <Interrupt::SetTimersInterruptPriority(INTERRUPT_PRIORITY, INTERRUPT_PRIORITY)>
	Interrupt::Enable(Timer1);
     144:	e3a00007 	mov	r0, #7	; 0x7
     148:	eb0001db 	bl	8bc <Interrupt::Enable(INTERRUPTS)>
	Timer::Configure(500000, 10);
     14c:	e59f0018 	ldr	r0, [pc, #24]	; 16c <.text+0x16c>
     150:	e3a0100a 	mov	r1, #10	; 0xa
     154:	eb00024e 	bl	a94 <Timer::Configure(unsigned long, unsigned long)>
	Timer::Enable();
     158:	eb000271 	bl	b24 <Timer::Enable()>
	Interrupt::EnableIRQ();	
     15c:	e59f300c 	ldr	r3, [pc, #12]	; 170 <.text+0x170>
     160:	e1a0e00f 	mov	lr, pc
     164:	e12fff13 	bx	r3
}
     168:	e89da800 	ldmia	sp, {fp, sp, pc}
     16c:	0007a120 	andeq	sl, r7, r0, lsr #2
     170:	00000288 	andeq	r0, r0, r8, lsl #5

00000174 <main>:

int main( void)
     174:	e1a0c00d 	mov	ip, sp
     178:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     17c:	e24cb004 	sub	fp, ip, #4	; 0x4
     180:	e24dd014 	sub	sp, sp, #20	; 0x14
{
	uint32_t i = 0x20;
     184:	e3a03020 	mov	r3, #32	; 0x20
     188:	e50b3010 	str	r3, [fp, #-16]
	
    CPU::InitializeChipSelectZero(
         External_IO_Bank_0_BaseAddress, 
         External_IO_Bank_0_Size,
         HALFWORD,                      // Bus Width
         SEVEN,                         // Clocks OE or WE is asserted
         ONE,                           // Clocks address is held after CS negates
         ONE,                           // Clocks address is valid before CS asserts
         ONE);                          // Clocks address is valid before OE or WE assert
     18c:	e3a03000 	mov	r3, #0	; 0x0
     190:	e58d3000 	str	r3, [sp]
     194:	e3a03000 	mov	r3, #0	; 0x0
     198:	e58d3004 	str	r3, [sp, #4]
     19c:	e3a03000 	mov	r3, #0	; 0x0
     1a0:	e58d3008 	str	r3, [sp, #8]
     1a4:	e3a00632 	mov	r0, #52428800	; 0x3200000
     1a8:	e3a01501 	mov	r1, #4194304	; 0x400000
     1ac:	e3a02002 	mov	r2, #2	; 0x2
     1b0:	e3a03006 	mov	r3, #6	; 0x6
     1b4:	eb000433 	bl	1288 <CPU::InitializeChipSelectZero(unsigned long, unsigned long, BUS_WIDTH, CYCLES, CYCLES, CYCLES, CYCLES)>

    CPU::InitializeChipSelectOne(
         External_IO_Bank_1_BaseAddress, 
         External_IO_Bank_1_Size,
         HALFWORD,                      // Bus Width
         SEVEN,                         // Clocks OE or WE is asserted
         ONE,                           // Clocks address is held after CS negates
         ONE,                           // Clocks address is valid before CS asserts
         ONE);                          // Clocks address is valid before OE or WE assert
     1b8:	e3a03000 	mov	r3, #0	; 0x0
     1bc:	e58d3000 	str	r3, [sp]
     1c0:	e3a03000 	mov	r3, #0	; 0x0
     1c4:	e58d3004 	str	r3, [sp, #4]
     1c8:	e3a03000 	mov	r3, #0	; 0x0
     1cc:	e58d3008 	str	r3, [sp, #8]
     1d0:	e3a00636 	mov	r0, #56623104	; 0x3600000
     1d4:	e3a01501 	mov	r1, #4194304	; 0x400000
     1d8:	e3a02002 	mov	r2, #2	; 0x2
     1dc:	e3a03006 	mov	r3, #6	; 0x6
     1e0:	eb0003e1 	bl	116c <CPU::InitializeChipSelectOne(unsigned long, unsigned long, BUS_WIDTH, CYCLES, CYCLES, CYCLES, CYCLES)>

    CPU::InitializeChipSelectTwo(
         External_IO_Bank_2_BaseAddress, 
         External_IO_Bank_2_Size,
         WORD,                          // Bus Width
         SEVEN,                         // Clocks OE or WE is asserted
         TWO,                           // Clocks address is held after CS negates
         TWO,                           // Clocks address is valid before CS asserts
         TWO);                          // Clocks address is valid before OE or WE assert
     1e4:	e3a03001 	mov	r3, #1	; 0x1
     1e8:	e58d3000 	str	r3, [sp]
     1ec:	e3a03001 	mov	r3, #1	; 0x1
     1f0:	e58d3004 	str	r3, [sp, #4]
     1f4:	e3a03001 	mov	r3, #1	; 0x1
     1f8:	e58d3008 	str	r3, [sp, #8]
     1fc:	e3a0063a 	mov	r0, #60817408	; 0x3a00000
     200:	e3a01501 	mov	r1, #4194304	; 0x400000
     204:	e3a02003 	mov	r2, #3	; 0x3
     208:	e3a03006 	mov	r3, #6	; 0x6
     20c:	eb00038f 	bl	1050 <CPU::InitializeChipSelectTwo(unsigned long, unsigned long, BUS_WIDTH, CYCLES, CYCLES, CYCLES, CYCLES)>
         
#if 0
	Pins::ConfigureAsOutput(GPIO_15);	
	
    for (;;) {
		Pins::WriteAllPins(0);
		// for (int i = 0; i < 100000; i++) ;
		Pins::WriteAllPins(0x8000);
		//for (int i = 0; i < 100000; i++) ;
    }
#endif

	CPU::SetSystemClockSpeed(MHz_166);
     210:	e3a00000 	mov	r0, #0	; 0x0
     214:	eb000312 	bl	e64 <CPU::SetSystemClockSpeed(CLOCK_SPEED)>
	CPU::EnableICache();
     218:	eb000358 	bl	f80 <CPU::EnableICache()>
	Watchdog::Initialize();
     21c:	eb0002bc 	bl	d14 <Watchdog::Initialize()>
	//Watchdog::DrugEmDanno(15);
	PolledUart::Initialize();
     220:	eb000031 	bl	2ec <PolledUart::Initialize()>
	Pins::ConfigureAsOutput(GPIO_15);
     224:	e3a00902 	mov	r0, #32768	; 0x8000
     228:	eb0000d3 	bl	57c <Pins::ConfigureAsOutput(PINS)>
	SetupTimersEnableInterrupts();
     22c:	ebffffbd 	bl	128 <SetupTimersEnableInterrupts()>
	for (;;) {
		PolledUart::PutString("Hello from the BIOSA CPU board ");
     230:	e59f0048 	ldr	r0, [pc, #72]	; 280 <.text+0x280>
     234:	eb00006e 	bl	3f4 <PolledUart::PutString(char const*)>
		PolledUart::PutCharacter(i);
     238:	e51b3010 	ldr	r3, [fp, #-16]
     23c:	e20330ff 	and	r3, r3, #255	; 0xff
     240:	e1a00003 	mov	r0, r3
     244:	eb00005b 	bl	3b8 <PolledUart::PutCharacter(char)>
		PolledUart::PutString("\n");
     248:	e59f0034 	ldr	r0, [pc, #52]	; 284 <.text+0x284>
     24c:	eb000068 	bl	3f4 <PolledUart::PutString(char const*)>
		i = (i == 0x80) ? 0x20 : (i + 1);
     250:	e51b3010 	ldr	r3, [fp, #-16]
     254:	e3530080 	cmp	r3, #128	; 0x80
     258:	0a000003 	beq	26c <main+0xf8>
     25c:	e51b3010 	ldr	r3, [fp, #-16]
     260:	e2833001 	add	r3, r3, #1	; 0x1
     264:	e50b3014 	str	r3, [fp, #-20]
     268:	ea000001 	b	274 <main+0x100>
     26c:	e3a03020 	mov	r3, #32	; 0x20
     270:	e50b3014 	str	r3, [fp, #-20]
     274:	e51b3014 	ldr	r3, [fp, #-20]
     278:	e50b3010 	str	r3, [fp, #-16]
     27c:	eaffffeb 	b	230 <main+0xbc>
     280:	00001604 	andeq	r1, r0, r4, lsl #12
     284:	00001624 	andeq	r1, r0, r4, lsr #12

00000288 <Interrupt::EnableIRQ()>:
    	
    static void SetBusErrorResponseInterruptPriority(
    	INTERRUPT_PRIORITY Priority );
    	
	__inline static void EnableIRQ(void) {
     288:	e1a0c00d 	mov	ip, sp
     28c:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     290:	e24cb004 	sub	fp, ip, #4	; 0x4
       asm (
             " mov r0, #0        \n\
               mrs r0, CPSR      \n\
               bic r0, r0, #0x80 \n\
               msr CPSR_c, r0"
               :
               : );
     294:	e3a00000 	mov	r0, #0	; 0x0
     298:	e10f0000 	mrs	r0, CPSR
     29c:	e3c00080 	bic	r0, r0, #128	; 0x80
     2a0:	e121f000 	msr	CPSR_c, r0
			}
     2a4:	e89da800 	ldmia	sp, {fp, sp, pc}

000002a8 <PolledUart::SetBaudRate(unsigned long)>:
const uint32_t	EvenParity	  					= (1 << 4);
const uint32_t	StickParityBit					= (1 << 5);
const uint32_t	SetBreakCondition			 	= (1 << 6);

void PolledUart::SetBaudRate(uint32_t baudRate)
     2a8:	e1a0c00d 	mov	ip, sp
     2ac:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     2b0:	e24cb004 	sub	fp, ip, #4	; 0x4
     2b4:	e24dd004 	sub	sp, sp, #4	; 0x4
     2b8:	e50b0010 	str	r0, [fp, #-16]
{
	regWrite(UART::BD, (TicksPerSecond / baudRate));
     2bc:	e59f0020 	ldr	r0, [pc, #32]	; 2e4 <.text+0x2e4>
     2c0:	e51b1010 	ldr	r1, [fp, #-16]
     2c4:	eb000489 	bl	14f0 <__aeabi_uidiv>
     2c8:	e1a03000 	mov	r3, r0
     2cc:	e3a0001c 	mov	r0, #28	; 0x1c
     2d0:	e1a01003 	mov	r1, r3
     2d4:	e59f300c 	ldr	r3, [pc, #12]	; 2e8 <.text+0x2e8>
     2d8:	e1a0e00f 	mov	lr, pc
     2dc:	e12fff13 	bx	r3
}
     2e0:	e89da808 	ldmia	sp, {r3, fp, sp, pc}
     2e4:	017d7840 	cmneq	sp, r0, asr #16
     2e8:	0000053c 	andeq	r0, r0, ip, lsr r5

000002ec <PolledUart::Initialize()>:

void PolledUart::Initialize(void)
     2ec:	e1a0c00d 	mov	ip, sp
     2f0:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     2f4:	e24cb004 	sub	fp, ip, #4	; 0x4
{
	SetBaudRate(38400);
     2f8:	e3a00c96 	mov	r0, #38400	; 0x9600
     2fc:	ebffffe9 	bl	2a8 <PolledUart::SetBaudRate(unsigned long)>
	regWrite(UART::LCR, (EightBitCharacters | OneStopBit | ParityDisable));
     300:	e3a0000c 	mov	r0, #12	; 0xc
     304:	e3a01003 	mov	r1, #3	; 0x3
     308:	e59f3008 	ldr	r3, [pc, #8]	; 318 <.text+0x318>
     30c:	e1a0e00f 	mov	lr, pc
     310:	e12fff13 	bx	r3
}
     314:	e89da800 	ldmia	sp, {fp, sp, pc}
     318:	0000053c 	andeq	r0, r0, ip, lsr r5

0000031c <PolledUart::RawPutCharacter(char)>:

void PolledUart::RawPutCharacter(const char character)
     31c:	e1a0c00d 	mov	ip, sp
     320:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     324:	e24cb004 	sub	fp, ip, #4	; 0x4
     328:	e24dd00c 	sub	sp, sp, #12	; 0xc
     32c:	e1a03000 	mov	r3, r0
     330:	e54b3018 	strb	r3, [fp, #-24]
{
	uint32_t c = character;
     334:	e55b3018 	ldrb	r3, [fp, #-24]
     338:	e50b3014 	str	r3, [fp, #-20]
	for (uint32_t i = 0; i < 0x100000; i++) {
     33c:	e3a03000 	mov	r3, #0	; 0x0
     340:	e50b3010 	str	r3, [fp, #-16]
     344:	ea00000d 	b	380 <PolledUart::RawPutCharacter(char)+0x64>
		if (regRead(UART::LSR) & TransmitHoldingRegisterEmpty)
     348:	e3a00014 	mov	r0, #20	; 0x14
     34c:	e59f3058 	ldr	r3, [pc, #88]	; 3ac <.text+0x3ac>
     350:	e1a0e00f 	mov	lr, pc
     354:	e12fff13 	bx	r3
     358:	e1a03000 	mov	r3, r0
     35c:	e2033020 	and	r3, r3, #32	; 0x20
     360:	e3530000 	cmp	r3, #0	; 0x0
     364:	03a03000 	moveq	r3, #0	; 0x0
     368:	13a03001 	movne	r3, #1	; 0x1
     36c:	e3530000 	cmp	r3, #0	; 0x0
     370:	1a000006 	bne	390 <PolledUart::RawPutCharacter(char)+0x74>
     374:	e51b3010 	ldr	r3, [fp, #-16]
     378:	e2833001 	add	r3, r3, #1	; 0x1
     37c:	e50b3010 	str	r3, [fp, #-16]
     380:	e51b2010 	ldr	r2, [fp, #-16]
     384:	e59f3024 	ldr	r3, [pc, #36]	; 3b0 <.text+0x3b0>
     388:	e1520003 	cmp	r2, r3
     38c:	9affffed 	bls	348 <PolledUart::RawPutCharacter(char)+0x2c>
			break;
	}
	regWrite(UART::TX, c);
     390:	e3a00004 	mov	r0, #4	; 0x4
     394:	e51b1014 	ldr	r1, [fp, #-20]
     398:	e59f3014 	ldr	r3, [pc, #20]	; 3b4 <.text+0x3b4>
     39c:	e1a0e00f 	mov	lr, pc
     3a0:	e12fff13 	bx	r3
}
     3a4:	e24bd00c 	sub	sp, fp, #12	; 0xc
     3a8:	e89da800 	ldmia	sp, {fp, sp, pc}
     3ac:	00000504 	andeq	r0, r0, r4, lsl #10
     3b0:	000fffff 	streqd	pc, [pc], -pc
     3b4:	0000053c 	andeq	r0, r0, ip, lsr r5

000003b8 <PolledUart::PutCharacter(char)>:

void PolledUart::PutCharacter(const char character)
     3b8:	e1a0c00d 	mov	ip, sp
     3bc:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     3c0:	e24cb004 	sub	fp, ip, #4	; 0x4
     3c4:	e24dd004 	sub	sp, sp, #4	; 0x4
     3c8:	e1a03000 	mov	r3, r0
     3cc:	e54b3010 	strb	r3, [fp, #-16]
{
	RawPutCharacter(character);
     3d0:	e55b3010 	ldrb	r3, [fp, #-16]
     3d4:	e1a00003 	mov	r0, r3
     3d8:	ebffffcf 	bl	31c <PolledUart::RawPutCharacter(char)>
	if (character == '\n')
     3dc:	e55b3010 	ldrb	r3, [fp, #-16]
     3e0:	e353000a 	cmp	r3, #10	; 0xa
     3e4:	1a000001 	bne	3f0 <PolledUart::PutCharacter(char)+0x38>
		RawPutCharacter('\r');
     3e8:	e3a0000d 	mov	r0, #13	; 0xd
     3ec:	ebffffca 	bl	31c <PolledUart::RawPutCharacter(char)>
}
     3f0:	e89da808 	ldmia	sp, {r3, fp, sp, pc}

000003f4 <PolledUart::PutString(char const*)>:

void PolledUart::PutString(const char *string)
     3f4:	e1a0c00d 	mov	ip, sp
     3f8:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     3fc:	e24cb004 	sub	fp, ip, #4	; 0x4
     400:	e24dd008 	sub	sp, sp, #8	; 0x8
     404:	e50b0014 	str	r0, [fp, #-20]
{
	char c;
	while ((c = *string++) != 0)
     408:	ea000002 	b	418 <SVC_STACK_SIZE+0x18>
		PutCharacter(c);
     40c:	e55b300d 	ldrb	r3, [fp, #-13]
     410:	e1a00003 	mov	r0, r3
     414:	ebffffe7 	bl	3b8 <PolledUart::PutCharacter(char)>
     418:	e51b3014 	ldr	r3, [fp, #-20]
     41c:	e5d33000 	ldrb	r3, [r3]
     420:	e54b300d 	strb	r3, [fp, #-13]
     424:	e55b300d 	ldrb	r3, [fp, #-13]
     428:	e3530000 	cmp	r3, #0	; 0x0
     42c:	03a02000 	moveq	r2, #0	; 0x0
     430:	13a02001 	movne	r2, #1	; 0x1
     434:	e51b3014 	ldr	r3, [fp, #-20]
     438:	e2833001 	add	r3, r3, #1	; 0x1
     43c:	e50b3014 	str	r3, [fp, #-20]
     440:	e3520000 	cmp	r2, #0	; 0x0
     444:	1afffff0 	bne	40c <SVC_STACK_SIZE+0xc>
}
     448:	e24bd00c 	sub	sp, fp, #12	; 0xc
     44c:	e89da800 	ldmia	sp, {fp, sp, pc}

00000450 <PolledUart::CharacterAvailable()>:

bool PolledUart::CharacterAvailable(void)
     450:	e1a0c00d 	mov	ip, sp
     454:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     458:	e24cb004 	sub	fp, ip, #4	; 0x4
{
	return ((regRead(UART::LSR) & ReceiveDataReady) ? true : false);
     45c:	e3a00014 	mov	r0, #20	; 0x14
     460:	e59f3018 	ldr	r3, [pc, #24]	; 480 <.text+0x480>
     464:	e1a0e00f 	mov	lr, pc
     468:	e12fff13 	bx	r3
     46c:	e1a03000 	mov	r3, r0
     470:	e2033001 	and	r3, r3, #1	; 0x1
     474:	e20330ff 	and	r3, r3, #255	; 0xff
}
     478:	e1a00003 	mov	r0, r3
     47c:	e89da800 	ldmia	sp, {fp, sp, pc}
     480:	00000504 	andeq	r0, r0, r4, lsl #10

00000484 <PolledUart::GetCharacter()>:

uint32_t PolledUart::GetCharacter(void)
     484:	e1a0c00d 	mov	ip, sp
     488:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     48c:	e24cb004 	sub	fp, ip, #4	; 0x4
{
	while ((regRead(UART::LSR) & ReceiveDataReady) == 0)
     490:	e3a00014 	mov	r0, #20	; 0x14
     494:	e59f303c 	ldr	r3, [pc, #60]	; 4d8 <.text+0x4d8>
     498:	e1a0e00f 	mov	lr, pc
     49c:	e12fff13 	bx	r3
     4a0:	e1a03000 	mov	r3, r0
     4a4:	e2033001 	and	r3, r3, #1	; 0x1
     4a8:	e3530000 	cmp	r3, #0	; 0x0
     4ac:	13a03000 	movne	r3, #0	; 0x0
     4b0:	03a03001 	moveq	r3, #1	; 0x1
     4b4:	e3530000 	cmp	r3, #0	; 0x0
     4b8:	1afffff4 	bne	490 <PolledUart::GetCharacter()+0xc>
		;
	return regRead(UART::RX);
     4bc:	e3a00000 	mov	r0, #0	; 0x0
     4c0:	e59f3010 	ldr	r3, [pc, #16]	; 4d8 <.text+0x4d8>
     4c4:	e1a0e00f 	mov	lr, pc
     4c8:	e12fff13 	bx	r3
     4cc:	e1a03000 	mov	r3, r0
}
     4d0:	e1a00003 	mov	r0, r3
     4d4:	e89da800 	ldmia	sp, {fp, sp, pc}
     4d8:	00000504 	andeq	r0, r0, r4, lsl #10

000004dc <UART::regAddress(UART::Registers)>:
		BD	= 0x001C,		// 0x1c	- Baud Rate (r/w) 
		SR	= 0x0020		// 0x20	- Status (r/w)
	};
	
	inline volatile uint32_t *regAddress(Registers reg)
     4dc:	e1a0c00d 	mov	ip, sp
     4e0:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     4e4:	e24cb004 	sub	fp, ip, #4	; 0x4
     4e8:	e24dd004 	sub	sp, sp, #4	; 0x4
     4ec:	e50b0010 	str	r0, [fp, #-16]
	{
	    return reinterpret_cast<volatile uint32_t*>(BaseAddress + reg);
     4f0:	e51b3010 	ldr	r3, [fp, #-16]
     4f4:	e28337ff 	add	r3, r3, #66846720	; 0x3fc0000
     4f8:	e2833a3e 	add	r3, r3, #253952	; 0x3e000
	}
     4fc:	e1a00003 	mov	r0, r3
     500:	e89da808 	ldmia	sp, {r3, fp, sp, pc}

00000504 <UART::regRead(UART::Registers)>:
	
	inline uint32_t regRead(Registers reg)
     504:	e1a0c00d 	mov	ip, sp
     508:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     50c:	e24cb004 	sub	fp, ip, #4	; 0x4
     510:	e24dd004 	sub	sp, sp, #4	; 0x4
     514:	e50b0010 	str	r0, [fp, #-16]
	{
	    return *regAddress(reg);
     518:	e51b0010 	ldr	r0, [fp, #-16]
     51c:	e59f3014 	ldr	r3, [pc, #20]	; 538 <.text+0x538>
     520:	e1a0e00f 	mov	lr, pc
     524:	e12fff13 	bx	r3
     528:	e1a03000 	mov	r3, r0
     52c:	e5933000 	ldr	r3, [r3]
	}
     530:	e1a00003 	mov	r0, r3
     534:	e89da808 	ldmia	sp, {r3, fp, sp, pc}
     538:	000004dc 	ldreqd	r0, [r0], -ip

0000053c <UART::regWrite(UART::Registers, unsigned long)>:
	
	inline void regWrite(Registers reg, uint32_t value)
     53c:	e1a0c00d 	mov	ip, sp
     540:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     544:	e24cb004 	sub	fp, ip, #4	; 0x4
     548:	e24dd008 	sub	sp, sp, #8	; 0x8
     54c:	e50b0010 	str	r0, [fp, #-16]
     550:	e50b1014 	str	r1, [fp, #-20]
	{
	    *regAddress(reg) = value;
     554:	e51b0010 	ldr	r0, [fp, #-16]
     558:	e59f3018 	ldr	r3, [pc, #24]	; 578 <.text+0x578>
     55c:	e1a0e00f 	mov	lr, pc
     560:	e12fff13 	bx	r3
     564:	e1a02000 	mov	r2, r0
     568:	e51b3014 	ldr	r3, [fp, #-20]
     56c:	e5823000 	str	r3, [r2]
	}
     570:	e24bd00c 	sub	sp, fp, #12	; 0xc
     574:	e89da800 	ldmia	sp, {fp, sp, pc}
     578:	000004dc 	ldreqd	r0, [r0], -ip

0000057c <Pins::ConfigureAsOutput(PINS)>:
#include "gpio.h"
#include "gpio_registers.h"

void Pins::ConfigureAsOutput(PINS pins)
     57c:	e1a0c00d 	mov	ip, sp
     580:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     584:	e24cb004 	sub	fp, ip, #4	; 0x4
     588:	e24dd004 	sub	sp, sp, #4	; 0x4
     58c:	e50b0010 	str	r0, [fp, #-16]
{
  regWrite(GPIO::IOPM, static_cast<uint32_t> (pins));
     590:	e51b3010 	ldr	r3, [fp, #-16]
     594:	e3a00000 	mov	r0, #0	; 0x0
     598:	e1a01003 	mov	r1, r3
     59c:	e59f3008 	ldr	r3, [pc, #8]	; 5ac <.text+0x5ac>
     5a0:	e1a0e00f 	mov	lr, pc
     5a4:	e12fff13 	bx	r3
}
     5a8:	e89da808 	ldmia	sp, {r3, fp, sp, pc}
     5ac:	00000718 	andeq	r0, r0, r8, lsl r7

000005b0 <Pins::ConfigureAsInput(PINS)>:

void Pins::ConfigureAsInput(PINS pins)
     5b0:	e1a0c00d 	mov	ip, sp
     5b4:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     5b8:	e24cb004 	sub	fp, ip, #4	; 0x4
     5bc:	e24dd004 	sub	sp, sp, #4	; 0x4
     5c0:	e50b0010 	str	r0, [fp, #-16]
{
  regWrite(GPIO::IOPM, static_cast<uint32_t> (~pins));
     5c4:	e51b3010 	ldr	r3, [fp, #-16]
     5c8:	e1e03003 	mvn	r3, r3
     5cc:	e3a00000 	mov	r0, #0	; 0x0
     5d0:	e1a01003 	mov	r1, r3
     5d4:	e59f3008 	ldr	r3, [pc, #8]	; 5e4 <.text+0x5e4>
     5d8:	e1a0e00f 	mov	lr, pc
     5dc:	e12fff13 	bx	r3
}
     5e0:	e89da808 	ldmia	sp, {r3, fp, sp, pc}
     5e4:	00000718 	andeq	r0, r0, r8, lsl r7

000005e8 <Pins::SetOutput(PINS)>:

void Pins::SetOutput(PINS pins)
     5e8:	e1a0c00d 	mov	ip, sp
     5ec:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     5f0:	e24cb004 	sub	fp, ip, #4	; 0x4
     5f4:	e24dd004 	sub	sp, sp, #4	; 0x4
     5f8:	e50b0010 	str	r0, [fp, #-16]
{
  regWrite(GPIO::IOPD, static_cast<uint32_t> (pins));
     5fc:	e51b3010 	ldr	r3, [fp, #-16]
     600:	e3a00008 	mov	r0, #8	; 0x8
     604:	e1a01003 	mov	r1, r3
     608:	e59f3008 	ldr	r3, [pc, #8]	; 618 <.text+0x618>
     60c:	e1a0e00f 	mov	lr, pc
     610:	e12fff13 	bx	r3
}
     614:	e89da808 	ldmia	sp, {r3, fp, sp, pc}
     618:	00000718 	andeq	r0, r0, r8, lsl r7

0000061c <Pins::ClearOutput(PINS)>:

void Pins::ClearOutput(PINS pins)
     61c:	e1a0c00d 	mov	ip, sp
     620:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     624:	e24cb004 	sub	fp, ip, #4	; 0x4
     628:	e24dd004 	sub	sp, sp, #4	; 0x4
     62c:	e50b0010 	str	r0, [fp, #-16]
{
  regWrite(GPIO::IOPD, static_cast<uint32_t> (~pins));
     630:	e51b3010 	ldr	r3, [fp, #-16]
     634:	e1e03003 	mvn	r3, r3
     638:	e3a00008 	mov	r0, #8	; 0x8
     63c:	e1a01003 	mov	r1, r3
     640:	e59f3008 	ldr	r3, [pc, #8]	; 650 <.text+0x650>
     644:	e1a0e00f 	mov	lr, pc
     648:	e12fff13 	bx	r3
}
     64c:	e89da808 	ldmia	sp, {r3, fp, sp, pc}
     650:	00000718 	andeq	r0, r0, r8, lsl r7

00000654 <Pins::WriteAllPins(unsigned long)>:

void Pins::WriteAllPins(uint32_t pins)
     654:	e1a0c00d 	mov	ip, sp
     658:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     65c:	e24cb004 	sub	fp, ip, #4	; 0x4
     660:	e24dd004 	sub	sp, sp, #4	; 0x4
     664:	e50b0010 	str	r0, [fp, #-16]
{
    regWrite(GPIO::IOPD, pins);
     668:	e3a00008 	mov	r0, #8	; 0x8
     66c:	e51b1010 	ldr	r1, [fp, #-16]
     670:	e59f3008 	ldr	r3, [pc, #8]	; 680 <.text+0x680>
     674:	e1a0e00f 	mov	lr, pc
     678:	e12fff13 	bx	r3
}
     67c:	e89da808 	ldmia	sp, {r3, fp, sp, pc}
     680:	00000718 	andeq	r0, r0, r8, lsl r7

00000684 <Pins::ReadAllPins()>:


uint32_t Pins::ReadAllPins( void )
     684:	e1a0c00d 	mov	ip, sp
     688:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     68c:	e24cb004 	sub	fp, ip, #4	; 0x4
{
    return regRead(GPIO::IOPD);
     690:	e3a00008 	mov	r0, #8	; 0x8
     694:	e59f3010 	ldr	r3, [pc, #16]	; 6ac <.text+0x6ac>
     698:	e1a0e00f 	mov	lr, pc
     69c:	e12fff13 	bx	r3
     6a0:	e1a03000 	mov	r3, r0
}
     6a4:	e1a00003 	mov	r0, r3
     6a8:	e89da800 	ldmia	sp, {fp, sp, pc}
     6ac:	000006e0 	andeq	r0, r0, r0, ror #13

000006b0 <GPIO::regAddress(GPIO::Registers)>:
		IOPC	= 0x0004,		// 0x04	- IO Port Control (rw)
		IOPD	= 0x0008		// 0x08 - IO Port Data
	};
	
	inline volatile uint32_t *regAddress(Registers reg)
     6b0:	e1a0c00d 	mov	ip, sp
     6b4:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     6b8:	e24cb004 	sub	fp, ip, #4	; 0x4
     6bc:	e24dd004 	sub	sp, sp, #4	; 0x4
     6c0:	e50b0010 	str	r0, [fp, #-16]
	{
	    return reinterpret_cast<volatile uint32_t*>(BaseAddress + reg);
     6c4:	e51b3010 	ldr	r3, [fp, #-16]
     6c8:	e1a02003 	mov	r2, r3
     6cc:	e59f3008 	ldr	r3, [pc, #8]	; 6dc <.text+0x6dc>
     6d0:	e0823003 	add	r3, r2, r3
	}
     6d4:	e1a00003 	mov	r0, r3
     6d8:	e89da808 	ldmia	sp, {r3, fp, sp, pc}
     6dc:	03ffe600 	mvneqs	lr, #0	; 0x0

000006e0 <GPIO::regRead(GPIO::Registers)>:
	
	inline uint32_t regRead(Registers reg)
     6e0:	e1a0c00d 	mov	ip, sp
     6e4:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     6e8:	e24cb004 	sub	fp, ip, #4	; 0x4
     6ec:	e24dd004 	sub	sp, sp, #4	; 0x4
     6f0:	e50b0010 	str	r0, [fp, #-16]
	{
	    return *regAddress(reg);
     6f4:	e51b0010 	ldr	r0, [fp, #-16]
     6f8:	e59f3014 	ldr	r3, [pc, #20]	; 714 <.text+0x714>
     6fc:	e1a0e00f 	mov	lr, pc
     700:	e12fff13 	bx	r3
     704:	e1a03000 	mov	r3, r0
     708:	e5933000 	ldr	r3, [r3]
	}
     70c:	e1a00003 	mov	r0, r3
     710:	e89da808 	ldmia	sp, {r3, fp, sp, pc}
     714:	000006b0 	streqh	r0, [r0], -r0

00000718 <GPIO::regWrite(GPIO::Registers, unsigned long)>:
	
	inline void regWrite(Registers reg, uint32_t value)
     718:	e1a0c00d 	mov	ip, sp
     71c:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     720:	e24cb004 	sub	fp, ip, #4	; 0x4
     724:	e24dd008 	sub	sp, sp, #8	; 0x8
     728:	e50b0010 	str	r0, [fp, #-16]
     72c:	e50b1014 	str	r1, [fp, #-20]
	{
	    *regAddress(reg) = value;
     730:	e51b0010 	ldr	r0, [fp, #-16]
     734:	e59f3018 	ldr	r3, [pc, #24]	; 754 <.text+0x754>
     738:	e1a0e00f 	mov	lr, pc
     73c:	e12fff13 	bx	r3
     740:	e1a02000 	mov	r2, r0
     744:	e51b3014 	ldr	r3, [fp, #-20]
     748:	e5823000 	str	r3, [r2]
	}
     74c:	e24bd00c 	sub	sp, fp, #12	; 0xc
     750:	e89da800 	ldmia	sp, {fp, sp, pc}
     754:	000006b0 	streqh	r0, [r0], -r0

00000758 <Interrupt::Initialize()>:
		regWrite(INTERRUPT::INTST, 0x80);
	}
}

void Interrupt::Initialize(void)
     758:	e1a0c00d 	mov	ip, sp
     75c:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     760:	e24cb004 	sub	fp, ip, #4	; 0x4
     764:	e24dd008 	sub	sp, sp, #8	; 0x8
{
	regWrite(INTERRUPT::INTMC, 0);
     768:	e3a00000 	mov	r0, #0	; 0x0
     76c:	e3a01000 	mov	r1, #0	; 0x0
     770:	e59f3044 	ldr	r3, [pc, #68]	; 7bc <.text+0x7bc>
     774:	e1a0e00f 	mov	lr, pc
     778:	e12fff13 	bx	r3
	uint32_t* vector = reinterpret_cast<uint32_t*> (0x18);
     77c:	e3a03018 	mov	r3, #24	; 0x18
     780:	e50b3014 	str	r3, [fp, #-20]
	uint32_t vec = ((reinterpret_cast<uint32_t>(&interruptHandler) - (uint32_t)vector - 0x8) >> 2 );
     784:	e59f3034 	ldr	r3, [pc, #52]	; 7c0 <.text+0x7c0>
     788:	e2432008 	sub	r2, r3, #8	; 0x8
     78c:	e51b3014 	ldr	r3, [fp, #-20]
     790:	e0633002 	rsb	r3, r3, r2
     794:	e1a03123 	mov	r3, r3, lsr #2
     798:	e50b3010 	str	r3, [fp, #-16]
	vec = static_cast<uint32_t>(0xEA000000 | vec);
     79c:	e51b3010 	ldr	r3, [fp, #-16]
     7a0:	e38334ea 	orr	r3, r3, #-369098752	; 0xea000000
     7a4:	e50b3010 	str	r3, [fp, #-16]
	*vector = vec;
     7a8:	e51b2014 	ldr	r2, [fp, #-20]
     7ac:	e51b3010 	ldr	r3, [fp, #-16]
     7b0:	e5823000 	str	r3, [r2]
}
     7b4:	e24bd00c 	sub	sp, fp, #12	; 0xc
     7b8:	e89da800 	ldmia	sp, {fp, sp, pc}
     7bc:	00000a54 	andeq	r0, r0, r4, asr sl
     7c0:	00000970 	andeq	r0, r0, r0, ror r9

000007c4 <Interrupt::Set_WAN_MAC_InterruptPriority(INTERRUPT_PRIORITY, INTERRUPT_PRIORITY, INTERRUPT_PRIORITY, INTERRUPT_PRIORITY, INTERRUPT_PRIORITY, INTERRUPT_PRIORITY, INTERRUPT_PRIORITY)>:
   
void Interrupt::Set_WAN_MAC_InterruptPriority(
	INTERRUPT_PRIORITY LinkChangedPriority,
	INTERRUPT_PRIORITY TransmitStatusPriority,
	INTERRUPT_PRIORITY ReceiveStatusPriority,
	INTERRUPT_PRIORITY TransmitBufferUnavailablePriority,
	INTERRUPT_PRIORITY ReceiveBufferUnavailablePriority,
	INTERRUPT_PRIORITY TransmitProcessStoppedPriority,
	INTERRUPT_PRIORITY ReceiveProcessStoppedPriority )
     7c4:	e1a0c00d 	mov	ip, sp
     7c8:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     7cc:	e24cb004 	sub	fp, ip, #4	; 0x4
     7d0:	e24dd010 	sub	sp, sp, #16	; 0x10
     7d4:	e50b0010 	str	r0, [fp, #-16]
     7d8:	e50b1014 	str	r1, [fp, #-20]
     7dc:	e50b2018 	str	r2, [fp, #-24]
     7e0:	e50b301c 	str	r3, [fp, #-28]
{
}
     7e4:	e24bd00c 	sub	sp, fp, #12	; 0xc
     7e8:	e89da800 	ldmia	sp, {fp, sp, pc}

000007ec <Interrupt::Set_LAN_MAC_InterruptPriority(INTERRUPT_PRIORITY, INTERRUPT_PRIORITY, INTERRUPT_PRIORITY, INTERRUPT_PRIORITY, INTERRUPT_PRIORITY, INTERRUPT_PRIORITY)>:
    	
void Interrupt::Set_LAN_MAC_InterruptPriority(
	INTERRUPT_PRIORITY TransmitStatusPriority,
	INTERRUPT_PRIORITY ReceiveStatusPriority,
	INTERRUPT_PRIORITY TransmitBufferUnavailablePriority,
	INTERRUPT_PRIORITY ReceiveBufferUnavailablePriority,
	INTERRUPT_PRIORITY TransmitProcessStoppedPriority,
	INTERRUPT_PRIORITY ReceiveProcessStoppedPriority )
     7ec:	e1a0c00d 	mov	ip, sp
     7f0:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     7f4:	e24cb004 	sub	fp, ip, #4	; 0x4
     7f8:	e24dd010 	sub	sp, sp, #16	; 0x10
     7fc:	e50b0010 	str	r0, [fp, #-16]
     800:	e50b1014 	str	r1, [fp, #-20]
     804:	e50b2018 	str	r2, [fp, #-24]
     808:	e50b301c 	str	r3, [fp, #-28]
{
}
     80c:	e24bd00c 	sub	sp, fp, #12	; 0xc
     810:	e89da800 	ldmia	sp, {fp, sp, pc}

00000814 <Interrupt::SetTimersInterruptPriority(INTERRUPT_PRIORITY, INTERRUPT_PRIORITY)>:
    
void Interrupt::SetTimersInterruptPriority(
	INTERRUPT_PRIORITY Timer1Priority,
	INTERRUPT_PRIORITY Timer0Priority )
     814:	e1a0c00d 	mov	ip, sp
     818:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     81c:	e24cb004 	sub	fp, ip, #4	; 0x4
     820:	e24dd008 	sub	sp, sp, #8	; 0x8
     824:	e50b0010 	str	r0, [fp, #-16]
     828:	e50b1014 	str	r1, [fp, #-20]
{
	regWrite(INTERRUPT::INTPT, 
		static_cast<uint32_t>(Timer1Priority) << 4 | 
		static_cast<uint32_t> (Timer0Priority));
     82c:	e51b3010 	ldr	r3, [fp, #-16]
     830:	e1a02203 	mov	r2, r3, lsl #4
     834:	e51b3014 	ldr	r3, [fp, #-20]
     838:	e1823003 	orr	r3, r2, r3
     83c:	e3a00018 	mov	r0, #24	; 0x18
     840:	e1a01003 	mov	r1, r3
     844:	e59f300c 	ldr	r3, [pc, #12]	; 858 <.text+0x858>
     848:	e1a0e00f 	mov	lr, pc
     84c:	e12fff13 	bx	r3
}
     850:	e24bd00c 	sub	sp, fp, #12	; 0xc
     854:	e89da800 	ldmia	sp, {fp, sp, pc}
     858:	00000a54 	andeq	r0, r0, r4, asr sl

0000085c <Interrupt::Set_UART_InterruptPriority(INTERRUPT_PRIORITY, INTERRUPT_PRIORITY, INTERRUPT_PRIORITY, INTERRUPT_PRIORITY)>:
    	
void Interrupt::Set_UART_InterruptPriority(
	INTERRUPT_PRIORITY ModemStatusPriority,
	INTERRUPT_PRIORITY LineErrorPriority,
	INTERRUPT_PRIORITY ReceivePriority,
	INTERRUPT_PRIORITY TransmitPriority )
     85c:	e1a0c00d 	mov	ip, sp
     860:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     864:	e24cb004 	sub	fp, ip, #4	; 0x4
     868:	e24dd010 	sub	sp, sp, #16	; 0x10
     86c:	e50b0010 	str	r0, [fp, #-16]
     870:	e50b1014 	str	r1, [fp, #-20]
     874:	e50b2018 	str	r2, [fp, #-24]
     878:	e50b301c 	str	r3, [fp, #-28]
{
}	
     87c:	e24bd00c 	sub	sp, fp, #12	; 0xc
     880:	e89da800 	ldmia	sp, {fp, sp, pc}

00000884 <Interrupt::SetCommunicationsChannelInterruptPriority(INTERRUPT_PRIORITY, INTERRUPT_PRIORITY)>:
    	
void Interrupt::SetCommunicationsChannelInterruptPriority(
	INTERRUPT_PRIORITY TransmitPriority,	
	INTERRUPT_PRIORITY ReceivePriority )
     884:	e1a0c00d 	mov	ip, sp
     888:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     88c:	e24cb004 	sub	fp, ip, #4	; 0x4
     890:	e24dd008 	sub	sp, sp, #8	; 0x8
     894:	e50b0010 	str	r0, [fp, #-16]
     898:	e50b1014 	str	r1, [fp, #-20]
{
}
     89c:	e24bd00c 	sub	sp, fp, #12	; 0xc
     8a0:	e89da800 	ldmia	sp, {fp, sp, pc}

000008a4 <Interrupt::SetBusErrorResponseInterruptPriority(INTERRUPT_PRIORITY)>:
    	
void Interrupt::SetBusErrorResponseInterruptPriority(
	INTERRUPT_PRIORITY Priority )  	
     8a4:	e1a0c00d 	mov	ip, sp
     8a8:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     8ac:	e24cb004 	sub	fp, ip, #4	; 0x4
     8b0:	e24dd004 	sub	sp, sp, #4	; 0x4
     8b4:	e50b0010 	str	r0, [fp, #-16]
{
}
     8b8:	e89da808 	ldmia	sp, {r3, fp, sp, pc}

000008bc <Interrupt::Enable(INTERRUPTS)>:

void Interrupt::Enable( INTERRUPTS irq )
     8bc:	e1a0c00d 	mov	ip, sp
     8c0:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     8c4:	e24cb004 	sub	fp, ip, #4	; 0x4
     8c8:	e24dd004 	sub	sp, sp, #4	; 0x4
     8cc:	e50b0010 	str	r0, [fp, #-16]
{
	regWrite(INTERRUPT::INTEN, 
		regRead(INTERRUPT::INTEN) | (1 << static_cast<uint32_t> (irq)));
     8d0:	e3a00004 	mov	r0, #4	; 0x4
     8d4:	e59f3030 	ldr	r3, [pc, #48]	; 90c <.text+0x90c>
     8d8:	e1a0e00f 	mov	lr, pc
     8dc:	e12fff13 	bx	r3
     8e0:	e1a01000 	mov	r1, r0
     8e4:	e51b2010 	ldr	r2, [fp, #-16]
     8e8:	e3a03001 	mov	r3, #1	; 0x1
     8ec:	e1a03213 	mov	r3, r3, lsl r2
     8f0:	e1813003 	orr	r3, r1, r3
     8f4:	e3a00004 	mov	r0, #4	; 0x4
     8f8:	e1a01003 	mov	r1, r3
     8fc:	e59f300c 	ldr	r3, [pc, #12]	; 910 <.text+0x910>
     900:	e1a0e00f 	mov	lr, pc
     904:	e12fff13 	bx	r3
}
     908:	e89da808 	ldmia	sp, {r3, fp, sp, pc}
     90c:	00000a1c 	andeq	r0, r0, ip, lsl sl
     910:	00000a54 	andeq	r0, r0, r4, asr sl

00000914 <Interrupt::Disable(INTERRUPTS)>:
   
void Interrupt::Disable( INTERRUPTS irq )
     914:	e1a0c00d 	mov	ip, sp
     918:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     91c:	e24cb004 	sub	fp, ip, #4	; 0x4
     920:	e24dd004 	sub	sp, sp, #4	; 0x4
     924:	e50b0010 	str	r0, [fp, #-16]
{
	regWrite(INTERRUPT::INTEN, 
		regRead(INTERRUPT::INTEN) & ~(1 << static_cast<uint32_t> (irq)));
     928:	e3a00004 	mov	r0, #4	; 0x4
     92c:	e59f3034 	ldr	r3, [pc, #52]	; 968 <.text+0x968>
     930:	e1a0e00f 	mov	lr, pc
     934:	e12fff13 	bx	r3
     938:	e1a01000 	mov	r1, r0
     93c:	e51b2010 	ldr	r2, [fp, #-16]
     940:	e3a03001 	mov	r3, #1	; 0x1
     944:	e1a03213 	mov	r3, r3, lsl r2
     948:	e1e03003 	mvn	r3, r3
     94c:	e0013003 	and	r3, r1, r3
     950:	e3a00004 	mov	r0, #4	; 0x4
     954:	e1a01003 	mov	r1, r3
     958:	e59f300c 	ldr	r3, [pc, #12]	; 96c <.text+0x96c>
     95c:	e1a0e00f 	mov	lr, pc
     960:	e12fff13 	bx	r3
}
     964:	e89da808 	ldmia	sp, {r3, fp, sp, pc}
     968:	00000a1c 	andeq	r0, r0, ip, lsl sl
     96c:	00000a54 	andeq	r0, r0, r4, asr sl

00000970 <Interrupt::interruptHandler()>:
     970:	e52dc004 	str	ip, [sp, #-4]!
     974:	e1a0c00d 	mov	ip, sp
     978:	e92dd80f 	stmdb	sp!, {r0, r1, r2, r3, fp, ip, lr, pc}
     97c:	e24cb004 	sub	fp, ip, #4	; 0x4
     980:	e24dd004 	sub	sp, sp, #4	; 0x4
     984:	e3a00008 	mov	r0, #8	; 0x8
     988:	e59f3054 	ldr	r3, [pc, #84]	; 9e4 <.text+0x9e4>
     98c:	e1a0e00f 	mov	lr, pc
     990:	e12fff13 	bx	r3
     994:	e1a03000 	mov	r3, r0
     998:	e50b3020 	str	r3, [fp, #-32]
     99c:	e51b3020 	ldr	r3, [fp, #-32]
     9a0:	e2033080 	and	r3, r3, #128	; 0x80
     9a4:	e3530000 	cmp	r3, #0	; 0x0
     9a8:	0a000009 	beq	9d4 <Interrupt::interruptHandler()+0x64>
     9ac:	ebffff34 	bl	684 <Pins::ReadAllPins()>
     9b0:	e1a03000 	mov	r3, r0
     9b4:	e2233902 	eor	r3, r3, #32768	; 0x8000
     9b8:	e1a00003 	mov	r0, r3
     9bc:	ebffff24 	bl	654 <Pins::WriteAllPins(unsigned long)>
     9c0:	e3a00008 	mov	r0, #8	; 0x8
     9c4:	e3a01080 	mov	r1, #128	; 0x80
     9c8:	e59f3018 	ldr	r3, [pc, #24]	; 9e8 <.text+0x9e8>
     9cc:	e1a0e00f 	mov	lr, pc
     9d0:	e12fff13 	bx	r3
     9d4:	e24bd01c 	sub	sp, fp, #28	; 0x1c
     9d8:	e89d680f 	ldmia	sp, {r0, r1, r2, r3, fp, sp, lr}
     9dc:	e8bd1000 	ldmia	sp!, {ip}
     9e0:	e25ef004 	subs	pc, lr, #4	; 0x4
     9e4:	00000a1c 	andeq	r0, r0, ip, lsl sl
     9e8:	00000a54 	andeq	r0, r0, r4, asr sl

000009ec <INTERRUPT::regAddress(INTERRUPT::Registers)>:
		INTHPF	= 0x0030,		// 0x30 - Interrupt Pending Highest Priority Register for FIQ (rw)
		INTHPI	= 0x0034		// 0x34 - Interrupt Pending Highest Priority Register for IRQ (rw)
	};
	
	inline volatile uint32_t *regAddress(Registers reg)
     9ec:	e1a0c00d 	mov	ip, sp
     9f0:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     9f4:	e24cb004 	sub	fp, ip, #4	; 0x4
     9f8:	e24dd004 	sub	sp, sp, #4	; 0x4
     9fc:	e50b0010 	str	r0, [fp, #-16]
	{
	    return reinterpret_cast<volatile uint32_t*>(BaseAddress + reg);
     a00:	e51b3010 	ldr	r3, [fp, #-16]
     a04:	e1a02003 	mov	r2, r3
     a08:	e59f3008 	ldr	r3, [pc, #8]	; a18 <.text+0xa18>
     a0c:	e0823003 	add	r3, r2, r3
	}
     a10:	e1a00003 	mov	r0, r3
     a14:	e89da808 	ldmia	sp, {r3, fp, sp, pc}
     a18:	03ffe200 	mvneqs	lr, #0	; 0x0

00000a1c <INTERRUPT::regRead(INTERRUPT::Registers)>:
	
	inline uint32_t regRead(Registers reg)
     a1c:	e1a0c00d 	mov	ip, sp
     a20:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     a24:	e24cb004 	sub	fp, ip, #4	; 0x4
     a28:	e24dd004 	sub	sp, sp, #4	; 0x4
     a2c:	e50b0010 	str	r0, [fp, #-16]
	{
	    return *regAddress(reg);
     a30:	e51b0010 	ldr	r0, [fp, #-16]
     a34:	e59f3014 	ldr	r3, [pc, #20]	; a50 <.text+0xa50>
     a38:	e1a0e00f 	mov	lr, pc
     a3c:	e12fff13 	bx	r3
     a40:	e1a03000 	mov	r3, r0
     a44:	e5933000 	ldr	r3, [r3]
	}
     a48:	e1a00003 	mov	r0, r3
     a4c:	e89da808 	ldmia	sp, {r3, fp, sp, pc}
     a50:	000009ec 	andeq	r0, r0, ip, ror #19

00000a54 <INTERRUPT::regWrite(INTERRUPT::Registers, unsigned long)>:
	
	inline void regWrite(Registers reg, uint32_t value)
     a54:	e1a0c00d 	mov	ip, sp
     a58:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     a5c:	e24cb004 	sub	fp, ip, #4	; 0x4
     a60:	e24dd008 	sub	sp, sp, #8	; 0x8
     a64:	e50b0010 	str	r0, [fp, #-16]
     a68:	e50b1014 	str	r1, [fp, #-20]
	{
	    *regAddress(reg) = value;
     a6c:	e51b0010 	ldr	r0, [fp, #-16]
     a70:	e59f3018 	ldr	r3, [pc, #24]	; a90 <.text+0xa90>
     a74:	e1a0e00f 	mov	lr, pc
     a78:	e12fff13 	bx	r3
     a7c:	e1a02000 	mov	r2, r0
     a80:	e51b3014 	ldr	r3, [fp, #-20]
     a84:	e5823000 	str	r3, [r2]
	}
     a88:	e24bd00c 	sub	sp, fp, #12	; 0xc
     a8c:	e89da800 	ldmia	sp, {fp, sp, pc}
     a90:	000009ec 	andeq	r0, r0, ip, ror #19

00000a94 <Timer::Configure(unsigned long, unsigned long)>:
	regWrite(TIMERS::T1TC, 1);
	regWrite(TIMERS::T1PD, 0);
}

void Timer::Configure(uint32_t periodInMicroSeconds, uint32_t tout0_HighTimeInMicroseconds)
     a94:	e1a0c00d 	mov	ip, sp
     a98:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     a9c:	e24cb004 	sub	fp, ip, #4	; 0x4
     aa0:	e24dd010 	sub	sp, sp, #16	; 0x10
     aa4:	e50b0018 	str	r0, [fp, #-24]
     aa8:	e50b101c 	str	r1, [fp, #-28]
{
	uint32_t periodInTicks 		= (periodInMicroSeconds * TicksPerMicrosecond);
     aac:	e51b2018 	ldr	r2, [fp, #-24]
     ab0:	e1a03002 	mov	r3, r2
     ab4:	e1a03103 	mov	r3, r3, lsl #2
     ab8:	e0833002 	add	r3, r3, r2
     abc:	e1a02103 	mov	r2, r3, lsl #2
     ac0:	e0833002 	add	r3, r3, r2
     ac4:	e50b3014 	str	r3, [fp, #-20]
	uint32_t highTimeInTicks	= (tout0_HighTimeInMicroseconds * TicksPerMicrosecond);
     ac8:	e51b201c 	ldr	r2, [fp, #-28]
     acc:	e1a03002 	mov	r3, r2
     ad0:	e1a03103 	mov	r3, r3, lsl #2
     ad4:	e0833002 	add	r3, r3, r2
     ad8:	e1a02103 	mov	r2, r3, lsl #2
     adc:	e0833002 	add	r3, r3, r2
     ae0:	e50b3010 	str	r3, [fp, #-16]
	
	regWrite(TIMERS::T1TC, (periodInTicks - highTimeInTicks));
     ae4:	e51b2014 	ldr	r2, [fp, #-20]
     ae8:	e51b3010 	ldr	r3, [fp, #-16]
     aec:	e0633002 	rsb	r3, r3, r2
     af0:	e3a00004 	mov	r0, #4	; 0x4
     af4:	e1a01003 	mov	r1, r3
     af8:	e59f3020 	ldr	r3, [pc, #32]	; b20 <.text+0xb20>
     afc:	e1a0e00f 	mov	lr, pc
     b00:	e12fff13 	bx	r3
	regWrite(TIMERS::T1PD, highTimeInTicks);
     b04:	e3a0000c 	mov	r0, #12	; 0xc
     b08:	e51b1010 	ldr	r1, [fp, #-16]
     b0c:	e59f300c 	ldr	r3, [pc, #12]	; b20 <.text+0xb20>
     b10:	e1a0e00f 	mov	lr, pc
     b14:	e12fff13 	bx	r3
}
     b18:	e24bd00c 	sub	sp, fp, #12	; 0xc
     b1c:	e89da800 	ldmia	sp, {fp, sp, pc}
     b20:	00000cd4 	ldreqd	r0, [r0], -r4

00000b24 <Timer::Enable()>:

void Timer::Enable(void)
     b24:	e1a0c00d 	mov	ip, sp
     b28:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     b2c:	e24cb004 	sub	fp, ip, #4	; 0x4
{
	regWrite(TIMERS::TMCON, (regRead(TIMERS::TMCON) |  Timer_Enable));
     b30:	e3a00000 	mov	r0, #0	; 0x0
     b34:	e59f3024 	ldr	r3, [pc, #36]	; b60 <.text+0xb60>
     b38:	e1a0e00f 	mov	lr, pc
     b3c:	e12fff13 	bx	r3
     b40:	e1a03000 	mov	r3, r0
     b44:	e3833002 	orr	r3, r3, #2	; 0x2
     b48:	e3a00000 	mov	r0, #0	; 0x0
     b4c:	e1a01003 	mov	r1, r3
     b50:	e59f300c 	ldr	r3, [pc, #12]	; b64 <.text+0xb64>
     b54:	e1a0e00f 	mov	lr, pc
     b58:	e12fff13 	bx	r3
}
     b5c:	e89da800 	ldmia	sp, {fp, sp, pc}
     b60:	00000c9c 	muleq	r0, ip, ip
     b64:	00000cd4 	ldreqd	r0, [r0], -r4

00000b68 <Timer::Disable()>:
		
void Timer::Disable(void)
     b68:	e1a0c00d 	mov	ip, sp
     b6c:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     b70:	e24cb004 	sub	fp, ip, #4	; 0x4
{
	regWrite(TIMERS::TMCON, (regRead(TIMERS::TMCON) & ~Timer_Enable));
     b74:	e3a00000 	mov	r0, #0	; 0x0
     b78:	e59f3024 	ldr	r3, [pc, #36]	; ba4 <.text+0xba4>
     b7c:	e1a0e00f 	mov	lr, pc
     b80:	e12fff13 	bx	r3
     b84:	e1a03000 	mov	r3, r0
     b88:	e3c33002 	bic	r3, r3, #2	; 0x2
     b8c:	e3a00000 	mov	r0, #0	; 0x0
     b90:	e1a01003 	mov	r1, r3
     b94:	e59f300c 	ldr	r3, [pc, #12]	; ba8 <.text+0xba8>
     b98:	e1a0e00f 	mov	lr, pc
     b9c:	e12fff13 	bx	r3
}
     ba0:	e89da800 	ldmia	sp, {fp, sp, pc}
     ba4:	00000c9c 	muleq	r0, ip, ip
     ba8:	00000cd4 	ldreqd	r0, [r0], -r4

00000bac <Timer::Initialize()>:
     bac:	e1a0c00d 	mov	ip, sp
     bb0:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     bb4:	e24cb004 	sub	fp, ip, #4	; 0x4
     bb8:	ebffffea 	bl	b68 <Timer::Disable()>
     bbc:	e3a00004 	mov	r0, #4	; 0x4
     bc0:	e3a01001 	mov	r1, #1	; 0x1
     bc4:	e59f301c 	ldr	r3, [pc, #28]	; be8 <.text+0xbe8>
     bc8:	e1a0e00f 	mov	lr, pc
     bcc:	e12fff13 	bx	r3
     bd0:	e3a0000c 	mov	r0, #12	; 0xc
     bd4:	e3a01000 	mov	r1, #0	; 0x0
     bd8:	e59f3008 	ldr	r3, [pc, #8]	; be8 <.text+0xbe8>
     bdc:	e1a0e00f 	mov	lr, pc
     be0:	e12fff13 	bx	r3
     be4:	e89da800 	ldmia	sp, {fp, sp, pc}
     be8:	00000cd4 	ldreqd	r0, [r0], -r4

00000bec <Timer::PolledWait(unsigned long)>:

void Timer::PolledWait(uint32_t waitForMicroseconds)
     bec:	e1a0c00d 	mov	ip, sp
     bf0:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     bf4:	e24cb004 	sub	fp, ip, #4	; 0x4
     bf8:	e24dd008 	sub	sp, sp, #8	; 0x8
     bfc:	e50b0014 	str	r0, [fp, #-20]
{
	bool done;
	Initialize();
     c00:	ebffffe9 	bl	bac <Timer::Initialize()>
	Configure(waitForMicroseconds, 10);
     c04:	e51b0014 	ldr	r0, [fp, #-20]
     c08:	e3a0100a 	mov	r1, #10	; 0xa
     c0c:	ebffffa0 	bl	a94 <Timer::Configure(unsigned long, unsigned long)>
	regWrite(INTERRUPT::INTST, (1 << Timer1));
     c10:	e3a00008 	mov	r0, #8	; 0x8
     c14:	e3a01080 	mov	r1, #128	; 0x80
     c18:	e59f304c 	ldr	r3, [pc, #76]	; c6c <.text+0xc6c>
     c1c:	e1a0e00f 	mov	lr, pc
     c20:	e12fff13 	bx	r3
	Enable();	
     c24:	ebffffbe 	bl	b24 <Timer::Enable()>
    do 
    	done = (regRead(INTERRUPT::INTST) & (1 << Timer1)) ? true : false;
     c28:	e3a00008 	mov	r0, #8	; 0x8
     c2c:	e59f303c 	ldr	r3, [pc, #60]	; c70 <.text+0xc70>
     c30:	e1a0e00f 	mov	lr, pc
     c34:	e12fff13 	bx	r3
     c38:	e1a03000 	mov	r3, r0
     c3c:	e2033080 	and	r3, r3, #128	; 0x80
     c40:	e3530000 	cmp	r3, #0	; 0x0
     c44:	03a03000 	moveq	r3, #0	; 0x0
     c48:	13a03001 	movne	r3, #1	; 0x1
     c4c:	e54b300d 	strb	r3, [fp, #-13]
     c50:	e55b300d 	ldrb	r3, [fp, #-13]
     c54:	e2233001 	eor	r3, r3, #1	; 0x1
     c58:	e20330ff 	and	r3, r3, #255	; 0xff
     c5c:	e3530000 	cmp	r3, #0	; 0x0
     c60:	1afffff0 	bne	c28 <Timer::PolledWait(unsigned long)+0x3c>
    while (!done);
}
     c64:	e24bd00c 	sub	sp, fp, #12	; 0xc
     c68:	e89da800 	ldmia	sp, {fp, sp, pc}
     c6c:	00000a54 	andeq	r0, r0, r4, asr sl
     c70:	00000a1c 	andeq	r0, r0, ip, lsl sl

00000c74 <TIMERS::regAddress(TIMERS::Registers)>:
		T1PD	= 0x000C,	// 0x0c	- Timer 1 Pulse Count Register (rw)
		T0PD	= 0x0010	// 0x10	- Timer 0 Pulse Count Register (rw)
	};
	
	inline volatile uint32_t *regAddress(Registers reg)
     c74:	e1a0c00d 	mov	ip, sp
     c78:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     c7c:	e24cb004 	sub	fp, ip, #4	; 0x4
     c80:	e24dd004 	sub	sp, sp, #4	; 0x4
     c84:	e50b0010 	str	r0, [fp, #-16]
	{
	    return reinterpret_cast<volatile uint32_t*>(BaseAddress + reg);
     c88:	e51b3010 	ldr	r3, [fp, #-16]
     c8c:	e28337ff 	add	r3, r3, #66846720	; 0x3fc0000
     c90:	e2833bf9 	add	r3, r3, #254976	; 0x3e400
	}
     c94:	e1a00003 	mov	r0, r3
     c98:	e89da808 	ldmia	sp, {r3, fp, sp, pc}

00000c9c <TIMERS::regRead(TIMERS::Registers)>:
	
	inline uint32_t regRead(Registers reg)
     c9c:	e1a0c00d 	mov	ip, sp
     ca0:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     ca4:	e24cb004 	sub	fp, ip, #4	; 0x4
     ca8:	e24dd004 	sub	sp, sp, #4	; 0x4
     cac:	e50b0010 	str	r0, [fp, #-16]
	{
	    return *regAddress(reg);
     cb0:	e51b0010 	ldr	r0, [fp, #-16]
     cb4:	e59f3014 	ldr	r3, [pc, #20]	; cd0 <.text+0xcd0>
     cb8:	e1a0e00f 	mov	lr, pc
     cbc:	e12fff13 	bx	r3
     cc0:	e1a03000 	mov	r3, r0
     cc4:	e5933000 	ldr	r3, [r3]
	}
     cc8:	e1a00003 	mov	r0, r3
     ccc:	e89da808 	ldmia	sp, {r3, fp, sp, pc}
     cd0:	00000c74 	andeq	r0, r0, r4, ror ip

00000cd4 <TIMERS::regWrite(TIMERS::Registers, unsigned long)>:
	
	inline void regWrite(Registers reg, uint32_t value)
     cd4:	e1a0c00d 	mov	ip, sp
     cd8:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     cdc:	e24cb004 	sub	fp, ip, #4	; 0x4
     ce0:	e24dd008 	sub	sp, sp, #8	; 0x8
     ce4:	e50b0010 	str	r0, [fp, #-16]
     ce8:	e50b1014 	str	r1, [fp, #-20]
	{
	    *regAddress(reg) = value;
     cec:	e51b0010 	ldr	r0, [fp, #-16]
     cf0:	e59f3018 	ldr	r3, [pc, #24]	; d10 <.text+0xd10>
     cf4:	e1a0e00f 	mov	lr, pc
     cf8:	e12fff13 	bx	r3
     cfc:	e1a02000 	mov	r2, r0
     d00:	e51b3014 	ldr	r3, [fp, #-20]
     d04:	e5823000 	str	r3, [r2]
	}
     d08:	e24bd00c 	sub	sp, fp, #12	; 0xc
     d0c:	e89da800 	ldmia	sp, {fp, sp, pc}
     d10:	00000c74 	andeq	r0, r0, r4, ror ip

00000d14 <Watchdog::Initialize()>:

const uint32_t Timer_0_Enable				= (1 << 0);
const uint32_t Timer_0_WatchdogEnableMask 	= 0xFF; 

void Watchdog::Initialize(void)
     d14:	e1a0c00d 	mov	ip, sp
     d18:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     d1c:	e24cb004 	sub	fp, ip, #4	; 0x4
{
	regWrite(TIMERS::TMCON, (regRead(TIMERS::TMCON) & ~Timer_0_Enable));
     d20:	e3a00000 	mov	r0, #0	; 0x0
     d24:	e59f304c 	ldr	r3, [pc, #76]	; d78 <.text+0xd78>
     d28:	e1a0e00f 	mov	lr, pc
     d2c:	e12fff13 	bx	r3
     d30:	e1a03000 	mov	r3, r0
     d34:	e3c33001 	bic	r3, r3, #1	; 0x1
     d38:	e3a00000 	mov	r0, #0	; 0x0
     d3c:	e1a01003 	mov	r1, r3
     d40:	e59f3034 	ldr	r3, [pc, #52]	; d7c <.text+0xd7c>
     d44:	e1a0e00f 	mov	lr, pc
     d48:	e12fff13 	bx	r3
	regWrite(TIMERS::T0TC, 1);
     d4c:	e3a00008 	mov	r0, #8	; 0x8
     d50:	e3a01001 	mov	r1, #1	; 0x1
     d54:	e59f3020 	ldr	r3, [pc, #32]	; d7c <.text+0xd7c>
     d58:	e1a0e00f 	mov	lr, pc
     d5c:	e12fff13 	bx	r3
	regWrite(TIMERS::T0PD, 0);
     d60:	e3a00010 	mov	r0, #16	; 0x10
     d64:	e3a01000 	mov	r1, #0	; 0x0
     d68:	e59f300c 	ldr	r3, [pc, #12]	; d7c <.text+0xd7c>
     d6c:	e1a0e00f 	mov	lr, pc
     d70:	e12fff13 	bx	r3
}
     d74:	e89da800 	ldmia	sp, {fp, sp, pc}
     d78:	00000c9c 	muleq	r0, ip, ip
     d7c:	00000cd4 	ldreqd	r0, [r0], -r4

00000d80 <Watchdog::DrugEmDanno(unsigned long)>:

void Watchdog::DrugEmDanno(uint32_t timeoutIntervalInSeconds)
     d80:	e1a0c00d 	mov	ip, sp
     d84:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     d88:	e24cb004 	sub	fp, ip, #4	; 0x4
     d8c:	e24dd008 	sub	sp, sp, #8	; 0x8
     d90:	e50b0014 	str	r0, [fp, #-20]
{
	regWrite(TIMERS::TMCON, (regRead(TIMERS::TMCON) & ~Timer_0_Enable));
     d94:	e3a00000 	mov	r0, #0	; 0x0
     d98:	e59f30bc 	ldr	r3, [pc, #188]	; e5c <.text+0xe5c>
     d9c:	e1a0e00f 	mov	lr, pc
     da0:	e12fff13 	bx	r3
     da4:	e1a03000 	mov	r3, r0
     da8:	e3c33001 	bic	r3, r3, #1	; 0x1
     dac:	e3a00000 	mov	r0, #0	; 0x0
     db0:	e1a01003 	mov	r1, r3
     db4:	e59f30a4 	ldr	r3, [pc, #164]	; e60 <.text+0xe60>
     db8:	e1a0e00f 	mov	lr, pc
     dbc:	e12fff13 	bx	r3
	uint32_t timeoutIntervalInTicks = timeoutIntervalInSeconds * TicksPerSecond;
     dc0:	e51b1014 	ldr	r1, [fp, #-20]
     dc4:	e1a02001 	mov	r2, r1
     dc8:	e1a02282 	mov	r2, r2, lsl #5
     dcc:	e0612002 	rsb	r2, r1, r2
     dd0:	e1a03302 	mov	r3, r2, lsl #6
     dd4:	e0623003 	rsb	r3, r2, r3
     dd8:	e1a03183 	mov	r3, r3, lsl #3
     ddc:	e0833001 	add	r3, r3, r1
     de0:	e1a02103 	mov	r2, r3, lsl #2
     de4:	e0833002 	add	r3, r3, r2
     de8:	e1a02103 	mov	r2, r3, lsl #2
     dec:	e0833002 	add	r3, r3, r2
     df0:	e1a03303 	mov	r3, r3, lsl #6
     df4:	e50b3010 	str	r3, [fp, #-16]
	regWrite(TIMERS::T0TC, (timeoutIntervalInTicks | Timer_0_WatchdogEnableMask));
     df8:	e51b3010 	ldr	r3, [fp, #-16]
     dfc:	e38330ff 	orr	r3, r3, #255	; 0xff
     e00:	e3a00008 	mov	r0, #8	; 0x8
     e04:	e1a01003 	mov	r1, r3
     e08:	e59f3050 	ldr	r3, [pc, #80]	; e60 <.text+0xe60>
     e0c:	e1a0e00f 	mov	lr, pc
     e10:	e12fff13 	bx	r3
	regWrite(TIMERS::T0PD, 0);
     e14:	e3a00010 	mov	r0, #16	; 0x10
     e18:	e3a01000 	mov	r1, #0	; 0x0
     e1c:	e59f303c 	ldr	r3, [pc, #60]	; e60 <.text+0xe60>
     e20:	e1a0e00f 	mov	lr, pc
     e24:	e12fff13 	bx	r3
	regWrite(TIMERS::TMCON, (regRead(TIMERS::TMCON) |  Timer_0_Enable));
     e28:	e3a00000 	mov	r0, #0	; 0x0
     e2c:	e59f3028 	ldr	r3, [pc, #40]	; e5c <.text+0xe5c>
     e30:	e1a0e00f 	mov	lr, pc
     e34:	e12fff13 	bx	r3
     e38:	e1a03000 	mov	r3, r0
     e3c:	e3833001 	orr	r3, r3, #1	; 0x1
     e40:	e3a00000 	mov	r0, #0	; 0x0
     e44:	e1a01003 	mov	r1, r3
     e48:	e59f3010 	ldr	r3, [pc, #16]	; e60 <.text+0xe60>
     e4c:	e1a0e00f 	mov	lr, pc
     e50:	e12fff13 	bx	r3
}
     e54:	e24bd00c 	sub	sp, fp, #12	; 0xc
     e58:	e89da800 	ldmia	sp, {fp, sp, pc}
     e5c:	00000c9c 	muleq	r0, ip, ip
     e60:	00000cd4 	ldreqd	r0, [r0], -r4

00000e64 <CPU::SetSystemClockSpeed(CLOCK_SPEED)>:
const uint32_t	DCacheMask		=	0x00000004;
const uint32_t	ICacheMask		=	0x00001000;
const uint32_t	FCSEMask		=	0xC0000000;

void CPU::SetSystemClockSpeed(CLOCK_SPEED speed)
     e64:	e1a0c00d 	mov	ip, sp
     e68:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     e6c:	e24cb004 	sub	fp, ip, #4	; 0x4
     e70:	e24dd004 	sub	sp, sp, #4	; 0x4
     e74:	e50b0010 	str	r0, [fp, #-16]
{
	regWrite(BUS_CONTROL::CLKCON, static_cast<uint32_t>(speed));
     e78:	e51b3010 	ldr	r3, [fp, #-16]
     e7c:	e3a00004 	mov	r0, #4	; 0x4
     e80:	e1a01003 	mov	r1, r3
     e84:	e59f3008 	ldr	r3, [pc, #8]	; e94 <.text+0xe94>
     e88:	e1a0e00f 	mov	lr, pc
     e8c:	e12fff13 	bx	r3
}
     e90:	e89da808 	ldmia	sp, {r3, fp, sp, pc}
     e94:	000013cc 	andeq	r1, r0, ip, asr #7

00000e98 <CPU::Reset()>:

void CPU::Reset(void)
     e98:	e1a0c00d 	mov	ip, sp
     e9c:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     ea0:	e24cb004 	sub	fp, ip, #4	; 0x4
     ea4:	e24dd004 	sub	sp, sp, #4	; 0x4
{
	const uint32_t Timer_0_Enable	= (1 << 0);
     ea8:	e3a03001 	mov	r3, #1	; 0x1
     eac:	e50b3010 	str	r3, [fp, #-16]
	
	regWrite(TIMERS::T0TC, 0x1FF);
     eb0:	e3a00008 	mov	r0, #8	; 0x8
     eb4:	e59f104c 	ldr	r1, [pc, #76]	; f08 <.text+0xf08>
     eb8:	e59f304c 	ldr	r3, [pc, #76]	; f0c <.text+0xf0c>
     ebc:	e1a0e00f 	mov	lr, pc
     ec0:	e12fff13 	bx	r3
	regWrite(TIMERS::T0PD, 0);
     ec4:	e3a00010 	mov	r0, #16	; 0x10
     ec8:	e3a01000 	mov	r1, #0	; 0x0
     ecc:	e59f3038 	ldr	r3, [pc, #56]	; f0c <.text+0xf0c>
     ed0:	e1a0e00f 	mov	lr, pc
     ed4:	e12fff13 	bx	r3
	regWrite(TIMERS::TMCON, (regRead(TIMERS::TMCON) |  Timer_0_Enable));
     ed8:	e3a00000 	mov	r0, #0	; 0x0
     edc:	e59f302c 	ldr	r3, [pc, #44]	; f10 <.text+0xf10>
     ee0:	e1a0e00f 	mov	lr, pc
     ee4:	e12fff13 	bx	r3
     ee8:	e1a03000 	mov	r3, r0
     eec:	e3833001 	orr	r3, r3, #1	; 0x1
     ef0:	e3a00000 	mov	r0, #0	; 0x0
     ef4:	e1a01003 	mov	r1, r3
     ef8:	e59f300c 	ldr	r3, [pc, #12]	; f0c <.text+0xf0c>
     efc:	e1a0e00f 	mov	lr, pc
     f00:	e12fff13 	bx	r3
	// Wait until watchdog resets CPU
	for (;;) ;
     f04:	eafffffe 	b	f04 <CPU::Reset()+0x6c>
     f08:	000001ff 	streqd	r0, [r0], -pc
     f0c:	00000cd4 	ldreqd	r0, [r0], -r4
     f10:	00000c9c 	muleq	r0, ip, ip

00000f14 <CPU::setCoprocessorRegisterBits(unsigned long)>:
}
                  
void CPU::InitializeChipSelectZero(uint32_t 	baseAddress, 
							       uint32_t 	size,
							  	   BUS_WIDTH  	width,
                              	   CYCLES 		time_OE_or_WE_Asserted,
							  	   CYCLES 		addressHoldTimeAfter_CS_Negated, 
							       CYCLES 		addressSetupTimeBefore_CS_Asserted,
						           CYCLES 		addressSetupTimeBefore_OE_or_WE_Asserted)
{
	bitWrite(EXTERNAL_IO::ERGCON, 	EXTERNAL_IO::BUS_WIDTH_FOR_EXTERNAL_BANK_0, width);
	bitWrite(EXTERNAL_IO::EXTACON0, EXTERNAL_IO::LAST_ADDRESS, ((baseAddress + size - 1) >> 16));
	bitWrite(EXTERNAL_IO::EXTACON0, EXTERNAL_IO::BASE_ADDRESS, (baseAddress >> 16));
	bitWrite(EXTERNAL_IO::EXTACON0, EXTERNAL_IO::TIME_OE_OR_WE_IS_ASSERTED, 
	           time_OE_or_WE_Asserted);
	bitWrite(EXTERNAL_IO::EXTACON0, EXTERNAL_IO::CS_HOLD_TIME_AFTER_OE_OR_WE, 
	           addressHoldTimeAfter_CS_Negated);
	bitWrite(EXTERNAL_IO::EXTACON0, EXTERNAL_IO::ADDRESS_SETUP_TIME_BEFORE_CS, 
	           addressSetupTimeBefore_CS_Asserted );
	bitWrite(EXTERNAL_IO::EXTACON0, EXTERNAL_IO::CS_SETUP_TIME_BEFORE_OE_OR_WE, 
	           addressSetupTimeBefore_OE_or_WE_Asserted );
}

void CPU::InitializeChipSelectOne(uint32_t 		baseAddress, 
							      uint32_t 		size,
							  	  BUS_WIDTH  	width,
                              	  CYCLES 		time_OE_or_WE_Asserted,
							  	  CYCLES 		addressHoldTimeAfter_CS_Negated, 
							      CYCLES 		addressSetupTimeBefore_CS_Asserted,
						          CYCLES 		addressSetupTimeBefore_OE_or_WE_Asserted)
{
	bitWrite(EXTERNAL_IO::ERGCON,   EXTERNAL_IO::BUS_WIDTH_FOR_EXTERNAL_BANK_1, width);
	bitWrite(EXTERNAL_IO::EXTACON1, EXTERNAL_IO::LAST_ADDRESS, ((baseAddress + size - 1) >> 16));
	bitWrite(EXTERNAL_IO::EXTACON1, EXTERNAL_IO::BASE_ADDRESS, (baseAddress >> 16));
	bitWrite(EXTERNAL_IO::EXTACON1, EXTERNAL_IO::TIME_OE_OR_WE_IS_ASSERTED, 
	           time_OE_or_WE_Asserted);
	bitWrite(EXTERNAL_IO::EXTACON1, EXTERNAL_IO::CS_HOLD_TIME_AFTER_OE_OR_WE, 
	           addressHoldTimeAfter_CS_Negated);
	bitWrite(EXTERNAL_IO::EXTACON1, EXTERNAL_IO::ADDRESS_SETUP_TIME_BEFORE_CS, 
	           addressSetupTimeBefore_CS_Asserted );
	bitWrite(EXTERNAL_IO::EXTACON1, EXTERNAL_IO::CS_SETUP_TIME_BEFORE_OE_OR_WE, 
	           addressSetupTimeBefore_OE_or_WE_Asserted );
}

void CPU::InitializeChipSelectTwo(uint32_t 		baseAddress, 
							      uint32_t 		size,
							  	  BUS_WIDTH  	width,
                              	  CYCLES 		time_OE_or_WE_Asserted,
							  	  CYCLES 		addressHoldTimeAfter_CS_Negated, 
							      CYCLES 		addressSetupTimeBefore_CS_Asserted,
						          CYCLES 		addressSetupTimeBefore_OE_or_WE_Asserted)
{
	bitWrite(EXTERNAL_IO::ERGCON, 	EXTERNAL_IO::BUS_WIDTH_FOR_EXTERNAL_BANK_2, width);
	bitWrite(EXTERNAL_IO::EXTACON2, EXTERNAL_IO::LAST_ADDRESS, ((baseAddress + size - 1) >> 16));
	bitWrite(EXTERNAL_IO::EXTACON2, EXTERNAL_IO::BASE_ADDRESS,  (baseAddress >> 16));
	bitWrite(EXTERNAL_IO::EXTACON2, EXTERNAL_IO::TIME_OE_OR_WE_IS_ASSERTED, 
	           time_OE_or_WE_Asserted);
	bitWrite(EXTERNAL_IO::EXTACON2, EXTERNAL_IO::CS_HOLD_TIME_AFTER_OE_OR_WE, 
	           addressHoldTimeAfter_CS_Negated);
	bitWrite(EXTERNAL_IO::EXTACON2, EXTERNAL_IO::ADDRESS_SETUP_TIME_BEFORE_CS, 
	           addressSetupTimeBefore_CS_Asserted );
	bitWrite(EXTERNAL_IO::EXTACON2, EXTERNAL_IO::CS_SETUP_TIME_BEFORE_OE_OR_WE, 
	           addressSetupTimeBefore_OE_or_WE_Asserted );
}

void CPU::EnableMMU(void)
{
	setCoprocessorRegisterBits(MMU_Mask);
}

void CPU::EnableICache(void)
{
	setCoprocessorRegisterBits(ICacheMask);
}

void CPU::EnableDCache(void)
{
	setCoprocessorRegisterBits(DCacheMask);
}

void CPU::EnableFastContextSwitch(void)
{
	setCoprocessorRegisterBits(FCSEMask);
}

void CPU::DisableMMU(void)
{
	clearCoprocessorRegisterBits(MMU_Mask);
}

void CPU::DisableICache(void)
{
	clearCoprocessorRegisterBits(ICacheMask);
}

void CPU::DisableDCache(void)
{
	clearCoprocessorRegisterBits(DCacheMask);
}

void CPU::DisableFastContextSwitch(void)
{
	clearCoprocessorRegisterBits(FCSEMask);
}

void CPU::setCoprocessorRegisterBits(uint32_t mask)
     f14:	e1a0c00d 	mov	ip, sp
     f18:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     f1c:	e24cb004 	sub	fp, ip, #4	; 0x4
     f20:	e24dd008 	sub	sp, sp, #8	; 0x8
     f24:	e50b0014 	str	r0, [fp, #-20]
{	
	uint32_t c1format;
   	asm volatile ("  MRC      p15, 0, r0, c1, c0 ,0"
   	              : "=r"(c1format)
   	              );
     f28:	ee110f10 	mrc	15, 0, r0, cr1, cr0, {0}
     f2c:	e50b3010 	str	r3, [fp, #-16]
   	              
   	c1format = c1format | mask;
     f30:	e51b2010 	ldr	r2, [fp, #-16]
     f34:	e51b3014 	ldr	r3, [fp, #-20]
     f38:	e1823003 	orr	r3, r2, r3
     f3c:	e50b3010 	str	r3, [fp, #-16]
   	
	asm volatile ("  MCR      p15, 0, r0, c1, c0 ,0"
            	  :
                  : "r" (c1format)
                  );
     f40:	e51b3010 	ldr	r3, [fp, #-16]
     f44:	ee010f10 	mcr	15, 0, r0, cr1, cr0, {0}
}
     f48:	e24bd00c 	sub	sp, fp, #12	; 0xc
     f4c:	e89da800 	ldmia	sp, {fp, sp, pc}

00000f50 <CPU::EnableFastContextSwitch()>:
     f50:	e1a0c00d 	mov	ip, sp
     f54:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     f58:	e24cb004 	sub	fp, ip, #4	; 0x4
     f5c:	e3a00103 	mov	r0, #-1073741824	; 0xc0000000
     f60:	ebffffeb 	bl	f14 <CPU::setCoprocessorRegisterBits(unsigned long)>
     f64:	e89da800 	ldmia	sp, {fp, sp, pc}

00000f68 <CPU::EnableDCache()>:
     f68:	e1a0c00d 	mov	ip, sp
     f6c:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     f70:	e24cb004 	sub	fp, ip, #4	; 0x4
     f74:	e3a00004 	mov	r0, #4	; 0x4
     f78:	ebffffe5 	bl	f14 <CPU::setCoprocessorRegisterBits(unsigned long)>
     f7c:	e89da800 	ldmia	sp, {fp, sp, pc}

00000f80 <CPU::EnableICache()>:
     f80:	e1a0c00d 	mov	ip, sp
     f84:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     f88:	e24cb004 	sub	fp, ip, #4	; 0x4
     f8c:	e3a00a01 	mov	r0, #4096	; 0x1000
     f90:	ebffffdf 	bl	f14 <CPU::setCoprocessorRegisterBits(unsigned long)>
     f94:	e89da800 	ldmia	sp, {fp, sp, pc}

00000f98 <CPU::EnableMMU()>:
     f98:	e1a0c00d 	mov	ip, sp
     f9c:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     fa0:	e24cb004 	sub	fp, ip, #4	; 0x4
     fa4:	e3a00001 	mov	r0, #1	; 0x1
     fa8:	ebffffd9 	bl	f14 <CPU::setCoprocessorRegisterBits(unsigned long)>
     fac:	e89da800 	ldmia	sp, {fp, sp, pc}

00000fb0 <CPU::clearCoprocessorRegisterBits(unsigned long)>:

void CPU::clearCoprocessorRegisterBits(uint32_t mask)
     fb0:	e1a0c00d 	mov	ip, sp
     fb4:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     fb8:	e24cb004 	sub	fp, ip, #4	; 0x4
     fbc:	e24dd008 	sub	sp, sp, #8	; 0x8
     fc0:	e50b0014 	str	r0, [fp, #-20]
{	
	uint32_t c1format;
   	asm volatile ("  MRC      p15, 0, r0 , c1, c0 ,0"
   	              : "=r"(c1format)
   	              );
     fc4:	ee110f10 	mrc	15, 0, r0, cr1, cr0, {0}
     fc8:	e50b3010 	str	r3, [fp, #-16]
   	c1format = c1format & ~mask;
     fcc:	e51b3014 	ldr	r3, [fp, #-20]
     fd0:	e1e02003 	mvn	r2, r3
     fd4:	e51b3010 	ldr	r3, [fp, #-16]
     fd8:	e0033002 	and	r3, r3, r2
     fdc:	e50b3010 	str	r3, [fp, #-16]
   	
	asm volatile ("  MCR      p15, 0, r0, c1, c0 ,0"
            	  :
            	  : "r" (c1format)
            	  );
     fe0:	e51b3010 	ldr	r3, [fp, #-16]
     fe4:	ee010f10 	mcr	15, 0, r0, cr1, cr0, {0}
}
     fe8:	e24bd00c 	sub	sp, fp, #12	; 0xc
     fec:	e89da800 	ldmia	sp, {fp, sp, pc}

00000ff0 <CPU::DisableFastContextSwitch()>:
     ff0:	e1a0c00d 	mov	ip, sp
     ff4:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
     ff8:	e24cb004 	sub	fp, ip, #4	; 0x4
     ffc:	e3a00103 	mov	r0, #-1073741824	; 0xc0000000
    1000:	ebffffea 	bl	fb0 <CPU::clearCoprocessorRegisterBits(unsigned long)>
    1004:	e89da800 	ldmia	sp, {fp, sp, pc}

00001008 <CPU::DisableDCache()>:
    1008:	e1a0c00d 	mov	ip, sp
    100c:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
    1010:	e24cb004 	sub	fp, ip, #4	; 0x4
    1014:	e3a00004 	mov	r0, #4	; 0x4
    1018:	ebffffe4 	bl	fb0 <CPU::clearCoprocessorRegisterBits(unsigned long)>
    101c:	e89da800 	ldmia	sp, {fp, sp, pc}

00001020 <CPU::DisableICache()>:
    1020:	e1a0c00d 	mov	ip, sp
    1024:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
    1028:	e24cb004 	sub	fp, ip, #4	; 0x4
    102c:	e3a00a01 	mov	r0, #4096	; 0x1000
    1030:	ebffffde 	bl	fb0 <CPU::clearCoprocessorRegisterBits(unsigned long)>
    1034:	e89da800 	ldmia	sp, {fp, sp, pc}

00001038 <CPU::DisableMMU()>:
    1038:	e1a0c00d 	mov	ip, sp
    103c:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
    1040:	e24cb004 	sub	fp, ip, #4	; 0x4
    1044:	e3a00001 	mov	r0, #1	; 0x1
    1048:	ebffffd8 	bl	fb0 <CPU::clearCoprocessorRegisterBits(unsigned long)>
    104c:	e89da800 	ldmia	sp, {fp, sp, pc}

00001050 <CPU::InitializeChipSelectTwo(unsigned long, unsigned long, BUS_WIDTH, CYCLES, CYCLES, CYCLES, CYCLES)>:
    1050:	e1a0c00d 	mov	ip, sp
    1054:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
    1058:	e24cb004 	sub	fp, ip, #4	; 0x4
    105c:	e24dd010 	sub	sp, sp, #16	; 0x10
    1060:	e50b0010 	str	r0, [fp, #-16]
    1064:	e50b1014 	str	r1, [fp, #-20]
    1068:	e50b2018 	str	r2, [fp, #-24]
    106c:	e50b301c 	str	r3, [fp, #-28]
    1070:	e51b3018 	ldr	r3, [fp, #-24]
    1074:	e3a00020 	mov	r0, #32	; 0x20
    1078:	e59f10d0 	ldr	r1, [pc, #208]	; 1150 <.text+0x1150>
    107c:	e1a02003 	mov	r2, r3
    1080:	e59f30cc 	ldr	r3, [pc, #204]	; 1154 <.text+0x1154>
    1084:	e1a0e00f 	mov	lr, pc
    1088:	e12fff13 	bx	r3
    108c:	e51b2010 	ldr	r2, [fp, #-16]
    1090:	e51b3014 	ldr	r3, [fp, #-20]
    1094:	e0823003 	add	r3, r2, r3
    1098:	e2433001 	sub	r3, r3, #1	; 0x1
    109c:	e1a03823 	mov	r3, r3, lsr #16
    10a0:	e3a00008 	mov	r0, #8	; 0x8
    10a4:	e59f10ac 	ldr	r1, [pc, #172]	; 1158 <.text+0x1158>
    10a8:	e1a02003 	mov	r2, r3
    10ac:	e59f30a0 	ldr	r3, [pc, #160]	; 1154 <.text+0x1154>
    10b0:	e1a0e00f 	mov	lr, pc
    10b4:	e12fff13 	bx	r3
    10b8:	e51b3010 	ldr	r3, [fp, #-16]
    10bc:	e1a03823 	mov	r3, r3, lsr #16
    10c0:	e3a00008 	mov	r0, #8	; 0x8
    10c4:	e59f1090 	ldr	r1, [pc, #144]	; 115c <.text+0x115c>
    10c8:	e1a02003 	mov	r2, r3
    10cc:	e59f3080 	ldr	r3, [pc, #128]	; 1154 <.text+0x1154>
    10d0:	e1a0e00f 	mov	lr, pc
    10d4:	e12fff13 	bx	r3
    10d8:	e51b301c 	ldr	r3, [fp, #-28]
    10dc:	e3a00008 	mov	r0, #8	; 0x8
    10e0:	e59f1078 	ldr	r1, [pc, #120]	; 1160 <.text+0x1160>
    10e4:	e1a02003 	mov	r2, r3
    10e8:	e59f3064 	ldr	r3, [pc, #100]	; 1154 <.text+0x1154>
    10ec:	e1a0e00f 	mov	lr, pc
    10f0:	e12fff13 	bx	r3
    10f4:	e59b3004 	ldr	r3, [fp, #4]
    10f8:	e3a00008 	mov	r0, #8	; 0x8
    10fc:	e59f1060 	ldr	r1, [pc, #96]	; 1164 <.text+0x1164>
    1100:	e1a02003 	mov	r2, r3
    1104:	e59f3048 	ldr	r3, [pc, #72]	; 1154 <.text+0x1154>
    1108:	e1a0e00f 	mov	lr, pc
    110c:	e12fff13 	bx	r3
    1110:	e59b3008 	ldr	r3, [fp, #8]
    1114:	e3a00008 	mov	r0, #8	; 0x8
    1118:	e59f1048 	ldr	r1, [pc, #72]	; 1168 <.text+0x1168>
    111c:	e1a02003 	mov	r2, r3
    1120:	e59f302c 	ldr	r3, [pc, #44]	; 1154 <.text+0x1154>
    1124:	e1a0e00f 	mov	lr, pc
    1128:	e12fff13 	bx	r3
    112c:	e59b300c 	ldr	r3, [fp, #12]
    1130:	e3a00008 	mov	r0, #8	; 0x8
    1134:	e3a01003 	mov	r1, #3	; 0x3
    1138:	e1a02003 	mov	r2, r3
    113c:	e59f3010 	ldr	r3, [pc, #16]	; 1154 <.text+0x1154>
    1140:	e1a0e00f 	mov	lr, pc
    1144:	e12fff13 	bx	r3
    1148:	e24bd00c 	sub	sp, fp, #12	; 0xc
    114c:	e89da800 	ldmia	sp, {fp, sp, pc}
    1150:	00140002 	andeqs	r0, r4, r2
    1154:	00001434 	andeq	r1, r0, r4, lsr r4
    1158:	0016000a 	andeqs	r0, r6, sl
    115c:	000c000a 	andeq	r0, ip, sl
    1160:	00090003 	andeq	r0, r9, r3
    1164:	00060003 	andeq	r0, r6, r3
    1168:	00030003 	andeq	r0, r3, r3

0000116c <CPU::InitializeChipSelectOne(unsigned long, unsigned long, BUS_WIDTH, CYCLES, CYCLES, CYCLES, CYCLES)>:
    116c:	e1a0c00d 	mov	ip, sp
    1170:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
    1174:	e24cb004 	sub	fp, ip, #4	; 0x4
    1178:	e24dd010 	sub	sp, sp, #16	; 0x10
    117c:	e50b0010 	str	r0, [fp, #-16]
    1180:	e50b1014 	str	r1, [fp, #-20]
    1184:	e50b2018 	str	r2, [fp, #-24]
    1188:	e50b301c 	str	r3, [fp, #-28]
    118c:	e51b3018 	ldr	r3, [fp, #-24]
    1190:	e3a00020 	mov	r0, #32	; 0x20
    1194:	e59f10d0 	ldr	r1, [pc, #208]	; 126c <.text+0x126c>
    1198:	e1a02003 	mov	r2, r3
    119c:	e59f30cc 	ldr	r3, [pc, #204]	; 1270 <.text+0x1270>
    11a0:	e1a0e00f 	mov	lr, pc
    11a4:	e12fff13 	bx	r3
    11a8:	e51b2010 	ldr	r2, [fp, #-16]
    11ac:	e51b3014 	ldr	r3, [fp, #-20]
    11b0:	e0823003 	add	r3, r2, r3
    11b4:	e2433001 	sub	r3, r3, #1	; 0x1
    11b8:	e1a03823 	mov	r3, r3, lsr #16
    11bc:	e3a00004 	mov	r0, #4	; 0x4
    11c0:	e59f10ac 	ldr	r1, [pc, #172]	; 1274 <.text+0x1274>
    11c4:	e1a02003 	mov	r2, r3
    11c8:	e59f30a0 	ldr	r3, [pc, #160]	; 1270 <.text+0x1270>
    11cc:	e1a0e00f 	mov	lr, pc
    11d0:	e12fff13 	bx	r3
    11d4:	e51b3010 	ldr	r3, [fp, #-16]
    11d8:	e1a03823 	mov	r3, r3, lsr #16
    11dc:	e3a00004 	mov	r0, #4	; 0x4
    11e0:	e59f1090 	ldr	r1, [pc, #144]	; 1278 <.text+0x1278>
    11e4:	e1a02003 	mov	r2, r3
    11e8:	e59f3080 	ldr	r3, [pc, #128]	; 1270 <.text+0x1270>
    11ec:	e1a0e00f 	mov	lr, pc
    11f0:	e12fff13 	bx	r3
    11f4:	e51b301c 	ldr	r3, [fp, #-28]
    11f8:	e3a00004 	mov	r0, #4	; 0x4
    11fc:	e59f1078 	ldr	r1, [pc, #120]	; 127c <.text+0x127c>
    1200:	e1a02003 	mov	r2, r3
    1204:	e59f3064 	ldr	r3, [pc, #100]	; 1270 <.text+0x1270>
    1208:	e1a0e00f 	mov	lr, pc
    120c:	e12fff13 	bx	r3
    1210:	e59b3004 	ldr	r3, [fp, #4]
    1214:	e3a00004 	mov	r0, #4	; 0x4
    1218:	e59f1060 	ldr	r1, [pc, #96]	; 1280 <.text+0x1280>
    121c:	e1a02003 	mov	r2, r3
    1220:	e59f3048 	ldr	r3, [pc, #72]	; 1270 <.text+0x1270>
    1224:	e1a0e00f 	mov	lr, pc
    1228:	e12fff13 	bx	r3
    122c:	e59b3008 	ldr	r3, [fp, #8]
    1230:	e3a00004 	mov	r0, #4	; 0x4
    1234:	e59f1048 	ldr	r1, [pc, #72]	; 1284 <.text+0x1284>
    1238:	e1a02003 	mov	r2, r3
    123c:	e59f302c 	ldr	r3, [pc, #44]	; 1270 <.text+0x1270>
    1240:	e1a0e00f 	mov	lr, pc
    1244:	e12fff13 	bx	r3
    1248:	e59b300c 	ldr	r3, [fp, #12]
    124c:	e3a00004 	mov	r0, #4	; 0x4
    1250:	e3a01003 	mov	r1, #3	; 0x3
    1254:	e1a02003 	mov	r2, r3
    1258:	e59f3010 	ldr	r3, [pc, #16]	; 1270 <.text+0x1270>
    125c:	e1a0e00f 	mov	lr, pc
    1260:	e12fff13 	bx	r3
    1264:	e24bd00c 	sub	sp, fp, #12	; 0xc
    1268:	e89da800 	ldmia	sp, {fp, sp, pc}
    126c:	00120002 	andeqs	r0, r2, r2
    1270:	00001434 	andeq	r1, r0, r4, lsr r4
    1274:	0016000a 	andeqs	r0, r6, sl
    1278:	000c000a 	andeq	r0, ip, sl
    127c:	00090003 	andeq	r0, r9, r3
    1280:	00060003 	andeq	r0, r6, r3
    1284:	00030003 	andeq	r0, r3, r3

00001288 <CPU::InitializeChipSelectZero(unsigned long, unsigned long, BUS_WIDTH, CYCLES, CYCLES, CYCLES, CYCLES)>:
    1288:	e1a0c00d 	mov	ip, sp
    128c:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
    1290:	e24cb004 	sub	fp, ip, #4	; 0x4
    1294:	e24dd010 	sub	sp, sp, #16	; 0x10
    1298:	e50b0010 	str	r0, [fp, #-16]
    129c:	e50b1014 	str	r1, [fp, #-20]
    12a0:	e50b2018 	str	r2, [fp, #-24]
    12a4:	e50b301c 	str	r3, [fp, #-28]
    12a8:	e51b3018 	ldr	r3, [fp, #-24]
    12ac:	e3a00020 	mov	r0, #32	; 0x20
    12b0:	e59f10d0 	ldr	r1, [pc, #208]	; 1388 <.text+0x1388>
    12b4:	e1a02003 	mov	r2, r3
    12b8:	e59f30cc 	ldr	r3, [pc, #204]	; 138c <.text+0x138c>
    12bc:	e1a0e00f 	mov	lr, pc
    12c0:	e12fff13 	bx	r3
    12c4:	e51b2010 	ldr	r2, [fp, #-16]
    12c8:	e51b3014 	ldr	r3, [fp, #-20]
    12cc:	e0823003 	add	r3, r2, r3
    12d0:	e2433001 	sub	r3, r3, #1	; 0x1
    12d4:	e1a03823 	mov	r3, r3, lsr #16
    12d8:	e3a00000 	mov	r0, #0	; 0x0
    12dc:	e59f10ac 	ldr	r1, [pc, #172]	; 1390 <.text+0x1390>
    12e0:	e1a02003 	mov	r2, r3
    12e4:	e59f30a0 	ldr	r3, [pc, #160]	; 138c <.text+0x138c>
    12e8:	e1a0e00f 	mov	lr, pc
    12ec:	e12fff13 	bx	r3
    12f0:	e51b3010 	ldr	r3, [fp, #-16]
    12f4:	e1a03823 	mov	r3, r3, lsr #16
    12f8:	e3a00000 	mov	r0, #0	; 0x0
    12fc:	e59f1090 	ldr	r1, [pc, #144]	; 1394 <.text+0x1394>
    1300:	e1a02003 	mov	r2, r3
    1304:	e59f3080 	ldr	r3, [pc, #128]	; 138c <.text+0x138c>
    1308:	e1a0e00f 	mov	lr, pc
    130c:	e12fff13 	bx	r3
    1310:	e51b301c 	ldr	r3, [fp, #-28]
    1314:	e3a00000 	mov	r0, #0	; 0x0
    1318:	e59f1078 	ldr	r1, [pc, #120]	; 1398 <.text+0x1398>
    131c:	e1a02003 	mov	r2, r3
    1320:	e59f3064 	ldr	r3, [pc, #100]	; 138c <.text+0x138c>
    1324:	e1a0e00f 	mov	lr, pc
    1328:	e12fff13 	bx	r3
    132c:	e59b3004 	ldr	r3, [fp, #4]
    1330:	e3a00000 	mov	r0, #0	; 0x0
    1334:	e59f1060 	ldr	r1, [pc, #96]	; 139c <.text+0x139c>
    1338:	e1a02003 	mov	r2, r3
    133c:	e59f3048 	ldr	r3, [pc, #72]	; 138c <.text+0x138c>
    1340:	e1a0e00f 	mov	lr, pc
    1344:	e12fff13 	bx	r3
    1348:	e59b3008 	ldr	r3, [fp, #8]
    134c:	e3a00000 	mov	r0, #0	; 0x0
    1350:	e59f1048 	ldr	r1, [pc, #72]	; 13a0 <.text+0x13a0>
    1354:	e1a02003 	mov	r2, r3
    1358:	e59f302c 	ldr	r3, [pc, #44]	; 138c <.text+0x138c>
    135c:	e1a0e00f 	mov	lr, pc
    1360:	e12fff13 	bx	r3
    1364:	e59b300c 	ldr	r3, [fp, #12]
    1368:	e3a00000 	mov	r0, #0	; 0x0
    136c:	e3a01003 	mov	r1, #3	; 0x3
    1370:	e1a02003 	mov	r2, r3
    1374:	e59f3010 	ldr	r3, [pc, #16]	; 138c <.text+0x138c>
    1378:	e1a0e00f 	mov	lr, pc
    137c:	e12fff13 	bx	r3
    1380:	e24bd00c 	sub	sp, fp, #12	; 0xc
    1384:	e89da800 	ldmia	sp, {fp, sp, pc}
    1388:	00100002 	andeqs	r0, r0, r2
    138c:	00001434 	andeq	r1, r0, r4, lsr r4
    1390:	0016000a 	andeqs	r0, r6, sl
    1394:	000c000a 	andeq	r0, ip, sl
    1398:	00090003 	andeq	r0, r9, r3
    139c:	00060003 	andeq	r0, r6, r3
    13a0:	00030003 	andeq	r0, r3, r3

000013a4 <BUS_CONTROL::regAddress(BUS_CONTROL::Registers)>:
	{
		CLKCON	= 0x0004		// 0x00	- System Clock and Bus Control Register (rw)
	};
	
	inline volatile uint32_t *regAddress(Registers reg)
    13a4:	e1a0c00d 	mov	ip, sp
    13a8:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
    13ac:	e24cb004 	sub	fp, ip, #4	; 0x4
    13b0:	e24dd004 	sub	sp, sp, #4	; 0x4
    13b4:	e50b0010 	str	r0, [fp, #-16]
	{
	    return reinterpret_cast<volatile uint32_t*>(BaseAddress + reg);
    13b8:	e51b3010 	ldr	r3, [fp, #-16]
    13bc:	e28337ff 	add	r3, r3, #66846720	; 0x3fc0000
    13c0:	e2833803 	add	r3, r3, #196608	; 0x30000
	}
    13c4:	e1a00003 	mov	r0, r3
    13c8:	e89da808 	ldmia	sp, {r3, fp, sp, pc}

000013cc <BUS_CONTROL::regWrite(BUS_CONTROL::Registers, unsigned long)>:
	
	inline uint32_t regRead(Registers reg)
	{
	    return *regAddress(reg);
	}
	
	inline void regWrite(Registers reg, uint32_t value)
    13cc:	e1a0c00d 	mov	ip, sp
    13d0:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
    13d4:	e24cb004 	sub	fp, ip, #4	; 0x4
    13d8:	e24dd008 	sub	sp, sp, #8	; 0x8
    13dc:	e50b0010 	str	r0, [fp, #-16]
    13e0:	e50b1014 	str	r1, [fp, #-20]
	{
	    *regAddress(reg) = value;
    13e4:	e51b0010 	ldr	r0, [fp, #-16]
    13e8:	e59f3018 	ldr	r3, [pc, #24]	; 1408 <.text+0x1408>
    13ec:	e1a0e00f 	mov	lr, pc
    13f0:	e12fff13 	bx	r3
    13f4:	e1a02000 	mov	r2, r0
    13f8:	e51b3014 	ldr	r3, [fp, #-20]
    13fc:	e5823000 	str	r3, [r2]
	}
    1400:	e24bd00c 	sub	sp, fp, #12	; 0xc
    1404:	e89da800 	ldmia	sp, {fp, sp, pc}
    1408:	000013a4 	andeq	r1, r0, r4, lsr #7

0000140c <EXTERNAL_IO::regAddress(EXTERNAL_IO::Registers)>:
		BUS_WIDTH_FOR_FLASH_BANK_1		= REGISTER_BIT_DEFINITION( 3,  2),
		BUS_WIDTH_FOR_FLASH_BANK_0		= REGISTER_BIT_DEFINITION( 1,  0)				
	};
	
	inline volatile uint32_t *regAddress(Registers reg)
    140c:	e1a0c00d 	mov	ip, sp
    1410:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
    1414:	e24cb004 	sub	fp, ip, #4	; 0x4
    1418:	e24dd004 	sub	sp, sp, #4	; 0x4
    141c:	e50b0010 	str	r0, [fp, #-16]
	{
	    return reinterpret_cast<volatile uint32_t*>(BaseAddress + reg);
    1420:	e51b3010 	ldr	r3, [fp, #-16]
    1424:	e28337ff 	add	r3, r3, #66846720	; 0x3fc0000
    1428:	e283390d 	add	r3, r3, #212992	; 0x34000
	}
    142c:	e1a00003 	mov	r0, r3
    1430:	e89da808 	ldmia	sp, {r3, fp, sp, pc}

00001434 <void bitWrite<EXTERNAL_IO::Registers>(EXTERNAL_IO::Registers, unsigned long, unsigned long)>:
	return regval;
}

template <typename RegType>
void bitWrite(RegType reg, uint32_t bits, uint32_t value)
    1434:	e1a0c00d 	mov	ip, sp
    1438:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
    143c:	e24cb004 	sub	fp, ip, #4	; 0x4
    1440:	e24dd018 	sub	sp, sp, #24	; 0x18
    1444:	e50b001c 	str	r0, [fp, #-28]
    1448:	e50b1020 	str	r1, [fp, #-32]
    144c:	e50b2024 	str	r2, [fp, #-36]
{
	uint32_t regval = *regAddress(reg);
    1450:	e51b001c 	ldr	r0, [fp, #-28]
    1454:	e59f3090 	ldr	r3, [pc, #144]	; 14ec <.text+0x14ec>
    1458:	e1a0e00f 	mov	lr, pc
    145c:	e12fff13 	bx	r3
    1460:	e1a03000 	mov	r3, r0
    1464:	e5933000 	ldr	r3, [r3]
    1468:	e50b3018 	str	r3, [fp, #-24]
	const uint32_t width = bits & 0xff;
    146c:	e51b3020 	ldr	r3, [fp, #-32]
    1470:	e20330ff 	and	r3, r3, #255	; 0xff
    1474:	e50b3014 	str	r3, [fp, #-20]
	const uint32_t bitno = bits >> 16;
    1478:	e51b3020 	ldr	r3, [fp, #-32]
    147c:	e1a03823 	mov	r3, r3, lsr #16
    1480:	e50b3010 	str	r3, [fp, #-16]
	regval &= ~(((1 << width) - 1) << bitno);
    1484:	e51b2014 	ldr	r2, [fp, #-20]
    1488:	e3a03001 	mov	r3, #1	; 0x1
    148c:	e1a03213 	mov	r3, r3, lsl r2
    1490:	e2432001 	sub	r2, r3, #1	; 0x1
    1494:	e51b3010 	ldr	r3, [fp, #-16]
    1498:	e1a03312 	mov	r3, r2, lsl r3
    149c:	e1e03003 	mvn	r3, r3
    14a0:	e1a02003 	mov	r2, r3
    14a4:	e51b3018 	ldr	r3, [fp, #-24]
    14a8:	e0033002 	and	r3, r3, r2
    14ac:	e50b3018 	str	r3, [fp, #-24]
	regval |= value << bitno;
    14b0:	e51b2010 	ldr	r2, [fp, #-16]
    14b4:	e51b3024 	ldr	r3, [fp, #-36]
    14b8:	e1a02213 	mov	r2, r3, lsl r2
    14bc:	e51b3018 	ldr	r3, [fp, #-24]
    14c0:	e1833002 	orr	r3, r3, r2
    14c4:	e50b3018 	str	r3, [fp, #-24]
	*regAddress(reg) = regval;
    14c8:	e51b001c 	ldr	r0, [fp, #-28]
    14cc:	e59f3018 	ldr	r3, [pc, #24]	; 14ec <.text+0x14ec>
    14d0:	e1a0e00f 	mov	lr, pc
    14d4:	e12fff13 	bx	r3
    14d8:	e1a02000 	mov	r2, r0
    14dc:	e51b3018 	ldr	r3, [fp, #-24]
    14e0:	e5823000 	str	r3, [r2]
    14e4:	e24bd00c 	sub	sp, fp, #12	; 0xc
    14e8:	e89da800 	ldmia	sp, {fp, sp, pc}
    14ec:	0000140c 	andeq	r1, r0, ip, lsl #8

000014f0 <__aeabi_uidiv>:
    14f0:	e2512001 	subs	r2, r1, #1	; 0x1
    14f4:	012fff1e 	bxeq	lr
    14f8:	3a000036 	bcc	15d8 <__aeabi_uidiv+0xe8>
    14fc:	e1500001 	cmp	r0, r1
    1500:	9a000022 	bls	1590 <__aeabi_uidiv+0xa0>
    1504:	e1110002 	tst	r1, r2
    1508:	0a000023 	beq	159c <__aeabi_uidiv+0xac>
    150c:	e311020e 	tst	r1, #-536870912	; 0xe0000000
    1510:	01a01181 	moveq	r1, r1, lsl #3
    1514:	03a03008 	moveq	r3, #8	; 0x8
    1518:	13a03001 	movne	r3, #1	; 0x1
    151c:	e3510201 	cmp	r1, #268435456	; 0x10000000
    1520:	31510000 	cmpcc	r1, r0
    1524:	31a01201 	movcc	r1, r1, lsl #4
    1528:	31a03203 	movcc	r3, r3, lsl #4
    152c:	3afffffa 	bcc	151c <__aeabi_uidiv+0x2c>
    1530:	e3510102 	cmp	r1, #-2147483648	; 0x80000000
    1534:	31510000 	cmpcc	r1, r0
    1538:	31a01081 	movcc	r1, r1, lsl #1
    153c:	31a03083 	movcc	r3, r3, lsl #1
    1540:	3afffffa 	bcc	1530 <__aeabi_uidiv+0x40>
    1544:	e3a02000 	mov	r2, #0	; 0x0
    1548:	e1500001 	cmp	r0, r1
    154c:	20400001 	subcs	r0, r0, r1
    1550:	21822003 	orrcs	r2, r2, r3
    1554:	e15000a1 	cmp	r0, r1, lsr #1
    1558:	204000a1 	subcs	r0, r0, r1, lsr #1
    155c:	218220a3 	orrcs	r2, r2, r3, lsr #1
    1560:	e1500121 	cmp	r0, r1, lsr #2
    1564:	20400121 	subcs	r0, r0, r1, lsr #2
    1568:	21822123 	orrcs	r2, r2, r3, lsr #2
    156c:	e15001a1 	cmp	r0, r1, lsr #3
    1570:	204001a1 	subcs	r0, r0, r1, lsr #3
    1574:	218221a3 	orrcs	r2, r2, r3, lsr #3
    1578:	e3500000 	cmp	r0, #0	; 0x0
    157c:	11b03223 	movnes	r3, r3, lsr #4
    1580:	11a01221 	movne	r1, r1, lsr #4
    1584:	1affffef 	bne	1548 <__aeabi_uidiv+0x58>
    1588:	e1a00002 	mov	r0, r2
    158c:	e12fff1e 	bx	lr
    1590:	03a00001 	moveq	r0, #1	; 0x1
    1594:	13a00000 	movne	r0, #0	; 0x0
    1598:	e12fff1e 	bx	lr
    159c:	e3510801 	cmp	r1, #65536	; 0x10000
    15a0:	21a01821 	movcs	r1, r1, lsr #16
    15a4:	23a02010 	movcs	r2, #16	; 0x10
    15a8:	33a02000 	movcc	r2, #0	; 0x0
    15ac:	e3510c01 	cmp	r1, #256	; 0x100
    15b0:	21a01421 	movcs	r1, r1, lsr #8
    15b4:	22822008 	addcs	r2, r2, #8	; 0x8
    15b8:	e3510010 	cmp	r1, #16	; 0x10
    15bc:	21a01221 	movcs	r1, r1, lsr #4
    15c0:	22822004 	addcs	r2, r2, #4	; 0x4
    15c4:	e3510004 	cmp	r1, #4	; 0x4
    15c8:	82822003 	addhi	r2, r2, #3	; 0x3
    15cc:	908220a1 	addls	r2, r2, r1, lsr #1
    15d0:	e1a00230 	mov	r0, r0, lsr r2
    15d4:	e12fff1e 	bx	lr
    15d8:	e52de008 	str	lr, [sp, #-8]!
    15dc:	eb000007 	bl	1600 <__aeabi_idiv0>
    15e0:	e3a00000 	mov	r0, #0	; 0x0
    15e4:	e49df008 	ldr	pc, [sp], #8

000015e8 <__aeabi_uidivmod>:
    15e8:	e92d4003 	stmdb	sp!, {r0, r1, lr}
    15ec:	ebffffbf 	bl	14f0 <__aeabi_uidiv>
    15f0:	e8bd4006 	ldmia	sp!, {r1, r2, lr}
    15f4:	e0030092 	mul	r3, r2, r0
    15f8:	e0411003 	sub	r1, r1, r3
    15fc:	e12fff1e 	bx	lr

00001600 <__aeabi_idiv0>:
    1600:	e12fff1e 	bx	lr
    1604:	6c6c6548 	cfstr64vs	mvdx6, [ip], #-288
    1608:	7266206f 	rsbvc	r2, r6, #111	; 0x6f
    160c:	74206d6f 	strvct	r6, [r0], #-3439
    1610:	42206568 	eormi	r6, r0, #436207616	; 0x1a000000
    1614:	41534f49 	cmpmi	r3, r9, asr #30
    1618:	55504320 	ldrplb	r4, [r0, #-800]
    161c:	616f6220 	cmnvs	pc, r0, lsr #4
    1620:	00206472 	eoreq	r6, r0, r2, ror r4
    1624:	0000000a 	andeq	r0, r0, sl