/******************************  sleepydwarf.h  *****************************
 * $Source: /home/cvs/ESP/gen2/software/msp430/include/sleepydwarf.h,v $
 *  Copyright (C) 2003 MBARI
 *
 *  MBARI Proprietary Information. All rights reserved.
 * $Id: sleepydwarf.h,v 1.2 2005/04/07 22:32:55 brent Exp $
 *
 * This header documents the hardware interface between the
 * 'sleepy' MSP430F1xx microcontroller and its motherboard,
 * particularly the registers in the board's CPLD.
 *
 *****************************************************************************/

#ifndef sleepydwarf_h
#define sleepydwarf_h

// Status LEDs
// PWM control is on port 4 (TIMER B)
#define SLPYLEDOUT  P4OUT
#define SLPYLEDSEL  P4SEL
#define SLPYLEDDIR  P4DIR
#define SLPYGRN     0x1     //Green LED active high
#define SLPYRED     0x2     //Red LED active high
#define SLPYYEL     0x4     //Yellow LED active high

// Misc. Control outputs
#define SLPYCTLOUT  P5OUT
#define SLPYCTLSEL  P5SEL
#define SLPYCTLDIR  P5DIR
#define SLPYCMDTXEN 0x1     //command port power (1=on)
#define SLPYCMDRXDI 0x2     //command port receiver disable (1=disabled)
#define SLPYMUX104  0x4     //octal usart bus mux (1=PC/104, 0=sleepy)
#define SLPYENVON   0x8     //environmental sensor enable (1=on)

//sleepy must override the usual clock output setup
#define initDWRFCLKS() { \
  SLPYCTLOUT = ~SLPYMUX104; /*insure PC/104 bus is not selected on power up */ \
  SLPYCTLSEL = 0x70;  /* drive MCLK out P5.4, SMCLK out P5.5, ACLK out P5.6 */ \
  SLPYCTLDIR = -1; \
}

// Analog Environmental Sensor
#define SLPYENVIN   P6IN
#define SLPYENVSEL  P6SEL
#define SLPYENVDIR  P6DIR

// CPLD Registers unique to 'Sleepy', bits are:
#define SLPYCONNECT   2     //high to energize latching relay to connect a port
#define SLPYLOOP      3     //high to energize latching relay to isolate a port
#define SLPYRXDI      4     //high to disable the receiver for a port
#define SLPYTXEN      5     //high to enable the transceiver for a port
#define SLPYPWRCTL1   6     //power distribution control register 1
#define SLPYPWRCTL2   7     //power distribution control register 2
#define SLPY104ADR    8     //upper 8 bits of base address for octal usart


// serial ports for SLPYCONNECT, SLPYISOLATE, SLPYPORTRDI & SLPYPORTON
enum {
  SLPYCONSENS0,SLPYCONSENS1, SLPYCONSENS2,  //contextual sensors
  SLPYAMOD0, SLPYAMOD1, SLPYAMOD2,          //analytical modules
  SLPYEXTSAMP, SLPYMODEM,                   //external sampler, (radio) modem
  SLPYPORTS
};                

// SLPYPWRCTL1 power control bits, all active high
#define SLPYSYSPWR     0x1     //main power for system and PC/104 stack
#define SLPYDWARFPWR   0x2     //power for dwarves on the I2C bus
#define SLPYCAMERAPWR  0x4     //power for USB camera
#define SLPYAMOD0PWR   (1<<SLPYAMOD0)  //power to analytical module 0
#define SLPYAMOD1PWR   (1<<SLPYAMOD1)  //power to analytical module 1
#define SLPYAMOD2PWR   (1<<SLPYAMOD2)  //power to analytical module 2
#define SLPYEXTSAMPPWR (1<<SLPYEXTSAMP) //external sampler power
#define SLPYMODEMPWR   (1<<SLPYMODEM)  //radio modem power

// SLPYPWRCTL2 power control bits, all active high
#define SLPYRAWPWR  0x1     //high to turn on raw power out to the other dwarves


#endif