1. In the FRR_Control window:	press FPGA_Load
2. In the FRR_DATA window:
	Select PROTOCOL Page
	Press Get_Protocol
	Edit Protocol if necessary 
		(keep the time interval between flashes at 1 us for now)
	Press Parse_Protocol
	Press Save_Seq_File
3. Go back to the FIT page, Press Load SEQ, and select sequencer file
4. Select number of runs (keep nmber of runs at one when adjusting the    gain), press START
5. Adjust the FGain
6. Select number of runs
7. Press START to acquire the data
8. Form the File menu press SaveASCIIData to store the data
9. Press FIT to reduce the data
10. From the File menu, press SaveResults to store the results