(ExpressProject "Time Lapse"
  (ProjectVersion "19981106")
  (ProjectType "PCB")
  (Folder "Design Resources"
    (Folder "Library")
    (NoModify)
    (File ".\time lapse.dsn"
      (Type "Schematic Design"))
    (BuildFileAddedOrDeleted "x")
    (CompileFileAddedOrDeleted "x")
    (Board_sim_option "VHDL_flow"))
  (Folder "Outputs")
  (Folder "Referenced Projects")
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      (FullPartName "DS229.Normal")
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    ("CAP NP"
      (FullPartName "CAP NP.Normal")
      (LibraryName
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  (LastUsedLibraryBrowseDirectory "C:\Cadence\SPB_16.5\tools\capture\library")
  (GlobalState
    (FileView
      (Path "Design Resources")
      (Path "Design Resources" ".\time lapse.dsn")
      (Path "Design Resources" ".\time lapse.dsn" "SCHEMATIC1")
      (Select "Design Resources" ".\time lapse.dsn" "SCHEMATIC1" "ODI MINKL"))
    (HierarchyView)
    (Doc
      (Type "COrCapturePMDoc")
      (Frame
        (Placement "44 2 3 0 673 -4 -23 0 200 0 591"))
      (Tab 0)))
  (MPSSessionName "dacr"))