.ALIASES
R_R2            R2(1=0 2=N15389 ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS14280@ANALOG.R.Normal(chips)
R_R1            R1(1=N15389 2=BUS ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS14297@ANALOG.R.Normal(chips)
V_V1            V1(+=N14424 -=0 ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS14358@SOURCE.VPULSE.Normal(chips)
V_V3            V3(+=N15037 -=0 ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS14801@SOURCE.VDC.Normal(chips)
R_R3            R3(1=N14424 2=BUS ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS15262@ANALOG.R.Normal(chips)
V_V2            V2(+=N15602 -=0 ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS15526@SOURCE.VDC.Normal(chips)
X_U3A           U3A(+=N15389 -=N23829 V+=N15602 V-=0 OUT=N20847 ) CN @REGEN
+CIRCUIT.SCHEMATIC1(sch_1):INS18774@LIN_TECH.LT1014/LT.Normal(chips)
X_M1            M1(D=BUS G=G S=0 ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS20462@IRF.IRL2910.Normal(chips)
R_R4            R4(1=N20847 2=G ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS20732@ANALOG.R.Normal(chips)
C_C1            C1(1=G 2=BUS ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS20891@ANALOG.C.Normal(chips)
R_R5            R5(1=N15037 2=N23829 ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS23670@ANALOG.R.Normal(chips)
R_R6            R6(1=N23829 2=N20847 ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS25547@ANALOG.R.Normal(chips)
C_C2            C2(1=0 2=BUS ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS26292@ANALOG.C.Normal(chips)
C_C3            C3(1=0 2=BUS ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS31357@ANALOG.C.Normal(chips)
R_R9            R9(1=0 2=N40076 ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS31439@ANALOG.R.Normal(chips)
R_R10           R10(1=N40076 2=BUS ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS31459@ANALOG.R.Normal(chips)
V_V4            V4(+=N31531 -=0 ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS31479@SOURCE.VPULSE.Normal(chips)
R_R11           R11(1=N31531 2=BUS ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS31595@ANALOG.R.Normal(chips)
V_V6            V6(+=N31653 -=0 ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS31631@SOURCE.VDC.Normal(chips)
X_U3B           U3B(+=N40076 -=N31873 V+=N31653 V-=0 OUT=N39827 ) CN @REGEN
+CIRCUIT.SCHEMATIC1(sch_1):INS31687@LIN_TECH.LT1014/LT.Normal(chips)
X_M2            M2(D=N31833 G=G S=0 ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS31725@IRF.IRL2910.Normal(chips)
R_R12           R12(1=N39827 2=G ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS31765@ANALOG.R.Normal(chips)
R_R13           R13(1=N31573 2=N31873 ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS31835@ANALOG.R.Normal(chips)
V_V7            V7(+=N31573 -=0 ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS33397@SOURCE.VDC.Normal(chips)
R_R17           R17(1=N36907 2=BUS ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS36761@ANALOG.R.Normal(chips)
R_R15           R15(1=0 2=N41599 ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS36693@ANALOG.R.Normal(chips)
C_C5            C5(1=0 2=BUS ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS36663@ANALOG.C.Normal(chips)
X_M3            M3(D=BUS G=G S=N41599 ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS37005@IRF.IRL2910.Normal(chips)
V_V9            V9(+=N36853 -=0 ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS37191@SOURCE.VDC.Normal(chips)
R_R16           R16(1=0 2=N36907 ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS36741@ANALOG.R.Normal(chips)
V_V5            V5(+=N36833 -=0 ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS36781@SOURCE.VPULSE.Normal(chips)
R_R20           R20(1=N36853 2=N37141 ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS37117@ANALOG.R.Normal(chips)
R_R19           R19(1=N37069 2=G ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS37045@ANALOG.R.Normal(chips)
X_U4B           U4B(+=N36907 -=N37141 V+=N36933 V-=0 OUT=N37069 ) CN @REGEN
+CIRCUIT.SCHEMATIC1(sch_1):INS36967@LIN_TECH.LT1014/LT.Normal(chips)
V_V8            V8(+=N36933 -=0 ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS36911@SOURCE.VDC.Normal(chips)
R_R21           R21(1=N37141 2=N37069 ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS37163@ANALOG.R.Normal(chips)
R_R18           R18(1=N36833 2=BUS ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS36875@ANALOG.R.Normal(chips)
C_C6            C6(1=G 2=BUS ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS38392@ANALOG.C.Normal(chips)
R_R14           R14(1=N31873 2=N39827 ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS39911@ANALOG.R.Normal(chips)
R_R22           R22(1=N31833 2=BUS ) CN @REGEN CIRCUIT.SCHEMATIC1(sch_1):INS40343@ANALOG.R.Normal(chips)
_    _(GND_0=0)
_    _(GND_0=0)
_    _(GND_0=0)
_    _(bus=BUS)
_    _(bus=BUS)
_    _(bus=BUS)
_    _(g=G)
_    _(g=G)
_    _(g=G)
.ENDALIASES