(ExpressProject "SV3_Tiny_Wiring"
  (ProjectVersion "19981106")
  (SoftwareVersion "17.4-2019 P001 (3823098) [10/7/2019]-[04/24/17]")
  (ProjectType "PCB")
  (Folder "Design Resources"
    (Folder "Library")
    (NoModify)
    (File ".\sv3_tiny_wiring.dsn"
      (Type "Schematic Design"))
    (BuildFileAddedOrDeleted "x")
    (CompileFileAddedOrDeleted "x")
    (Board_sim_option "VHDL_flow")
    (DOCKED "TRUE")
    (DOCKING_POSITION "59420"))
  (Folder "Layout")
  (Folder "Outputs")
  (Folder "Referenced Projects")
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  (GlobalState
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      (Path "Design Resources" ".\sv3_tiny_wiring.dsn" "SCHEMATIC1")
      (Select "Design Resources" ".\sv3_tiny_wiring.dsn" "SCHEMATIC1"
         "1U_PAYLOADr3"))
    (HierarchyView)
    (Doc
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      (Frame
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      (Tab 0))
    (Doc
      (Type "COrSchematicDoc")
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      (Schematic "SCHEMATIC1")
      (Page "1U_PAYLOAD"))
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      (Schematic "SCHEMATIC1")
      (Page "1U_PAYLOADr2"))
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        (Scroll "-310 -10")
        (Zoom "109")
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      (Path
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      (Schematic "SCHEMATIC1")
      (Page "1U_PAYLOADr3")))
  (MPSSessionName "cwahl")
  (Folder "PSpice Resources"
    (Folder "Simulation Profiles")
    (Folder "Model Libraries"
      (Sort User))
    (Folder "Stimulus Files"
      (Sort User))
    (Folder "Include Files"
      (Sort User)))
  (Folder "Logs"))