(ExpressProject "DTN_Field_Test"
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  (ProjectType "PCB")
  (Folder "Design Resources"
    (Folder "Library")
    (NoModify)
    (File ".\dtn_field_test.dsn"
      (Type "Schematic Design"))
    (BuildFileAddedOrDeleted "x")
    (CompileFileAddedOrDeleted "x")
    (Board_sim_option "VHDL_flow"))
  (Folder "Outputs")
  (Folder "Referenced Projects")
  (PartMRUSelector
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    ("4 HEADER"
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      (DeviceIndex "0")))
  (LastUsedLibraryBrowseDirectory "C:\Cadence\SPB_16.5\tools\capture\library")
  (GlobalState
    (FileView
      (Path "Design Resources")
      (Path "Design Resources"
         "x:\901411.hotspot\engineeringdesigndocumentation\schematics_dtnfieldtest\dtn_field_test.dsn")
      (Path "Design Resources"
         "x:\901411.hotspot\engineeringdesigndocumentation\schematics_dtnfieldtest\dtn_field_test.dsn"
         "DTNFieldTest")
      (Select "Design Resources"
         "x:\901411.hotspot\engineeringdesigndocumentation\schematics_dtnfieldtest\dtn_field_test.dsn"
         "DTNFieldTest" "2012DTNFieldTest_rev.A"))
    (HierarchyView)
    (Doc
      (Type "COrCapturePMDoc")
      (Frame
        (Placement "44 2 3 -1 -1 -9 -36 0 1739 0 1007"))
      (Tab 0)))
  (MPSSessionName "chma"))