\t (00:00:01) allegro 17.4 S020 Windows SPB 64-bit Edition
\t (00:00:01)     Journal start - Fri Feb  9 12:42:00 2024
\t (00:00:01)         Host=HAZEL User=drthom Pid=9780 CPUs=8
\t (00:00:01) CmdLine= c:\cadence\spb_17.4\tools\bin\allegro.exe \\atlas.shore.mbari.org\ProjectLibrary\901415 Ventana Ctrl Sys Upgrade\Drawings\Orcad asBuilt\10021143rA_Ventana_Vicor_Micro\allegro\10021143rA_Ventana_Vicor_Micro.brd
\t (00:00:01) 
   (00:00:01) Loading axlcore.cxt 
\t (00:00:01) Loading "C:/Users/drthom/AppData/Roaming/SPB_Data/cdssetup/OrCAD_Capture/17.4.0/tclscripts/capAutoLoad/EDMClient/EDM/ClientAdapter/Skill/edm.csj"
\t (00:00:02) Log will be written to C:\Users\drthom\AppData\Roaming/edm/edmSkill.log
\t (00:00:02) Opening existing design...
\i (00:00:05) fillin yes 
\w (00:00:05) WARNING(SPMHDB-213): DRC set to "out of date". The current product selection supports a different DRC capability than what is saved in the design.
\i (00:00:06) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "10021143rA_Ventana_Vicor_Micro"
\d (00:00:06) Design opened: //atlas.shore.mbari.org/ProjectLibrary/901415 Ventana Ctrl Sys Upgrade/Drawings/Orcad asBuilt/10021143rA_Ventana_Vicor_Micro/allegro/10021143rA_Ventana_Vicor_Micro.brd
\i (00:00:06) trapsize 178
\i (00:00:06) trapsize 181
\i (00:00:06) trapsize 174
\i (00:00:06) trapsize 176
\i (00:00:06) trapsize 233
\i (00:00:06) generaledit 
\i (00:00:10) zoom fit 
\i (00:00:10) trapsize 74
\i (00:00:12) zoom out 1 
\i (00:00:12) setwindow pcb
\i (00:00:12) zoom out 1448.2 1260.6
\i (00:00:12) trapsize 147
\i (00:00:12) zoom out 1 
\i (00:00:12) setwindow pcb
\i (00:00:12) zoom out 2270.5 1260.6
\i (00:00:12) trapsize 295
\i (00:00:12) zoom out 1 
\i (00:00:12) setwindow pcb
\i (00:00:12) zoom out 5691.1 2340.9
\i (00:00:12) trapsize 467
\i (00:00:13) zoom out 1 
\i (00:00:13) setwindow pcb
\i (00:00:13) zoom out 9681.9 5296.2
\i (00:00:13) trapsize 467
\i (00:00:19) color192 
\i (00:00:19) generaledit 
\i (00:00:23) QtSignal CVDLayerTable VertHeader clickedCheckBox Top 1
\i (00:00:23) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 0 0
\i (00:00:30) QtSignal CVDLayerTable VertHeader clickedCheckBox Bottom 1
\i (00:00:30) QtSignal CVDLayerSplitter CVDLayerTable dataChanged 1 0
\i (00:00:47) trapsize 467
\i (00:00:47) trapsize 467
\i (00:00:48) exit 
\t (00:00:49)     Journal end - Fri Feb  9 12:42:47 2024
