/**
  @Generated MPLABŪ Code Configurator Source File

  @Company:
    Microchip Technology Inc.

  @File Name:
    mcc.c

  @Summary:
    This is the mcc.c file generated using MPLABŪ Code Configurator

  @Description:
    This header file provides implementations for driver APIs for all modules selected in the GUI.
    Generation Information :
        Product Revision  :  MPLABŪ Code Configurator - v3.00 Beta
        Device            :  PIC24FJ128GA406
        Driver Version    :  1.02
    The generated drivers are tested against the following:
        Compiler          :  XC16 v1.25
        MPLAB             :  MPLAB X v3.10
*/

/*
Copyright (c) 2013 - 2015 released Microchip Technology Inc.  All rights reserved.

Microchip licenses to you the right to use, modify, copy and distribute
Software only when embedded on a Microchip microcontroller or digital signal
controller that is integrated into your product or third party product
(pursuant to the sublicense terms in the accompanying license agreement).

You should refer to the license agreement accompanying this Software for
additional information regarding your rights and obligations.

SOFTWARE AND DOCUMENTATION ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND,
EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF
MERCHANTABILITY, TITLE, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE OR OBLIGATED UNDER
CONTRACT, NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH OF WARRANTY, OR
OTHER LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT DAMAGES OR EXPENSES
INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL, SPECIAL, INDIRECT, PUNITIVE OR
CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF PROCUREMENT OF
SUBSTITUTE GOODS, TECHNOLOGY, SERVICES, OR ANY CLAIMS BY THIRD PARTIES
(INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS.
 */

// Configuration bits: selected in the GUI

// FSEC
#pragma config BWRP = OFF        // Boot Segment Write Protect->Boot segment may be written
#pragma config BSS = OFF         // Boot segment Protect->No Protection (other than BWRP)
#pragma config BSEN = OFF        // Boot Segment Control bit->No Boot Segment
#pragma config GWRP = OFF        // General Segment Write Protect->Writes to program memory are allowed
#pragma config GSS = OFF         // General Segment Code Protect->Code protection is disabled
#pragma config CWRP = OFF        // Configuration Segment Program Write Protection bit->Configuration Segment may be written
#pragma config CSS = DIS         // Configuration Segment Code Protection Level bits->No Protection (other than CWRP)
#pragma config AIVTDIS = DISABLE // Alternate Interrupt Vector Table Disable bit->Disable AIVT

// FOSCSEL
#pragma config FNOSC = PRI       // Oscillator Select->Primary Oscillator (XT, HS, EC)
#pragma config PLLMODE = DISABLED // Frequency Multiplier Select Bits->No PLL used; PLLEN bit is not available
#pragma config IESO = ON        // Internal External Switchover->Start up device with FRC, then switch to user-selected oscillator source

// FOSC
#ifdef O5_DB
#pragma config POSCMOD = HS      // DB runs at 20MHz, needs High Speed oscillator mode
#else
#pragma config POSCMOD = XT      // Primary Oscillator Select->XT oscillator mode selected
#endif
#pragma config OSCIOFCN = OFF    // OSCO Pin Configuration->OSCO/CLKO/RC15 functions as CLKO (FOSC/2)
#pragma config SOSCSEL = ON      // SOSC Power Selection Configuration bits->SOSC is used in crystal (SOSCI/SOSCO) mode
#pragma config PLLSS = PLL_PRI   // PLL Secondary Selection Configuration bit->PLL is fed by the Primary oscillator
#pragma config IOL1WAY = OFF     // The IOLOCK bit can be set and cleared using the unlock sequence
#pragma config FCKSM = CSDCMD    // Clock Switching and Monitor Selection->Clock switching and Fail-Safe Clock Monitor are disabled

// FWDT
#pragma config WDTPS = PS32768   // Watchdog Timer Postscaler->1:32,768
#pragma config FWPSA = PR128     // WDT Prescaler->Prescaler ratio of 1:128
#pragma config FWDTEN = OFF      // Watchdog Timer Enable->Watchdog Timer is disabled
#pragma config WINDIS = OFF      // Windowed Watchdog Timer Disable bit->Standard Watchdog Timer enabled (Windowed-mode is disabled)
#pragma config WDTWIN = PS25_0   // Watchdog Window Select bits->Watch Dog Timer Window Width is 25 percent
#pragma config WDTCMX = WDTCLK   // WDT Clock Source Select bits->WDT clock source is determined by the WDTCLK Configuration bits
#pragma config WDTCLK = LPRC     // WDT Clock Source Select bits->WDT uses LPRC

// FPOR
#pragma config BOREN = ON        // Brown-out Reset Enable bits->Brown-out Reset Enable
#pragma config LPCFG = OFF       // Low power regulator control->Disabled

// FICD
#pragma config ICS = PGx1        // Emulator Pin Placement Select bits->Emulator functions are shared with PGEC1/PGED1
#pragma config JTAGEN = OFF      // JTAG Port Enable->JTAG port is disabled
#pragma config BTSWP = OFF       // BOOTSWP Instruction Enable bit->BOOTSWP instruction is disabled

// FDS
#pragma config DSWDTPS = DSWDTPS1F // Deep Sleep Watchdog Timer Postscale Select bits->1:68,719,476,736 (25.7 days)
#pragma config DSWDTOSC = LPRC   // DSWDT Reference Clock Select bit->DSWDT uses Low Power RC Oscillator (LPRC)
#pragma config DSBOREN = OFF     // Deep Sleep Zero-Power BOR Enable bit->Deep Sleep BOR enabled in Deep Sleep
#pragma config DSWDTEN = OFF     // Deep Sleep Watchdog Timer Enable bit->DSWDT enabled

// FDEVOPT1
#pragma config ALTCMPI = DISABLE // Alternate Comparator Input Enable bit->C1INC, C2INC, and C3INC are on their standard pin locations
#pragma config TMPRPIN = OFF     // Tamper Pin Enable bit->TMPRN pin function is disabled
#pragma config TMPRWIPE = OFF    // RAM Based Entryption Key Wipe Enable bit->Cryptographic Engine Key RAM is not erased onTMPR pin events
#pragma config ALTVREF = ALTVREFDIS // Alternate VREF location Enable->VREF is on an alternate pin (VREF+ on RB0 and VREF- on RB1)

// FBOOT
#pragma config BTMODE = SINGLE   // Boot Mode Select bits->Device is in Single Boot (legacy) mode

#include "mcc.h"

void SYSTEM_Initialize(void)
{
    OSCILLATOR_Initialize();
}

void OSCILLATOR_Initialize(void)
{
    // CF no clock failure; NOSC PRI; SOSCEN disabled; POSCEN disabled; CLKLOCK unlocked; OSWEN Switch is Complete; IOLOCK not-active; 
    __builtin_write_OSCCONL((uint8_t) (0x0200 & 0x00FF));
    // CPDIV 1:1; PLLEN disabled; RCDIV FRC/2; DOZE 1:16; DOZEN disabled; ROI disabled; 
    CLKDIV = 0x4100;
    // STOR disabled; STORPOL Interrupt when STOR is 1; STSIDL disabled; STLPOL Interrupt when STLOCK is 1; STLOCK disabled; STSRC SOSC; STEN disabled; TUN Center frequency; 
    OSCTUN = 0x0000;
    // ROEN disabled; ROSEL FOSC; ROSIDL disabled; ROSWEN disabled; ROOUT disabled; ROSLP disabled; 
    REFOCONL = 0x0000;
    // RODIV 0; 
    REFOCONH = 0x0000;
    // ROTRIM 0; 
    REFOTRIML = 0x0000;
}

/**
 End of File
*/