/************************************************************************/
/* Copyright 2003-2008 MBARI											*/
/************************************************************************/
/* Summary	: Definitions for the BRS controller SPI I/O Bits			*/
/* Filename : spi.h														*/
/* Author	: Robert Herlien (rah)										*/
/* Project	: Midwater/Benthic Respirometers							*/
/* Revision: 1.0														*/
/* Created	: 01/10/2003												*/
/*																			*/
/* MBARI provides this documentation and code "as is", with no warranty,	*/
/* express or implied, of its quality or consistency. It is provided without*/
/* support and without obligation on the part of the Monterey Bay Aquarium	*/
/* Research Institute to assist in its use, correction, modification, or	*/
/* enhancement. This information should not be published or distributed to	*/
/* third parties without specific written permission from MBARI.			*/
/*																			*/
/************************************************************************/
/* Modification History:												*/
/* 10jan2003 rah - created												*/
/* 08dec2008 rah - modified for respirometer controller					*/ 
/************************************************************************/

#ifndef INCspih
#define INCspih 1


/************************************************/
/* Definitions for Max3701 PIO chips on OASIS3	*/
/************************************************/

#define PIO_BIT_CMD(n, val)				(((n + 0x20) << 8) + (val & 1))
#define PIO_BYTE_CMD(startBit, val)		(((startBit + 0x40) << 8) + (val & 0xff))
#define PIO_READ_BYTE(startBit)			((startBit + 0xc0) << 8)
#define PIO_READ_BIT(bitNum)			((bitNum + 0xa0) << 8)

#define NUM_PIO_CHIPS	2

#define MAX_QPB_SLOTS	8				/* We decode 8 SPI selects		*/
#define GPIO_SLOT		0
#define RELAY_SLOT		1
#define AD_SLOT			2
#define GPIO_CHIP		GPIO_SLOT
#define RELAY_CHIP		RELAY_SLOT

#define PIO_NOP			0
#define PIO_DBL_NOP		0L
#define PIO_READ		0x8000
#define PIO_ON			0x0401
#define PIO_SHUTDOWN	0x0400
#define MAX146CMD		0x80
#define MAX146PDFULL	0x00
#define MAX146EXT		0x03
#define MAX146INT		0x02


/************************************************/
/* Bit Offsets on SPI PIO chips					*/
/************************************************/

/* PIO(0) bits			*/
#define NOT_SHUTDN(n)			(3*n+1)
#define DE_485(n)				(3*n+2)
#define SENSE_485(n)			(3*n+3)
#define WDT_BIT					25
#define HEARTBEAT_BIT			26
#define ENABLE_12V_BIT			28
#define ANALOG_ENABLE_BIT		29
#define GF_HIGH					30
#define GF_LOW					31

/* PIO(1) bits			*/
#define SER_RELAY_SET(n)		(n+3)
#define SER_RELAY_RESET(n)		(n+17)
#define PWR_RELAY_SET(n)		(n+10)
#define PWR_RELAY_RESET(n)		(n+24)
#define PWR_SET_OFFSET			10
#define PWR_RESET_OFFSET		24
#define PWR_BIT_MASK			0xfe


/****************************************/
/* Function Declarations				*/
/****************************************/

Nat16	spiTransactPIO(Nat16 chip, Nat16 sendData);
Void	spiSetPIOBit(Nat16 chip, Nat16 bitNum, Nat16 state);
Void	spiSetPIOByte(Nat16 chip, Nat16 bitOffset, Nat16 val);
Nat16	spiReadPIOByte(Nat16 chip, Nat16 bitOffset);
Nat16	spiReadPIOBit(Nat16 chip, Nat16 bitNum);
Void	spiAtoDPower(MBool onoff, Nat16 channel);
Nat16	spiAtoD(Nat16 channel);
Void	spiInit(Void);
Void	spiPwrdown(Void);
Void	spiShutdownMode(MBool onoff);

#endif	/* INCioh */
