/**
  ******************************************************************************
  * @file    pib_testpts.h
  * @author  C. Otten.
  * @version V0.1.0
  * @date    04/08/2011
  * @brief   Prototypes and definitions for test points
  ******************************************************************************
  *
  * COPYRIGHT 2011 Liquid Robotics, Inc.
  **/

#ifndef __PIB_TESTPTS_H__
#define __PIB_TESTPTS_H__

#define TP03BIT   _BV(PJ6)
#define TP04BIT   _BV(PK7)
#define TP05BIT   _BV(PJ7)
#define TP06BIT   _BV(PH3)
#define TP07BIT   _BV(PE4)
#define TP08BIT   _BV(PE2)
#define TP09BIT   _BV(PE5)
#define TP10BIT   _BV(PG5)
#define TP11BIT   _BV(PD4)
#define TP12BIT   _BV(PL7)
#define TP13BIT   _BV(PL3)

#define TP03DDR   DDRJ
#define TP04DDR   DDRK
#define TP05DDR   DDRJ
#define TP06DDR   DDRH
#define TP07DDR   DDRE
#define TP08DDR   DDRE
#define TP09DDR   DDRE
#define TP10DDR   DDRG
#define TP11DDR   DDRD
#define TP12DDR   DDRL
#define TP13DDR   DDRL

#define TP03PORT  PORTJ
#define TP04PORT  PORTK
#define TP05PORT  PORTJ
#define TP06PORT  PORTH
#define TP07PORT  PORTE
#define TP08PORT  PORTE
#define TP09PORT  PORTE
#define TP10PORT  PORTG
#define TP11PORT  PORTD
#define TP12PORT  PORTL
#define TP13PORT  PORTL

#define INITTP_03 {TP03DDR |=  TP03BIT;}
#define INITTP_04 {TP04DDR |=  TP04BIT;}
#define INITTP_05 {TP05DDR |=  TP05BIT;}
#define INITTP_06 {TP06DDR |=  TP06BIT;}
#define INITTP_07 {asm volatile ("sbi 0x0D, 4");}
#define INITTP_08 {asm volatile ("sbi 0x0D, 2");}
#define INITTP_09 {asm volatile ("sbi 0x0D, 5");}
#define INITTP_10 {asm volatile ("sbi 0x13, 5");}
#define INITTP_11 {asm volatile ("sbi 0x0A, 4");}
#define INITTP_12 {TP12DDR |=  TP12BIT;}
#define INITTP_13 {TP13DDR |=  TP13BIT;}
#define INITTP_14 {TP14DDR |=  TP14BIT;}

#define SETTO1_03 {TP03PORT |=  TP03BIT;}
#define SETTO0_03 {TP03PORT &= ~TP03BIT;}
#define SETTO1_04 {TP04PORT |=  TP04BIT;}
#define SETTO0_04 {TP04PORT &= ~TP04BIT;}
#define SETTO1_05 {TP05PORT |=  TP05BIT;}
#define SETTO0_05 {TP05PORT &= ~TP05BIT;}
#define SETTO1_06 {TP06PORT |=  TP06BIT;}
#define SETTO0_06 {TP06PORT &= ~TP06BIT;}
/*
#define SETTO1_07 {TP07PORT |=  TP07BIT;}
#define SETTO0_07 {TP07PORT &= ~TP07BIT;}
#define SETTO1_08 {TP08PORT |=  TP08BIT;}
#define SETTO0_08 {TP08PORT &= ~TP08BIT;}
#define SETTO1_09 {TP09PORT |=  TP09BIT;}
#define SETTO0_09 {TP09PORT &= ~TP09BIT;}
#define SETTO1_10 {TP10PORT |=  TP10BIT;}
#define SETTO0_10 {TP10PORT &= ~TP10BIT;}
#define SETTO1_11 {TP11PORT |=  TP11BIT;}
#define SETTO0_11 {TP11PORT &= ~TP11BIT;}
*/
#define SETTO1_07 {asm volatile ("sbi 0x0E, 4");}
#define SETTO0_07 {asm volatile ("cbi 0x0E, 4");}
#define SETTO1_08 {asm volatile ("sbi 0x0E, 2");}
#define SETTO0_08 {asm volatile ("cbi 0x0E, 2");}
#define SETTO1_09 {asm volatile ("sbi 0x0E, 5");}
#define SETTO0_09 {asm volatile ("cbi 0x0E, 5");}
#define SETTO1_10 {asm volatile ("sbi 0x14, 5");}
#define SETTO0_10 {asm volatile ("cbi 0x14, 5");}
#define SETTO1_11 {asm volatile ("sbi 0x0B, 4");}
#define SETTO0_11 {asm volatile ("cbi 0x0B, 4");}

#define SETTO1_12 {TP12PORT |=  TP12BIT;}
#define SETTO0_12 {TP12PORT &= ~TP12BIT;}
#define SETTO1_13 {TP13PORT |=  TP13BIT;}
#define SETTO0_13 {TP13PORT &= ~TP13BIT;}

#define GETTP_03  (TP03PORT & TP03BIT)
#define GETTP_04  (TP04PORT & TP04BIT)
#define GETTP_05  (TP05PORT & TP05BIT)
#define GETTP_06  (TP06PORT & TP06BIT)
#define GETTP_07  (TP07PORT & TP07BIT)
#define GETTP_08  (TP08PORT & TP08BIT)
#define GETTP_09  (TP09PORT & TP09BIT)
#define GETTP_10  (TP10PORT & TP10BIT)
#define GETTP_11  (TP11PORT & TP11BIT)
#define GETTP_12  (TP12PORT & TP12BIT)
#define GETTP_13  (TP13PORT & TP13BIT)
#define GETTP_14  (TP14PORT & TP14BIT)

#endif // __PIB_TESTPTS_H__