(ExpressProject ""
  (ProjectVersion "19981106")
  (ProjectType "PCB")
  (Folder "Design Resources"
    (Folder "Library")
    (File ".\lander fiber mux connector board.dsn"
      (Type "Schematic Design"))
    (BuildFileAddedOrDeleted "x")
    (CompileFileAddedOrDeleted "x")
    (DRC_Scope "0")
    (DRC_Action "0")
    (DRC_Create_Warnings "FALSE")
    (DRC_View_Output "FALSE")
    (DRC_Preserved_Waived "FALSE")
    (DRC_Run_Electrical_Rules "TRUE")
    (DRC_Run_Physical_Rules "FALSE")
    (DRC_Report_File
       "C:\AA PROJECT DATA\ORCADDATA\BENTHIC OBSERVATION SYSTEM\LANDER\LANDER FIBER MUX CONNECTOR BOARD\LANDER FIBER MUX CONNECTOR BOARD.DRC")
    (DRC_Check_Ports "FALSE")
    (DRC_Check_Off-Page_Connectors "FALSE")
    (DRC_Report_Ports_and_Off-page_Connectors "FALSE")
    (DRC_SDT_Compatibility "FALSE")
    (DRC_Report_Off-grid_Objects "FALSE")
    (DRC_Check_Unconnected_Nets "TRUE")
    (DRC_Check_for_Misleading_TAP "FALSE")
    (DRC_Report_Netnames "FALSE")
    (DRC_Check_Single_Node_Nets "TRUE")
    (DRC_Run_Electrical_Custom_DRC "FALSE")
    (DRC_Check_No_Driving_Source "TRUE")
    (DRC_Check_Duplicate_NetNames "TRUE")
    (DRC_Check_Floating_Pins "TRUE")
    (DRC_Check_Physical_Power_Pins_Visibility "TRUE")
    (DRC_Check_PCB_Footprint_Property "TRUE")
    (DRC_Check_Normal_Convert_View_Sync "TRUE")
    (DRC_Check_Incorrect_PinGroup_Assignment "TRUE")
    (DRC_Check_High_Speed_Props_Syntax "TRUE")
    (DRC_Check_Missing_Pin_Numbers "TRUE")
    (DRC_Check_Device_With_No_Pins "TRUE")
    (DRC_Check_Power_Ground_Short "TRUE")
    (DRC_Identical_References "TRUE")
    (DRC_Type_Mismatch "TRUE")
    (DRC_Visible_Power_pins "FALSE")
    (DRC_Report_Unused_Part_Packages "TRUE")
    (DRC_Check_Name_Prop_For_HierBlocks "TRUE")
    (DRC_Run_Physical_Custom_DRC "FALSE")
    (NoModify)
    (Netlist_TAB "0")
    ("Create Allegro Netlist" "TRUE")
    ("Allegro Netlist Directory" "allegro")
    ("View Allegro Netlist Files" "FALSE")
    ("Allegro Netlist Create DCF File" "FALSE")
    ("Update Allegro Board" "FALSE")
    ("Allegro Netlist Output Board File"
       "allegro\LANDER FIBER MUX CONNECTOR BOARD.brd")
    ("Allegro Netlist Remove Etch" "FALSE")
    ("Allegro Netlist Place Changed Component" "ALWAYS_REPLACE")
    ("Allegro Netlist Open Board in Allegro" "ALLEGRO")
    ("Allegro Setup Backup Versions" "3")
    ("Allegro Setup Ignore Constraints" "FALSE")
    ("Allegro Setup Part Type Length" "31")
    ("Allegro Netlist Combine Property String" "PCB Footprint")
    ("Allegro Netlist Ignore Fixed Property" "FALSE")
    ("Allegro Netlist User Defined Property" "FALSE"))
  (Folder "Outputs"
    (File ".\lander fiber mux connector board.drc"
      (Type "Report"))
    (File ".\allegro\pstxnet.dat"
      (Type "Report")
      (DisplayName "pstxnet.dat"))
    (File ".\allegro\pstxprt.dat"
      (Type "Report")
      (DisplayName "pstxprt.dat"))
    (File ".\allegro\pstchip.dat"
      (Type "Report")
      (DisplayName "pstchip.dat")))
  (Folder "Referenced Projects")
  (PartMRUSelector
    (SMA_EDGE_SYM-MOD2
      (FullPartName "SMA_EDGE_SYM-MOD2.Normal")
      (LibraryName "\\WATER\SCHEMATIC_SYMBOLS\CONNECTORS.OLB")
      (DeviceIndex "0"))
    (SAMTEC_MEC1-130-02-x-D-A
      (FullPartName "SAMTEC_MEC1-130-02-x-D-A.Normal")
      (LibraryName "\\WATER\SCHEMATIC_SYMBOLS\CONNECTORS.OLB")
      (DeviceIndex "0")))
  (GlobalState
    (FileView
      (Path "Design Resources")
      (Path "Design Resources" ".\lander fiber mux connector board.dsn")
      (Path "Design Resources" ".\lander fiber mux connector board.dsn"
         "SCHEMATIC1")
      (Path "Outputs")
      (Select "Design Resources" ".\lander fiber mux connector board.dsn"
         "SCHEMATIC1" "PAGE1"))
    (HierarchyView)
    (Doc
      (Type "COrCapturePMDoc")
      (Frame
        (Placement "44 2 3 -1 -1 -8 -31 0 200 0 799"))
      (Tab 0)))
  (ISPCBBASICLICENSE "false")
  (MPSSessionName "ckecy"))