LRAUV Long ("Power") Backplane
MBARI 11021164 
Design Notes

2015 Jul 9	ecm	collect from emails and scribbles

Requirements

1)	handle existing and future loads
2)	fit into existing space
3) 	work with existing Mobo expansion interface (SPI + with chip select addressing)
4)	work with existing Load Control Boards (connector, pinout)
    
5)    	increase backplane slots -- was 16, desire 20-24
6)    	improve DC/DC efficiency
7)    	reduce battery inrush current at startup, prevent UV trips
8)    	reduce system noise due to DC/DCs, especially on Mobo
9)    	clean up SPI bus

Approach

Design Notes

1.	Original plan for 7-pin Boost connector foiled by limited availability (only 1 distributor with stock).  Switch to 8-pin single row for Boost connector, and change Battery Input connector from 8-pin single to 8-pin double row, same as on Motherboard.

2.	Current Limiter Overvoltage Clamp:   not required, but available on LT4363 so will use.
	50k divider at 24 V input wastes ~12 mW.
	2.5k impedance at 1 uA max FB input has ~2.5 mV error or .2% (sim shows 30 nA input current).
	Set divider for 1.24V (Vfb min over temperature) minus 2% for divider tolerance.
	Set divider with input at 25V, for margin.

3.	Undervoltage cutoff:   available on LT4363, but not implemented since this function is performed by U25 "Low Battery Cutoff Circuit" on motherboard.  (LT4363 min op voltage ~4V, shuts off below that.)

4.	Current limiter:  Target 20A limit (per section) requires 2.5 e-3 ohm shunt, not readily available.  3e-3 shunt, easily available, plus divider give required 50 mV feedback voltage.  N.b. divider needs to be on "Out" pin, as shown, since large gate currents flow through the Sns pin during gate voltage transients (returning to MOSFET  S terminal). 

5.	Current Limiter Fault timer:   Available cap (1 uF) gives 15 msec shutdown at 20A (per section) overcurrent at 24V input.  (This value from simulation since shutdown varies with voltage drop.)

6.	Current Limiter Inrush:  C25/C40 limit dV/dt during inrush to a value less than full limit current – easier on connectors and perhaps bulk capacitors.  10A per section (20A total) should allow any load to start.  Default .012uF value gives 10A with 10mF bulk cap in sim.  BkpBatt+ rise time 0-24V ~20 msec, fairly linear.

7.	Current Limiter/Master Disconnect Enable:  Enable_Pwr signal originates from always-on tristate buffer U18 on Mobo.  22k pulldown disables all power if control signal is not present or disconnected.  2.2k series limits fault current to Mobo in event of short on Backplane.  0.47uF C58 provides lowpass filter and some noise immunity against ground bounce on the BkpHVCom rail.  

8.	Current Limiter Fault signal:   \PS_Fault signal requires inverting and opto U15 adds ground bounce rejection.    Opto LED is only on during fault so 10mA drive gives good Vcesat of 0.3 V max.  LED limit resistor R37: (3.15V-1.3V)/10mA = 180 ohm.   22k pulldown R22 deals with 1uA opto dark current. 

Checkout Notes

1.  Wrong logic sense was assumed for LC_BOARD_SELECT_ENABLE going to 74LVC125 /OE pin at U3-4, and U3-10.  Preliminary fix is to tie U3-4 and U3-10 high, which will permanently enable Bkp_Sck and Bkp_MOSI instead of gating them with the board enable.  Consequence should merely be slightly higher power consumption since these signals are also gated by a /Group_Sel within each board group. 

2.  Wrong logic sense was assumed for LC_BOARD_SELECT_ENABLE going to 74LVC125 /OE pin at U4-1.  Preliminary fix is to bypass buffer U4A, since the Bkp_MISO signal that is being buffered is also buffered and tri-stated within each board group.  Consequence is a longer trace being driven (full length of backplane plus ribbon cable plus trace on CPU) with slower risetime and greater chance of reflections.

3.  OrCAD schematic drafting error led to /RESOUT_LC and SPI2_MOSI nets being tied together causing contention and 50 MHz oscillations on Bkp_MOSI.  Fix is trace cuts and blue wires to separate the nets.  No consequence to performance.

Blue Wire ECOs

1.  For Checkout Note #1:
1) Cut trace going to U3-4 and trace going to U3-10.
2) Tie U3-4 to Bkp3.15Com (at U3-1).
3) Tie U3-10 to Bkp3.15Com (at U3-13).

2.  For Checkout Note #2:
1) Cut trace between U4-3 and J3-17.
2) Connect U4-2 to J3-17 (connection to U4-2 can be at TP10 to avoid running wire thru board).

3.  For Checkout Note #3:
1) Cut trace between J3-22 and J3-23 (remove J3 if necessary  ).
2) Cut trace going to U3-9, between pin and via.
3) Connect U3-9 to J3-22.  Route wire through board at J5 mounting hole, or other suitable route.

Future ECOs

1.  Substitute 74LVC126, which has active-high OE input, for 74LVC125 which has active low /OE.  Cut traces to tied-low /OE inputs at U3-1 and at U4-4, U4-10, and U4-13, and then tie those inputs high. (Could tie U4 inputs to adjacent TP12 or D7 cathode, to avoid daisy chaining blue wires at pads.)