/* * init_TM4C123GH6PM_64pin.c * * Created on: Apr 18, 2021 * Author: thomm */ #include "system.h" #include "init.h" #include "microsd.h" #include "uartstdio.h" // User local version with larger RX buffer #include "sleep.h" #include "i2c_fram.h" extern int microSD_flg; extern struct systemSamplingData sys_samp; // TODO, use #include for these... extern void profile2_toggle(int target); extern void ADS1248_gpio_init(void); extern void AUX1_init(void); extern void optode_init(void); extern void led_init(void); void init_TM4C123GH6PM_64pin(void); void init_TM4C123GH6PM_64pin(void) { // Enable lazy stacking for interrupt handlers. This allows floating-point // instructions to be used within interrupt handlers, but at the expense of2 // extra stack usage. ROM_FPULazyStackingEnable(); //enable floats ROM_FPUEnable(); //set the system clock...50MHZ ROM_SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN); ROM_SysCtlDelay(MILLISECOND*2); // THOM, fast startup //TM4C123GH6PM = 64 (43 GPIO) //PA0 - PA7 8 //PB0 - PB7 8 //PC0 - PC7 8 //PD0 - PD7 8 //PE0 - PE5 6 //PF0 - PF4 5 /*** Enable the GPIO ports used ***/ ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); //PA0 - PA7 8 ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); //PB0 - PB7 8 ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); //PC0 - PC7 8 ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD); //PD0 - PD7 8 ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE); //PE0 - PE5 6 ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); //PF0 - PF4 5 // THOM TODO Init GPIO to low power state by default (check processor defaults, this might already be done in hardware) #ifdef NOCODE_DEFS_FOR_PINS_DAG_NANOFET // + means checked, * means different between nanoFET and DAG, nanoFET is subset of DAG NANOFET // DAG +1 PB6 PB6_ADC_START // PB6_ADC_START +4* PB7 NC // PB7_SHUTDOWN_ISO (not connected in DAG or nFET) +5 PF4 PF4_ADC_RESET // PF4_ADC_RESET +6* PE3 NC // PE3_AIN0_VOLTAGE +7* PE2 NC // PE2_AIN1_HUMIDITY +8* PE1 NC // PE1_AIN2_TMP_CS3 +9* PE0 NC // PE0_MUX_X6_A1 +10* PD7 NC // PD7_MUX_X6_A0 +13 PC7 PC7_LED_RED_WDOG // PC7_LED_RED_WDOG +14 PC6 PC6_GREEN_LED // PC6_GREEN_LED +15* PC5 PC5_NC // PC5_SPARE_TX4 +16* PC4 PC4_NC // PC4_SPARE_RX4 +17 PA0 PA0_CONSOLE_RX // PA0_CONSOLE_RX0 +18 PA1 PA1_CONSOLE_TX // PA1_CONSOLE_TX0 +19 PA2 PA2_FLASH_CLK // PA2_FLASH_CLK +20 PA3/SSI0FSS PA3_FLASH_CS0 // PA3_FLASH_CS0 +21 PA4 PA4_FLASH_MISO // PA4_FLASH_MISO +22 PA5 PA5_FLASH_MOSI // PA5_FLASH_MOSI +23* PA6 PA6_NC // PA6_FLASH_CS1 +24 PA7 PA7_FLASH_HOLD // PA7_FLASH_CS2 (TODO, FLASH_HOLD vs Chip select?) +28* PF0 PF0_NC // PF0_CONSOLE_PS +29* PF1 PF1_NC // PF1_CONSOLE_MODE +30* PF2 PF2_NC // PF2_DRIVER_MODE +31* PF3 PF3_NC // PF3_DRIVER_PS +43* PD4 PD4_NC // PD4_SPARE_RX6 +44* PD5 PD5_NC // PD5_SPARE_TX6 +45* PB0/USB0ID PB0_NC // PB0_SPARE_RX1 +46* PB1/USB0VBUS PB1_NC // PB1_SPARE_TX1 +47 PB2/I2C0SCL I2C_SCL // I2C_SCL +48 PB3/I2C0SDA I2C_SDA // I2C_SDA +53 PD6 PD6_DRDY // PD6_DRDY +57 PB5 PB5_ENV_ENABLE // PB5_NC +58 PB4 PB4_NC // PB4_VENABLE_NC +59 PE4 PE4_NC // PE4_SPARE_RX5 +60 PE5 PE5_NC // PE5_SPARE_TX5 +61 PD0 PD0_SSI3_CLK // PD0_SSI3_CLK +62 PD1 PD1_SSI3_SS_CS // PD1_SSI3_SS_CS +63 PD2 PD2_SSI3_RX_MISO // PD2_SSI3_RX_MISO +64 PD3 PD3_SSI3_TX_MOSI // PD3_SSI3_TX_MOSI #endif //1 PB6 PB6_ADC_START // PB6_ADC_START ROM_GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_6); // 1 PB6 PB6_ADC_START ROM_GPIOPinWrite(GPIO_PORTB_BASE, GPIO_PIN_6, 0xFF); // ADC_START=1 is inactive #if BOARD_DAG == 1 //+4* PB7 NC // PB7_SHUTDOWN_ISO ROM_GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_7); ROM_GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_7, 0xFF); // Init to 1 (NC on both DAG and nFET) #endif //+5 PF4 PF4_ADC_RESET // PF4_ADC_RESET ROM_GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_4); // 5 PF4 PF4_ADC_RESET ROM_GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_4, 0xFF); // ADC_RESET to ADS1284 active low reset (init to 1) #if BOARD_DAG == 1 ROM_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_3); // 6 PE3 NC // PE3_AIN0_VOLTAGE ROM_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_2); // 7 PE2 NC // PE2_AIN1_HUMIDITY ROM_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_1); // 8 PE1 NC // PE1_AIN2_TMP_CS3 ROM_GPIOPinTypeGPIOOutput(GPIO_PORTE_BASE, GPIO_PIN_0); // 9 PE0 NC // PE0_MUX_X6_A1 ROM_GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_0, 0x00); // ROM_GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE, GPIO_PIN_7); // 10 PD7 NC // PD7_MUX_X6_A0 ROM_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_7, 0x00); // #endif led_init(); // defd in board_util.c #ifdef OLDCODE6Apr2021 ROM_GPIOPinTypeGPIOOutput(GPIO_PORTC_BASE, GPIO_PIN_7); // 13 PC7 PC7_LED_RED_WDOG ROM_GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, 0x00); // ??? TBD high or low as inactive ROM_GPIOPinTypeGPIOOutput(GPIO_PORTC_BASE, GPIO_PIN_6); // 14 PC6 PC6_GREEN_LED ROM_GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_6, 0x00); // ??? TBD high or low as inactive #endif #if BOARD_DAG == 1 /*** Initialize UART4 ***/ //15 PC5 PC5_NC //PC5_SPARE_TX4 //16 PC4 PC4_NC //PC4_SPARE_RX4 ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART4); ROM_GPIOPinConfigure(GPIO_PC5_U4TX); ROM_GPIOPinConfigure(GPIO_PC4_U4RX); ROM_GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_4 | GPIO_PIN_5); UARTClockSourceSet(UART4_BASE, UART_CLOCK_PIOSC); MicroCAT_UARTConfig(4, 9600, 16000000); // 115200 bits per second MicroCAT_UARTEchoSet(0); // Disable echo to MicroCAT #endif /*** Initialize UART0 for use as the console, printf, etc ***/ //17 PA0/U0RX PA0_CONSOLE_RX0 //18 PA1/U0TX PA1_CONSOLE_TX0 ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); ROM_GPIOPinConfigure(GPIO_PA0_U0RX); ROM_GPIOPinConfigure(GPIO_PA1_U0TX); ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); UARTClockSourceSet(UART0_BASE, UART_CLOCK_PIOSC); UARTStdioConfig(0, 115200, 16000000); // 115200 bits per second UARTEchoSet(true); // Enable console echo //19 - 24 are SPI for FLASH/SDCARD, set in init_SDcard() TODO, init pins for low power in case SD card is not usedc //28 - 46 are NC for nanoFET (DAg uses pins) #if BOARD_DAG == 1 // TODO: DAg will require proper settings for these gpio pins ROM_GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_0); // 28 PF0 PF0_NC //PF0_CONSOLE_PS ROM_GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_0, 0x00); // Clear ROM_GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_1); // 29 PF1 PF1_NC //PF1_CONSOLE_MODE ROM_GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_1, 0x00); // Clear ROM_GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_2); // 30 PF2 PF2_NC //PF2_DRIVER_MODE ROM_GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_2, 0x00); // Clear ROM_GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_3); // 31 PF3 PF3_NC //PF3_DRIVER_PS ROM_GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_3, 0x00); // Clear // THOM TODO: if not using UART6, then config for low power (move these outside BOARD_DAG) //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE, GPIO_PIN_4); // 43 PD4 PD4_NC //PD4_SPARE_RX6 //ROM_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_4, 0x00); // Clear //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE, GPIO_PIN_5); // 44 PD5 PD5_NC //PD5_SPARE_TX6 //ROM_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_5, 0x00); // Clear /*** Initialize UART6 ***/ // 43 PD4 PD4_NC //PD4_SPARE_RX6 // 44 PD5 PD5_NC //PD5_SPARE_TX6 ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART6); ROM_GPIOPinConfigure(GPIO_PD4_U6RX); // 43 PD4 PD4_NC //PD4_SPARE_RX6 ROM_GPIOPinConfigure(GPIO_PD5_U6TX); // 44 PD5 PD5_NC //PD5_SPARE_TX6 ROM_GPIOPinTypeUART(GPIO_PORTD_BASE, GPIO_PIN_4 | GPIO_PIN_5); UARTClockSourceSet(UART6_BASE, UART_CLOCK_PIOSC); // init_UART6(115200, 16000000, 0); // THOM TODO refactor uart code, pass in baud, clock, echoFlg //MicroCAT_UARTConfig(4, 9600, 16000000); // 115200 bits per second //MicroCAT_UARTEchoSet(0); // Disable echo to MicroCAT // THOM TODO (same as above for UART6 GPIO when not used, set for lowest power) //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_0); // 45 PB0/USB0ID PB0_NC //PB0_SPARE_RX1 //ROM_GPIOPinWrite(GPIO_PORTB_BASE, GPIO_PIN_0, 0x00); // Clear //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_1); // 46 PB1/USB0VBUS PB1_NC //PB1_SPARE_TX1 //ROM_GPIOPinWrite(GPIO_PORTB_BASE, GPIO_PIN_1, 0x00); // Clear /*** Initialize UART1 ***/ // 45 PB0/USB0ID PB0_NC //PB0_SPARE_RX // 46 PB1/USB0VBUS PB1_NC //PB1_SPARE_TX1 ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART1); ROM_GPIOPinConfigure(GPIO_PB0_U1RX); // 45 PB0/USB0ID PB0_NC //PB0_SPARE_RX1 ROM_GPIOPinConfigure(GPIO_PB1_U1TX); // 46 PB1/USB0VBUS PB1_NC //PB1_SPARE_TX1 ROM_GPIOPinTypeUART(GPIO_PORTB_BASE, GPIO_PIN_0 | GPIO_PIN_1); UARTClockSourceSet(UART1_BASE, UART_CLOCK_PIOSC); // init_UART1(115200, 16000000); // THOM TODO refactor uart code, pass in baud, clock, echoFlg #endif // THOM TODO, figure out best way to manage I2C for low power, default is to set as GPIO high so to not pull down resistors for now // 47 PB2/I2C0SCL I2C_SCL // 48 PB3/I2C0SDA I2C_SDA ROM_GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_2); // 47 PB2/I2C0SCL I2C_SCL ROM_GPIOPinWrite(GPIO_PORTB_BASE, GPIO_PIN_2, 0xFF); // Set high (maybe should float?) ROM_GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_3); // 48 PB3/I2C0SDA I2C_SDA ROM_GPIOPinWrite(GPIO_PORTB_BASE, GPIO_PIN_3, 0xFF); // Set // FRAM init calls i2c_init - need to figure out peripheral init backplane policy (recommend calling i2c_init here) // void i2c0_init(bool bFast) // DRDY input pin for ADS1284 ROM_GPIOPinTypeGPIOInput(GPIO_PORTD_BASE, GPIO_PIN_6); // Input 53 PD6 PD6_DRDY // NC on both DAG and nanoFET, DAG has named the pins ROM_GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_5); // 57 PB5 PB5_ENV_ENABLE (no connect on DAG) ROM_GPIOPinWrite(GPIO_PORTB_BASE, GPIO_PIN_5, 0x00); ROM_GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_4); // 58 PB4 PB4_NC //PB4_VENABLE_NC (no connect on DAG) ROM_GPIOPinWrite(GPIO_PORTB_BASE, GPIO_PIN_4, 0x00); #if BOARD_DAG == 1 /*** Initialize UART1 ***/ // 59 PE4 PE4_NC // PE4_SPARE_RX5 // 60 PE5 PE5_NC // PE5_SPARE_TX5 ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART5); ROM_GPIOPinConfigure(GPIO_PE4_U5RX); // 59 PE4 PE4_NC // PE4_SPARE_RX5 ROM_GPIOPinConfigure(GPIO_PE5_U5TX); // 60 PE5 PE5_NC // PE5_SPARE_TX5 ROM_GPIOPinTypeUART(GPIO_PORTE_BASE, GPIO_PIN_4 | GPIO_PIN_5); UARTClockSourceSet(UART5_BASE, UART_CLOCK_PIOSC); // init_UART5(115200, 16000000, 0); // THOM TODO refactor uart code, pass in baud, clock, echoFlg #endif /*** Initialize ADS1248 pins as GPIO to reduce power consumption, SPI config happens in ADS1284_xxx.c ***/ // THOM TODO on nanoFET and DAG - ADS1284 routines need tweaking ROM_GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE, GPIO_PIN_0); // SSI3CLK 61 PD0 PD0_SSI3_CLK ROM_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_0, 0x00); ROM_GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE, GPIO_PIN_1); // SSI3Fss 62 PD1 PD1_SSI3_SS_CS ROM_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_1, 0x00); ROM_GPIOPinTypeGPIOInput(GPIO_PORTD_BASE, GPIO_PIN_2); // SSI3Rx 63 PD2 PD2_SSI3_RX_MISO ROM_GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE, GPIO_PIN_3); // SSI3Tx 64 PD3 PD3_SSI3_TX_MOSI ROM_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_3, 0x00); //---------- Done with 'pin' init -------------------------- /*** Configure SysTick for a 100Hz interrupt. The FatFs driver and 10 ms timer share a 10 ms tick ***/ ROM_SysTickPeriodSet(ROM_SysCtlClockGet() / 100); ROM_SysTickEnable(); ROM_SysTickIntEnable(); //THOM DEBUG // uprintf("\nSysTick setup ROM_SysCtlClockGet() = %u\n", ROM_SysCtlClockGet()); // uprintf("SysTick setup ROM_SysTickPeriodGet() = %u\n",ROM_SysTickPeriodGet()); // if i2c does not have a device, the fram_probe hangs (on MFET v1) THOM TODO enhance error handling fram_init(); // calls i2c0_init(TRUE); // fast mode 400kpbs, defd in i2c_fram.c /*** Retrieve saved sys_data variables ***/ retrieveSysDataVariables(); // defd in system.c, moved down in init until after i2c init (in fram) #ifdef OLDCODE // THOM debug if(sys_data.state == IDLE) dbg_printf("Init.c: sys_data.state = IDLE\n"); if(sys_data.state == START) dbg_printf("Init.c: sys_data.state = START\n"); if(sys_data.state == COMMAND) dbg_printf("Init.c: sys_data.state = COMMAND\n"); if(sys_data.state == DEPLOYED) dbg_printf("Init.c: sys_data.state = DEPLOYED\n"); #endif // default is 115200 and this is set above - if sys_data.baud_rate is specified, then re(set) here. if(sys_data.baud_rate == 9600L) { UARTStdioConfig(0, 9600, 16000000); // 9600 bits per second } // Find out what woke us and decide what to do THOM TODO - new fresh nanoFET hangs in sleep handler (retrieveSysDataVariable are not setup??? #ifdef CODEHANGS_SLEEPHANDLER_SUSPECT32k ///sleep_handler(); // moved to main() 25 May 2021 #endif sys_samp.state = IDLE; // Drop through to main menu // 19 PA2 PA2_FLASH_CLK // PA2_FLASH_CLK // 20 PA3/SSI0FSS PA3_FLASH_CS0 // PA3_FLASH_CS0 // 21 PA4 PA4_FLASH_MISO // PA4_FLASH_MISO // 22 PA5 PA5_FLASH_MOSI // PA5_FLASH_MOSI // 23* PA6 PA6_NC // PA6_FLASH_CS1 // 24 PA7 PA7_FLASH_HOLD // PA7_FLASH_CS2 (TODO, FLASH_HOLD vs Chip select?) // Initialize MicroSD card and FatFs //ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); //ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); //PA2 to PA5 if(sys_data.app_cfg[APPCFG_MICROSD_ENABLE] == 1) // Fix 6 Aug 2021 { Init_SDCard(); sd_format(); //hangs in disk initialize } }