/*
 * init_TM4C123GH6PGE_144pin.c
 *
 *  Created on: Apr 10, 2022
 *      Author: thomm
 */

#include "system.h"
#include "init.h"

#include "microsd.h"
#include "uartstdio.h"  // User local version with larger RX buffer
#include "sleep.h"
#include "i2c_fram.h"

extern int microSD_flg;
extern struct systemSamplingData sys_samp;

// TODO, use #include for these...
extern void profile2_toggle(int target);
extern void ADS1248_gpio_init(void);
extern void AUX1_init(void);
extern void optode_init(void);
extern void led_init(void);

// Stupid pinMux problems
// PD7 kills U2TX, AIN4 mapped.  U2 on alternate PG4,5
// PD5 kills U6TX
// PD0-PD3 kills SSI1, these GPIO outs can be mapped elsewhere easily
// PK0-2 kills SSI2, these GPIO outs can be mapped elsewhere easily.   Near term focused hardware design that makes future expandability difficult

// GPIO and onchip peripheral init for the 144 pin parts
// assumes ROM_FPUxxx and ROM_SysCtlClockSet called before calling this function
void init_TM4C123GH6PGE_144pin(void)
{
#ifdef NOCODE
    // This code pushed into each init_chipx routine
    // Enable lazy stacking for interrupt handlers.  This allows floating-point
    // instructions to be used within interrupt handlers, but at the expense of2
    // extra stack usage.
    ROM_FPULazyStackingEnable();

    //enable floats
    ROM_FPUEnable();

    //set the system clock...Using 400MHz PLL and DIV_4 yields 100MHz (comment says 50MHZ ?)
    ROM_SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
#endif

    //TM4C123GH6PGE = 144     (105 GPIO)
    //PA0 - PA7       8
    //PB0 - PB5       6
    //PC0 - PC7       8
    //PD0 - PD7       8
    //PE0 - PE7       8
    //PF0 - PF7       8
    //PG0 - PG7       8
    //PH0 - PH7       8
    //PJ0 - PJ7       8
    //PK0 - PK7       8
    //PL0 - PL7       8
    //PM0 - PM7       8
    //PN0 - PN7       8
    //PP0 - PP2       3

    //ROM_SysCtlDelay(MILLISECOND*100);       //THOM MFET is not usable after experimenting with delay

    /*** Enable the GPIO ports used ***/
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOK);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOL);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOM);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPION);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOP);

    /*** Initialize Green and Red LED ***/
    // This is done early in init to enable oscope timing
    led_init();
    led_power_on();
#if BOARD_MFET == 2
    // Set PA1 high to avoid RS232 glitch, later in init(), this will be setup as console serial port  (Looks like CONSOLE SHUTDOWN is all that is req'd)
    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_1); // PA1 is console TX
    ROM_GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_1, 0xFF);        // was 0xff  // BUG Fix 19 May 2022 (PORTP to PORTA)

    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_1); // PL0, pin 107             // CONSOLE SHUTDOWN # (active low)
    ROM_GPIOPinWrite(GPIO_PORTL_BASE, GPIO_PIN_1, 0x00);    // Keep max3232 in shutdown until after console uart is config'd
#endif
    ROM_SysCtlDelay(MILLISECOND*2);       // THOM, fast startup

    // Temporarily Setup unused ports as GPIO (change this if I2C, SSI2, or M0PWM used)

    // According to the TM4c123g tech ref manual, GPIO are set as inputs after power on reset
    // The init policy will be to only setup GPIO as output for those that are used on a particular board (minimize power consumption)
    // Also, UARTs, SPI, and I2C peripherals will be configured in a peripheral specific init function just ahead of use.

    //*********** Initialize unused pins ****************
    // NOTE: unused pins are configured as inputs at processor reset, precursor to init() being called, lowest power

    // ***    PortA    ****
    // PA0,PA1 Console UART, PA2-PA5 SPI for uSD, PA6, PA7 unused

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_6);   // PA6, pin 45
    //ROM_GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_6, 0x00);  // Clear

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_7);   // PA7, pin 46
    //ROM_GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_7, 0x00);  // Clear

    // ***    PortB    ****
    // PB0 unused, PB1 unused, PB2,PB3 are SCL/SDA, PB4 is Humidity, PB5 unused, PB6, PB7 not routed on 144 pin chip

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_0);   // PB0, pin 97
    //ROM_GPIOPinWrite(GPIO_PORTB_BASE, GPIO_PIN_0, 0x00);  // Clear

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_1);   // PB1, pin 98
    //ROM_GPIOPinWrite(GPIO_PORTB_BASE, GPIO_PIN_1, 0x00);  // Clear

    // ---- i2c -----
    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_2); // PB2, pin 99  SCL i2c for FRAM
    ROM_GPIOPinWrite(GPIO_PORTB_BASE, GPIO_PIN_2, 0xFF);    // Set (R62 pull up)

    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_3); // PB3, pin 100, SDA for FRAM
    ROM_GPIOPinWrite(GPIO_PORTB_BASE, GPIO_PIN_3, 0xFF);    // Set (R63 pull up)

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_4);   // PB4, pin 136  Humidity ADC
    //ROM_GPIOPinWrite(GPIO_PORTB_BASE, GPIO_PIN_4, 0x00);  // Clear

    // ***     PortD    ****
    // PD0 to PD3 (MPHOX port power control), not used on MFET, PD4 unused, PD5 Pressure no longer used, PD6 not used, PD7 Input Voltage
#if BOARD_MPHOX >= 1  || BOARD_MSC == 2
    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE, GPIO_PIN_0); // CTDpwr off  PD0, (pin 1, on 144) CTDpwr on MPHOX, unused pin on MFET
    ROM_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_0, 0x00);    // CTDpwr=off   silk: J8

    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE, GPIO_PIN_1); // AUXpwr1 off  PD1, (pin 2) AUXpwr1 on MPHOX, unused pin on MFET
    ROM_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_1, 0x00);    // AUXpwr1=off   silk: J12 AUX - PWR1

    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE, GPIO_PIN_2); // AUXpwr2 off  PD2, (pin 3)  AUXpwr2 on MPHOX, unused pin on MFET
    ROM_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_2, 0x00);    // AUXpwr2=off   silk: J13 AUX - PWR2

    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE, GPIO_PIN_3); // AUXpwr3 (MPHOX) (PD3, pin 4)  AUXPwr3 on MPHOX, unused pin on MFET
    ROM_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_3, 0x00);    // AUXpwr3=0     silk: J14  COMM - PWR
#endif

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE, GPIO_PIN_5);   // PD5, pin 142  Pressure (no longer used)
    //ROM_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_5, 0x00);  // Clear

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE, GPIO_PIN_7);   // PD7, pin 144  Input Voltage (ADC12)
    //ROM_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_7, 0x00);  // Clear


    // ***     PortE    ****
    // PE3 is green LED on MPHOX, PP2 is red LED, handled in led_init(), all other PortE pins are unused on MPHOX and MFET
    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTE_BASE, GPIO_PIN_3); // Green LED (PE3, pin 12)
    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTP_BASE, GPIO_PIN_2); // Red LED (PP2, pin 11)  (HMMM)

    ROM_GPIOPinWrite(GPIO_PORTP_BASE, GPIO_PIN_2, 0xFF);    // Red LED off
    ROM_GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_3, 0x00);    // LED GREEN off

#if BOARD_MSC == 2
    // PK0 = en_xcvr  (output)
    // PE0 = CTS (input)
    // PE1 = RTS (output)

    ROM_GPIOPinTypeGPIOInput(GPIO_PORTE_BASE, GPIO_PIN_0); // PE0 = CTS (input)
    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTE_BASE, GPIO_PIN_1); // PE1 = RTS (output)

    ROM_GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_1, 0xFF);    // RTS = 1 is the default (inactive)
#endif

    // ***     PortG    ****
    // PG0 - PG7 not used on MFET, PG7,PG6,PG2,PG0 not used on MPHOX,  UART on PG4,PG5 is UART2 for CTD,  PG3/PG1 are PWM on MPHOX
#if BOARD_MPHOX >= 1  || BOARD_MSC == 2
    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE, GPIO_PIN_1); // PG1, pin 54  MPHOX solenoid
    ROM_GPIOPinWrite(GPIO_PORTG_BASE, GPIO_PIN_1, 0x00);    // Clear

    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE, GPIO_PIN_3); // PG3, pin 52  MPHOX solenoid
    ROM_GPIOPinWrite(GPIO_PORTG_BASE, GPIO_PIN_3, 0x00);    // Clear
#endif

    // ***     PortH    ****
    // PH0, PH1, PH2, PH3 are SPI, PH4-PH7 are unused
    /*** Initialize isolated ADS1248 pins as GPIO to reduce power consumption, this will be init'd later as SPI ***/
    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE, GPIO_PIN_0);     // SSI3CLK
    ROM_GPIOPinWrite(GPIO_PORTH_BASE, GPIO_PIN_0, 0x00);

    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE, GPIO_PIN_1);     // SSI3Fss
    ROM_GPIOPinWrite(GPIO_PORTH_BASE, GPIO_PIN_1, 0x00);

    ROM_GPIOPinTypeGPIOInput(GPIO_PORTH_BASE, GPIO_PIN_2);      // SSI3Rx

    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE, GPIO_PIN_3);     // SSI3Tx
    ROM_GPIOPinWrite(GPIO_PORTH_BASE, GPIO_PIN_3, 0x00);

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE, GPIO_PIN_4); // PH4, pin 26
    //ROM_GPIOPinWrite(GPIO_PORTH_BASE, GPIO_PIN_4, 0x00);    // Clear

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE, GPIO_PIN_5); // PH5, pin 23
    //ROM_GPIOPinWrite(GPIO_PORTH_BASE, GPIO_PIN_5, 0x00);    // Clear

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE, GPIO_PIN_6); // PH6, pin 22
    //ROM_GPIOPinWrite(GPIO_PORTH_BASE, GPIO_PIN_6, 0x00);    // Clear

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE, GPIO_PIN_7); // PH7, pin 21
    //ROM_GPIOPinWrite(GPIO_PORTH_BASE, GPIO_PIN_7, 0x00);    // Clear

    // ***     PORTJ   ****
    // PJ0-PJ7 unused on MPHOX and MFET

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTJ_BASE, GPIO_PIN_0);   // PJ0, pin 120
    //ROM_GPIOPinWrite(GPIO_PORTJ_BASE, GPIO_PIN_0, 0x00);  // Clear

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTJ_BASE, GPIO_PIN_1);   // PJ1, pin 121
    //ROM_GPIOPinWrite(GPIO_PORTJ_BASE, GPIO_PIN_1, 0x00);  // Clear

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTJ_BASE, GPIO_PIN_4);   // PJ4, pin 127
    //ROM_GPIOPinWrite(GPIO_PORTJ_BASE, GPIO_PIN_4, 0x00);  // Clear

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTJ_BASE, GPIO_PIN_5);   // PJ5, pin 128
    //ROM_GPIOPinWrite(GPIO_PORTJ_BASE, GPIO_PIN_5, 0x00);  // Clear

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTJ_BASE, GPIO_PIN_6);   // PJ6, pin 129
    //ROM_GPIOPinWrite(GPIO_PORTJ_BASE, GPIO_PIN_6, 0x00);  // Clear

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTJ_BASE, GPIO_PIN_7);   // PJ7, pin 130
    //ROM_GPIOPinWrite(GPIO_PORTJ_BASE, GPIO_PIN_7, 0x00);  // Clear


    // ***     PORT K    ****
    // PK0, PK1 ADC, PK2 IsoPwr, PK3,PK4,PK5,PK6,PK7 unused
    // Isolated power
    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTK_BASE, GPIO_PIN_2);
    ROM_GPIOPinWrite(GPIO_PORTK_BASE, GPIO_PIN_2, 0x00);        // PK2 pin 18 Iso-power Off

#if BOARD_MSC == 2
    // PK0 = en_xcvr  (output)

    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTK_BASE, GPIO_PIN_0); // PK0 = xcvr en (output)

    ROM_GPIOPinWrite(GPIO_PORTK_BASE, GPIO_PIN_0, 0x00);

#endif

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTK_BASE, GPIO_PIN_5);   // PK5, pin 111
    //ROM_GPIOPinWrite(GPIO_PORTK_BASE, GPIO_PIN_5, 0x00);  // Clear

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTK_BASE, GPIO_PIN_6);   // PK6, pin 110
    //ROM_GPIOPinWrite(GPIO_PORTK_BASE, GPIO_PIN_6, 0x00);  // Clear

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTK_BASE, GPIO_PIN_7);   // PK7, pin 109
    //ROM_GPIOPinWrite(GPIO_PORTK_BASE, GPIO_PIN_7, 0x00);  // Clear

    // ***     Port L   ****
    // PL0 Console Enable, PL1 Console Shutdown, PL2 5V Optode Power, PL3,PL4 unused, PL5 SDpresent, PL6,PL7 unused
#ifdef WRONGSPOT   // caused garbage char on power up, moved up to top of init  Mar 2022
#if BOARD_MFET == 2
    // MFET revB has MAX3222EETP+  ENABLE# is active low, SHUTDOWN# is active low   Dual level translator
    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_0); // PL0, pin 108             // CONSOLE ENABLE #
    ROM_GPIOPinWrite(GPIO_PORTL_BASE, GPIO_PIN_0, 0x00);    // Clear pin to turn console driver on

    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_1); // PL0, pin 107             // CONSOLE SHUTDOWN # (active low)
    ROM_GPIOPinWrite(GPIO_PORTL_BASE, GPIO_PIN_1, 0xff);    // Set to disable shutdown (part is enabled)
#endif
#endif
#if BOARD_MPHOX >= 1  || BOARD_MSC == 2
    // MPHOX revA has ADM3312    ENABLE# is active low, SHUTDOWN is active high   Triple RS232 level translator

    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_0); // PL0, pin 108             // CONSOLE ENABLE active ;pe
    ROM_GPIOPinWrite(GPIO_PORTL_BASE, GPIO_PIN_0, 0x00);    // Set pin 108 to turn console driver on

    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_1); // PL0, pin 107             // CONSOLE SHUTDOWN  (active high)
    ROM_GPIOPinWrite(GPIO_PORTL_BASE, GPIO_PIN_1, 0x00);    // Clear pin 107 to disable shutdown (part is enabled)

    // Thom TODO: config the pins for the Spare RS232 level translator
    // PMO, PM1 on MPHOX only
#endif

    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_2); // PL2, pin 106   5vOn signal for optode port power
    ROM_GPIOPinWrite(GPIO_PORTL_BASE, GPIO_PIN_2, 0x00);    // Clear

    ROM_GPIOPinTypeGPIOInput(GPIO_PORTL_BASE, GPIO_PIN_5);  // PL5, pin 103  SDpresent (input)  (BUG FIX 16 Nov 2021, was setup as an output)

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_3);   // PL3, pin 105
    //ROM_GPIOPinWrite(GPIO_PORTL_BASE, GPIO_PIN_3, 0x00);  // Clear

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_4);   // PL4, pin 104
    //ROM_GPIOPinWrite(GPIO_PORTL_BASE, GPIO_PIN_4, 0x00);  // Clear

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_6);   // PL6, pin 96
    //ROM_GPIOPinWrite(GPIO_PORTL_BASE, GPIO_PIN_6, 0x00);  // Clear

    // ***     Port M   ****
    // PM0-PM5 unused on MFET  PM0,PM1 Spare Enable/Shutdown rs232,  PM6 Venable, PM7 EnvEnable
#if BOARD_MPHOX >= 1  || BOARD_MSC == 2
    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTM_BASE, GPIO_PIN_0); // PM0, pin 89
    ROM_GPIOPinWrite(GPIO_PORTM_BASE, GPIO_PIN_0, 0x00);    // Clear

    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTM_BASE, GPIO_PIN_1); // PM1, pin 88
    ROM_GPIOPinWrite(GPIO_PORTM_BASE, GPIO_PIN_1, 0x00);    // Clear
#endif

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTM_BASE, GPIO_PIN_2);   // PM2, pin 87
    //ROM_GPIOPinWrite(GPIO_PORTM_BASE, GPIO_PIN_2, 0x00);  // Clear

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTM_BASE, GPIO_PIN_3);   // PM3, pin 86
    //ROM_GPIOPinWrite(GPIO_PORTM_BASE, GPIO_PIN_3, 0x00);  // Clear

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTM_BASE, GPIO_PIN_5);
    //ROM_GPIOPinWrite(GPIO_PORTM_BASE, GPIO_PIN_5, 0x00);        // PM5 pin 84 unused

    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTM_BASE, GPIO_PIN_6); // PM6, pin 83  Venable - turns off vbat to adc
    ROM_GPIOPinWrite(GPIO_PORTM_BASE, GPIO_PIN_6, 0x00);    // Clear

    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTM_BASE, GPIO_PIN_7); // PM7, pin 82  EnvVenable - turns on power to env sensor
    ROM_GPIOPinWrite(GPIO_PORTM_BASE, GPIO_PIN_7, 0x00);    // Clear

    // ***     Port N   ****
    // PN0, PN1, PN2, PN7 unused   PN3, PN4, PN5, PN6 are SPI for ADC on MCAP
    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_0);   // PN0, pin 81
    //ROM_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_0, 0x00);  // Clear

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_1);   // PN1, pin 80
    //ROM_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_1, 0x00);  // Clear

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_2);   // PN2, pin 20
    //ROM_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_2, 0x00);  // Clear

    // START pin (non-iso)  SEAPHOX ONLY
    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_7);
    //ROM_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_7, 0x00);        // Clear pin

    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_4);     // PN4 pin 71 Routed to TP3
    ROM_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_4, 0x00);

    ROM_GPIOPinTypeGPIOInput(GPIO_PORTN_BASE, GPIO_PIN_3);      // PN3 pin 119 MCAP ADS1248 SPI DRDY as Input

    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_5);     // PN5 pin 70 RESET high
    ROM_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_5, 0xFF);          // ADS1248 MCAP RESET pin

    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_6);    // PN6 pin 69 START should be high by default
    ROM_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_6, 0xFF);       // ADS1248 SPI START pin (iso)  MCAP

    // ***     Port P   ****
    // Unused PPO, PP1
    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTP_BASE, GPIO_PIN_0); // PP0, pin 131
    //ROM_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_0, 0x00);    // Clear

    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTP_BASE, GPIO_PIN_1); // PP1, pin 132
    //ROM_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_1, 0x00);    // Clear

    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTP_BASE, GPIO_PIN_2); // Red LED (PP2, pin 11)  (HMMM)
    ROM_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_2, 0x00);    // Clear


    //*********************** Onchip special function peripheral setup ***************************************


    /*** Initialize the console uart0 ***/
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
    ROM_GPIOPinConfigure(GPIO_PA0_U0RX);
    ROM_GPIOPinConfigure(GPIO_PA1_U0TX);
    ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
    UARTClockSourceSet(UART0_BASE, UART_CLOCK_PIOSC);
    UARTStdioConfig(0, 115200, 16000000);       // 115200 bits per second
#if BOARD_MFET == 2
    // MFET revB has MAX3222EETP+  ENABLE# is active low, SHUTDOWN# is active low   Dual level translator
    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_0); // PL0, pin 108             // CONSOLE ENABLE #
    ROM_GPIOPinWrite(GPIO_PORTL_BASE, GPIO_PIN_0, 0x00);    // Clear pin to turn console driver on

    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_1); // PL0, pin 107             // CONSOLE SHUTDOWN # (active low)
    ROM_GPIOPinWrite(GPIO_PORTL_BASE, GPIO_PIN_1, 0xff);    // Set to disable shutdown (part is enabled)
#endif
#if BOARD_MPHOX >= 1  || BOARD_MSC == 2
    // MPHOX revA has ADM3312    ENABLE# is active low, SHUTDOWN is active high   Triple RS232 level translator

    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_0); // PL0, pin 108             // CONSOLE ENABLE active ;pe
    ROM_GPIOPinWrite(GPIO_PORTL_BASE, GPIO_PIN_0, 0x00);    // Set pin 108 to turn console driver on

    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_1); // PL0, pin 107             // CONSOLE SHUTDOWN  (active high)
    ROM_GPIOPinWrite(GPIO_PORTL_BASE, GPIO_PIN_1, 0x00);    // Clear pin 107 to disable shutdown (part is enabled)

    // Thom TODO: config the pins for the Spare RS232 level translator
    // PMO, PM1 on MPHOX only
#endif
    UARTEchoSet(true);  // Enable console echo


    //**** onchip ADC Setup

#if BOARD_MFET >= 1 || BOARD_MPHOX == 1  || BOARD_MSC == 2       // onchip ADC setup
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
    ROM_SysCtlDelay(3);

    //Reset the ADC peripherals
    ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_ADC0);
    //Wait "READY"
    while(!ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_ADC0));

    // Select the external reference for greatest accuracy.
    //ROM_ADCReferenceSet(ADC0_BASE, ADC_REF_EXT_3V);

    //ROM_ADCClockConfigSet(ADC_CLOCK_RATE_HALF);     // 500K rather than default 1M
#endif





}
