\t (00:00:04) allegro 17.2 S047 Windows SPB 64-bit Edition
\t (00:00:04)     Journal start - Tue May 07 09:18:24 2019
\t (00:00:04)         Host=ARCHER User=jrosal Pid=15700 CPUs=16
\t (00:00:04) CmdLine= c:\cadence\spb_17.2\tools\bin\allegro.exe X:\901805-Coastal Biogeochemical Sensing\Project.Drawings\Project.EE.Dwgs\MFET\PCB_REVB\100221249rB_MFET.brd
\t (00:00:04) 
   (00:00:04) Loading axlcore.cxt 
\t (00:00:04) Opening existing design...
\i (00:00:05) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged 100221249rB_MFET
\w (00:00:05) WARNING(SPMHDB-212): Design feature(s) are disabled because selected product and option(s) do not
match design capability required: Via Z. DRC set "out of date".. Either select required product and
option(s) in Product Choices or click Update to Tier in File Properties to
suppress the message. See Allegro PCB Design Solutions datasheet on
www.cadence.com for mapping of products and options to design features.
\i (00:00:06) fillin confirm
\d (00:00:06) Design opened: X:/901805-Coastal Biogeochemical Sensing/Project.Drawings/Project.EE.Dwgs/MFET/PCB_REVB/100221249rB_MFET.brd
\i (00:00:07) trapsize 412
\i (00:00:07) trapsize 419
\i (00:00:07) trapsize 412
\i (00:00:07) trapsize 511
\i (00:00:07) trapsize 450
\i (00:00:07) trapsize 511
\i (00:00:07) trapsize 450
\i (00:00:07) generaledit 
\i (00:00:09) exit 
\t (00:00:10)     Journal end - Tue May 07 09:18:29 2019