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    ("Allegro Netlist Directory" "PCB_REVB")
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    ("Allegro Netlist Output Board File" ".\allegro\glider.brd")
    ("Allegro Netlist Remove Etch" "FALSE")
    ("Allegro Netlist Place Changed Component" "ALWAYS_REPLACE")
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    (File ".\mfet_revb.dsn"
      (Type "Schematic Design"))
    (Board_sim_option "VHDL_flow")
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  (Folder "Layout")
  (Folder "Outputs"
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      (DisplayName "pstxnet.dat"))
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    (Sort User)
    (File "MFET_REVB.PRP"
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      (DisplayName "MFET_REVB.PRP")))
  (Folder "Referenced Projects")
  (GlobalState
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      (Path "Design Resources"
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      (Path "Outputs"))
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  (Folder "PSpice Resources"
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    (Folder "Model Libraries"
      (Sort User))
    (Folder "Stimulus Files"
      (Sort User))
    (Folder "Include Files"
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  (Folder "Logs")
  (MPSSessionName "sjensen"))