********************************************************************************
*  Performance checking for design X:/Underway DuraFET/Project.Drawings/Project.EE.Dwgs/glider/allegro/Size_B_4LAYERS_Complete.brd
********************************************************************************

Ratsnest schedule check
-------------------------------
* OK.

DRC checks
----------------------
* OK.

Constraint region check
-------------------------------
* OK.

Dynamic shape check
-------------------------------
* Generated positive dynamic shape has no voids.
  Suggest replacing with a static shape.
  ISSUE: Voidless shapes (e.g. thick etch) should be static shapes to avoid
         processing overhead.
      shape/region location:  (685.0 495.0)
      layer:                  ETCH/BOTTOM


Sector table check
-------------------------------
* OK.

Constraint set check
---------------------------------
* OK.

NODRC_SYM_SAME_PIN check
---------------------------------
* OK.

Cross section check for bad dielectric constant values
--------------------------------------------------------
* OK.

Padstack size check
----------------------
* OK.

Conductor line check
------------------------------
* OK.

Design Constraints Statistics
---------------------------------
  Physical csets       =     1
  Spacing csets        =     1
  Same net csets       =     1
  Electrical csets     =     0
  Other csets          =     0
  Total csets        ===     3

  Cset relation table  =     0

  Constraint regions   =     0
  Constraint shapes    =     0

* OK.

=========
SUMMARY
=========

1 problems found.	0 maintenance problems found.