Protel Design System Design Rule Check
PCB File : C:\Users\rob\Dropbox\Glatts\Sch\SeapHOx-E.PcbDoc
Date     : 10/9/2014
Time     : 3:24:31 PM

Processing Rule : Net Antennae (Tolerance=0mil) (Disabled)(All)
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=8mil) (All),(All)
Rule Violations :0

Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
Rule Violations :0

Processing Rule : Width Constraint (Min=8mil) (Max=100mil) (Preferred=10mil) (All)
Rule Violations :0

Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
Rule Violations :0

Processing Rule : Hole Size Constraint (Min=15mil) (Max=200mil) (All)
Rule Violations :0

Processing Rule : Hole To Hole Clearance (Gap=10mil) (All),(All)
Rule Violations :0

Processing Rule : Minimum Solder Mask Sliver (Gap=5mil) (Disabled)(All),(All)
Rule Violations :0

Processing Rule : Silk To Solder Mask (Clearance=3mil) (IsPad),(All)
Rule Violations :0

Processing Rule : Silk to Silk (Clearance=1mil) (All),(All)
Rule Violations :0

Processing Rule : Silk primitive without silk layer
Rule Violations :0

Processing Rule : SMD Neck-Down Constraint (Percent=100%) (All)
Rule Violations :0


Violations Detected : 0
Time Elapsed        : 00:00:03