/*******************************************************************************
**	cf2_qsm332.h -- 68332 CF2 Queued Serial Module Definitions
**  07may2008, adapted from TT8 qsm332.h
**  hardwired for metrowerks bit field format
**  now cf2 SPI calls can be done in a similar way to the TT8
*******************************************************************************/

#ifndef		__cf2_qsm332_H
#define		__cf2_qsm332_H

#ifdef __cplusplus
  extern "C" {
#endif

// following taken from tat332.h code -----------------------------------------
#ifdef __MWERKS__ 
	#define FIRST_BF_8000	/* bit field assignment 8000,4000,2000,...,0001 */
#endif	/* __MWERKS__ */
//**note below is only defined for above=true

// typedefs used below for recasting addresses to pointer to structs
typedef volatile unsigned int   unsint;	// 17Feb2002--jhg
typedef volatile uchar		   *ucpv;
typedef volatile ushort		   *uspv;
typedef volatile ulong		   *ulpv;
typedef char 				   *ptr;

#define IMBASE			0xFFFFF000
// QSM_BASE_ADDR is defined in persistor's mc68332.h
// #define	QSM_BASE_ADDR		0xFFFFFC00...so yes, IMBASE is correct
//-----------------------------------------------------------------------------



// define memory map to QSM registers
// these are now (either byte or short) pointers to each register

#define		QMCR			    ((uspv) (IMBASE + 0xC00)) // master config
#define		QILR				((ucpv) (IMBASE + 0xC04)) // interrupt level
#define		QVLR				((ucpv) (IMBASE + 0xC05)) // interrupt vector

#define		QPDR			    ((ucpv) (IMBASE + 0xC15)) // PORTQS
#define		QPAR			    ((ucpv) (IMBASE + 0xC16)) // Pin-Assign-Register
#define		QDDR			    ((ucpv) (IMBASE + 0xC17)) // data-direction

#define		SPCR0				((uspv) (IMBASE + 0xC18)) // SPI control reg0
#define		SPCR1				((uspv) (IMBASE + 0xC1A)) // SPI control reg1
#define		SPCR2				((uspv) (IMBASE + 0xC1C)) // SPI control reg2
#define		SPCR3				((ucpv) (IMBASE + 0xC1E)) // SPI control reg3
#define		SPSR				((ucpv) (IMBASE + 0xC1F)) // SPI status reg.

#define		SCCR0				((uspv) (IMBASE + 0xC08)) // SCI control reg0
#define		SCCR1				((uspv) (IMBASE + 0xC0A)) // SCI control reg1
#define		SCSR				((uspv) (IMBASE + 0xC0C)) // SCI status register
#define		SCDR				((uspv) (IMBASE + 0xC0E)) // SCI data register


// SPI RAM --------------------------------------------------------------------
#define		SPIRCV				((uspv) (IMBASE + 0xD00)) // RCV RAM
#define		SPIXMT				((uspv) (IMBASE + 0xD20)) // XMT RAM
#define		SPICMD				((ucpv) (IMBASE + 0xD40))
#define		SPICMDARRAY			((uchar *) (IMBASE + 0xD40))
/****************************************************************************/
// QSPI COMMAND CONTROL RAM (SPICMD)  [SIM-5-33] 
// p. D-32 has the bit definitions
	#define		M_CONT		0x80		// 1=keep CS asserted, 0= returns to PORTQS value
	#define		M_BITSE		0x40		// 0=8 bits, 1=use SPCR0->BITS setting
	#define		M_DT		0x20		// 0=no delay after xfr,1=use SPCR1->DTL setting
	#define		M_DSCK		0x10		// 0=1/2SCK for initial delay, 1=use SPCR1->DSCKL
	
	#define		M_CS3		0x08		// use chip select 3
	#define		M_CS2		0x04		// use chip select 2	
	#define		M_CS1		0x02		// use chip select 1
	#define		M_CS0		0x01		// use chip select 0
	



//following defines bit structures for easy access to register bits.

/****************************************************************************/
struct	QMCR_			/* QSM CONFIGURATION REGISTER (QMCR)  [SIM-5-11]	*/
	{ // p. D-20
#ifdef FIRST_BF_8000
	unsint		QSTOP	:	1;
	#define		M_QSTOP		0x8000			/* 1 = QSM clock stopped		*/
	unsint		FRZ1	:	1;
	#define		M_FRZ1		0x4000			/* 1 = halt QSM @ FREEZE		*/
	unsint		FRZ0	:	1;
	#define		M_FRZ0		0x2000			/* reserved for future			*/
	unsint				:	5;
	unsint		QSUPV	:	1;
	#define		M_QSUPV		0x0080			/* 1 = restrict access			*/
	unsint				:	3;
	unsint		QIARB	:	4;
	#define		M_QIARB		0x0004			/* interrupt arbitration bits	*/
#endif
	};

#define		_QMCR			(  (struct QMCR_ *) QMCR   )

	

/****************************************************************************/
struct	QPDR_			/* QSM PIN DATA REGISTER (QPDR)  [SIM-5-15]			*/
	{ // PORTQS, Port QS Data Register, p. D-26 
#ifdef FIRST_BF_8000
	unsint				:	8; // MSB=dummy, QPDR really starts at 0xC15
	unsint		TXD		:	1;		/* pin 7	(TXD)						*/
	unsint		PCS3	:	1;		/* pin 6	(PCS3)						*/
	unsint		PCS2	:	1;		/* pin 5	(PCS2)						*/
	unsint		PCS1	:	1;		/* pin 4	(PCS1)						*/
	unsint		PCS0	:	1;		/* pin 3	(PCS0)						*/
	unsint		SCK		:	1;		/* pin 2	(SCK)						*/
	unsint		MOSI	:	1;		/* pin 1	(MOSI)						*/
	unsint		MISO	:	1;		/* pin 0	(MISO)						*/
#endif
	};
#define		_QPDR			((volatile struct QPDR_ *) (IMBASE + 0xC14))


/****************************************************************************/
struct	QPAR_			/* QSM PIN ASSIGNMENT REGISTER (QPAR)  [SIM-5-15]	*/
	{ // p. D-D-26, PQSPAR
#ifdef FIRST_BF_8000
	unsint		TXD		:	1;      // pin 7
	unsint		PCS3	:	1;		/* pin 6	(PCS3)						*/
	unsint		PCS2	:	1;		/* pin 5	(PCS2)						*/
	unsint		PCS1	:	1;		/* pin 4	(PCS1)						*/
	
	unsint		PCS0	:	1;		/* pin 3	(PCS0)						*/
	unsint		SCK		:	1;		// pin 2    (SCK)
	unsint		MOSI	:	1;		/* pin 1	(MOSI)						*/
	unsint		MISO	:	1;		/* pin 0	(MISO)						*/
	unsint				:	8;
#endif
	};
#define		_QPAR			((struct QPAR_ *) QPAR)


/****************************************************************************/
struct	QDDR_			/* QSM DATA DIRECTION REGISTER (QDDR)  [SIM-5-16]	*/
	{ // p. D-26, DDRQS
#ifdef FIRST_BF_8000
	unsint				:	8;
	unsint		TXD		:	1;		/* pin 7	(TXD)						*/
	unsint		PCS3	:	1;		/* pin 6	(PCS3)						*/
	unsint		PCS2	:	1;		/* pin 5	(PCS2)						*/
	unsint		PCS1	:	1;		/* pin 4	(PCS1)						*/
	unsint		PCS0	:	1;		/* pin 3	(PCS0)						*/
	unsint		SCK		:	1;		/* pin 2	(SCK)						*/
	unsint		MOSI	:	1;		/* pin 1	(MOSI)						*/
	unsint		MISO	:	1;		/* pin 0	(MISO)						*/
#endif
	};
#define		_QDDR			((struct QDDR_ *) (IMBASE + 0xC16))

/****************************************************************************/
/*					MASKS FOR QPDR, QPAR, AND QDDR							*/
#define			M_TXD		0x80		/* pin 7	(TXD)					*/
#define			M_PCS3		0x40		/* pin 6	(PCS3)					*/
#define			M_PCS2		0x20		/* pin 5	(PCS2)					*/
#define			M_PCS1		0x10		/* pin 4	(PCS1)					*/
#define			M_PCS0		0x08		/* pin 3	(PCS0)					*/
#define			M_SCK		0x04		/* pin 2	(SCK)					*/
#define			M_MOSI		0x02		/* pin 1	(MOSI)					*/
#define			M_MISO		0x01		/* pin 0	(MISO)					*/


/****************************************************************************/
struct	SPCR0_				/* QSPI CONTROL REGISTER 0 (SPCR0)  [SIM-5-22]	*/
	{  // p. D-28
#ifdef FIRST_BF_8000
	unsint		MSTR	:	1;
	#define		M_MSTR		0x8000		/* 1 = Master, 0 = Slave		*/
	unsint		WOMQ	:	1;
	#define		M_WOMQ		0x4000		/* 1 = open drain, 0 = cmos		*/
	unsint		BITS	:	4;
	unsint		CPOL	:	1;
	#define		M_CPOL		0x0200		/* 1 = inactive SCK high		*/
	unsint		CPHA	:	1;
	#define		M_CPHA		0x0100		/* 1 = chg lding, capt folng	*/
	unsint		BAUD	:	8;
#endif
	};
#define		_SPCR0				((struct SPCR0_ *) SPCR0)


/****************************************************************************/
struct	SPCR1_				/* QSPI CONTROL REGISTER 1 (SPCR1)  [SIM-5-25]	*/
	{ // p. D-29
#ifdef FIRST_BF_8000
	unsint		SPE		:	1;
	#define		M_SPE		0x8000		/* QSPI enable = 1, 0 = I/O		*/
	unsint		DSCKL	:	7;  // see p. 6-19, start delay, from CS to SCK
	unsint		DTL		:	8;  // Delay After Transfer = 32*DTL/Sys_Clock p.6-20
#endif
	};
#define		_SPCR1				((struct SPCR1_ *) SPCR1)


/****************************************************************************/
struct	SPCR2_				/* QSPI CONTROL REGISTER 2 (SPCR2)  [SIM-5-25]	*/
	{ // p. D-30
#ifdef FIRST_BF_8000
	unsint		SPIFIE	:	1;
	#define		M_SPIFIE	0x8000		/* SPI finished rupt	= 1		*/
	unsint		WREN	:	1;
	#define		M_WREN		0x4000		/* wraparound enable = 1		*/
	unsint		WRTO	:	1;
	#define		M_WRTO		0x2000		/* wrap to 						*/
	unsint				:	1;
	unsint		ENDQP	:	4;			/* Ending Queue Pointer			*/
	unsint				:	4;
	unsint		NEWQP	:	4;			/* New Queue Pointer			*/
#endif
	};
#define		_SPCR2				((struct SPCR2_ *) SPCR2)


/****************************************************************************/
struct	SPCR3_				/* QSPI CONTROL REGISTER 3 (SPCR3)  [SIM-5-29]	*/
	{  // p. D-30
#ifdef FIRST_BF_8000
	unsint				:	5;
	unsint		LOOPQ	:	1;
	#define		M_LOOPQ		0x04		/* QSPI loop mode, 1=on			*/
	unsint		HMIE	:	1;
	#define		M_HMIE		0x02		/* HALTA & MODF rupt enable		*/
	unsint		HALT	:	1;
	#define		M_HALT		0x01		/* Halt							*/
	unsint				:	8;
#endif
	};
#define		_SPCR3				((struct SPCR3_ *) (IMBASE + 0xC1E))
// #define		_SPCR3				( (struct SPCR3_ *) (SPCR3) )



/****************************************************************************/
struct	SPSR_				/* QSPI STATUS REGISTER (SPSR)  [SIM-5-30]		*/
	{  // p. D-30
#ifdef FIRST_BF_8000
	unsint				:	8;
	unsint		SPIF	:	1;
	#define		M_SPIF		0x80		/* QSPI finished flag			*/
	unsint		MODF	:	1;
	#define		M_MODF		0x40		/* QSPI mode fault flag			*/
	unsint		HALTA	:	1;
	#define		M_HALTA		0x20		/* QSPI halt ack flag			*/
	unsint				:	1;
	unsint		CPTQP	:	4;			/* Completed Queue Pointer		*/
#endif
	};
#define		_SPSR				((struct SPSR_ *) (IMBASE + 0xC1E))





// SCI stuff, just for completeness.-------------------------------------------
//-----------------------------------------------------------------------------
	

/****************************************************************************/
struct	SCCR1_				/* SCI CONTROL REGISTER 1 (SCCR1)  [SIM-5-58]	*/
	{  // p. D-23
#ifdef FIRST_BF_8000
	unsint				:	1;
	unsint		LOOPS	:	1;
	#define		M_LOOPS		0x4000		/* 1 = test with loop enabled	*/
	unsint		WOMS	:	1;
	#define		M_WOMS		0x2000		/* 1 = TxD open drain, 0 = CMOS */
	unsint		ILT		:	1;
	#define		M_ILT		0x1000		/* 1 = long idle line detect	*/
	unsint		PT		:	1;
	#define		M_PT		0x0800		/* 1 = odd parity, 0 = even		*/
	unsint		PE		:	1;
	#define		M_PE		0x0400		/* 1 = parity enabled			*/
	unsint		M		:	1;
	#define		M_M			0x0200		/* 1 = 1s,9d,1s,  0 = 1s,8d,1s	*/
	unsint		WAKE	:	1;
	#define		M_WAKE		0x0100		/* 1 = wake addr mark, 0 = idle */
	unsint		TIE		:	1;
	#define		M_TIE		0x0080		/* 1 = enable TDRE interrupts	*/
	unsint		TCIE	:	1;
	#define		M_TCIE		0x0040		/* 1 = enable TC interrupts		*/
	unsint		RIE		:	1;
	#define		M_RIE		0x0020		/* 1 = enable RDRF interrupts	*/
	unsint		ILIE	:	1;
	#define		M_ILIE		0x0010		/* 1 = enable IDLE interrupts	*/
	unsint		TE		:	1;
	#define		M_TE		0x0008		/* 1 = TxD enabled, 0 = gp I/O	*/
	unsint		RE		:	1;
	#define		M_RE		0x0004		/* 1 = receiver enabled 		*/
	unsint		RWU		:	1;
	#define		M_RWU		0x0002		/* 1 = wakeup mode enabled		*/
	unsint		SBK		:	1;
	#define		M_SBK		0x0001		/* 1 = send break				*/
#endif
	};
#define		_SCCR1				((struct SCCR1_ *) SCCR1)


/****************************************************************************/
struct	SCSR_					/* SCI STATUS REGISTER (SCSR)  [SIM-5-62]	*/
	{  // p. D-24
#ifdef FIRST_BF_8000
	unsint				:	7;
	unsint		TDRE	:	1;
	#define		M_TDRE		0x0100		/* Transmit Data Register Empty	*/
	unsint		TC		:	1;
	#define		M_TC		0x0080		/* Transmit Complete Flag		*/
	unsint		RDRF	:	1;
	#define		M_RDRF		0x0040		/* Receive Data Register Full	*/
	unsint		RAF		:	1;
	#define		M_RAF		0x0020		/* Receiver Active Flag			*/
	unsint		IDLE	:	1;
	#define		M_IDLE		0x0010		/* Idle-Line Detected Flag		*/
	unsint		OR		:	1;
	#define		M_OR		0x0008		/* Overrun Error Flag			*/
	unsint		NF		:	1;
	#define		M_NF		0x0004		/* Noise Error Flag				*/
	unsint		FE		:	1;
	#define		M_FE		0x0002		/* Framing Error Flag			*/
	unsint		PF		:	1;
	#define		M_PF		0x0001		/* Parity Error Flag			*/
#endif
	};
#define		_SCSR				((struct SCSR_ *) SCSR)



#ifdef __cplusplus
 }
#endif

#endif	/*	__qsm332_H */

