Index of /internal/projects/902204_CoMPAS/ME.Drawings/AlexYinDesigns/Physical Design/Main Box Design/Stereo Cam/depthai-hardware-master/BW2098POE_PoE_Board/PCB

[ICO]NameLast modifiedSizeDescription

[PARENTDIR]Parent Directory  -  
[   ]Assembly_Drawing.PCBDwf2023-02-02 12:41 2.8M 
[   ]BOOT_JTAG_AUX.Harness2023-02-02 12:41 297  
[   ]BOOT_JTAG_AUX.SchDoc2023-02-02 12:38 532K 
[   ]BW2098POE.BomDoc2023-02-02 12:38 453K 
[   ]BW2098POE.PcbDoc2023-02-02 12:41 11M 
[   ]BW2098POE.PcbLib2023-02-02 12:41 2.7M 
[   ]BW2098POE.PrjPcb2023-02-02 12:41 57K 
[   ]BW2098POE.PrjPcbVariants2023-02-02 12:38 4.0K 
[   ]BW2098POE.SchLib2023-02-02 12:41 902K 
[   ]BW2098_MIPI_CAM.Harness2023-02-02 12:38 205  
[   ]BW2098_MIPI_CAM.SchDoc2023-02-02 12:41 55K 
[   ]BW2098_USB.Harness2023-02-02 12:41 56  
[   ]BW2098_USB.SchDoc2023-02-02 12:41 356K 
[   ]CONNECTOR_A.Harness2023-02-02 12:41 629  
[   ]CONNECTOR_A.SchDoc2023-02-02 12:41 119K 
[   ]CONNECTOR_B.Harness2023-02-02 12:41 371  
[   ]CONNECTOR_B.SchDoc2023-02-02 12:41 110K 
[   ]ETH_PCIE_PHY.Harness2023-02-02 12:41 215  
[   ]ETH_PCIE_PHY.SchDoc2023-02-02 12:41 380K 
[   ]Fabrication_Drawing.PCBDwf2023-02-02 12:41 1.1M 
[   ]PCIE_CLK.Harness2023-02-02 12:41 120  
[   ]PCIE_CLK.SchDoc2023-02-02 12:41 468K 
[   ]POWER_GEN.SchDoc2023-02-02 12:41 138K 
[   ]Project_Information.SchDoc2023-02-02 12:41 20K 
[   ]RJ45.Harness2023-02-02 12:41 57  

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