(---------------------------------------------------------------------)
(                                                                     )
(    Allegro Netrev Import Logic                                      )
(                                                                     )
(    Drawing          : Size_C_6LAYERS.brd                            )
(    Software Version : 17.2S047                                      )
(    Date/Time        : Thu May 16 09:49:05 2019                      )
(                                                                     )
(---------------------------------------------------------------------)


------ Directives ------------

Ripup etch:                  No
Ripup delete first segment:  No
Ripup retain bondwire:       No
Ripup symbols:               Always
Missing symbol has error:    No
DRC update:                  Yes
Schematic directory:         '.'
Design Directory:            'X:/CPF/Electrical Engr/Orcad Projects/Eds Stuff/Lower Half Elex P2/PCB'
Old design name:             'X:/CPF/Electrical Engr/Orcad Projects/Eds Stuff/Lower Half Elex P2/PCB/Size_C_6LAYERS.brd'
New design name:             'X:/CPF/Electrical Engr/Orcad Projects/Eds Stuff/Lower Half Elex P2/PCB/Size_C_6LAYERS.brd'

CmdLine: netrev -$ -i . -y 1 -h -q netrev_constraint_report.xml X:/CPF/Electrical Engr/Orcad Projects/Eds Stuff/Lower Half Elex P2/PCB/#Taaaaah13084.tmp

------ Preparing to read pst files ------

Starting to read ./pstchip.dat 
   Finished reading ./pstchip.dat (00:00:00.04)
Starting to read ./pstxprt.dat 
   Finished reading ./pstxprt.dat (00:00:00.03)
Starting to read ./pstxnet.dat 
   Finished reading ./pstxnet.dat (00:00:00.04)

------ Oversights/Warnings/Errors ------


------ Library Paths ------
MODULEPATH =  . 
           C:/Cadence/SPB_17.2/share/local/pcb/modules 

PSMPATH =  . 
           .. 
           //water2/CIP_Resources/Allegro_Library/Symbols 
           //water2/CIP_Resources/Allegro_Library/Pads 

PADPATH =  . 
           .. 
           //water2/CIP_Resources/Allegro_Library/Pads 
           //water2/CIP_Resources/Allegro_Library/PADS ARCHIVE 


------ Summary Statistics ------


netrev run on May 16 9:49:05 2019
   DESIGN NAME : '100221251 CPF LOWER HALF ELEX P2'
   PACKAGING ON Jan  2 2018 22:29:09

   COMPILE 'logic'
   CHECK_PIN_NAMES OFF
   CROSS_REFERENCE OFF
   FEEDBACK OFF
   INCREMENTAL OFF
   INTERFACE_TYPE PHYSICAL
   MAX_ERRORS 500
   MERGE_MINIMUM 5
   NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
   NET_NAME_LENGTH 24
   OVERSIGHTS ON
   REPLACE_CHECK OFF
   SINGLE_NODE_NETS ON
   SPLIT_MINIMUM 0
   SUPPRESS   20
   WARNINGS ON

 No error detected
 No oversight detected
 No warning detected

cpu time      0:01:25
elapsed time  0:00:00