(ExpressProject "Design1"
  (ProjectVersion "19981106")
  (SoftwareVersion "17.4-2019 S011 (3890763)  [9/18/2020]-[02/07/22]")
  (ProjectType "PCB")
  (Folder "Design Resources"
    (Folder "Library")
    (NoModify)
    (File ".\lowerhalfelexpribatt.dsn"
      (Type "Schematic Design")
      (DisplayName ".\lowerhalfelexpribatt.DSN"))
    (BuildFileAddedOrDeleted "x")
    (CompileFileAddedOrDeleted "x")
    (DOCKED "TRUE")
    (DOCKING_POSITION "59420")
    (Board_sim_option "VHDL_flow")
    (ANNOTATE_Scope "1")
    (ANNOTATE_Mode "1")
    (ANNOTATE_Action "1")
    (Annotate_Page_Order "0")
    (ANNOTATE_Reset_References_to_1 "TRUE")
    (ANNOTATE_No_Page_Number_Change "FALSE")
    (ANNOTATE_Property_Combine "{Value}{Source Package}{POWER_GROUP}")
    (ANNOTATE_IncludeNonPrimitive "FALSE")
    (ANNOTATE_PreserveDesignator "FALSE")
    (ANNOTATE_PreserveUserEdits "FALSE")
    (ANNOTATE_Refdes_Control_Required "FALSE")
    (Update_Instace_for_External_Design "FALSE")
    (Annotate_type "Default")
    (width_pages "100")
    (width_start "80")
    (width_End "80")
    (FLDSTUFF_Scope "0")
    (FLDSTUFF_Action "0")
    (FLDSTUFF_Report_File
       "z:\cpf\electrical engr\orcad projects\eds stuff\lowerhalfelexpribatt\schematics\lowerhalfelexpribatt.RPT")
    (FLDSTUFF_Update_File
       "z:\cpf\electrical engr\orcad projects\eds stuff\lowerhalfelexpribatt\schematics\lowerhalfelexpribatt.UPD")
    (FLDSTUFF__Uppercase_Result_Property "FALSE")
    (FLDSTUFF_Uppercase_Update_Property "FALSE")
    (FLDSTUFF_Uppercase_Unconditionally "FALSE")
    (FLDSTUFF_Visibility "0")
    (FLDSTUFF_inst_or_occurrence "0")
    (FLDSTUFF_Create_Report_File "FALSE")
    (Netlist_TAB "0")
    ("Create Allegro Netlist" "TRUE")
    ("Allegro Netlist Directory" "allegro")
    ("View Allegro Netlist Files" "FALSE")
    ("Allegro Netlist Create DCF File" "FALSE")
    ("Update Allegro Board" "FALSE")
    ("Allegro Netlist Output Board File" ".\allegro\lowerhalfelexpribatt.brd")
    ("Allegro Netlist Remove Etch" "FALSE")
    ("Allegro Netlist Place Changed Component" "ALWAYS_REPLACE")
    ("Allegro Netlist Open Board in Allegro" "ALLEGRO")
    ("Allegro Setup Backup Versions" "3")
    ("Allegro Setup Ignore Constraints" "FALSE")
    ("Allegro Setup Part Type Length" "255")
    ("Allegro Netlist Combine Property String" "PCB Footprint")
    ("Allegro Netlist Ignore Fixed Property" "FALSE")
    ("Allegro Netlist User Defined Property" "FALSE")
    (DRC_Scope "1")
    (DRC_Action "0")
    (DRC_Create_Warnings "TRUE")
    (DRC_View_Output "TRUE")
    (DRC_View_Output_Type "2")
    (DRC_Preserved_Waived "FALSE")
    (RUN_Online_Rules "TRUE")
    (DRC_Run_Electrical_Rules "TRUE")
    (DRC_Check_Single_Node_Nets "TRUE")
    (DRC_Check_No_Driving_Source "TRUE")
    (DRC_Check_Duplicate_NetNames "TRUE")
    (DRC_Check_Off-Page_Connectors "FALSE")
    (DRC_Check_Ports "FALSE")
    (DRC_Check_Unconnected_Nets "TRUE")
    (DRC_Check_Floating_Pins "TRUE")
    (DRC_SDT_Compatibility "FALSE")
    (DRC_Check_Single_Node_Nets_Online "TRUE")
    (DRC_Check_No_Driving_Source_Online "FALSE")
    (DRC_Check_Duplicate_NetNames_Online "TRUE")
    (DRC_Check_Off-Page_Connectors_Online "FALSE")
    (DRC_Check_Ports_Online "FALSE")
    (DRC_Check_Unconnected_Nets_Online "FALSE")
    (DRC_Check_Floating_Pins_Online "FALSE")
    (DRC_Run_Electrical_Reports "TRUE")
    (DRC_Report_Netnames "FALSE")
    (DRC_Report_Off-grid_Objects "FALSE")
    (DRC_Report_Ports_and_Off-page_Connectors "FALSE")
    (DRC_Check_for_Misleading_TAP "FALSE")
    (DRC_Run_Physical_Rules "TRUE")
    (DRC_Check_Physical_Power_Pins_Visibility "TRUE")
    (DRC_Check_PCB_Footprint_Property "TRUE")
    (DRC_Check_Normal_Convert_View_Sync "TRUE")
    (DRC_Check_Incorrect_PinGroup_Assignment "TRUE")
    (DRC_Check_High_Speed_Props_Syntax "TRUE")
    (DRC_Check_Missing_Pin_Numbers "TRUE")
    (DRC_Check_Device_With_No_Pins "TRUE")
    (DRC_Check_Power_Ground_Short "TRUE")
    (DRC_Check_Name_Prop_For_HierBlocks "TRUE")
    (DRC_Check_Physical_Power_Pins_Visibility_Online "FALSE")
    (DRC_Check_PCB_Footprint_Property_Online "TRUE")
    (DRC_Check_Normal_Convert_View_Sync_Online "FALSE")
    (DRC_Check_Incorrect_PinGroup_Assignment_Online "TRUE")
    (DRC_Check_Missing_Pin_Numbers_Online "TRUE")
    (DRC_Check_Device_With_No_Pins_Online "FALSE")
    (DRC_Check_Power_Ground_Short_Online "FALSE")
    (DRC_Check_Name_Prop_For_HierBlocks_Online "FALSE")
    (DRC_Run_Physical_Reports "TRUE")
    (DRC_Visible_Power_pins "FALSE")
    (DRC_Report_Unused_Part_Packages "TRUE")
    (DRC_Type_Mismatch "TRUE")
    (DRC_Identical_References "TRUE")
    (DRC_Run_Custom_Rules "FALSE")
    (DRC_Report_File
       "Z:\CPF\ELECTRICAL ENGR\ORCAD PROJECTS\EDS STUFF\LOWERHALFELEXPRIBATT\SCHEMATICS\LOWERHALFELEXPRIBATT.DRC"))
  (Folder "Layout")
  (Folder "Outputs"
    (File ".\allegro\pstxnet.dat"
      (Type "Report")
      (DisplayName "pstxnet.dat"))
    (File ".\allegro\pstxprt.dat"
      (Type "Report")
      (DisplayName "pstxprt.dat"))
    (File ".\allegro\pstchip.dat"
      (Type "Report")
      (DisplayName "pstchip.dat"))
    (File ".\lowerhalfelexpribatt.drc"
      (Type "Report")))
  (Folder "Referenced Projects")
  (PartMRUSelector
    (MOSFET_I_EN_GDSD
      (FullPartName "MOSFET_I_EN_GDSD.Normal")
      (LibraryName "\\WATER2\CIP_RESOURCES\SCHEMATIC_SYMBOLS\TRANSISTORS.OLB")
      (DeviceIndex "0"))
    (CON6
      (FullPartName "CON6.Normal")
      (LibraryName "\\WATER2\CIP_RESOURCES\SCHEMATIC_SYMBOLS\CONNECTORS.OLB")
      (DeviceIndex "0"))
    ("SCREW TERMINAL"
      (FullPartName "SCREW TERMINAL.Normal")
      (LibraryName "U:\UTILITY FILES\ORCAD LIBRARY\ED_NEW1.OLB")
      (DeviceIndex "0"))
    (IND_FB
      (FullPartName "IND_FB.Normal")
      (LibraryName "\\WATER2\CIP_RESOURCES\SCHEMATIC_SYMBOLS\INDUCTORS.OLB")
      (DeviceIndex "0"))
    (OpenDrainSmallPinless
      (FullPartName "OpenDrainSmallPinless.Normal")
      (LibraryName "U:\UTILITY FILES\ORCAD LIBRARY\PINLESSSHAPES.OLB")
      (DeviceIndex "0"))
    (OFFPAGELEFT-L
      (LibraryName "C:\CADENCE\SPB_17.2\TOOLS\CAPTURE\LIBRARY\CAPSYM.OLB")
      (DeviceIndex "0"))
    (OFFPAGELEFT-R
      (LibraryName "C:\CADENCE\SPB_17.2\TOOLS\CAPTURE\LIBRARY\CAPSYM.OLB")
      (DeviceIndex "0"))
    (RES
      (FullPartName "RES.Normal")
      (LibraryName "\\WATER2\CIP_RESOURCES\SCHEMATIC_SYMBOLS\RESISTORS.OLB")
      (DeviceIndex "0"))
    (CapAluSMTVert
      (FullPartName "CapAluSMTVert.Normal")
      (LibraryName "U:\UTILITY FILES\ORCAD LIBRARY\PLACEMENTSHAPESMEEDV1.OLB")
      (DeviceIndex "0"))
    (OptoPinless
      (FullPartName "OptoPinless.Normal")
      (LibraryName
         "\\ATLAS.SHORE.MBARI.ORG\MEED\UTILITY FILES\ORCAD LIBRARY\PINLESSSHAPES.OLB")
      (DeviceIndex "0"))
    (RPinless
      (FullPartName "RPinless.Normal")
      (LibraryName "U:\UTILITY FILES\ORCAD LIBRARY\PINLESSSHAPES.OLB")
      (DeviceIndex "0"))
    (NIMH
      (FullPartName "NIMH.Normal")
      (LibraryName
         "C:\CADENCE\SPB_17.2\TOOLS\CAPTURE\LIBRARY\PSPICE\BATTERY.OLB")
      (DeviceIndex "0")))
  (GlobalState
    (FileView
      (Path "Design Resources")
      (Path "Design Resources"
         "z:\cpf\electrical engr\orcad projects\eds stuff\lowerhalfelexpribatt\schematics\lowerhalfelexpribatt.dsn")
      (Path "Design Resources"
         "z:\cpf\electrical engr\orcad projects\eds stuff\lowerhalfelexpribatt\schematics\lowerhalfelexpribatt.dsn"
         "CPF_LHE_PriBatt_Schematic")
      (Path "Design Resources"
         "z:\cpf\electrical engr\orcad projects\eds stuff\lowerhalfelexpribatt\schematics\lowerhalfelexpribatt.dsn"
         "CPF_LHE_DC-DC_Schematic")
      (Path "Outputs")
      (Select "Design Resources"
         "z:\cpf\electrical engr\orcad projects\eds stuff\lowerhalfelexpribatt\schematics\lowerhalfelexpribatt.dsn"))
    (HierarchyView)
    (Doc
      (Type "COrCapturePMDoc")
      (Frame
        (Placement "44 0 1 -1 -1 -1 -1 0 200 0 569"))
      (Tab 0))
    (Doc
      (Type "COrSchematicDoc")
      (Frame
        (Placement "44 0 1 -1 -1 5 24 5 1290 24 610")
        (Scroll "-204 -3")
        (Zoom "36")
        (Occurrence "/"))
      (Path
         "Z:\CPF\ELECTRICAL ENGR\ORCAD PROJECTS\EDS STUFF\LOWERHALFELEXPRIBATT\SCHEMATICS\LOWERHALFELEXPRIBATT.DSN")
      (Schematic "CPF_LHE_PriBatt_Schematic")
      (Page "1_PwrCtrl"))
    (Doc
      (Type "COrSchematicDoc")
      (Frame
        (Placement "44 0 1 -1 -1 -1 -1 5 1290 24 610")
        (Scroll "-204 -3")
        (Zoom "36")
        (Occurrence "/"))
      (Path
         "Z:\CPF\ELECTRICAL ENGR\ORCAD PROJECTS\EDS STUFF\LOWERHALFELEXPRIBATT\SCHEMATICS\LOWERHALFELEXPRIBATT.DSN")
      (Schematic "CPF_LHE_PriBatt_Schematic")
      (Page "2_MoboIntfcSleepTimer")))
  (MPSSessionName "ckecy")
  (LastUsedLibraryBrowseDirectory "U:\Utility Files\OrCAD Library")
  (Folder "PSpice Resources"
    (Folder "Simulation Profiles")
    (Folder "Model Libraries"
      (Sort User))
    (Folder "Stimulus Files"
      (Sort User))
    (Folder "Include Files"
      (Sort User)))
  (Folder "Logs")
  (ISPCBBASICLICENSE "false"))
