NucleoUARTExample.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000002ac 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00006fcc 080002ac 080002ac 000102ac 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000038 08007278 08007278 00017278 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM 00000008 080072b0 080072b0 000172b0 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 4 .init_array 00000004 080072b8 080072b8 000172b8 2**2 CONTENTS, ALLOC, LOAD, DATA 5 .fini_array 00000004 080072bc 080072bc 000172bc 2**2 CONTENTS, ALLOC, LOAD, DATA 6 .data 00000024 24000000 080072c0 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .bss 00000148 24000024 080072e4 00020024 2**2 ALLOC 8 ._user_heap_stack 00000604 2400016c 080072e4 0002016c 2**0 ALLOC 9 .ARM.attributes 0000002e 00000000 00000000 00020024 2**0 CONTENTS, READONLY 10 .debug_info 00018bd4 00000000 00000000 00020052 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 11 .debug_abbrev 000026fa 00000000 00000000 00038c26 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 12 .debug_aranges 00000ae0 00000000 00000000 0003b320 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_ranges 00000a38 00000000 00000000 0003be00 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_macro 0002ec4c 00000000 00000000 0003c838 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_line 000100c2 00000000 00000000 0006b484 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_str 00132e90 00000000 00000000 0007b546 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .comment 00000053 00000000 00000000 001ae3d6 2**0 CONTENTS, READONLY 18 .debug_frame 00002c6c 00000000 00000000 001ae42c 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080002ac <__do_global_dtors_aux>: 80002ac: b510 push {r4, lr} 80002ae: 4c05 ldr r4, [pc, #20] ; (80002c4 <__do_global_dtors_aux+0x18>) 80002b0: 7823 ldrb r3, [r4, #0] 80002b2: b933 cbnz r3, 80002c2 <__do_global_dtors_aux+0x16> 80002b4: 4b04 ldr r3, [pc, #16] ; (80002c8 <__do_global_dtors_aux+0x1c>) 80002b6: b113 cbz r3, 80002be <__do_global_dtors_aux+0x12> 80002b8: 4804 ldr r0, [pc, #16] ; (80002cc <__do_global_dtors_aux+0x20>) 80002ba: f3af 8000 nop.w 80002be: 2301 movs r3, #1 80002c0: 7023 strb r3, [r4, #0] 80002c2: bd10 pop {r4, pc} 80002c4: 24000024 .word 0x24000024 80002c8: 00000000 .word 0x00000000 80002cc: 08007260 .word 0x08007260 080002d0 : 80002d0: b508 push {r3, lr} 80002d2: 4b03 ldr r3, [pc, #12] ; (80002e0 ) 80002d4: b11b cbz r3, 80002de 80002d6: 4903 ldr r1, [pc, #12] ; (80002e4 ) 80002d8: 4803 ldr r0, [pc, #12] ; (80002e8 ) 80002da: f3af 8000 nop.w 80002de: bd08 pop {r3, pc} 80002e0: 00000000 .word 0x00000000 80002e4: 24000028 .word 0x24000028 80002e8: 08007260 .word 0x08007260 080002ec <__aeabi_uldivmod>: 80002ec: b953 cbnz r3, 8000304 <__aeabi_uldivmod+0x18> 80002ee: b94a cbnz r2, 8000304 <__aeabi_uldivmod+0x18> 80002f0: 2900 cmp r1, #0 80002f2: bf08 it eq 80002f4: 2800 cmpeq r0, #0 80002f6: bf1c itt ne 80002f8: f04f 31ff movne.w r1, #4294967295 80002fc: f04f 30ff movne.w r0, #4294967295 8000300: f000 b96e b.w 80005e0 <__aeabi_idiv0> 8000304: f1ad 0c08 sub.w ip, sp, #8 8000308: e96d ce04 strd ip, lr, [sp, #-16]! 800030c: f000 f806 bl 800031c <__udivmoddi4> 8000310: f8dd e004 ldr.w lr, [sp, #4] 8000314: e9dd 2302 ldrd r2, r3, [sp, #8] 8000318: b004 add sp, #16 800031a: 4770 bx lr 0800031c <__udivmoddi4>: 800031c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8000320: 9d08 ldr r5, [sp, #32] 8000322: 4604 mov r4, r0 8000324: 468c mov ip, r1 8000326: 2b00 cmp r3, #0 8000328: f040 8083 bne.w 8000432 <__udivmoddi4+0x116> 800032c: 428a cmp r2, r1 800032e: 4617 mov r7, r2 8000330: d947 bls.n 80003c2 <__udivmoddi4+0xa6> 8000332: fab2 f282 clz r2, r2 8000336: b142 cbz r2, 800034a <__udivmoddi4+0x2e> 8000338: f1c2 0020 rsb r0, r2, #32 800033c: fa24 f000 lsr.w r0, r4, r0 8000340: 4091 lsls r1, r2 8000342: 4097 lsls r7, r2 8000344: ea40 0c01 orr.w ip, r0, r1 8000348: 4094 lsls r4, r2 800034a: ea4f 4817 mov.w r8, r7, lsr #16 800034e: 0c23 lsrs r3, r4, #16 8000350: fbbc f6f8 udiv r6, ip, r8 8000354: fa1f fe87 uxth.w lr, r7 8000358: fb08 c116 mls r1, r8, r6, ip 800035c: ea43 4301 orr.w r3, r3, r1, lsl #16 8000360: fb06 f10e mul.w r1, r6, lr 8000364: 4299 cmp r1, r3 8000366: d909 bls.n 800037c <__udivmoddi4+0x60> 8000368: 18fb adds r3, r7, r3 800036a: f106 30ff add.w r0, r6, #4294967295 800036e: f080 8119 bcs.w 80005a4 <__udivmoddi4+0x288> 8000372: 4299 cmp r1, r3 8000374: f240 8116 bls.w 80005a4 <__udivmoddi4+0x288> 8000378: 3e02 subs r6, #2 800037a: 443b add r3, r7 800037c: 1a5b subs r3, r3, r1 800037e: b2a4 uxth r4, r4 8000380: fbb3 f0f8 udiv r0, r3, r8 8000384: fb08 3310 mls r3, r8, r0, r3 8000388: ea44 4403 orr.w r4, r4, r3, lsl #16 800038c: fb00 fe0e mul.w lr, r0, lr 8000390: 45a6 cmp lr, r4 8000392: d909 bls.n 80003a8 <__udivmoddi4+0x8c> 8000394: 193c adds r4, r7, r4 8000396: f100 33ff add.w r3, r0, #4294967295 800039a: f080 8105 bcs.w 80005a8 <__udivmoddi4+0x28c> 800039e: 45a6 cmp lr, r4 80003a0: f240 8102 bls.w 80005a8 <__udivmoddi4+0x28c> 80003a4: 3802 subs r0, #2 80003a6: 443c add r4, r7 80003a8: ea40 4006 orr.w r0, r0, r6, lsl #16 80003ac: eba4 040e sub.w r4, r4, lr 80003b0: 2600 movs r6, #0 80003b2: b11d cbz r5, 80003bc <__udivmoddi4+0xa0> 80003b4: 40d4 lsrs r4, r2 80003b6: 2300 movs r3, #0 80003b8: e9c5 4300 strd r4, r3, [r5] 80003bc: 4631 mov r1, r6 80003be: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80003c2: b902 cbnz r2, 80003c6 <__udivmoddi4+0xaa> 80003c4: deff udf #255 ; 0xff 80003c6: fab2 f282 clz r2, r2 80003ca: 2a00 cmp r2, #0 80003cc: d150 bne.n 8000470 <__udivmoddi4+0x154> 80003ce: 1bcb subs r3, r1, r7 80003d0: ea4f 4e17 mov.w lr, r7, lsr #16 80003d4: fa1f f887 uxth.w r8, r7 80003d8: 2601 movs r6, #1 80003da: fbb3 fcfe udiv ip, r3, lr 80003de: 0c21 lsrs r1, r4, #16 80003e0: fb0e 331c mls r3, lr, ip, r3 80003e4: ea41 4103 orr.w r1, r1, r3, lsl #16 80003e8: fb08 f30c mul.w r3, r8, ip 80003ec: 428b cmp r3, r1 80003ee: d907 bls.n 8000400 <__udivmoddi4+0xe4> 80003f0: 1879 adds r1, r7, r1 80003f2: f10c 30ff add.w r0, ip, #4294967295 80003f6: d202 bcs.n 80003fe <__udivmoddi4+0xe2> 80003f8: 428b cmp r3, r1 80003fa: f200 80e9 bhi.w 80005d0 <__udivmoddi4+0x2b4> 80003fe: 4684 mov ip, r0 8000400: 1ac9 subs r1, r1, r3 8000402: b2a3 uxth r3, r4 8000404: fbb1 f0fe udiv r0, r1, lr 8000408: fb0e 1110 mls r1, lr, r0, r1 800040c: ea43 4401 orr.w r4, r3, r1, lsl #16 8000410: fb08 f800 mul.w r8, r8, r0 8000414: 45a0 cmp r8, r4 8000416: d907 bls.n 8000428 <__udivmoddi4+0x10c> 8000418: 193c adds r4, r7, r4 800041a: f100 33ff add.w r3, r0, #4294967295 800041e: d202 bcs.n 8000426 <__udivmoddi4+0x10a> 8000420: 45a0 cmp r8, r4 8000422: f200 80d9 bhi.w 80005d8 <__udivmoddi4+0x2bc> 8000426: 4618 mov r0, r3 8000428: eba4 0408 sub.w r4, r4, r8 800042c: ea40 400c orr.w r0, r0, ip, lsl #16 8000430: e7bf b.n 80003b2 <__udivmoddi4+0x96> 8000432: 428b cmp r3, r1 8000434: d909 bls.n 800044a <__udivmoddi4+0x12e> 8000436: 2d00 cmp r5, #0 8000438: f000 80b1 beq.w 800059e <__udivmoddi4+0x282> 800043c: 2600 movs r6, #0 800043e: e9c5 0100 strd r0, r1, [r5] 8000442: 4630 mov r0, r6 8000444: 4631 mov r1, r6 8000446: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800044a: fab3 f683 clz r6, r3 800044e: 2e00 cmp r6, #0 8000450: d14a bne.n 80004e8 <__udivmoddi4+0x1cc> 8000452: 428b cmp r3, r1 8000454: d302 bcc.n 800045c <__udivmoddi4+0x140> 8000456: 4282 cmp r2, r0 8000458: f200 80b8 bhi.w 80005cc <__udivmoddi4+0x2b0> 800045c: 1a84 subs r4, r0, r2 800045e: eb61 0103 sbc.w r1, r1, r3 8000462: 2001 movs r0, #1 8000464: 468c mov ip, r1 8000466: 2d00 cmp r5, #0 8000468: d0a8 beq.n 80003bc <__udivmoddi4+0xa0> 800046a: e9c5 4c00 strd r4, ip, [r5] 800046e: e7a5 b.n 80003bc <__udivmoddi4+0xa0> 8000470: f1c2 0320 rsb r3, r2, #32 8000474: fa20 f603 lsr.w r6, r0, r3 8000478: 4097 lsls r7, r2 800047a: fa01 f002 lsl.w r0, r1, r2 800047e: ea4f 4e17 mov.w lr, r7, lsr #16 8000482: 40d9 lsrs r1, r3 8000484: 4330 orrs r0, r6 8000486: 0c03 lsrs r3, r0, #16 8000488: fbb1 f6fe udiv r6, r1, lr 800048c: fa1f f887 uxth.w r8, r7 8000490: fb0e 1116 mls r1, lr, r6, r1 8000494: ea43 4301 orr.w r3, r3, r1, lsl #16 8000498: fb06 f108 mul.w r1, r6, r8 800049c: 4299 cmp r1, r3 800049e: fa04 f402 lsl.w r4, r4, r2 80004a2: d909 bls.n 80004b8 <__udivmoddi4+0x19c> 80004a4: 18fb adds r3, r7, r3 80004a6: f106 3cff add.w ip, r6, #4294967295 80004aa: f080 808d bcs.w 80005c8 <__udivmoddi4+0x2ac> 80004ae: 4299 cmp r1, r3 80004b0: f240 808a bls.w 80005c8 <__udivmoddi4+0x2ac> 80004b4: 3e02 subs r6, #2 80004b6: 443b add r3, r7 80004b8: 1a5b subs r3, r3, r1 80004ba: b281 uxth r1, r0 80004bc: fbb3 f0fe udiv r0, r3, lr 80004c0: fb0e 3310 mls r3, lr, r0, r3 80004c4: ea41 4103 orr.w r1, r1, r3, lsl #16 80004c8: fb00 f308 mul.w r3, r0, r8 80004cc: 428b cmp r3, r1 80004ce: d907 bls.n 80004e0 <__udivmoddi4+0x1c4> 80004d0: 1879 adds r1, r7, r1 80004d2: f100 3cff add.w ip, r0, #4294967295 80004d6: d273 bcs.n 80005c0 <__udivmoddi4+0x2a4> 80004d8: 428b cmp r3, r1 80004da: d971 bls.n 80005c0 <__udivmoddi4+0x2a4> 80004dc: 3802 subs r0, #2 80004de: 4439 add r1, r7 80004e0: 1acb subs r3, r1, r3 80004e2: ea40 4606 orr.w r6, r0, r6, lsl #16 80004e6: e778 b.n 80003da <__udivmoddi4+0xbe> 80004e8: f1c6 0c20 rsb ip, r6, #32 80004ec: fa03 f406 lsl.w r4, r3, r6 80004f0: fa22 f30c lsr.w r3, r2, ip 80004f4: 431c orrs r4, r3 80004f6: fa20 f70c lsr.w r7, r0, ip 80004fa: fa01 f306 lsl.w r3, r1, r6 80004fe: ea4f 4e14 mov.w lr, r4, lsr #16 8000502: fa21 f10c lsr.w r1, r1, ip 8000506: 431f orrs r7, r3 8000508: 0c3b lsrs r3, r7, #16 800050a: fbb1 f9fe udiv r9, r1, lr 800050e: fa1f f884 uxth.w r8, r4 8000512: fb0e 1119 mls r1, lr, r9, r1 8000516: ea43 4101 orr.w r1, r3, r1, lsl #16 800051a: fb09 fa08 mul.w sl, r9, r8 800051e: 458a cmp sl, r1 8000520: fa02 f206 lsl.w r2, r2, r6 8000524: fa00 f306 lsl.w r3, r0, r6 8000528: d908 bls.n 800053c <__udivmoddi4+0x220> 800052a: 1861 adds r1, r4, r1 800052c: f109 30ff add.w r0, r9, #4294967295 8000530: d248 bcs.n 80005c4 <__udivmoddi4+0x2a8> 8000532: 458a cmp sl, r1 8000534: d946 bls.n 80005c4 <__udivmoddi4+0x2a8> 8000536: f1a9 0902 sub.w r9, r9, #2 800053a: 4421 add r1, r4 800053c: eba1 010a sub.w r1, r1, sl 8000540: b2bf uxth r7, r7 8000542: fbb1 f0fe udiv r0, r1, lr 8000546: fb0e 1110 mls r1, lr, r0, r1 800054a: ea47 4701 orr.w r7, r7, r1, lsl #16 800054e: fb00 f808 mul.w r8, r0, r8 8000552: 45b8 cmp r8, r7 8000554: d907 bls.n 8000566 <__udivmoddi4+0x24a> 8000556: 19e7 adds r7, r4, r7 8000558: f100 31ff add.w r1, r0, #4294967295 800055c: d22e bcs.n 80005bc <__udivmoddi4+0x2a0> 800055e: 45b8 cmp r8, r7 8000560: d92c bls.n 80005bc <__udivmoddi4+0x2a0> 8000562: 3802 subs r0, #2 8000564: 4427 add r7, r4 8000566: ea40 4009 orr.w r0, r0, r9, lsl #16 800056a: eba7 0708 sub.w r7, r7, r8 800056e: fba0 8902 umull r8, r9, r0, r2 8000572: 454f cmp r7, r9 8000574: 46c6 mov lr, r8 8000576: 4649 mov r1, r9 8000578: d31a bcc.n 80005b0 <__udivmoddi4+0x294> 800057a: d017 beq.n 80005ac <__udivmoddi4+0x290> 800057c: b15d cbz r5, 8000596 <__udivmoddi4+0x27a> 800057e: ebb3 020e subs.w r2, r3, lr 8000582: eb67 0701 sbc.w r7, r7, r1 8000586: fa07 fc0c lsl.w ip, r7, ip 800058a: 40f2 lsrs r2, r6 800058c: ea4c 0202 orr.w r2, ip, r2 8000590: 40f7 lsrs r7, r6 8000592: e9c5 2700 strd r2, r7, [r5] 8000596: 2600 movs r6, #0 8000598: 4631 mov r1, r6 800059a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800059e: 462e mov r6, r5 80005a0: 4628 mov r0, r5 80005a2: e70b b.n 80003bc <__udivmoddi4+0xa0> 80005a4: 4606 mov r6, r0 80005a6: e6e9 b.n 800037c <__udivmoddi4+0x60> 80005a8: 4618 mov r0, r3 80005aa: e6fd b.n 80003a8 <__udivmoddi4+0x8c> 80005ac: 4543 cmp r3, r8 80005ae: d2e5 bcs.n 800057c <__udivmoddi4+0x260> 80005b0: ebb8 0e02 subs.w lr, r8, r2 80005b4: eb69 0104 sbc.w r1, r9, r4 80005b8: 3801 subs r0, #1 80005ba: e7df b.n 800057c <__udivmoddi4+0x260> 80005bc: 4608 mov r0, r1 80005be: e7d2 b.n 8000566 <__udivmoddi4+0x24a> 80005c0: 4660 mov r0, ip 80005c2: e78d b.n 80004e0 <__udivmoddi4+0x1c4> 80005c4: 4681 mov r9, r0 80005c6: e7b9 b.n 800053c <__udivmoddi4+0x220> 80005c8: 4666 mov r6, ip 80005ca: e775 b.n 80004b8 <__udivmoddi4+0x19c> 80005cc: 4630 mov r0, r6 80005ce: e74a b.n 8000466 <__udivmoddi4+0x14a> 80005d0: f1ac 0c02 sub.w ip, ip, #2 80005d4: 4439 add r1, r7 80005d6: e713 b.n 8000400 <__udivmoddi4+0xe4> 80005d8: 3802 subs r0, #2 80005da: 443c add r4, r7 80005dc: e724 b.n 8000428 <__udivmoddi4+0x10c> 80005de: bf00 nop 080005e0 <__aeabi_idiv0>: 80005e0: 4770 bx lr 80005e2: bf00 nop 080005e4 : // HAL_UART_IRQHandler(&huart1); // HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0, GPIO_PIN_RESET); //} void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 80005e4: b580 push {r7, lr} 80005e6: b082 sub sp, #8 80005e8: af00 add r7, sp, #0 80005ea: 6078 str r0, [r7, #4] HAL_GPIO_WritePin(GPIOC, GPIO_PIN_11, GPIO_PIN_RESET); 80005ec: 2200 movs r2, #0 80005ee: f44f 6100 mov.w r1, #2048 ; 0x800 80005f2: 4803 ldr r0, [pc, #12] ; (8000600 ) 80005f4: f001 fccc bl 8001f90 } 80005f8: bf00 nop 80005fa: 3708 adds r7, #8 80005fc: 46bd mov sp, r7 80005fe: bd80 pop {r7, pc} 8000600: 58020800 .word 0x58020800 08000604 : void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 8000604: b580 push {r7, lr} 8000606: b082 sub sp, #8 8000608: af00 add r7, sp, #0 800060a: 6078 str r0, [r7, #4] HAL_GPIO_WritePin(GPIOE, GPIO_PIN_1, GPIO_PIN_SET); 800060c: 2201 movs r2, #1 800060e: 2102 movs r1, #2 8000610: 4803 ldr r0, [pc, #12] ; (8000620 ) 8000612: f001 fcbd bl 8001f90 } 8000616: bf00 nop 8000618: 3708 adds r7, #8 800061a: 46bd mov sp, r7 800061c: bd80 pop {r7, pc} 800061e: bf00 nop 8000620: 58021000 .word 0x58021000 08000624
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000624: b580 push {r7, lr} 8000626: b082 sub sp, #8 8000628: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800062a: f000 fbd9 bl 8000de0 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 800062e: f000 f84d bl 80006cc /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000632: f000 f907 bl 8000844 // MX_USART2_UART_Init(); MX_USART1_UART_Init(); 8000636: f000 f8b7 bl 80007a8 /* USER CODE BEGIN 2 */ HAL_GPIO_WritePin(GPIOE, GPIO_PIN_1, GPIO_PIN_RESET); 800063a: 2200 movs r2, #0 800063c: 2102 movs r1, #2 800063e: 481e ldr r0, [pc, #120] ; (80006b8 ) 8000640: f001 fca6 bl 8001f90 HAL_GPIO_WritePin(GPIOE, GPIO_PIN_1, GPIO_PIN_SET); 8000644: 2201 movs r2, #1 8000646: 2102 movs r1, #2 8000648: 481b ldr r0, [pc, #108] ; (80006b8 ) 800064a: f001 fca1 bl 8001f90 HAL_Delay(500); 800064e: f44f 70fa mov.w r0, #500 ; 0x1f4 8000652: f000 fc57 bl 8000f04 HAL_GPIO_WritePin(GPIOE, GPIO_PIN_1, GPIO_PIN_RESET); 8000656: 2200 movs r2, #0 8000658: 2102 movs r1, #2 800065a: 4817 ldr r0, [pc, #92] ; (80006b8 ) 800065c: f001 fc98 bl 8001f90 HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0, GPIO_PIN_RESET); 8000660: 2200 movs r2, #0 8000662: 2101 movs r1, #1 8000664: 4815 ldr r0, [pc, #84] ; (80006bc ) 8000666: f001 fc93 bl 8001f90 HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0, GPIO_PIN_SET); 800066a: 2201 movs r2, #1 800066c: 2101 movs r1, #1 800066e: 4813 ldr r0, [pc, #76] ; (80006bc ) 8000670: f001 fc8e bl 8001f90 HAL_Delay(500); 8000674: f44f 70fa mov.w r0, #500 ; 0x1f4 8000678: f000 fc44 bl 8000f04 HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0, GPIO_PIN_RESET); 800067c: 2200 movs r2, #0 800067e: 2101 movs r1, #1 8000680: 480e ldr r0, [pc, #56] ; (80006bc ) 8000682: f001 fc85 bl 8001f90 HAL_StatusTypeDef halReturn; halReturn = HAL_UART_Receive_IT(&huart1, (uint8_t *)ctdRXBuffer, 5); 8000686: 2205 movs r2, #5 8000688: 490d ldr r1, [pc, #52] ; (80006c0 ) 800068a: 480e ldr r0, [pc, #56] ; (80006c4 ) 800068c: f004 f8aa bl 80047e4 8000690: 4603 mov r3, r0 8000692: 71fb strb r3, [r7, #7] if (halReturn != HAL_OK) 8000694: 79fb ldrb r3, [r7, #7] 8000696: 2b00 cmp r3, #0 8000698: d001 beq.n 800069e { Error_Handler(); 800069a: f000 f9f3 bl 8000a84 } halReturn = HAL_UART_Transmit_IT(&huart1, (uint8_t*)getCTDPressureCmdBytes, sizeof(getCTDPressureCmdBytes)); 800069e: 2212 movs r2, #18 80006a0: 4909 ldr r1, [pc, #36] ; (80006c8 ) 80006a2: 4808 ldr r0, [pc, #32] ; (80006c4 ) 80006a4: f003 fff6 bl 8004694 80006a8: 4603 mov r3, r0 80006aa: 71fb strb r3, [r7, #7] if(halReturn != HAL_OK) 80006ac: 79fb ldrb r3, [r7, #7] 80006ae: 2b00 cmp r3, #0 80006b0: d001 beq.n 80006b6 { Error_Handler(); 80006b2: f000 f9e7 bl 8000a84 /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 80006b6: e7fe b.n 80006b6 80006b8: 58021000 .word 0x58021000 80006bc: 58020400 .word 0x58020400 80006c0: 240000d0 .word 0x240000d0 80006c4: 24000040 .word 0x24000040 80006c8: 24000000 .word 0x24000000 080006cc : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 80006cc: b580 push {r7, lr} 80006ce: b09c sub sp, #112 ; 0x70 80006d0: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 80006d2: f107 0324 add.w r3, r7, #36 ; 0x24 80006d6: 224c movs r2, #76 ; 0x4c 80006d8: 2100 movs r1, #0 80006da: 4618 mov r0, r3 80006dc: f006 fdb8 bl 8007250 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 80006e0: 1d3b adds r3, r7, #4 80006e2: 2220 movs r2, #32 80006e4: 2100 movs r1, #0 80006e6: 4618 mov r0, r3 80006e8: f006 fdb2 bl 8007250 /** Supply configuration update enable */ HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY); 80006ec: 2004 movs r0, #4 80006ee: f001 fc69 bl 8001fc4 /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); 80006f2: 2300 movs r3, #0 80006f4: 603b str r3, [r7, #0] 80006f6: 4b2b ldr r3, [pc, #172] ; (80007a4 ) 80006f8: 699b ldr r3, [r3, #24] 80006fa: 4a2a ldr r2, [pc, #168] ; (80007a4 ) 80006fc: f443 4340 orr.w r3, r3, #49152 ; 0xc000 8000700: 6193 str r3, [r2, #24] 8000702: 4b28 ldr r3, [pc, #160] ; (80007a4 ) 8000704: 699b ldr r3, [r3, #24] 8000706: f403 4340 and.w r3, r3, #49152 ; 0xc000 800070a: 603b str r3, [r7, #0] 800070c: 683b ldr r3, [r7, #0] while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} 800070e: bf00 nop 8000710: 4b24 ldr r3, [pc, #144] ; (80007a4 ) 8000712: 699b ldr r3, [r3, #24] 8000714: f403 5300 and.w r3, r3, #8192 ; 0x2000 8000718: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 800071c: d1f8 bne.n 8000710 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 800071e: 2302 movs r3, #2 8000720: 627b str r3, [r7, #36] ; 0x24 RCC_OscInitStruct.HSIState = RCC_HSI_DIV1; 8000722: 2301 movs r3, #1 8000724: 633b str r3, [r7, #48] ; 0x30 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 8000726: 2340 movs r3, #64 ; 0x40 8000728: 637b str r3, [r7, #52] ; 0x34 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 800072a: 2302 movs r3, #2 800072c: 64bb str r3, [r7, #72] ; 0x48 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; 800072e: 2300 movs r3, #0 8000730: 64fb str r3, [r7, #76] ; 0x4c RCC_OscInitStruct.PLL.PLLM = 4; 8000732: 2304 movs r3, #4 8000734: 653b str r3, [r7, #80] ; 0x50 RCC_OscInitStruct.PLL.PLLN = 8; 8000736: 2308 movs r3, #8 8000738: 657b str r3, [r7, #84] ; 0x54 RCC_OscInitStruct.PLL.PLLP = 2; 800073a: 2302 movs r3, #2 800073c: 65bb str r3, [r7, #88] ; 0x58 RCC_OscInitStruct.PLL.PLLQ = 4; 800073e: 2304 movs r3, #4 8000740: 65fb str r3, [r7, #92] ; 0x5c RCC_OscInitStruct.PLL.PLLR = 2; 8000742: 2302 movs r3, #2 8000744: 663b str r3, [r7, #96] ; 0x60 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; 8000746: 230c movs r3, #12 8000748: 667b str r3, [r7, #100] ; 0x64 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; 800074a: 2300 movs r3, #0 800074c: 66bb str r3, [r7, #104] ; 0x68 RCC_OscInitStruct.PLL.PLLFRACN = 0; 800074e: 2300 movs r3, #0 8000750: 66fb str r3, [r7, #108] ; 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000752: f107 0324 add.w r3, r7, #36 ; 0x24 8000756: 4618 mov r0, r3 8000758: f001 fc8e bl 8002078 800075c: 4603 mov r3, r0 800075e: 2b00 cmp r3, #0 8000760: d001 beq.n 8000766 { Error_Handler(); 8000762: f000 f98f bl 8000a84 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000766: 233f movs r3, #63 ; 0x3f 8000768: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 800076a: 2303 movs r3, #3 800076c: 60bb str r3, [r7, #8] RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 800076e: 2300 movs r3, #0 8000770: 60fb str r3, [r7, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1; 8000772: 2300 movs r3, #0 8000774: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1; 8000776: 2300 movs r3, #0 8000778: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1; 800077a: 2300 movs r3, #0 800077c: 61bb str r3, [r7, #24] RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1; 800077e: 2300 movs r3, #0 8000780: 61fb str r3, [r7, #28] RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1; 8000782: 2300 movs r3, #0 8000784: 623b str r3, [r7, #32] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) 8000786: 1d3b adds r3, r7, #4 8000788: 2101 movs r1, #1 800078a: 4618 mov r0, r3 800078c: f002 f878 bl 8002880 8000790: 4603 mov r3, r0 8000792: 2b00 cmp r3, #0 8000794: d001 beq.n 800079a { Error_Handler(); 8000796: f000 f975 bl 8000a84 } } 800079a: bf00 nop 800079c: 3770 adds r7, #112 ; 0x70 800079e: 46bd mov sp, r7 80007a0: bd80 pop {r7, pc} 80007a2: bf00 nop 80007a4: 58024800 .word 0x58024800 080007a8 : * @brief USART1 Initialization Function * @param None * @retval None */ static void MX_USART1_UART_Init(void) { 80007a8: b580 push {r7, lr} 80007aa: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 80007ac: 4b23 ldr r3, [pc, #140] ; (800083c ) 80007ae: 4a24 ldr r2, [pc, #144] ; (8000840 ) 80007b0: 601a str r2, [r3, #0] huart1.Init.BaudRate = 9600; 80007b2: 4b22 ldr r3, [pc, #136] ; (800083c ) 80007b4: f44f 5216 mov.w r2, #9600 ; 0x2580 80007b8: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 80007ba: 4b20 ldr r3, [pc, #128] ; (800083c ) 80007bc: 2200 movs r2, #0 80007be: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 80007c0: 4b1e ldr r3, [pc, #120] ; (800083c ) 80007c2: 2200 movs r2, #0 80007c4: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 80007c6: 4b1d ldr r3, [pc, #116] ; (800083c ) 80007c8: 2200 movs r2, #0 80007ca: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 80007cc: 4b1b ldr r3, [pc, #108] ; (800083c ) 80007ce: 220c movs r2, #12 80007d0: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80007d2: 4b1a ldr r3, [pc, #104] ; (800083c ) 80007d4: 2200 movs r2, #0 80007d6: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 80007d8: 4b18 ldr r3, [pc, #96] ; (800083c ) 80007da: 2200 movs r2, #0 80007dc: 61da str r2, [r3, #28] huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 80007de: 4b17 ldr r3, [pc, #92] ; (800083c ) 80007e0: 2200 movs r2, #0 80007e2: 621a str r2, [r3, #32] huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; 80007e4: 4b15 ldr r3, [pc, #84] ; (800083c ) 80007e6: 2200 movs r2, #0 80007e8: 625a str r2, [r3, #36] ; 0x24 huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 80007ea: 4b14 ldr r3, [pc, #80] ; (800083c ) 80007ec: 2200 movs r2, #0 80007ee: 629a str r2, [r3, #40] ; 0x28 if (HAL_UART_Init(&huart1) != HAL_OK) 80007f0: 4812 ldr r0, [pc, #72] ; (800083c ) 80007f2: f003 feff bl 80045f4 80007f6: 4603 mov r3, r0 80007f8: 2b00 cmp r3, #0 80007fa: d001 beq.n 8000800 { Error_Handler(); 80007fc: f000 f942 bl 8000a84 } if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_2) != HAL_OK) 8000800: f04f 4180 mov.w r1, #1073741824 ; 0x40000000 8000804: 480d ldr r0, [pc, #52] ; (800083c ) 8000806: f006 fc34 bl 8007072 800080a: 4603 mov r3, r0 800080c: 2b00 cmp r3, #0 800080e: d001 beq.n 8000814 { Error_Handler(); 8000810: f000 f938 bl 8000a84 } if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_2) != HAL_OK) 8000814: f04f 6180 mov.w r1, #67108864 ; 0x4000000 8000818: 4808 ldr r0, [pc, #32] ; (800083c ) 800081a: f006 fc68 bl 80070ee 800081e: 4603 mov r3, r0 8000820: 2b00 cmp r3, #0 8000822: d001 beq.n 8000828 { Error_Handler(); 8000824: f000 f92e bl 8000a84 } if (HAL_UARTEx_EnableFifoMode(&huart1) != HAL_OK) 8000828: 4804 ldr r0, [pc, #16] ; (800083c ) 800082a: f006 fbe7 bl 8006ffc 800082e: 4603 mov r3, r0 8000830: 2b00 cmp r3, #0 8000832: d001 beq.n 8000838 { Error_Handler(); 8000834: f000 f926 bl 8000a84 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 8000838: bf00 nop 800083a: bd80 pop {r7, pc} 800083c: 24000040 .word 0x24000040 8000840: 40011000 .word 0x40011000 08000844 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8000844: b580 push {r7, lr} 8000846: b08e sub sp, #56 ; 0x38 8000848: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800084a: f107 0324 add.w r3, r7, #36 ; 0x24 800084e: 2200 movs r2, #0 8000850: 601a str r2, [r3, #0] 8000852: 605a str r2, [r3, #4] 8000854: 609a str r2, [r3, #8] 8000856: 60da str r2, [r3, #12] 8000858: 611a str r2, [r3, #16] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 800085a: 4b82 ldr r3, [pc, #520] ; (8000a64 ) 800085c: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8000860: 4a80 ldr r2, [pc, #512] ; (8000a64 ) 8000862: f043 0304 orr.w r3, r3, #4 8000866: f8c2 3140 str.w r3, [r2, #320] ; 0x140 800086a: 4b7e ldr r3, [pc, #504] ; (8000a64 ) 800086c: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8000870: f003 0304 and.w r3, r3, #4 8000874: 623b str r3, [r7, #32] 8000876: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOF_CLK_ENABLE(); 8000878: 4b7a ldr r3, [pc, #488] ; (8000a64 ) 800087a: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 800087e: 4a79 ldr r2, [pc, #484] ; (8000a64 ) 8000880: f043 0320 orr.w r3, r3, #32 8000884: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8000888: 4b76 ldr r3, [pc, #472] ; (8000a64 ) 800088a: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 800088e: f003 0320 and.w r3, r3, #32 8000892: 61fb str r3, [r7, #28] 8000894: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOH_CLK_ENABLE(); 8000896: 4b73 ldr r3, [pc, #460] ; (8000a64 ) 8000898: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 800089c: 4a71 ldr r2, [pc, #452] ; (8000a64 ) 800089e: f043 0380 orr.w r3, r3, #128 ; 0x80 80008a2: f8c2 3140 str.w r3, [r2, #320] ; 0x140 80008a6: 4b6f ldr r3, [pc, #444] ; (8000a64 ) 80008a8: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80008ac: f003 0380 and.w r3, r3, #128 ; 0x80 80008b0: 61bb str r3, [r7, #24] 80008b2: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOB_CLK_ENABLE(); 80008b4: 4b6b ldr r3, [pc, #428] ; (8000a64 ) 80008b6: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80008ba: 4a6a ldr r2, [pc, #424] ; (8000a64 ) 80008bc: f043 0302 orr.w r3, r3, #2 80008c0: f8c2 3140 str.w r3, [r2, #320] ; 0x140 80008c4: 4b67 ldr r3, [pc, #412] ; (8000a64 ) 80008c6: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80008ca: f003 0302 and.w r3, r3, #2 80008ce: 617b str r3, [r7, #20] 80008d0: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOD_CLK_ENABLE(); 80008d2: 4b64 ldr r3, [pc, #400] ; (8000a64 ) 80008d4: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80008d8: 4a62 ldr r2, [pc, #392] ; (8000a64 ) 80008da: f043 0308 orr.w r3, r3, #8 80008de: f8c2 3140 str.w r3, [r2, #320] ; 0x140 80008e2: 4b60 ldr r3, [pc, #384] ; (8000a64 ) 80008e4: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80008e8: f003 0308 and.w r3, r3, #8 80008ec: 613b str r3, [r7, #16] 80008ee: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOG_CLK_ENABLE(); 80008f0: 4b5c ldr r3, [pc, #368] ; (8000a64 ) 80008f2: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80008f6: 4a5b ldr r2, [pc, #364] ; (8000a64 ) 80008f8: f043 0340 orr.w r3, r3, #64 ; 0x40 80008fc: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8000900: 4b58 ldr r3, [pc, #352] ; (8000a64 ) 8000902: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8000906: f003 0340 and.w r3, r3, #64 ; 0x40 800090a: 60fb str r3, [r7, #12] 800090c: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 800090e: 4b55 ldr r3, [pc, #340] ; (8000a64 ) 8000910: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8000914: 4a53 ldr r2, [pc, #332] ; (8000a64 ) 8000916: f043 0301 orr.w r3, r3, #1 800091a: f8c2 3140 str.w r3, [r2, #320] ; 0x140 800091e: 4b51 ldr r3, [pc, #324] ; (8000a64 ) 8000920: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8000924: f003 0301 and.w r3, r3, #1 8000928: 60bb str r3, [r7, #8] 800092a: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOE_CLK_ENABLE(); 800092c: 4b4d ldr r3, [pc, #308] ; (8000a64 ) 800092e: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8000932: 4a4c ldr r2, [pc, #304] ; (8000a64 ) 8000934: f043 0310 orr.w r3, r3, #16 8000938: f8c2 3140 str.w r3, [r2, #320] ; 0x140 800093c: 4b49 ldr r3, [pc, #292] ; (8000a64 ) 800093e: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8000942: f003 0310 and.w r3, r3, #16 8000946: 607b str r3, [r7, #4] 8000948: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(USB_FS_PWR_EN_GPIO_Port, USB_FS_PWR_EN_Pin, GPIO_PIN_RESET); 800094a: 2200 movs r2, #0 800094c: f44f 6180 mov.w r1, #1024 ; 0x400 8000950: 4845 ldr r0, [pc, #276] ; (8000a68 ) 8000952: f001 fb1d bl 8001f90 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, LD1_Pin|LD3_Pin, GPIO_PIN_RESET); 8000956: 2200 movs r2, #0 8000958: f244 0101 movw r1, #16385 ; 0x4001 800095c: 4843 ldr r0, [pc, #268] ; (8000a6c ) 800095e: f001 fb17 bl 8001f90 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET); 8000962: 2200 movs r2, #0 8000964: 2102 movs r1, #2 8000966: 4842 ldr r0, [pc, #264] ; (8000a70 ) 8000968: f001 fb12 bl 8001f90 /*Configure GPIO pin : B1_Pin */ GPIO_InitStruct.Pin = B1_Pin; 800096c: f44f 5300 mov.w r3, #8192 ; 0x2000 8000970: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000972: 2300 movs r3, #0 8000974: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000976: 2300 movs r3, #0 8000978: 62fb str r3, [r7, #44] ; 0x2c HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct); 800097a: f107 0324 add.w r3, r7, #36 ; 0x24 800097e: 4619 mov r1, r3 8000980: 483c ldr r0, [pc, #240] ; (8000a74 ) 8000982: f001 f955 bl 8001c30 /*Configure GPIO pin : USB_FS_PWR_EN_Pin */ GPIO_InitStruct.Pin = USB_FS_PWR_EN_Pin; 8000986: f44f 6380 mov.w r3, #1024 ; 0x400 800098a: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800098c: 2301 movs r3, #1 800098e: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000990: 2300 movs r3, #0 8000992: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000994: 2300 movs r3, #0 8000996: 633b str r3, [r7, #48] ; 0x30 HAL_GPIO_Init(USB_FS_PWR_EN_GPIO_Port, &GPIO_InitStruct); 8000998: f107 0324 add.w r3, r7, #36 ; 0x24 800099c: 4619 mov r1, r3 800099e: 4832 ldr r0, [pc, #200] ; (8000a68 ) 80009a0: f001 f946 bl 8001c30 /*Configure GPIO pins : LD1_Pin LD3_Pin */ GPIO_InitStruct.Pin = LD1_Pin|LD3_Pin; 80009a4: f244 0301 movw r3, #16385 ; 0x4001 80009a8: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80009aa: 2301 movs r3, #1 80009ac: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 80009ae: 2300 movs r3, #0 80009b0: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80009b2: 2300 movs r3, #0 80009b4: 633b str r3, [r7, #48] ; 0x30 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80009b6: f107 0324 add.w r3, r7, #36 ; 0x24 80009ba: 4619 mov r1, r3 80009bc: 482b ldr r0, [pc, #172] ; (8000a6c ) 80009be: f001 f937 bl 8001c30 /*Configure GPIO pins : STLINK_RX_Pin STLINK_TX_Pin */ GPIO_InitStruct.Pin = STLINK_RX_Pin|STLINK_TX_Pin; 80009c2: f44f 7340 mov.w r3, #768 ; 0x300 80009c6: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80009c8: 2302 movs r3, #2 80009ca: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 80009cc: 2300 movs r3, #0 80009ce: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80009d0: 2300 movs r3, #0 80009d2: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Alternate = GPIO_AF7_USART3; 80009d4: 2307 movs r3, #7 80009d6: 637b str r3, [r7, #52] ; 0x34 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 80009d8: f107 0324 add.w r3, r7, #36 ; 0x24 80009dc: 4619 mov r1, r3 80009de: 4826 ldr r0, [pc, #152] ; (8000a78 ) 80009e0: f001 f926 bl 8001c30 /*Configure GPIO pin : USB_FS_OVCR_Pin */ GPIO_InitStruct.Pin = USB_FS_OVCR_Pin; 80009e4: 2380 movs r3, #128 ; 0x80 80009e6: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; 80009e8: f44f 1388 mov.w r3, #1114112 ; 0x110000 80009ec: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 80009ee: 2300 movs r3, #0 80009f0: 62fb str r3, [r7, #44] ; 0x2c HAL_GPIO_Init(USB_FS_OVCR_GPIO_Port, &GPIO_InitStruct); 80009f2: f107 0324 add.w r3, r7, #36 ; 0x24 80009f6: 4619 mov r1, r3 80009f8: 4820 ldr r0, [pc, #128] ; (8000a7c ) 80009fa: f001 f919 bl 8001c30 /*Configure GPIO pin : USB_FS_ID_Pin */ GPIO_InitStruct.Pin = USB_FS_ID_Pin; 80009fe: f44f 6380 mov.w r3, #1024 ; 0x400 8000a02: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000a04: 2302 movs r3, #2 8000a06: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000a08: 2300 movs r3, #0 8000a0a: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000a0c: 2300 movs r3, #0 8000a0e: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_HS; 8000a10: 230a movs r3, #10 8000a12: 637b str r3, [r7, #52] ; 0x34 HAL_GPIO_Init(USB_FS_ID_GPIO_Port, &GPIO_InitStruct); 8000a14: f107 0324 add.w r3, r7, #36 ; 0x24 8000a18: 4619 mov r1, r3 8000a1a: 4819 ldr r0, [pc, #100] ; (8000a80 ) 8000a1c: f001 f908 bl 8001c30 /*Configure GPIO pins : USB_FS_N_Pin USB_FS_P_Pin */ GPIO_InitStruct.Pin = USB_FS_N_Pin|USB_FS_P_Pin; 8000a20: f44f 53c0 mov.w r3, #6144 ; 0x1800 8000a24: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000a26: 2302 movs r3, #2 8000a28: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000a2a: 2300 movs r3, #0 8000a2c: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000a2e: 2300 movs r3, #0 8000a30: 633b str r3, [r7, #48] ; 0x30 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000a32: f107 0324 add.w r3, r7, #36 ; 0x24 8000a36: 4619 mov r1, r3 8000a38: 4811 ldr r0, [pc, #68] ; (8000a80 ) 8000a3a: f001 f8f9 bl 8001c30 /*Configure GPIO pin : LD2_Pin */ GPIO_InitStruct.Pin = LD2_Pin; 8000a3e: 2302 movs r3, #2 8000a40: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000a42: 2301 movs r3, #1 8000a44: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000a46: 2300 movs r3, #0 8000a48: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000a4a: 2300 movs r3, #0 8000a4c: 633b str r3, [r7, #48] ; 0x30 HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct); 8000a4e: f107 0324 add.w r3, r7, #36 ; 0x24 8000a52: 4619 mov r1, r3 8000a54: 4806 ldr r0, [pc, #24] ; (8000a70 ) 8000a56: f001 f8eb bl 8001c30 } 8000a5a: bf00 nop 8000a5c: 3738 adds r7, #56 ; 0x38 8000a5e: 46bd mov sp, r7 8000a60: bd80 pop {r7, pc} 8000a62: bf00 nop 8000a64: 58024400 .word 0x58024400 8000a68: 58021400 .word 0x58021400 8000a6c: 58020400 .word 0x58020400 8000a70: 58021000 .word 0x58021000 8000a74: 58020800 .word 0x58020800 8000a78: 58020c00 .word 0x58020c00 8000a7c: 58021800 .word 0x58021800 8000a80: 58020000 .word 0x58020000 08000a84 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000a84: b480 push {r7} 8000a86: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000a88: b672 cpsid i } 8000a8a: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000a8c: e7fe b.n 8000a8c ... 08000a90 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000a90: b480 push {r7} 8000a92: b083 sub sp, #12 8000a94: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8000a96: 4b0a ldr r3, [pc, #40] ; (8000ac0 ) 8000a98: f8d3 3154 ldr.w r3, [r3, #340] ; 0x154 8000a9c: 4a08 ldr r2, [pc, #32] ; (8000ac0 ) 8000a9e: f043 0302 orr.w r3, r3, #2 8000aa2: f8c2 3154 str.w r3, [r2, #340] ; 0x154 8000aa6: 4b06 ldr r3, [pc, #24] ; (8000ac0 ) 8000aa8: f8d3 3154 ldr.w r3, [r3, #340] ; 0x154 8000aac: f003 0302 and.w r3, r3, #2 8000ab0: 607b str r3, [r7, #4] 8000ab2: 687b ldr r3, [r7, #4] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8000ab4: bf00 nop 8000ab6: 370c adds r7, #12 8000ab8: 46bd mov sp, r7 8000aba: f85d 7b04 ldr.w r7, [sp], #4 8000abe: 4770 bx lr 8000ac0: 58024400 .word 0x58024400 08000ac4 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 8000ac4: b580 push {r7, lr} 8000ac6: b0ba sub sp, #232 ; 0xe8 8000ac8: af00 add r7, sp, #0 8000aca: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000acc: f107 03d4 add.w r3, r7, #212 ; 0xd4 8000ad0: 2200 movs r2, #0 8000ad2: 601a str r2, [r3, #0] 8000ad4: 605a str r2, [r3, #4] 8000ad6: 609a str r2, [r3, #8] 8000ad8: 60da str r2, [r3, #12] 8000ada: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8000adc: f107 031c add.w r3, r7, #28 8000ae0: 22b8 movs r2, #184 ; 0xb8 8000ae2: 2100 movs r1, #0 8000ae4: 4618 mov r0, r3 8000ae6: f006 fbb3 bl 8007250 if(huart->Instance==USART1) 8000aea: 687b ldr r3, [r7, #4] 8000aec: 681b ldr r3, [r3, #0] 8000aee: 4a4c ldr r2, [pc, #304] ; (8000c20 ) 8000af0: 4293 cmp r3, r2 8000af2: d14a bne.n 8000b8a /* USER CODE BEGIN USART1_MspInit 0 */ /* USER CODE END USART1_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1; 8000af4: 2301 movs r3, #1 8000af6: 61fb str r3, [r7, #28] PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16910CLKSOURCE_D2PCLK2; 8000af8: 2300 movs r3, #0 8000afa: f8c7 309c str.w r3, [r7, #156] ; 0x9c if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8000afe: f107 031c add.w r3, r7, #28 8000b02: 4618 mov r0, r3 8000b04: f002 fa48 bl 8002f98 8000b08: 4603 mov r3, r0 8000b0a: 2b00 cmp r3, #0 8000b0c: d001 beq.n 8000b12 { Error_Handler(); 8000b0e: f7ff ffb9 bl 8000a84 } /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); 8000b12: 4b44 ldr r3, [pc, #272] ; (8000c24 ) 8000b14: f8d3 3150 ldr.w r3, [r3, #336] ; 0x150 8000b18: 4a42 ldr r2, [pc, #264] ; (8000c24 ) 8000b1a: f043 0310 orr.w r3, r3, #16 8000b1e: f8c2 3150 str.w r3, [r2, #336] ; 0x150 8000b22: 4b40 ldr r3, [pc, #256] ; (8000c24 ) 8000b24: f8d3 3150 ldr.w r3, [r3, #336] ; 0x150 8000b28: f003 0310 and.w r3, r3, #16 8000b2c: 61bb str r3, [r7, #24] 8000b2e: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000b30: 4b3c ldr r3, [pc, #240] ; (8000c24 ) 8000b32: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8000b36: 4a3b ldr r2, [pc, #236] ; (8000c24 ) 8000b38: f043 0302 orr.w r3, r3, #2 8000b3c: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8000b40: 4b38 ldr r3, [pc, #224] ; (8000c24 ) 8000b42: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8000b46: f003 0302 and.w r3, r3, #2 8000b4a: 617b str r3, [r7, #20] 8000b4c: 697b ldr r3, [r7, #20] /**USART1 GPIO Configuration PB6 ------> USART1_TX PB7 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; 8000b4e: 23c0 movs r3, #192 ; 0xc0 8000b50: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000b54: 2302 movs r3, #2 8000b56: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000b5a: 2300 movs r3, #0 8000b5c: f8c7 30dc str.w r3, [r7, #220] ; 0xdc GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000b60: 2300 movs r3, #0 8000b62: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 GPIO_InitStruct.Alternate = GPIO_AF7_USART1; 8000b66: 2307 movs r3, #7 8000b68: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000b6c: f107 03d4 add.w r3, r7, #212 ; 0xd4 8000b70: 4619 mov r1, r3 8000b72: 482d ldr r0, [pc, #180] ; (8000c28 ) 8000b74: f001 f85c bl 8001c30 /* USART1 interrupt Init */ HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); 8000b78: 2200 movs r2, #0 8000b7a: 2100 movs r1, #0 8000b7c: 2025 movs r0, #37 ; 0x25 8000b7e: f000 fac0 bl 8001102 HAL_NVIC_EnableIRQ(USART1_IRQn); 8000b82: 2025 movs r0, #37 ; 0x25 8000b84: f000 fad7 bl 8001136 /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } 8000b88: e046 b.n 8000c18 else if(huart->Instance==USART2) 8000b8a: 687b ldr r3, [r7, #4] 8000b8c: 681b ldr r3, [r3, #0] 8000b8e: 4a27 ldr r2, [pc, #156] ; (8000c2c ) 8000b90: 4293 cmp r3, r2 8000b92: d141 bne.n 8000c18 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART2; 8000b94: 2302 movs r3, #2 8000b96: 61fb str r3, [r7, #28] PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; 8000b98: 2300 movs r3, #0 8000b9a: f8c7 3098 str.w r3, [r7, #152] ; 0x98 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8000b9e: f107 031c add.w r3, r7, #28 8000ba2: 4618 mov r0, r3 8000ba4: f002 f9f8 bl 8002f98 8000ba8: 4603 mov r3, r0 8000baa: 2b00 cmp r3, #0 8000bac: d001 beq.n 8000bb2 Error_Handler(); 8000bae: f7ff ff69 bl 8000a84 __HAL_RCC_USART2_CLK_ENABLE(); 8000bb2: 4b1c ldr r3, [pc, #112] ; (8000c24 ) 8000bb4: f8d3 3148 ldr.w r3, [r3, #328] ; 0x148 8000bb8: 4a1a ldr r2, [pc, #104] ; (8000c24 ) 8000bba: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8000bbe: f8c2 3148 str.w r3, [r2, #328] ; 0x148 8000bc2: 4b18 ldr r3, [pc, #96] ; (8000c24 ) 8000bc4: f8d3 3148 ldr.w r3, [r3, #328] ; 0x148 8000bc8: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000bcc: 613b str r3, [r7, #16] 8000bce: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOD_CLK_ENABLE(); 8000bd0: 4b14 ldr r3, [pc, #80] ; (8000c24 ) 8000bd2: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8000bd6: 4a13 ldr r2, [pc, #76] ; (8000c24 ) 8000bd8: f043 0308 orr.w r3, r3, #8 8000bdc: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8000be0: 4b10 ldr r3, [pc, #64] ; (8000c24 ) 8000be2: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8000be6: f003 0308 and.w r3, r3, #8 8000bea: 60fb str r3, [r7, #12] 8000bec: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6; 8000bee: 2360 movs r3, #96 ; 0x60 8000bf0: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000bf4: 2302 movs r3, #2 8000bf6: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000bfa: 2300 movs r3, #0 8000bfc: f8c7 30dc str.w r3, [r7, #220] ; 0xdc GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000c00: 2300 movs r3, #0 8000c02: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 GPIO_InitStruct.Alternate = GPIO_AF7_USART2; 8000c06: 2307 movs r3, #7 8000c08: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8000c0c: f107 03d4 add.w r3, r7, #212 ; 0xd4 8000c10: 4619 mov r1, r3 8000c12: 4807 ldr r0, [pc, #28] ; (8000c30 ) 8000c14: f001 f80c bl 8001c30 } 8000c18: bf00 nop 8000c1a: 37e8 adds r7, #232 ; 0xe8 8000c1c: 46bd mov sp, r7 8000c1e: bd80 pop {r7, pc} 8000c20: 40011000 .word 0x40011000 8000c24: 58024400 .word 0x58024400 8000c28: 58020400 .word 0x58020400 8000c2c: 40004400 .word 0x40004400 8000c30: 58020c00 .word 0x58020c00 08000c34 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8000c34: b480 push {r7} 8000c36: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8000c38: e7fe b.n 8000c38 08000c3a : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8000c3a: b480 push {r7} 8000c3c: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8000c3e: e7fe b.n 8000c3e 08000c40 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8000c40: b480 push {r7} 8000c42: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8000c44: e7fe b.n 8000c44 08000c46 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 8000c46: b480 push {r7} 8000c48: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8000c4a: e7fe b.n 8000c4a 08000c4c : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8000c4c: b480 push {r7} 8000c4e: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8000c50: e7fe b.n 8000c50 08000c52 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8000c52: b480 push {r7} 8000c54: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8000c56: bf00 nop 8000c58: 46bd mov sp, r7 8000c5a: f85d 7b04 ldr.w r7, [sp], #4 8000c5e: 4770 bx lr 08000c60 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8000c60: b480 push {r7} 8000c62: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8000c64: bf00 nop 8000c66: 46bd mov sp, r7 8000c68: f85d 7b04 ldr.w r7, [sp], #4 8000c6c: 4770 bx lr 08000c6e : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8000c6e: b480 push {r7} 8000c70: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8000c72: bf00 nop 8000c74: 46bd mov sp, r7 8000c76: f85d 7b04 ldr.w r7, [sp], #4 8000c7a: 4770 bx lr 08000c7c : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8000c7c: b580 push {r7, lr} 8000c7e: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8000c80: f000 f920 bl 8000ec4 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8000c84: bf00 nop 8000c86: bd80 pop {r7, pc} 08000c88 : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 8000c88: b580 push {r7, lr} 8000c8a: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 8000c8c: 4802 ldr r0, [pc, #8] ; (8000c98 ) 8000c8e: f003 fdff bl 8004890 /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 8000c92: bf00 nop 8000c94: bd80 pop {r7, pc} 8000c96: bf00 nop 8000c98: 24000040 .word 0x24000040 08000c9c : * configuration. * @param None * @retval None */ void SystemInit (void) { 8000c9c: b480 push {r7} 8000c9e: af00 add r7, sp, #0 __IO uint32_t tmpreg; #endif /* DATA_IN_D2_SRAM */ /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ 8000ca0: 4b32 ldr r3, [pc, #200] ; (8000d6c ) 8000ca2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8000ca6: 4a31 ldr r2, [pc, #196] ; (8000d6c ) 8000ca8: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 8000cac: f8c2 3088 str.w r3, [r2, #136] ; 0x88 #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Increasing the CPU frequency */ if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 8000cb0: 4b2f ldr r3, [pc, #188] ; (8000d70 ) 8000cb2: 681b ldr r3, [r3, #0] 8000cb4: f003 030f and.w r3, r3, #15 8000cb8: 2b02 cmp r3, #2 8000cba: d807 bhi.n 8000ccc { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 8000cbc: 4b2c ldr r3, [pc, #176] ; (8000d70 ) 8000cbe: 681b ldr r3, [r3, #0] 8000cc0: f023 030f bic.w r3, r3, #15 8000cc4: 4a2a ldr r2, [pc, #168] ; (8000d70 ) 8000cc6: f043 0303 orr.w r3, r3, #3 8000cca: 6013 str r3, [r2, #0] } /* Set HSION bit */ RCC->CR |= RCC_CR_HSION; 8000ccc: 4b29 ldr r3, [pc, #164] ; (8000d74 ) 8000cce: 681b ldr r3, [r3, #0] 8000cd0: 4a28 ldr r2, [pc, #160] ; (8000d74 ) 8000cd2: f043 0301 orr.w r3, r3, #1 8000cd6: 6013 str r3, [r2, #0] /* Reset CFGR register */ RCC->CFGR = 0x00000000; 8000cd8: 4b26 ldr r3, [pc, #152] ; (8000d74 ) 8000cda: 2200 movs r2, #0 8000cdc: 611a str r2, [r3, #16] /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ RCC->CR &= 0xEAF6ED7FU; 8000cde: 4b25 ldr r3, [pc, #148] ; (8000d74 ) 8000ce0: 681a ldr r2, [r3, #0] 8000ce2: 4924 ldr r1, [pc, #144] ; (8000d74 ) 8000ce4: 4b24 ldr r3, [pc, #144] ; (8000d78 ) 8000ce6: 4013 ands r3, r2 8000ce8: 600b str r3, [r1, #0] /* Decreasing the number of wait states because of lower CPU frequency */ if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 8000cea: 4b21 ldr r3, [pc, #132] ; (8000d70 ) 8000cec: 681b ldr r3, [r3, #0] 8000cee: f003 030c and.w r3, r3, #12 8000cf2: 2b00 cmp r3, #0 8000cf4: d007 beq.n 8000d06 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 8000cf6: 4b1e ldr r3, [pc, #120] ; (8000d70 ) 8000cf8: 681b ldr r3, [r3, #0] 8000cfa: f023 030f bic.w r3, r3, #15 8000cfe: 4a1c ldr r2, [pc, #112] ; (8000d70 ) 8000d00: f043 0303 orr.w r3, r3, #3 8000d04: 6013 str r3, [r2, #0] /* Reset D3CFGR register */ RCC->D3CFGR = 0x00000000; #else /* Reset CDCFGR1 register */ RCC->CDCFGR1 = 0x00000000; 8000d06: 4b1b ldr r3, [pc, #108] ; (8000d74 ) 8000d08: 2200 movs r2, #0 8000d0a: 619a str r2, [r3, #24] /* Reset CDCFGR2 register */ RCC->CDCFGR2 = 0x00000000; 8000d0c: 4b19 ldr r3, [pc, #100] ; (8000d74 ) 8000d0e: 2200 movs r2, #0 8000d10: 61da str r2, [r3, #28] /* Reset SRDCFGR register */ RCC->SRDCFGR = 0x00000000; 8000d12: 4b18 ldr r3, [pc, #96] ; (8000d74 ) 8000d14: 2200 movs r2, #0 8000d16: 621a str r2, [r3, #32] #endif /* Reset PLLCKSELR register */ RCC->PLLCKSELR = 0x02020200; 8000d18: 4b16 ldr r3, [pc, #88] ; (8000d74 ) 8000d1a: 4a18 ldr r2, [pc, #96] ; (8000d7c ) 8000d1c: 629a str r2, [r3, #40] ; 0x28 /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x01FF0000; 8000d1e: 4b15 ldr r3, [pc, #84] ; (8000d74 ) 8000d20: 4a17 ldr r2, [pc, #92] ; (8000d80 ) 8000d22: 62da str r2, [r3, #44] ; 0x2c /* Reset PLL1DIVR register */ RCC->PLL1DIVR = 0x01010280; 8000d24: 4b13 ldr r3, [pc, #76] ; (8000d74 ) 8000d26: 4a17 ldr r2, [pc, #92] ; (8000d84 ) 8000d28: 631a str r2, [r3, #48] ; 0x30 /* Reset PLL1FRACR register */ RCC->PLL1FRACR = 0x00000000; 8000d2a: 4b12 ldr r3, [pc, #72] ; (8000d74 ) 8000d2c: 2200 movs r2, #0 8000d2e: 635a str r2, [r3, #52] ; 0x34 /* Reset PLL2DIVR register */ RCC->PLL2DIVR = 0x01010280; 8000d30: 4b10 ldr r3, [pc, #64] ; (8000d74 ) 8000d32: 4a14 ldr r2, [pc, #80] ; (8000d84 ) 8000d34: 639a str r2, [r3, #56] ; 0x38 /* Reset PLL2FRACR register */ RCC->PLL2FRACR = 0x00000000; 8000d36: 4b0f ldr r3, [pc, #60] ; (8000d74 ) 8000d38: 2200 movs r2, #0 8000d3a: 63da str r2, [r3, #60] ; 0x3c /* Reset PLL3DIVR register */ RCC->PLL3DIVR = 0x01010280; 8000d3c: 4b0d ldr r3, [pc, #52] ; (8000d74 ) 8000d3e: 4a11 ldr r2, [pc, #68] ; (8000d84 ) 8000d40: 641a str r2, [r3, #64] ; 0x40 /* Reset PLL3FRACR register */ RCC->PLL3FRACR = 0x00000000; 8000d42: 4b0c ldr r3, [pc, #48] ; (8000d74 ) 8000d44: 2200 movs r2, #0 8000d46: 645a str r2, [r3, #68] ; 0x44 /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; 8000d48: 4b0a ldr r3, [pc, #40] ; (8000d74 ) 8000d4a: 681b ldr r3, [r3, #0] 8000d4c: 4a09 ldr r2, [pc, #36] ; (8000d74 ) 8000d4e: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8000d52: 6013 str r3, [r2, #0] /* Disable all interrupts */ RCC->CIER = 0x00000000; 8000d54: 4b07 ldr r3, [pc, #28] ; (8000d74 ) 8000d56: 2200 movs r2, #0 8000d58: 661a str r2, [r3, #96] ; 0x60 /* * Disable the FMC bank1 (enabled after reset). * This, prevents CPU speculation access on this bank which blocks the use of FMC during * 24us. During this time the others FMC master (such as LTDC) cannot use it! */ FMC_Bank1_R->BTCR[0] = 0x000030D2; 8000d5a: 4b0b ldr r3, [pc, #44] ; (8000d88 ) 8000d5c: f243 02d2 movw r2, #12498 ; 0x30d2 8000d60: 601a str r2, [r3, #0] SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */ #endif /* USER_VECT_TAB_ADDRESS */ #endif /*DUAL_CORE && CORE_CM4*/ } 8000d62: bf00 nop 8000d64: 46bd mov sp, r7 8000d66: f85d 7b04 ldr.w r7, [sp], #4 8000d6a: 4770 bx lr 8000d6c: e000ed00 .word 0xe000ed00 8000d70: 52002000 .word 0x52002000 8000d74: 58024400 .word 0x58024400 8000d78: eaf6ed7f .word 0xeaf6ed7f 8000d7c: 02020200 .word 0x02020200 8000d80: 01ff0000 .word 0x01ff0000 8000d84: 01010280 .word 0x01010280 8000d88: 52004000 .word 0x52004000 08000d8c : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 8000d8c: f8df d034 ldr.w sp, [pc, #52] ; 8000dc4 /* Call the clock system initialization function.*/ bl SystemInit 8000d90: f7ff ff84 bl 8000c9c /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8000d94: 480c ldr r0, [pc, #48] ; (8000dc8 ) ldr r1, =_edata 8000d96: 490d ldr r1, [pc, #52] ; (8000dcc ) ldr r2, =_sidata 8000d98: 4a0d ldr r2, [pc, #52] ; (8000dd0 ) movs r3, #0 8000d9a: 2300 movs r3, #0 b LoopCopyDataInit 8000d9c: e002 b.n 8000da4 08000d9e : CopyDataInit: ldr r4, [r2, r3] 8000d9e: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8000da0: 50c4 str r4, [r0, r3] adds r3, r3, #4 8000da2: 3304 adds r3, #4 08000da4 : LoopCopyDataInit: adds r4, r0, r3 8000da4: 18c4 adds r4, r0, r3 cmp r4, r1 8000da6: 428c cmp r4, r1 bcc CopyDataInit 8000da8: d3f9 bcc.n 8000d9e /* Zero fill the bss segment. */ ldr r2, =_sbss 8000daa: 4a0a ldr r2, [pc, #40] ; (8000dd4 ) ldr r4, =_ebss 8000dac: 4c0a ldr r4, [pc, #40] ; (8000dd8 ) movs r3, #0 8000dae: 2300 movs r3, #0 b LoopFillZerobss 8000db0: e001 b.n 8000db6 08000db2 : FillZerobss: str r3, [r2] 8000db2: 6013 str r3, [r2, #0] adds r2, r2, #4 8000db4: 3204 adds r2, #4 08000db6 : LoopFillZerobss: cmp r2, r4 8000db6: 42a2 cmp r2, r4 bcc FillZerobss 8000db8: d3fb bcc.n 8000db2 /* Call static constructors */ bl __libc_init_array 8000dba: f006 fa25 bl 8007208 <__libc_init_array> /* Call the application's entry point.*/ bl main 8000dbe: f7ff fc31 bl 8000624
bx lr 8000dc2: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 8000dc4: 24100000 .word 0x24100000 ldr r0, =_sdata 8000dc8: 24000000 .word 0x24000000 ldr r1, =_edata 8000dcc: 24000024 .word 0x24000024 ldr r2, =_sidata 8000dd0: 080072c0 .word 0x080072c0 ldr r2, =_sbss 8000dd4: 24000024 .word 0x24000024 ldr r4, =_ebss 8000dd8: 2400016c .word 0x2400016c 08000ddc : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8000ddc: e7fe b.n 8000ddc ... 08000de0 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8000de0: b580 push {r7, lr} 8000de2: b082 sub sp, #8 8000de4: af00 add r7, sp, #0 __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */ __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */ #endif /* DUAL_CORE && CORE_CM4 */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8000de6: 2003 movs r0, #3 8000de8: f000 f980 bl 80010ec /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); #else common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); 8000dec: f001 fefe bl 8002bec 8000df0: 4602 mov r2, r0 8000df2: 4b15 ldr r3, [pc, #84] ; (8000e48 ) 8000df4: 699b ldr r3, [r3, #24] 8000df6: 0a1b lsrs r3, r3, #8 8000df8: f003 030f and.w r3, r3, #15 8000dfc: 4913 ldr r1, [pc, #76] ; (8000e4c ) 8000dfe: 5ccb ldrb r3, [r1, r3] 8000e00: f003 031f and.w r3, r3, #31 8000e04: fa22 f303 lsr.w r3, r2, r3 8000e08: 607b str r3, [r7, #4] /* Update the SystemD2Clock global variable */ #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); #else SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); 8000e0a: 4b0f ldr r3, [pc, #60] ; (8000e48 ) 8000e0c: 699b ldr r3, [r3, #24] 8000e0e: f003 030f and.w r3, r3, #15 8000e12: 4a0e ldr r2, [pc, #56] ; (8000e4c ) 8000e14: 5cd3 ldrb r3, [r2, r3] 8000e16: f003 031f and.w r3, r3, #31 8000e1a: 687a ldr r2, [r7, #4] 8000e1c: fa22 f303 lsr.w r3, r2, r3 8000e20: 4a0b ldr r2, [pc, #44] ; (8000e50 ) 8000e22: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 8000e24: 4a0b ldr r2, [pc, #44] ; (8000e54 ) 8000e26: 687b ldr r3, [r7, #4] 8000e28: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 8000e2a: 2000 movs r0, #0 8000e2c: f000 f814 bl 8000e58 8000e30: 4603 mov r3, r0 8000e32: 2b00 cmp r3, #0 8000e34: d001 beq.n 8000e3a { return HAL_ERROR; 8000e36: 2301 movs r3, #1 8000e38: e002 b.n 8000e40 } /* Init the low level hardware */ HAL_MspInit(); 8000e3a: f7ff fe29 bl 8000a90 /* Return function status */ return HAL_OK; 8000e3e: 2300 movs r3, #0 } 8000e40: 4618 mov r0, r3 8000e42: 3708 adds r7, #8 8000e44: 46bd mov sp, r7 8000e46: bd80 pop {r7, pc} 8000e48: 58024400 .word 0x58024400 8000e4c: 08007278 .word 0x08007278 8000e50: 24000018 .word 0x24000018 8000e54: 24000014 .word 0x24000014 08000e58 : * implementation in user file. * @param TickPriority: Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8000e58: b580 push {r7, lr} 8000e5a: b082 sub sp, #8 8000e5c: af00 add r7, sp, #0 8000e5e: 6078 str r0, [r7, #4] /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/ if((uint32_t)uwTickFreq == 0UL) 8000e60: 4b15 ldr r3, [pc, #84] ; (8000eb8 ) 8000e62: 781b ldrb r3, [r3, #0] 8000e64: 2b00 cmp r3, #0 8000e66: d101 bne.n 8000e6c { return HAL_ERROR; 8000e68: 2301 movs r3, #1 8000e6a: e021 b.n 8000eb0 } /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U) 8000e6c: 4b13 ldr r3, [pc, #76] ; (8000ebc ) 8000e6e: 681a ldr r2, [r3, #0] 8000e70: 4b11 ldr r3, [pc, #68] ; (8000eb8 ) 8000e72: 781b ldrb r3, [r3, #0] 8000e74: 4619 mov r1, r3 8000e76: f44f 737a mov.w r3, #1000 ; 0x3e8 8000e7a: fbb3 f3f1 udiv r3, r3, r1 8000e7e: fbb2 f3f3 udiv r3, r2, r3 8000e82: 4618 mov r0, r3 8000e84: f000 f965 bl 8001152 8000e88: 4603 mov r3, r0 8000e8a: 2b00 cmp r3, #0 8000e8c: d001 beq.n 8000e92 { return HAL_ERROR; 8000e8e: 2301 movs r3, #1 8000e90: e00e b.n 8000eb0 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8000e92: 687b ldr r3, [r7, #4] 8000e94: 2b0f cmp r3, #15 8000e96: d80a bhi.n 8000eae { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8000e98: 2200 movs r2, #0 8000e9a: 6879 ldr r1, [r7, #4] 8000e9c: f04f 30ff mov.w r0, #4294967295 8000ea0: f000 f92f bl 8001102 uwTickPrio = TickPriority; 8000ea4: 4a06 ldr r2, [pc, #24] ; (8000ec0 ) 8000ea6: 687b ldr r3, [r7, #4] 8000ea8: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8000eaa: 2300 movs r3, #0 8000eac: e000 b.n 8000eb0 return HAL_ERROR; 8000eae: 2301 movs r3, #1 } 8000eb0: 4618 mov r0, r3 8000eb2: 3708 adds r7, #8 8000eb4: 46bd mov sp, r7 8000eb6: bd80 pop {r7, pc} 8000eb8: 24000020 .word 0x24000020 8000ebc: 24000014 .word 0x24000014 8000ec0: 2400001c .word 0x2400001c 08000ec4 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8000ec4: b480 push {r7} 8000ec6: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; 8000ec8: 4b06 ldr r3, [pc, #24] ; (8000ee4 ) 8000eca: 781b ldrb r3, [r3, #0] 8000ecc: 461a mov r2, r3 8000ece: 4b06 ldr r3, [pc, #24] ; (8000ee8 ) 8000ed0: 681b ldr r3, [r3, #0] 8000ed2: 4413 add r3, r2 8000ed4: 4a04 ldr r2, [pc, #16] ; (8000ee8 ) 8000ed6: 6013 str r3, [r2, #0] } 8000ed8: bf00 nop 8000eda: 46bd mov sp, r7 8000edc: f85d 7b04 ldr.w r7, [sp], #4 8000ee0: 4770 bx lr 8000ee2: bf00 nop 8000ee4: 24000020 .word 0x24000020 8000ee8: 24000168 .word 0x24000168 08000eec : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8000eec: b480 push {r7} 8000eee: af00 add r7, sp, #0 return uwTick; 8000ef0: 4b03 ldr r3, [pc, #12] ; (8000f00 ) 8000ef2: 681b ldr r3, [r3, #0] } 8000ef4: 4618 mov r0, r3 8000ef6: 46bd mov sp, r7 8000ef8: f85d 7b04 ldr.w r7, [sp], #4 8000efc: 4770 bx lr 8000efe: bf00 nop 8000f00: 24000168 .word 0x24000168 08000f04 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8000f04: b580 push {r7, lr} 8000f06: b084 sub sp, #16 8000f08: af00 add r7, sp, #0 8000f0a: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8000f0c: f7ff ffee bl 8000eec 8000f10: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 8000f12: 687b ldr r3, [r7, #4] 8000f14: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8000f16: 68fb ldr r3, [r7, #12] 8000f18: f1b3 3fff cmp.w r3, #4294967295 8000f1c: d005 beq.n 8000f2a { wait += (uint32_t)(uwTickFreq); 8000f1e: 4b0a ldr r3, [pc, #40] ; (8000f48 ) 8000f20: 781b ldrb r3, [r3, #0] 8000f22: 461a mov r2, r3 8000f24: 68fb ldr r3, [r7, #12] 8000f26: 4413 add r3, r2 8000f28: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 8000f2a: bf00 nop 8000f2c: f7ff ffde bl 8000eec 8000f30: 4602 mov r2, r0 8000f32: 68bb ldr r3, [r7, #8] 8000f34: 1ad3 subs r3, r2, r3 8000f36: 68fa ldr r2, [r7, #12] 8000f38: 429a cmp r2, r3 8000f3a: d8f7 bhi.n 8000f2c { } } 8000f3c: bf00 nop 8000f3e: bf00 nop 8000f40: 3710 adds r7, #16 8000f42: 46bd mov sp, r7 8000f44: bd80 pop {r7, pc} 8000f46: bf00 nop 8000f48: 24000020 .word 0x24000020 08000f4c <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8000f4c: b480 push {r7} 8000f4e: b085 sub sp, #20 8000f50: af00 add r7, sp, #0 8000f52: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8000f54: 687b ldr r3, [r7, #4] 8000f56: f003 0307 and.w r3, r3, #7 8000f5a: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8000f5c: 4b0b ldr r3, [pc, #44] ; (8000f8c <__NVIC_SetPriorityGrouping+0x40>) 8000f5e: 68db ldr r3, [r3, #12] 8000f60: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8000f62: 68ba ldr r2, [r7, #8] 8000f64: f64f 03ff movw r3, #63743 ; 0xf8ff 8000f68: 4013 ands r3, r2 8000f6a: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8000f6c: 68fb ldr r3, [r7, #12] 8000f6e: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8000f70: 68bb ldr r3, [r7, #8] 8000f72: 431a orrs r2, r3 reg_value = (reg_value | 8000f74: 4b06 ldr r3, [pc, #24] ; (8000f90 <__NVIC_SetPriorityGrouping+0x44>) 8000f76: 4313 orrs r3, r2 8000f78: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8000f7a: 4a04 ldr r2, [pc, #16] ; (8000f8c <__NVIC_SetPriorityGrouping+0x40>) 8000f7c: 68bb ldr r3, [r7, #8] 8000f7e: 60d3 str r3, [r2, #12] } 8000f80: bf00 nop 8000f82: 3714 adds r7, #20 8000f84: 46bd mov sp, r7 8000f86: f85d 7b04 ldr.w r7, [sp], #4 8000f8a: 4770 bx lr 8000f8c: e000ed00 .word 0xe000ed00 8000f90: 05fa0000 .word 0x05fa0000 08000f94 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8000f94: b480 push {r7} 8000f96: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8000f98: 4b04 ldr r3, [pc, #16] ; (8000fac <__NVIC_GetPriorityGrouping+0x18>) 8000f9a: 68db ldr r3, [r3, #12] 8000f9c: 0a1b lsrs r3, r3, #8 8000f9e: f003 0307 and.w r3, r3, #7 } 8000fa2: 4618 mov r0, r3 8000fa4: 46bd mov sp, r7 8000fa6: f85d 7b04 ldr.w r7, [sp], #4 8000faa: 4770 bx lr 8000fac: e000ed00 .word 0xe000ed00 08000fb0 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8000fb0: b480 push {r7} 8000fb2: b083 sub sp, #12 8000fb4: af00 add r7, sp, #0 8000fb6: 4603 mov r3, r0 8000fb8: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 8000fba: f9b7 3006 ldrsh.w r3, [r7, #6] 8000fbe: 2b00 cmp r3, #0 8000fc0: db0b blt.n 8000fda <__NVIC_EnableIRQ+0x2a> { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8000fc2: 88fb ldrh r3, [r7, #6] 8000fc4: f003 021f and.w r2, r3, #31 8000fc8: 4907 ldr r1, [pc, #28] ; (8000fe8 <__NVIC_EnableIRQ+0x38>) 8000fca: f9b7 3006 ldrsh.w r3, [r7, #6] 8000fce: 095b lsrs r3, r3, #5 8000fd0: 2001 movs r0, #1 8000fd2: fa00 f202 lsl.w r2, r0, r2 8000fd6: f841 2023 str.w r2, [r1, r3, lsl #2] __COMPILER_BARRIER(); } } 8000fda: bf00 nop 8000fdc: 370c adds r7, #12 8000fde: 46bd mov sp, r7 8000fe0: f85d 7b04 ldr.w r7, [sp], #4 8000fe4: 4770 bx lr 8000fe6: bf00 nop 8000fe8: e000e100 .word 0xe000e100 08000fec <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8000fec: b480 push {r7} 8000fee: b083 sub sp, #12 8000ff0: af00 add r7, sp, #0 8000ff2: 4603 mov r3, r0 8000ff4: 6039 str r1, [r7, #0] 8000ff6: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 8000ff8: f9b7 3006 ldrsh.w r3, [r7, #6] 8000ffc: 2b00 cmp r3, #0 8000ffe: db0a blt.n 8001016 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001000: 683b ldr r3, [r7, #0] 8001002: b2da uxtb r2, r3 8001004: 490c ldr r1, [pc, #48] ; (8001038 <__NVIC_SetPriority+0x4c>) 8001006: f9b7 3006 ldrsh.w r3, [r7, #6] 800100a: 0112 lsls r2, r2, #4 800100c: b2d2 uxtb r2, r2 800100e: 440b add r3, r1 8001010: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8001014: e00a b.n 800102c <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001016: 683b ldr r3, [r7, #0] 8001018: b2da uxtb r2, r3 800101a: 4908 ldr r1, [pc, #32] ; (800103c <__NVIC_SetPriority+0x50>) 800101c: 88fb ldrh r3, [r7, #6] 800101e: f003 030f and.w r3, r3, #15 8001022: 3b04 subs r3, #4 8001024: 0112 lsls r2, r2, #4 8001026: b2d2 uxtb r2, r2 8001028: 440b add r3, r1 800102a: 761a strb r2, [r3, #24] } 800102c: bf00 nop 800102e: 370c adds r7, #12 8001030: 46bd mov sp, r7 8001032: f85d 7b04 ldr.w r7, [sp], #4 8001036: 4770 bx lr 8001038: e000e100 .word 0xe000e100 800103c: e000ed00 .word 0xe000ed00 08001040 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8001040: b480 push {r7} 8001042: b089 sub sp, #36 ; 0x24 8001044: af00 add r7, sp, #0 8001046: 60f8 str r0, [r7, #12] 8001048: 60b9 str r1, [r7, #8] 800104a: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800104c: 68fb ldr r3, [r7, #12] 800104e: f003 0307 and.w r3, r3, #7 8001052: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8001054: 69fb ldr r3, [r7, #28] 8001056: f1c3 0307 rsb r3, r3, #7 800105a: 2b04 cmp r3, #4 800105c: bf28 it cs 800105e: 2304 movcs r3, #4 8001060: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8001062: 69fb ldr r3, [r7, #28] 8001064: 3304 adds r3, #4 8001066: 2b06 cmp r3, #6 8001068: d902 bls.n 8001070 800106a: 69fb ldr r3, [r7, #28] 800106c: 3b03 subs r3, #3 800106e: e000 b.n 8001072 8001070: 2300 movs r3, #0 8001072: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001074: f04f 32ff mov.w r2, #4294967295 8001078: 69bb ldr r3, [r7, #24] 800107a: fa02 f303 lsl.w r3, r2, r3 800107e: 43da mvns r2, r3 8001080: 68bb ldr r3, [r7, #8] 8001082: 401a ands r2, r3 8001084: 697b ldr r3, [r7, #20] 8001086: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8001088: f04f 31ff mov.w r1, #4294967295 800108c: 697b ldr r3, [r7, #20] 800108e: fa01 f303 lsl.w r3, r1, r3 8001092: 43d9 mvns r1, r3 8001094: 687b ldr r3, [r7, #4] 8001096: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001098: 4313 orrs r3, r2 ); } 800109a: 4618 mov r0, r3 800109c: 3724 adds r7, #36 ; 0x24 800109e: 46bd mov sp, r7 80010a0: f85d 7b04 ldr.w r7, [sp], #4 80010a4: 4770 bx lr ... 080010a8 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 80010a8: b580 push {r7, lr} 80010aa: b082 sub sp, #8 80010ac: af00 add r7, sp, #0 80010ae: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 80010b0: 687b ldr r3, [r7, #4] 80010b2: 3b01 subs r3, #1 80010b4: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 80010b8: d301 bcc.n 80010be { return (1UL); /* Reload value impossible */ 80010ba: 2301 movs r3, #1 80010bc: e00f b.n 80010de } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 80010be: 4a0a ldr r2, [pc, #40] ; (80010e8 ) 80010c0: 687b ldr r3, [r7, #4] 80010c2: 3b01 subs r3, #1 80010c4: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 80010c6: 210f movs r1, #15 80010c8: f04f 30ff mov.w r0, #4294967295 80010cc: f7ff ff8e bl 8000fec <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 80010d0: 4b05 ldr r3, [pc, #20] ; (80010e8 ) 80010d2: 2200 movs r2, #0 80010d4: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 80010d6: 4b04 ldr r3, [pc, #16] ; (80010e8 ) 80010d8: 2207 movs r2, #7 80010da: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 80010dc: 2300 movs r3, #0 } 80010de: 4618 mov r0, r3 80010e0: 3708 adds r7, #8 80010e2: 46bd mov sp, r7 80010e4: bd80 pop {r7, pc} 80010e6: bf00 nop 80010e8: e000e010 .word 0xe000e010 080010ec : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80010ec: b580 push {r7, lr} 80010ee: b082 sub sp, #8 80010f0: af00 add r7, sp, #0 80010f2: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 80010f4: 6878 ldr r0, [r7, #4] 80010f6: f7ff ff29 bl 8000f4c <__NVIC_SetPriorityGrouping> } 80010fa: bf00 nop 80010fc: 3708 adds r7, #8 80010fe: 46bd mov sp, r7 8001100: bd80 pop {r7, pc} 08001102 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8001102: b580 push {r7, lr} 8001104: b086 sub sp, #24 8001106: af00 add r7, sp, #0 8001108: 4603 mov r3, r0 800110a: 60b9 str r1, [r7, #8] 800110c: 607a str r2, [r7, #4] 800110e: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8001110: f7ff ff40 bl 8000f94 <__NVIC_GetPriorityGrouping> 8001114: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8001116: 687a ldr r2, [r7, #4] 8001118: 68b9 ldr r1, [r7, #8] 800111a: 6978 ldr r0, [r7, #20] 800111c: f7ff ff90 bl 8001040 8001120: 4602 mov r2, r0 8001122: f9b7 300e ldrsh.w r3, [r7, #14] 8001126: 4611 mov r1, r2 8001128: 4618 mov r0, r3 800112a: f7ff ff5f bl 8000fec <__NVIC_SetPriority> } 800112e: bf00 nop 8001130: 3718 adds r7, #24 8001132: 46bd mov sp, r7 8001134: bd80 pop {r7, pc} 08001136 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8001136: b580 push {r7, lr} 8001138: b082 sub sp, #8 800113a: af00 add r7, sp, #0 800113c: 4603 mov r3, r0 800113e: 80fb strh r3, [r7, #6] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8001140: f9b7 3006 ldrsh.w r3, [r7, #6] 8001144: 4618 mov r0, r3 8001146: f7ff ff33 bl 8000fb0 <__NVIC_EnableIRQ> } 800114a: bf00 nop 800114c: 3708 adds r7, #8 800114e: 46bd mov sp, r7 8001150: bd80 pop {r7, pc} 08001152 : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8001152: b580 push {r7, lr} 8001154: b082 sub sp, #8 8001156: af00 add r7, sp, #0 8001158: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 800115a: 6878 ldr r0, [r7, #4] 800115c: f7ff ffa4 bl 80010a8 8001160: 4603 mov r3, r0 } 8001162: 4618 mov r0, r3 8001164: 3708 adds r7, #8 8001166: 46bd mov sp, r7 8001168: bd80 pop {r7, pc} ... 0800116c : * and the Stream will be effectively disabled only after the transfer of * this single data is finished. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 800116c: b580 push {r7, lr} 800116e: b086 sub sp, #24 8001170: af00 add r7, sp, #0 8001172: 6078 str r0, [r7, #4] /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma; BDMA_Base_Registers *regs_bdma; const __IO uint32_t *enableRegister; uint32_t tickstart = HAL_GetTick(); 8001174: f7ff feba bl 8000eec 8001178: 6138 str r0, [r7, #16] /* Check the DMA peripheral handle */ if(hdma == NULL) 800117a: 687b ldr r3, [r7, #4] 800117c: 2b00 cmp r3, #0 800117e: d101 bne.n 8001184 { return HAL_ERROR; 8001180: 2301 movs r3, #1 8001182: e2dc b.n 800173e } /* Check the DMA peripheral state */ if(hdma->State != HAL_DMA_STATE_BUSY) 8001184: 687b ldr r3, [r7, #4] 8001186: f893 3035 ldrb.w r3, [r3, #53] ; 0x35 800118a: b2db uxtb r3, r3 800118c: 2b02 cmp r3, #2 800118e: d008 beq.n 80011a2 { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8001190: 687b ldr r3, [r7, #4] 8001192: 2280 movs r2, #128 ; 0x80 8001194: 655a str r2, [r3, #84] ; 0x54 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001196: 687b ldr r3, [r7, #4] 8001198: 2200 movs r2, #0 800119a: f883 2034 strb.w r2, [r3, #52] ; 0x34 return HAL_ERROR; 800119e: 2301 movs r3, #1 80011a0: e2cd b.n 800173e } else { /* Disable all the transfer interrupts */ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 80011a2: 687b ldr r3, [r7, #4] 80011a4: 681b ldr r3, [r3, #0] 80011a6: 4a76 ldr r2, [pc, #472] ; (8001380 ) 80011a8: 4293 cmp r3, r2 80011aa: d04a beq.n 8001242 80011ac: 687b ldr r3, [r7, #4] 80011ae: 681b ldr r3, [r3, #0] 80011b0: 4a74 ldr r2, [pc, #464] ; (8001384 ) 80011b2: 4293 cmp r3, r2 80011b4: d045 beq.n 8001242 80011b6: 687b ldr r3, [r7, #4] 80011b8: 681b ldr r3, [r3, #0] 80011ba: 4a73 ldr r2, [pc, #460] ; (8001388 ) 80011bc: 4293 cmp r3, r2 80011be: d040 beq.n 8001242 80011c0: 687b ldr r3, [r7, #4] 80011c2: 681b ldr r3, [r3, #0] 80011c4: 4a71 ldr r2, [pc, #452] ; (800138c ) 80011c6: 4293 cmp r3, r2 80011c8: d03b beq.n 8001242 80011ca: 687b ldr r3, [r7, #4] 80011cc: 681b ldr r3, [r3, #0] 80011ce: 4a70 ldr r2, [pc, #448] ; (8001390 ) 80011d0: 4293 cmp r3, r2 80011d2: d036 beq.n 8001242 80011d4: 687b ldr r3, [r7, #4] 80011d6: 681b ldr r3, [r3, #0] 80011d8: 4a6e ldr r2, [pc, #440] ; (8001394 ) 80011da: 4293 cmp r3, r2 80011dc: d031 beq.n 8001242 80011de: 687b ldr r3, [r7, #4] 80011e0: 681b ldr r3, [r3, #0] 80011e2: 4a6d ldr r2, [pc, #436] ; (8001398 ) 80011e4: 4293 cmp r3, r2 80011e6: d02c beq.n 8001242 80011e8: 687b ldr r3, [r7, #4] 80011ea: 681b ldr r3, [r3, #0] 80011ec: 4a6b ldr r2, [pc, #428] ; (800139c ) 80011ee: 4293 cmp r3, r2 80011f0: d027 beq.n 8001242 80011f2: 687b ldr r3, [r7, #4] 80011f4: 681b ldr r3, [r3, #0] 80011f6: 4a6a ldr r2, [pc, #424] ; (80013a0 ) 80011f8: 4293 cmp r3, r2 80011fa: d022 beq.n 8001242 80011fc: 687b ldr r3, [r7, #4] 80011fe: 681b ldr r3, [r3, #0] 8001200: 4a68 ldr r2, [pc, #416] ; (80013a4 ) 8001202: 4293 cmp r3, r2 8001204: d01d beq.n 8001242 8001206: 687b ldr r3, [r7, #4] 8001208: 681b ldr r3, [r3, #0] 800120a: 4a67 ldr r2, [pc, #412] ; (80013a8 ) 800120c: 4293 cmp r3, r2 800120e: d018 beq.n 8001242 8001210: 687b ldr r3, [r7, #4] 8001212: 681b ldr r3, [r3, #0] 8001214: 4a65 ldr r2, [pc, #404] ; (80013ac ) 8001216: 4293 cmp r3, r2 8001218: d013 beq.n 8001242 800121a: 687b ldr r3, [r7, #4] 800121c: 681b ldr r3, [r3, #0] 800121e: 4a64 ldr r2, [pc, #400] ; (80013b0 ) 8001220: 4293 cmp r3, r2 8001222: d00e beq.n 8001242 8001224: 687b ldr r3, [r7, #4] 8001226: 681b ldr r3, [r3, #0] 8001228: 4a62 ldr r2, [pc, #392] ; (80013b4 ) 800122a: 4293 cmp r3, r2 800122c: d009 beq.n 8001242 800122e: 687b ldr r3, [r7, #4] 8001230: 681b ldr r3, [r3, #0] 8001232: 4a61 ldr r2, [pc, #388] ; (80013b8 ) 8001234: 4293 cmp r3, r2 8001236: d004 beq.n 8001242 8001238: 687b ldr r3, [r7, #4] 800123a: 681b ldr r3, [r3, #0] 800123c: 4a5f ldr r2, [pc, #380] ; (80013bc ) 800123e: 4293 cmp r3, r2 8001240: d101 bne.n 8001246 8001242: 2301 movs r3, #1 8001244: e000 b.n 8001248 8001246: 2300 movs r3, #0 8001248: 2b00 cmp r3, #0 800124a: d013 beq.n 8001274 { /* Disable DMA All Interrupts */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); 800124c: 687b ldr r3, [r7, #4] 800124e: 681b ldr r3, [r3, #0] 8001250: 681a ldr r2, [r3, #0] 8001252: 687b ldr r3, [r7, #4] 8001254: 681b ldr r3, [r3, #0] 8001256: f022 021e bic.w r2, r2, #30 800125a: 601a str r2, [r3, #0] ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 800125c: 687b ldr r3, [r7, #4] 800125e: 681b ldr r3, [r3, #0] 8001260: 695a ldr r2, [r3, #20] 8001262: 687b ldr r3, [r7, #4] 8001264: 681b ldr r3, [r3, #0] 8001266: f022 0280 bic.w r2, r2, #128 ; 0x80 800126a: 615a str r2, [r3, #20] enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef *)hdma->Instance)->CR)); 800126c: 687b ldr r3, [r7, #4] 800126e: 681b ldr r3, [r3, #0] 8001270: 617b str r3, [r7, #20] 8001272: e00a b.n 800128a } else /* BDMA channel */ { /* Disable DMA All Interrupts */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); 8001274: 687b ldr r3, [r7, #4] 8001276: 681b ldr r3, [r3, #0] 8001278: 681a ldr r2, [r3, #0] 800127a: 687b ldr r3, [r7, #4] 800127c: 681b ldr r3, [r3, #0] 800127e: f022 020e bic.w r2, r2, #14 8001282: 601a str r2, [r3, #0] enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR)); 8001284: 687b ldr r3, [r7, #4] 8001286: 681b ldr r3, [r3, #0] 8001288: 617b str r3, [r7, #20] } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 800128a: 687b ldr r3, [r7, #4] 800128c: 681b ldr r3, [r3, #0] 800128e: 4a3c ldr r2, [pc, #240] ; (8001380 ) 8001290: 4293 cmp r3, r2 8001292: d072 beq.n 800137a 8001294: 687b ldr r3, [r7, #4] 8001296: 681b ldr r3, [r3, #0] 8001298: 4a3a ldr r2, [pc, #232] ; (8001384 ) 800129a: 4293 cmp r3, r2 800129c: d06d beq.n 800137a 800129e: 687b ldr r3, [r7, #4] 80012a0: 681b ldr r3, [r3, #0] 80012a2: 4a39 ldr r2, [pc, #228] ; (8001388 ) 80012a4: 4293 cmp r3, r2 80012a6: d068 beq.n 800137a 80012a8: 687b ldr r3, [r7, #4] 80012aa: 681b ldr r3, [r3, #0] 80012ac: 4a37 ldr r2, [pc, #220] ; (800138c ) 80012ae: 4293 cmp r3, r2 80012b0: d063 beq.n 800137a 80012b2: 687b ldr r3, [r7, #4] 80012b4: 681b ldr r3, [r3, #0] 80012b6: 4a36 ldr r2, [pc, #216] ; (8001390 ) 80012b8: 4293 cmp r3, r2 80012ba: d05e beq.n 800137a 80012bc: 687b ldr r3, [r7, #4] 80012be: 681b ldr r3, [r3, #0] 80012c0: 4a34 ldr r2, [pc, #208] ; (8001394 ) 80012c2: 4293 cmp r3, r2 80012c4: d059 beq.n 800137a 80012c6: 687b ldr r3, [r7, #4] 80012c8: 681b ldr r3, [r3, #0] 80012ca: 4a33 ldr r2, [pc, #204] ; (8001398 ) 80012cc: 4293 cmp r3, r2 80012ce: d054 beq.n 800137a 80012d0: 687b ldr r3, [r7, #4] 80012d2: 681b ldr r3, [r3, #0] 80012d4: 4a31 ldr r2, [pc, #196] ; (800139c ) 80012d6: 4293 cmp r3, r2 80012d8: d04f beq.n 800137a 80012da: 687b ldr r3, [r7, #4] 80012dc: 681b ldr r3, [r3, #0] 80012de: 4a30 ldr r2, [pc, #192] ; (80013a0 ) 80012e0: 4293 cmp r3, r2 80012e2: d04a beq.n 800137a 80012e4: 687b ldr r3, [r7, #4] 80012e6: 681b ldr r3, [r3, #0] 80012e8: 4a2e ldr r2, [pc, #184] ; (80013a4 ) 80012ea: 4293 cmp r3, r2 80012ec: d045 beq.n 800137a 80012ee: 687b ldr r3, [r7, #4] 80012f0: 681b ldr r3, [r3, #0] 80012f2: 4a2d ldr r2, [pc, #180] ; (80013a8 ) 80012f4: 4293 cmp r3, r2 80012f6: d040 beq.n 800137a 80012f8: 687b ldr r3, [r7, #4] 80012fa: 681b ldr r3, [r3, #0] 80012fc: 4a2b ldr r2, [pc, #172] ; (80013ac ) 80012fe: 4293 cmp r3, r2 8001300: d03b beq.n 800137a 8001302: 687b ldr r3, [r7, #4] 8001304: 681b ldr r3, [r3, #0] 8001306: 4a2a ldr r2, [pc, #168] ; (80013b0 ) 8001308: 4293 cmp r3, r2 800130a: d036 beq.n 800137a 800130c: 687b ldr r3, [r7, #4] 800130e: 681b ldr r3, [r3, #0] 8001310: 4a28 ldr r2, [pc, #160] ; (80013b4 ) 8001312: 4293 cmp r3, r2 8001314: d031 beq.n 800137a 8001316: 687b ldr r3, [r7, #4] 8001318: 681b ldr r3, [r3, #0] 800131a: 4a27 ldr r2, [pc, #156] ; (80013b8 ) 800131c: 4293 cmp r3, r2 800131e: d02c beq.n 800137a 8001320: 687b ldr r3, [r7, #4] 8001322: 681b ldr r3, [r3, #0] 8001324: 4a25 ldr r2, [pc, #148] ; (80013bc ) 8001326: 4293 cmp r3, r2 8001328: d027 beq.n 800137a 800132a: 687b ldr r3, [r7, #4] 800132c: 681b ldr r3, [r3, #0] 800132e: 4a24 ldr r2, [pc, #144] ; (80013c0 ) 8001330: 4293 cmp r3, r2 8001332: d022 beq.n 800137a 8001334: 687b ldr r3, [r7, #4] 8001336: 681b ldr r3, [r3, #0] 8001338: 4a22 ldr r2, [pc, #136] ; (80013c4 ) 800133a: 4293 cmp r3, r2 800133c: d01d beq.n 800137a 800133e: 687b ldr r3, [r7, #4] 8001340: 681b ldr r3, [r3, #0] 8001342: 4a21 ldr r2, [pc, #132] ; (80013c8 ) 8001344: 4293 cmp r3, r2 8001346: d018 beq.n 800137a 8001348: 687b ldr r3, [r7, #4] 800134a: 681b ldr r3, [r3, #0] 800134c: 4a1f ldr r2, [pc, #124] ; (80013cc ) 800134e: 4293 cmp r3, r2 8001350: d013 beq.n 800137a 8001352: 687b ldr r3, [r7, #4] 8001354: 681b ldr r3, [r3, #0] 8001356: 4a1e ldr r2, [pc, #120] ; (80013d0 ) 8001358: 4293 cmp r3, r2 800135a: d00e beq.n 800137a 800135c: 687b ldr r3, [r7, #4] 800135e: 681b ldr r3, [r3, #0] 8001360: 4a1c ldr r2, [pc, #112] ; (80013d4 ) 8001362: 4293 cmp r3, r2 8001364: d009 beq.n 800137a 8001366: 687b ldr r3, [r7, #4] 8001368: 681b ldr r3, [r3, #0] 800136a: 4a1b ldr r2, [pc, #108] ; (80013d8 ) 800136c: 4293 cmp r3, r2 800136e: d004 beq.n 800137a 8001370: 687b ldr r3, [r7, #4] 8001372: 681b ldr r3, [r3, #0] 8001374: 4a19 ldr r2, [pc, #100] ; (80013dc ) 8001376: 4293 cmp r3, r2 8001378: d132 bne.n 80013e0 800137a: 2301 movs r3, #1 800137c: e031 b.n 80013e2 800137e: bf00 nop 8001380: 40020010 .word 0x40020010 8001384: 40020028 .word 0x40020028 8001388: 40020040 .word 0x40020040 800138c: 40020058 .word 0x40020058 8001390: 40020070 .word 0x40020070 8001394: 40020088 .word 0x40020088 8001398: 400200a0 .word 0x400200a0 800139c: 400200b8 .word 0x400200b8 80013a0: 40020410 .word 0x40020410 80013a4: 40020428 .word 0x40020428 80013a8: 40020440 .word 0x40020440 80013ac: 40020458 .word 0x40020458 80013b0: 40020470 .word 0x40020470 80013b4: 40020488 .word 0x40020488 80013b8: 400204a0 .word 0x400204a0 80013bc: 400204b8 .word 0x400204b8 80013c0: 58025408 .word 0x58025408 80013c4: 5802541c .word 0x5802541c 80013c8: 58025430 .word 0x58025430 80013cc: 58025444 .word 0x58025444 80013d0: 58025458 .word 0x58025458 80013d4: 5802546c .word 0x5802546c 80013d8: 58025480 .word 0x58025480 80013dc: 58025494 .word 0x58025494 80013e0: 2300 movs r3, #0 80013e2: 2b00 cmp r3, #0 80013e4: d007 beq.n 80013f6 { /* disable the DMAMUX sync overrun IT */ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 80013e6: 687b ldr r3, [r7, #4] 80013e8: 6e1b ldr r3, [r3, #96] ; 0x60 80013ea: 681a ldr r2, [r3, #0] 80013ec: 687b ldr r3, [r7, #4] 80013ee: 6e1b ldr r3, [r3, #96] ; 0x60 80013f0: f422 7280 bic.w r2, r2, #256 ; 0x100 80013f4: 601a str r2, [r3, #0] } /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 80013f6: 687b ldr r3, [r7, #4] 80013f8: 681b ldr r3, [r3, #0] 80013fa: 4a6d ldr r2, [pc, #436] ; (80015b0 ) 80013fc: 4293 cmp r3, r2 80013fe: d04a beq.n 8001496 8001400: 687b ldr r3, [r7, #4] 8001402: 681b ldr r3, [r3, #0] 8001404: 4a6b ldr r2, [pc, #428] ; (80015b4 ) 8001406: 4293 cmp r3, r2 8001408: d045 beq.n 8001496 800140a: 687b ldr r3, [r7, #4] 800140c: 681b ldr r3, [r3, #0] 800140e: 4a6a ldr r2, [pc, #424] ; (80015b8 ) 8001410: 4293 cmp r3, r2 8001412: d040 beq.n 8001496 8001414: 687b ldr r3, [r7, #4] 8001416: 681b ldr r3, [r3, #0] 8001418: 4a68 ldr r2, [pc, #416] ; (80015bc ) 800141a: 4293 cmp r3, r2 800141c: d03b beq.n 8001496 800141e: 687b ldr r3, [r7, #4] 8001420: 681b ldr r3, [r3, #0] 8001422: 4a67 ldr r2, [pc, #412] ; (80015c0 ) 8001424: 4293 cmp r3, r2 8001426: d036 beq.n 8001496 8001428: 687b ldr r3, [r7, #4] 800142a: 681b ldr r3, [r3, #0] 800142c: 4a65 ldr r2, [pc, #404] ; (80015c4 ) 800142e: 4293 cmp r3, r2 8001430: d031 beq.n 8001496 8001432: 687b ldr r3, [r7, #4] 8001434: 681b ldr r3, [r3, #0] 8001436: 4a64 ldr r2, [pc, #400] ; (80015c8 ) 8001438: 4293 cmp r3, r2 800143a: d02c beq.n 8001496 800143c: 687b ldr r3, [r7, #4] 800143e: 681b ldr r3, [r3, #0] 8001440: 4a62 ldr r2, [pc, #392] ; (80015cc ) 8001442: 4293 cmp r3, r2 8001444: d027 beq.n 8001496 8001446: 687b ldr r3, [r7, #4] 8001448: 681b ldr r3, [r3, #0] 800144a: 4a61 ldr r2, [pc, #388] ; (80015d0 ) 800144c: 4293 cmp r3, r2 800144e: d022 beq.n 8001496 8001450: 687b ldr r3, [r7, #4] 8001452: 681b ldr r3, [r3, #0] 8001454: 4a5f ldr r2, [pc, #380] ; (80015d4 ) 8001456: 4293 cmp r3, r2 8001458: d01d beq.n 8001496 800145a: 687b ldr r3, [r7, #4] 800145c: 681b ldr r3, [r3, #0] 800145e: 4a5e ldr r2, [pc, #376] ; (80015d8 ) 8001460: 4293 cmp r3, r2 8001462: d018 beq.n 8001496 8001464: 687b ldr r3, [r7, #4] 8001466: 681b ldr r3, [r3, #0] 8001468: 4a5c ldr r2, [pc, #368] ; (80015dc ) 800146a: 4293 cmp r3, r2 800146c: d013 beq.n 8001496 800146e: 687b ldr r3, [r7, #4] 8001470: 681b ldr r3, [r3, #0] 8001472: 4a5b ldr r2, [pc, #364] ; (80015e0 ) 8001474: 4293 cmp r3, r2 8001476: d00e beq.n 8001496 8001478: 687b ldr r3, [r7, #4] 800147a: 681b ldr r3, [r3, #0] 800147c: 4a59 ldr r2, [pc, #356] ; (80015e4 ) 800147e: 4293 cmp r3, r2 8001480: d009 beq.n 8001496 8001482: 687b ldr r3, [r7, #4] 8001484: 681b ldr r3, [r3, #0] 8001486: 4a58 ldr r2, [pc, #352] ; (80015e8 ) 8001488: 4293 cmp r3, r2 800148a: d004 beq.n 8001496 800148c: 687b ldr r3, [r7, #4] 800148e: 681b ldr r3, [r3, #0] 8001490: 4a56 ldr r2, [pc, #344] ; (80015ec ) 8001492: 4293 cmp r3, r2 8001494: d108 bne.n 80014a8 8001496: 687b ldr r3, [r7, #4] 8001498: 681b ldr r3, [r3, #0] 800149a: 681a ldr r2, [r3, #0] 800149c: 687b ldr r3, [r7, #4] 800149e: 681b ldr r3, [r3, #0] 80014a0: f022 0201 bic.w r2, r2, #1 80014a4: 601a str r2, [r3, #0] 80014a6: e007 b.n 80014b8 80014a8: 687b ldr r3, [r7, #4] 80014aa: 681b ldr r3, [r3, #0] 80014ac: 681a ldr r2, [r3, #0] 80014ae: 687b ldr r3, [r7, #4] 80014b0: 681b ldr r3, [r3, #0] 80014b2: f022 0201 bic.w r2, r2, #1 80014b6: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while(((*enableRegister) & DMA_SxCR_EN) != 0U) 80014b8: e013 b.n 80014e2 { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 80014ba: f7ff fd17 bl 8000eec 80014be: 4602 mov r2, r0 80014c0: 693b ldr r3, [r7, #16] 80014c2: 1ad3 subs r3, r2, r3 80014c4: 2b05 cmp r3, #5 80014c6: d90c bls.n 80014e2 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 80014c8: 687b ldr r3, [r7, #4] 80014ca: 2220 movs r2, #32 80014cc: 655a str r2, [r3, #84] ; 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_ERROR; 80014ce: 687b ldr r3, [r7, #4] 80014d0: 2203 movs r2, #3 80014d2: f883 2035 strb.w r2, [r3, #53] ; 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80014d6: 687b ldr r3, [r7, #4] 80014d8: 2200 movs r2, #0 80014da: f883 2034 strb.w r2, [r3, #52] ; 0x34 return HAL_ERROR; 80014de: 2301 movs r3, #1 80014e0: e12d b.n 800173e while(((*enableRegister) & DMA_SxCR_EN) != 0U) 80014e2: 697b ldr r3, [r7, #20] 80014e4: 681b ldr r3, [r3, #0] 80014e6: f003 0301 and.w r3, r3, #1 80014ea: 2b00 cmp r3, #0 80014ec: d1e5 bne.n 80014ba } } /* Clear all interrupt flags at correct offset within the register */ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 80014ee: 687b ldr r3, [r7, #4] 80014f0: 681b ldr r3, [r3, #0] 80014f2: 4a2f ldr r2, [pc, #188] ; (80015b0 ) 80014f4: 4293 cmp r3, r2 80014f6: d04a beq.n 800158e 80014f8: 687b ldr r3, [r7, #4] 80014fa: 681b ldr r3, [r3, #0] 80014fc: 4a2d ldr r2, [pc, #180] ; (80015b4 ) 80014fe: 4293 cmp r3, r2 8001500: d045 beq.n 800158e 8001502: 687b ldr r3, [r7, #4] 8001504: 681b ldr r3, [r3, #0] 8001506: 4a2c ldr r2, [pc, #176] ; (80015b8 ) 8001508: 4293 cmp r3, r2 800150a: d040 beq.n 800158e 800150c: 687b ldr r3, [r7, #4] 800150e: 681b ldr r3, [r3, #0] 8001510: 4a2a ldr r2, [pc, #168] ; (80015bc ) 8001512: 4293 cmp r3, r2 8001514: d03b beq.n 800158e 8001516: 687b ldr r3, [r7, #4] 8001518: 681b ldr r3, [r3, #0] 800151a: 4a29 ldr r2, [pc, #164] ; (80015c0 ) 800151c: 4293 cmp r3, r2 800151e: d036 beq.n 800158e 8001520: 687b ldr r3, [r7, #4] 8001522: 681b ldr r3, [r3, #0] 8001524: 4a27 ldr r2, [pc, #156] ; (80015c4 ) 8001526: 4293 cmp r3, r2 8001528: d031 beq.n 800158e 800152a: 687b ldr r3, [r7, #4] 800152c: 681b ldr r3, [r3, #0] 800152e: 4a26 ldr r2, [pc, #152] ; (80015c8 ) 8001530: 4293 cmp r3, r2 8001532: d02c beq.n 800158e 8001534: 687b ldr r3, [r7, #4] 8001536: 681b ldr r3, [r3, #0] 8001538: 4a24 ldr r2, [pc, #144] ; (80015cc ) 800153a: 4293 cmp r3, r2 800153c: d027 beq.n 800158e 800153e: 687b ldr r3, [r7, #4] 8001540: 681b ldr r3, [r3, #0] 8001542: 4a23 ldr r2, [pc, #140] ; (80015d0 ) 8001544: 4293 cmp r3, r2 8001546: d022 beq.n 800158e 8001548: 687b ldr r3, [r7, #4] 800154a: 681b ldr r3, [r3, #0] 800154c: 4a21 ldr r2, [pc, #132] ; (80015d4 ) 800154e: 4293 cmp r3, r2 8001550: d01d beq.n 800158e 8001552: 687b ldr r3, [r7, #4] 8001554: 681b ldr r3, [r3, #0] 8001556: 4a20 ldr r2, [pc, #128] ; (80015d8 ) 8001558: 4293 cmp r3, r2 800155a: d018 beq.n 800158e 800155c: 687b ldr r3, [r7, #4] 800155e: 681b ldr r3, [r3, #0] 8001560: 4a1e ldr r2, [pc, #120] ; (80015dc ) 8001562: 4293 cmp r3, r2 8001564: d013 beq.n 800158e 8001566: 687b ldr r3, [r7, #4] 8001568: 681b ldr r3, [r3, #0] 800156a: 4a1d ldr r2, [pc, #116] ; (80015e0 ) 800156c: 4293 cmp r3, r2 800156e: d00e beq.n 800158e 8001570: 687b ldr r3, [r7, #4] 8001572: 681b ldr r3, [r3, #0] 8001574: 4a1b ldr r2, [pc, #108] ; (80015e4 ) 8001576: 4293 cmp r3, r2 8001578: d009 beq.n 800158e 800157a: 687b ldr r3, [r7, #4] 800157c: 681b ldr r3, [r3, #0] 800157e: 4a1a ldr r2, [pc, #104] ; (80015e8 ) 8001580: 4293 cmp r3, r2 8001582: d004 beq.n 800158e 8001584: 687b ldr r3, [r7, #4] 8001586: 681b ldr r3, [r3, #0] 8001588: 4a18 ldr r2, [pc, #96] ; (80015ec ) 800158a: 4293 cmp r3, r2 800158c: d101 bne.n 8001592 800158e: 2301 movs r3, #1 8001590: e000 b.n 8001594 8001592: 2300 movs r3, #0 8001594: 2b00 cmp r3, #0 8001596: d02b beq.n 80015f0 { regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8001598: 687b ldr r3, [r7, #4] 800159a: 6d9b ldr r3, [r3, #88] ; 0x58 800159c: 60bb str r3, [r7, #8] regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 800159e: 687b ldr r3, [r7, #4] 80015a0: 6ddb ldr r3, [r3, #92] ; 0x5c 80015a2: f003 031f and.w r3, r3, #31 80015a6: 223f movs r2, #63 ; 0x3f 80015a8: 409a lsls r2, r3 80015aa: 68bb ldr r3, [r7, #8] 80015ac: 609a str r2, [r3, #8] 80015ae: e02a b.n 8001606 80015b0: 40020010 .word 0x40020010 80015b4: 40020028 .word 0x40020028 80015b8: 40020040 .word 0x40020040 80015bc: 40020058 .word 0x40020058 80015c0: 40020070 .word 0x40020070 80015c4: 40020088 .word 0x40020088 80015c8: 400200a0 .word 0x400200a0 80015cc: 400200b8 .word 0x400200b8 80015d0: 40020410 .word 0x40020410 80015d4: 40020428 .word 0x40020428 80015d8: 40020440 .word 0x40020440 80015dc: 40020458 .word 0x40020458 80015e0: 40020470 .word 0x40020470 80015e4: 40020488 .word 0x40020488 80015e8: 400204a0 .word 0x400204a0 80015ec: 400204b8 .word 0x400204b8 } else /* BDMA channel */ { regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 80015f0: 687b ldr r3, [r7, #4] 80015f2: 6d9b ldr r3, [r3, #88] ; 0x58 80015f4: 60fb str r3, [r7, #12] regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 80015f6: 687b ldr r3, [r7, #4] 80015f8: 6ddb ldr r3, [r3, #92] ; 0x5c 80015fa: f003 031f and.w r3, r3, #31 80015fe: 2201 movs r2, #1 8001600: 409a lsls r2, r3 8001602: 68fb ldr r3, [r7, #12] 8001604: 605a str r2, [r3, #4] } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8001606: 687b ldr r3, [r7, #4] 8001608: 681b ldr r3, [r3, #0] 800160a: 4a4f ldr r2, [pc, #316] ; (8001748 ) 800160c: 4293 cmp r3, r2 800160e: d072 beq.n 80016f6 8001610: 687b ldr r3, [r7, #4] 8001612: 681b ldr r3, [r3, #0] 8001614: 4a4d ldr r2, [pc, #308] ; (800174c ) 8001616: 4293 cmp r3, r2 8001618: d06d beq.n 80016f6 800161a: 687b ldr r3, [r7, #4] 800161c: 681b ldr r3, [r3, #0] 800161e: 4a4c ldr r2, [pc, #304] ; (8001750 ) 8001620: 4293 cmp r3, r2 8001622: d068 beq.n 80016f6 8001624: 687b ldr r3, [r7, #4] 8001626: 681b ldr r3, [r3, #0] 8001628: 4a4a ldr r2, [pc, #296] ; (8001754 ) 800162a: 4293 cmp r3, r2 800162c: d063 beq.n 80016f6 800162e: 687b ldr r3, [r7, #4] 8001630: 681b ldr r3, [r3, #0] 8001632: 4a49 ldr r2, [pc, #292] ; (8001758 ) 8001634: 4293 cmp r3, r2 8001636: d05e beq.n 80016f6 8001638: 687b ldr r3, [r7, #4] 800163a: 681b ldr r3, [r3, #0] 800163c: 4a47 ldr r2, [pc, #284] ; (800175c ) 800163e: 4293 cmp r3, r2 8001640: d059 beq.n 80016f6 8001642: 687b ldr r3, [r7, #4] 8001644: 681b ldr r3, [r3, #0] 8001646: 4a46 ldr r2, [pc, #280] ; (8001760 ) 8001648: 4293 cmp r3, r2 800164a: d054 beq.n 80016f6 800164c: 687b ldr r3, [r7, #4] 800164e: 681b ldr r3, [r3, #0] 8001650: 4a44 ldr r2, [pc, #272] ; (8001764 ) 8001652: 4293 cmp r3, r2 8001654: d04f beq.n 80016f6 8001656: 687b ldr r3, [r7, #4] 8001658: 681b ldr r3, [r3, #0] 800165a: 4a43 ldr r2, [pc, #268] ; (8001768 ) 800165c: 4293 cmp r3, r2 800165e: d04a beq.n 80016f6 8001660: 687b ldr r3, [r7, #4] 8001662: 681b ldr r3, [r3, #0] 8001664: 4a41 ldr r2, [pc, #260] ; (800176c ) 8001666: 4293 cmp r3, r2 8001668: d045 beq.n 80016f6 800166a: 687b ldr r3, [r7, #4] 800166c: 681b ldr r3, [r3, #0] 800166e: 4a40 ldr r2, [pc, #256] ; (8001770 ) 8001670: 4293 cmp r3, r2 8001672: d040 beq.n 80016f6 8001674: 687b ldr r3, [r7, #4] 8001676: 681b ldr r3, [r3, #0] 8001678: 4a3e ldr r2, [pc, #248] ; (8001774 ) 800167a: 4293 cmp r3, r2 800167c: d03b beq.n 80016f6 800167e: 687b ldr r3, [r7, #4] 8001680: 681b ldr r3, [r3, #0] 8001682: 4a3d ldr r2, [pc, #244] ; (8001778 ) 8001684: 4293 cmp r3, r2 8001686: d036 beq.n 80016f6 8001688: 687b ldr r3, [r7, #4] 800168a: 681b ldr r3, [r3, #0] 800168c: 4a3b ldr r2, [pc, #236] ; (800177c ) 800168e: 4293 cmp r3, r2 8001690: d031 beq.n 80016f6 8001692: 687b ldr r3, [r7, #4] 8001694: 681b ldr r3, [r3, #0] 8001696: 4a3a ldr r2, [pc, #232] ; (8001780 ) 8001698: 4293 cmp r3, r2 800169a: d02c beq.n 80016f6 800169c: 687b ldr r3, [r7, #4] 800169e: 681b ldr r3, [r3, #0] 80016a0: 4a38 ldr r2, [pc, #224] ; (8001784 ) 80016a2: 4293 cmp r3, r2 80016a4: d027 beq.n 80016f6 80016a6: 687b ldr r3, [r7, #4] 80016a8: 681b ldr r3, [r3, #0] 80016aa: 4a37 ldr r2, [pc, #220] ; (8001788 ) 80016ac: 4293 cmp r3, r2 80016ae: d022 beq.n 80016f6 80016b0: 687b ldr r3, [r7, #4] 80016b2: 681b ldr r3, [r3, #0] 80016b4: 4a35 ldr r2, [pc, #212] ; (800178c ) 80016b6: 4293 cmp r3, r2 80016b8: d01d beq.n 80016f6 80016ba: 687b ldr r3, [r7, #4] 80016bc: 681b ldr r3, [r3, #0] 80016be: 4a34 ldr r2, [pc, #208] ; (8001790 ) 80016c0: 4293 cmp r3, r2 80016c2: d018 beq.n 80016f6 80016c4: 687b ldr r3, [r7, #4] 80016c6: 681b ldr r3, [r3, #0] 80016c8: 4a32 ldr r2, [pc, #200] ; (8001794 ) 80016ca: 4293 cmp r3, r2 80016cc: d013 beq.n 80016f6 80016ce: 687b ldr r3, [r7, #4] 80016d0: 681b ldr r3, [r3, #0] 80016d2: 4a31 ldr r2, [pc, #196] ; (8001798 ) 80016d4: 4293 cmp r3, r2 80016d6: d00e beq.n 80016f6 80016d8: 687b ldr r3, [r7, #4] 80016da: 681b ldr r3, [r3, #0] 80016dc: 4a2f ldr r2, [pc, #188] ; (800179c ) 80016de: 4293 cmp r3, r2 80016e0: d009 beq.n 80016f6 80016e2: 687b ldr r3, [r7, #4] 80016e4: 681b ldr r3, [r3, #0] 80016e6: 4a2e ldr r2, [pc, #184] ; (80017a0 ) 80016e8: 4293 cmp r3, r2 80016ea: d004 beq.n 80016f6 80016ec: 687b ldr r3, [r7, #4] 80016ee: 681b ldr r3, [r3, #0] 80016f0: 4a2c ldr r2, [pc, #176] ; (80017a4 ) 80016f2: 4293 cmp r3, r2 80016f4: d101 bne.n 80016fa 80016f6: 2301 movs r3, #1 80016f8: e000 b.n 80016fc 80016fa: 2300 movs r3, #0 80016fc: 2b00 cmp r3, #0 80016fe: d015 beq.n 800172c { /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8001700: 687b ldr r3, [r7, #4] 8001702: 6e5b ldr r3, [r3, #100] ; 0x64 8001704: 687a ldr r2, [r7, #4] 8001706: 6e92 ldr r2, [r2, #104] ; 0x68 8001708: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 800170a: 687b ldr r3, [r7, #4] 800170c: 6edb ldr r3, [r3, #108] ; 0x6c 800170e: 2b00 cmp r3, #0 8001710: d00c beq.n 800172c { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */ /* disable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 8001712: 687b ldr r3, [r7, #4] 8001714: 6edb ldr r3, [r3, #108] ; 0x6c 8001716: 681a ldr r2, [r3, #0] 8001718: 687b ldr r3, [r7, #4] 800171a: 6edb ldr r3, [r3, #108] ; 0x6c 800171c: f422 7280 bic.w r2, r2, #256 ; 0x100 8001720: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8001722: 687b ldr r3, [r7, #4] 8001724: 6f1b ldr r3, [r3, #112] ; 0x70 8001726: 687a ldr r2, [r7, #4] 8001728: 6f52 ldr r2, [r2, #116] ; 0x74 800172a: 605a str r2, [r3, #4] } } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800172c: 687b ldr r3, [r7, #4] 800172e: 2201 movs r2, #1 8001730: f883 2035 strb.w r2, [r3, #53] ; 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001734: 687b ldr r3, [r7, #4] 8001736: 2200 movs r2, #0 8001738: f883 2034 strb.w r2, [r3, #52] ; 0x34 } return HAL_OK; 800173c: 2300 movs r3, #0 } 800173e: 4618 mov r0, r3 8001740: 3718 adds r7, #24 8001742: 46bd mov sp, r7 8001744: bd80 pop {r7, pc} 8001746: bf00 nop 8001748: 40020010 .word 0x40020010 800174c: 40020028 .word 0x40020028 8001750: 40020040 .word 0x40020040 8001754: 40020058 .word 0x40020058 8001758: 40020070 .word 0x40020070 800175c: 40020088 .word 0x40020088 8001760: 400200a0 .word 0x400200a0 8001764: 400200b8 .word 0x400200b8 8001768: 40020410 .word 0x40020410 800176c: 40020428 .word 0x40020428 8001770: 40020440 .word 0x40020440 8001774: 40020458 .word 0x40020458 8001778: 40020470 .word 0x40020470 800177c: 40020488 .word 0x40020488 8001780: 400204a0 .word 0x400204a0 8001784: 400204b8 .word 0x400204b8 8001788: 58025408 .word 0x58025408 800178c: 5802541c .word 0x5802541c 8001790: 58025430 .word 0x58025430 8001794: 58025444 .word 0x58025444 8001798: 58025458 .word 0x58025458 800179c: 5802546c .word 0x5802546c 80017a0: 58025480 .word 0x58025480 80017a4: 58025494 .word 0x58025494 080017a8 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 80017a8: b580 push {r7, lr} 80017aa: b084 sub sp, #16 80017ac: af00 add r7, sp, #0 80017ae: 6078 str r0, [r7, #4] BDMA_Base_Registers *regs_bdma; /* Check the DMA peripheral handle */ if(hdma == NULL) 80017b0: 687b ldr r3, [r7, #4] 80017b2: 2b00 cmp r3, #0 80017b4: d101 bne.n 80017ba { return HAL_ERROR; 80017b6: 2301 movs r3, #1 80017b8: e205 b.n 8001bc6 } if(hdma->State != HAL_DMA_STATE_BUSY) 80017ba: 687b ldr r3, [r7, #4] 80017bc: f893 3035 ldrb.w r3, [r3, #53] ; 0x35 80017c0: b2db uxtb r3, r3 80017c2: 2b02 cmp r3, #2 80017c4: d004 beq.n 80017d0 { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 80017c6: 687b ldr r3, [r7, #4] 80017c8: 2280 movs r2, #128 ; 0x80 80017ca: 655a str r2, [r3, #84] ; 0x54 return HAL_ERROR; 80017cc: 2301 movs r3, #1 80017ce: e1fa b.n 8001bc6 } else { if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 80017d0: 687b ldr r3, [r7, #4] 80017d2: 681b ldr r3, [r3, #0] 80017d4: 4a8c ldr r2, [pc, #560] ; (8001a08 ) 80017d6: 4293 cmp r3, r2 80017d8: d04a beq.n 8001870 80017da: 687b ldr r3, [r7, #4] 80017dc: 681b ldr r3, [r3, #0] 80017de: 4a8b ldr r2, [pc, #556] ; (8001a0c ) 80017e0: 4293 cmp r3, r2 80017e2: d045 beq.n 8001870 80017e4: 687b ldr r3, [r7, #4] 80017e6: 681b ldr r3, [r3, #0] 80017e8: 4a89 ldr r2, [pc, #548] ; (8001a10 ) 80017ea: 4293 cmp r3, r2 80017ec: d040 beq.n 8001870 80017ee: 687b ldr r3, [r7, #4] 80017f0: 681b ldr r3, [r3, #0] 80017f2: 4a88 ldr r2, [pc, #544] ; (8001a14 ) 80017f4: 4293 cmp r3, r2 80017f6: d03b beq.n 8001870 80017f8: 687b ldr r3, [r7, #4] 80017fa: 681b ldr r3, [r3, #0] 80017fc: 4a86 ldr r2, [pc, #536] ; (8001a18 ) 80017fe: 4293 cmp r3, r2 8001800: d036 beq.n 8001870 8001802: 687b ldr r3, [r7, #4] 8001804: 681b ldr r3, [r3, #0] 8001806: 4a85 ldr r2, [pc, #532] ; (8001a1c ) 8001808: 4293 cmp r3, r2 800180a: d031 beq.n 8001870 800180c: 687b ldr r3, [r7, #4] 800180e: 681b ldr r3, [r3, #0] 8001810: 4a83 ldr r2, [pc, #524] ; (8001a20 ) 8001812: 4293 cmp r3, r2 8001814: d02c beq.n 8001870 8001816: 687b ldr r3, [r7, #4] 8001818: 681b ldr r3, [r3, #0] 800181a: 4a82 ldr r2, [pc, #520] ; (8001a24 ) 800181c: 4293 cmp r3, r2 800181e: d027 beq.n 8001870 8001820: 687b ldr r3, [r7, #4] 8001822: 681b ldr r3, [r3, #0] 8001824: 4a80 ldr r2, [pc, #512] ; (8001a28 ) 8001826: 4293 cmp r3, r2 8001828: d022 beq.n 8001870 800182a: 687b ldr r3, [r7, #4] 800182c: 681b ldr r3, [r3, #0] 800182e: 4a7f ldr r2, [pc, #508] ; (8001a2c ) 8001830: 4293 cmp r3, r2 8001832: d01d beq.n 8001870 8001834: 687b ldr r3, [r7, #4] 8001836: 681b ldr r3, [r3, #0] 8001838: 4a7d ldr r2, [pc, #500] ; (8001a30 ) 800183a: 4293 cmp r3, r2 800183c: d018 beq.n 8001870 800183e: 687b ldr r3, [r7, #4] 8001840: 681b ldr r3, [r3, #0] 8001842: 4a7c ldr r2, [pc, #496] ; (8001a34 ) 8001844: 4293 cmp r3, r2 8001846: d013 beq.n 8001870 8001848: 687b ldr r3, [r7, #4] 800184a: 681b ldr r3, [r3, #0] 800184c: 4a7a ldr r2, [pc, #488] ; (8001a38 ) 800184e: 4293 cmp r3, r2 8001850: d00e beq.n 8001870 8001852: 687b ldr r3, [r7, #4] 8001854: 681b ldr r3, [r3, #0] 8001856: 4a79 ldr r2, [pc, #484] ; (8001a3c ) 8001858: 4293 cmp r3, r2 800185a: d009 beq.n 8001870 800185c: 687b ldr r3, [r7, #4] 800185e: 681b ldr r3, [r3, #0] 8001860: 4a77 ldr r2, [pc, #476] ; (8001a40 ) 8001862: 4293 cmp r3, r2 8001864: d004 beq.n 8001870 8001866: 687b ldr r3, [r7, #4] 8001868: 681b ldr r3, [r3, #0] 800186a: 4a76 ldr r2, [pc, #472] ; (8001a44 ) 800186c: 4293 cmp r3, r2 800186e: d101 bne.n 8001874 8001870: 2301 movs r3, #1 8001872: e000 b.n 8001876 8001874: 2300 movs r3, #0 8001876: 2b00 cmp r3, #0 8001878: d065 beq.n 8001946 { /* Set Abort State */ hdma->State = HAL_DMA_STATE_ABORT; 800187a: 687b ldr r3, [r7, #4] 800187c: 2204 movs r2, #4 800187e: f883 2035 strb.w r2, [r3, #53] ; 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 8001882: 687b ldr r3, [r7, #4] 8001884: 681b ldr r3, [r3, #0] 8001886: 4a60 ldr r2, [pc, #384] ; (8001a08 ) 8001888: 4293 cmp r3, r2 800188a: d04a beq.n 8001922 800188c: 687b ldr r3, [r7, #4] 800188e: 681b ldr r3, [r3, #0] 8001890: 4a5e ldr r2, [pc, #376] ; (8001a0c ) 8001892: 4293 cmp r3, r2 8001894: d045 beq.n 8001922 8001896: 687b ldr r3, [r7, #4] 8001898: 681b ldr r3, [r3, #0] 800189a: 4a5d ldr r2, [pc, #372] ; (8001a10 ) 800189c: 4293 cmp r3, r2 800189e: d040 beq.n 8001922 80018a0: 687b ldr r3, [r7, #4] 80018a2: 681b ldr r3, [r3, #0] 80018a4: 4a5b ldr r2, [pc, #364] ; (8001a14 ) 80018a6: 4293 cmp r3, r2 80018a8: d03b beq.n 8001922 80018aa: 687b ldr r3, [r7, #4] 80018ac: 681b ldr r3, [r3, #0] 80018ae: 4a5a ldr r2, [pc, #360] ; (8001a18 ) 80018b0: 4293 cmp r3, r2 80018b2: d036 beq.n 8001922 80018b4: 687b ldr r3, [r7, #4] 80018b6: 681b ldr r3, [r3, #0] 80018b8: 4a58 ldr r2, [pc, #352] ; (8001a1c ) 80018ba: 4293 cmp r3, r2 80018bc: d031 beq.n 8001922 80018be: 687b ldr r3, [r7, #4] 80018c0: 681b ldr r3, [r3, #0] 80018c2: 4a57 ldr r2, [pc, #348] ; (8001a20 ) 80018c4: 4293 cmp r3, r2 80018c6: d02c beq.n 8001922 80018c8: 687b ldr r3, [r7, #4] 80018ca: 681b ldr r3, [r3, #0] 80018cc: 4a55 ldr r2, [pc, #340] ; (8001a24 ) 80018ce: 4293 cmp r3, r2 80018d0: d027 beq.n 8001922 80018d2: 687b ldr r3, [r7, #4] 80018d4: 681b ldr r3, [r3, #0] 80018d6: 4a54 ldr r2, [pc, #336] ; (8001a28 ) 80018d8: 4293 cmp r3, r2 80018da: d022 beq.n 8001922 80018dc: 687b ldr r3, [r7, #4] 80018de: 681b ldr r3, [r3, #0] 80018e0: 4a52 ldr r2, [pc, #328] ; (8001a2c ) 80018e2: 4293 cmp r3, r2 80018e4: d01d beq.n 8001922 80018e6: 687b ldr r3, [r7, #4] 80018e8: 681b ldr r3, [r3, #0] 80018ea: 4a51 ldr r2, [pc, #324] ; (8001a30 ) 80018ec: 4293 cmp r3, r2 80018ee: d018 beq.n 8001922 80018f0: 687b ldr r3, [r7, #4] 80018f2: 681b ldr r3, [r3, #0] 80018f4: 4a4f ldr r2, [pc, #316] ; (8001a34 ) 80018f6: 4293 cmp r3, r2 80018f8: d013 beq.n 8001922 80018fa: 687b ldr r3, [r7, #4] 80018fc: 681b ldr r3, [r3, #0] 80018fe: 4a4e ldr r2, [pc, #312] ; (8001a38 ) 8001900: 4293 cmp r3, r2 8001902: d00e beq.n 8001922 8001904: 687b ldr r3, [r7, #4] 8001906: 681b ldr r3, [r3, #0] 8001908: 4a4c ldr r2, [pc, #304] ; (8001a3c ) 800190a: 4293 cmp r3, r2 800190c: d009 beq.n 8001922 800190e: 687b ldr r3, [r7, #4] 8001910: 681b ldr r3, [r3, #0] 8001912: 4a4b ldr r2, [pc, #300] ; (8001a40 ) 8001914: 4293 cmp r3, r2 8001916: d004 beq.n 8001922 8001918: 687b ldr r3, [r7, #4] 800191a: 681b ldr r3, [r3, #0] 800191c: 4a49 ldr r2, [pc, #292] ; (8001a44 ) 800191e: 4293 cmp r3, r2 8001920: d108 bne.n 8001934 8001922: 687b ldr r3, [r7, #4] 8001924: 681b ldr r3, [r3, #0] 8001926: 681a ldr r2, [r3, #0] 8001928: 687b ldr r3, [r7, #4] 800192a: 681b ldr r3, [r3, #0] 800192c: f022 0201 bic.w r2, r2, #1 8001930: 601a str r2, [r3, #0] 8001932: e147 b.n 8001bc4 8001934: 687b ldr r3, [r7, #4] 8001936: 681b ldr r3, [r3, #0] 8001938: 681a ldr r2, [r3, #0] 800193a: 687b ldr r3, [r7, #4] 800193c: 681b ldr r3, [r3, #0] 800193e: f022 0201 bic.w r2, r2, #1 8001942: 601a str r2, [r3, #0] 8001944: e13e b.n 8001bc4 } else /* BDMA channel */ { /* Disable DMA All Interrupts */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); 8001946: 687b ldr r3, [r7, #4] 8001948: 681b ldr r3, [r3, #0] 800194a: 681a ldr r2, [r3, #0] 800194c: 687b ldr r3, [r7, #4] 800194e: 681b ldr r3, [r3, #0] 8001950: f022 020e bic.w r2, r2, #14 8001954: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8001956: 687b ldr r3, [r7, #4] 8001958: 681b ldr r3, [r3, #0] 800195a: 4a2b ldr r2, [pc, #172] ; (8001a08 ) 800195c: 4293 cmp r3, r2 800195e: d04a beq.n 80019f6 8001960: 687b ldr r3, [r7, #4] 8001962: 681b ldr r3, [r3, #0] 8001964: 4a29 ldr r2, [pc, #164] ; (8001a0c ) 8001966: 4293 cmp r3, r2 8001968: d045 beq.n 80019f6 800196a: 687b ldr r3, [r7, #4] 800196c: 681b ldr r3, [r3, #0] 800196e: 4a28 ldr r2, [pc, #160] ; (8001a10 ) 8001970: 4293 cmp r3, r2 8001972: d040 beq.n 80019f6 8001974: 687b ldr r3, [r7, #4] 8001976: 681b ldr r3, [r3, #0] 8001978: 4a26 ldr r2, [pc, #152] ; (8001a14 ) 800197a: 4293 cmp r3, r2 800197c: d03b beq.n 80019f6 800197e: 687b ldr r3, [r7, #4] 8001980: 681b ldr r3, [r3, #0] 8001982: 4a25 ldr r2, [pc, #148] ; (8001a18 ) 8001984: 4293 cmp r3, r2 8001986: d036 beq.n 80019f6 8001988: 687b ldr r3, [r7, #4] 800198a: 681b ldr r3, [r3, #0] 800198c: 4a23 ldr r2, [pc, #140] ; (8001a1c ) 800198e: 4293 cmp r3, r2 8001990: d031 beq.n 80019f6 8001992: 687b ldr r3, [r7, #4] 8001994: 681b ldr r3, [r3, #0] 8001996: 4a22 ldr r2, [pc, #136] ; (8001a20 ) 8001998: 4293 cmp r3, r2 800199a: d02c beq.n 80019f6 800199c: 687b ldr r3, [r7, #4] 800199e: 681b ldr r3, [r3, #0] 80019a0: 4a20 ldr r2, [pc, #128] ; (8001a24 ) 80019a2: 4293 cmp r3, r2 80019a4: d027 beq.n 80019f6 80019a6: 687b ldr r3, [r7, #4] 80019a8: 681b ldr r3, [r3, #0] 80019aa: 4a1f ldr r2, [pc, #124] ; (8001a28 ) 80019ac: 4293 cmp r3, r2 80019ae: d022 beq.n 80019f6 80019b0: 687b ldr r3, [r7, #4] 80019b2: 681b ldr r3, [r3, #0] 80019b4: 4a1d ldr r2, [pc, #116] ; (8001a2c ) 80019b6: 4293 cmp r3, r2 80019b8: d01d beq.n 80019f6 80019ba: 687b ldr r3, [r7, #4] 80019bc: 681b ldr r3, [r3, #0] 80019be: 4a1c ldr r2, [pc, #112] ; (8001a30 ) 80019c0: 4293 cmp r3, r2 80019c2: d018 beq.n 80019f6 80019c4: 687b ldr r3, [r7, #4] 80019c6: 681b ldr r3, [r3, #0] 80019c8: 4a1a ldr r2, [pc, #104] ; (8001a34 ) 80019ca: 4293 cmp r3, r2 80019cc: d013 beq.n 80019f6 80019ce: 687b ldr r3, [r7, #4] 80019d0: 681b ldr r3, [r3, #0] 80019d2: 4a19 ldr r2, [pc, #100] ; (8001a38 ) 80019d4: 4293 cmp r3, r2 80019d6: d00e beq.n 80019f6 80019d8: 687b ldr r3, [r7, #4] 80019da: 681b ldr r3, [r3, #0] 80019dc: 4a17 ldr r2, [pc, #92] ; (8001a3c ) 80019de: 4293 cmp r3, r2 80019e0: d009 beq.n 80019f6 80019e2: 687b ldr r3, [r7, #4] 80019e4: 681b ldr r3, [r3, #0] 80019e6: 4a16 ldr r2, [pc, #88] ; (8001a40 ) 80019e8: 4293 cmp r3, r2 80019ea: d004 beq.n 80019f6 80019ec: 687b ldr r3, [r7, #4] 80019ee: 681b ldr r3, [r3, #0] 80019f0: 4a14 ldr r2, [pc, #80] ; (8001a44 ) 80019f2: 4293 cmp r3, r2 80019f4: d128 bne.n 8001a48 80019f6: 687b ldr r3, [r7, #4] 80019f8: 681b ldr r3, [r3, #0] 80019fa: 681a ldr r2, [r3, #0] 80019fc: 687b ldr r3, [r7, #4] 80019fe: 681b ldr r3, [r3, #0] 8001a00: f022 0201 bic.w r2, r2, #1 8001a04: 601a str r2, [r3, #0] 8001a06: e027 b.n 8001a58 8001a08: 40020010 .word 0x40020010 8001a0c: 40020028 .word 0x40020028 8001a10: 40020040 .word 0x40020040 8001a14: 40020058 .word 0x40020058 8001a18: 40020070 .word 0x40020070 8001a1c: 40020088 .word 0x40020088 8001a20: 400200a0 .word 0x400200a0 8001a24: 400200b8 .word 0x400200b8 8001a28: 40020410 .word 0x40020410 8001a2c: 40020428 .word 0x40020428 8001a30: 40020440 .word 0x40020440 8001a34: 40020458 .word 0x40020458 8001a38: 40020470 .word 0x40020470 8001a3c: 40020488 .word 0x40020488 8001a40: 400204a0 .word 0x400204a0 8001a44: 400204b8 .word 0x400204b8 8001a48: 687b ldr r3, [r7, #4] 8001a4a: 681b ldr r3, [r3, #0] 8001a4c: 681a ldr r2, [r3, #0] 8001a4e: 687b ldr r3, [r7, #4] 8001a50: 681b ldr r3, [r3, #0] 8001a52: f022 0201 bic.w r2, r2, #1 8001a56: 601a str r2, [r3, #0] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8001a58: 687b ldr r3, [r7, #4] 8001a5a: 681b ldr r3, [r3, #0] 8001a5c: 4a5c ldr r2, [pc, #368] ; (8001bd0 ) 8001a5e: 4293 cmp r3, r2 8001a60: d072 beq.n 8001b48 8001a62: 687b ldr r3, [r7, #4] 8001a64: 681b ldr r3, [r3, #0] 8001a66: 4a5b ldr r2, [pc, #364] ; (8001bd4 ) 8001a68: 4293 cmp r3, r2 8001a6a: d06d beq.n 8001b48 8001a6c: 687b ldr r3, [r7, #4] 8001a6e: 681b ldr r3, [r3, #0] 8001a70: 4a59 ldr r2, [pc, #356] ; (8001bd8 ) 8001a72: 4293 cmp r3, r2 8001a74: d068 beq.n 8001b48 8001a76: 687b ldr r3, [r7, #4] 8001a78: 681b ldr r3, [r3, #0] 8001a7a: 4a58 ldr r2, [pc, #352] ; (8001bdc ) 8001a7c: 4293 cmp r3, r2 8001a7e: d063 beq.n 8001b48 8001a80: 687b ldr r3, [r7, #4] 8001a82: 681b ldr r3, [r3, #0] 8001a84: 4a56 ldr r2, [pc, #344] ; (8001be0 ) 8001a86: 4293 cmp r3, r2 8001a88: d05e beq.n 8001b48 8001a8a: 687b ldr r3, [r7, #4] 8001a8c: 681b ldr r3, [r3, #0] 8001a8e: 4a55 ldr r2, [pc, #340] ; (8001be4 ) 8001a90: 4293 cmp r3, r2 8001a92: d059 beq.n 8001b48 8001a94: 687b ldr r3, [r7, #4] 8001a96: 681b ldr r3, [r3, #0] 8001a98: 4a53 ldr r2, [pc, #332] ; (8001be8 ) 8001a9a: 4293 cmp r3, r2 8001a9c: d054 beq.n 8001b48 8001a9e: 687b ldr r3, [r7, #4] 8001aa0: 681b ldr r3, [r3, #0] 8001aa2: 4a52 ldr r2, [pc, #328] ; (8001bec ) 8001aa4: 4293 cmp r3, r2 8001aa6: d04f beq.n 8001b48 8001aa8: 687b ldr r3, [r7, #4] 8001aaa: 681b ldr r3, [r3, #0] 8001aac: 4a50 ldr r2, [pc, #320] ; (8001bf0 ) 8001aae: 4293 cmp r3, r2 8001ab0: d04a beq.n 8001b48 8001ab2: 687b ldr r3, [r7, #4] 8001ab4: 681b ldr r3, [r3, #0] 8001ab6: 4a4f ldr r2, [pc, #316] ; (8001bf4 ) 8001ab8: 4293 cmp r3, r2 8001aba: d045 beq.n 8001b48 8001abc: 687b ldr r3, [r7, #4] 8001abe: 681b ldr r3, [r3, #0] 8001ac0: 4a4d ldr r2, [pc, #308] ; (8001bf8 ) 8001ac2: 4293 cmp r3, r2 8001ac4: d040 beq.n 8001b48 8001ac6: 687b ldr r3, [r7, #4] 8001ac8: 681b ldr r3, [r3, #0] 8001aca: 4a4c ldr r2, [pc, #304] ; (8001bfc ) 8001acc: 4293 cmp r3, r2 8001ace: d03b beq.n 8001b48 8001ad0: 687b ldr r3, [r7, #4] 8001ad2: 681b ldr r3, [r3, #0] 8001ad4: 4a4a ldr r2, [pc, #296] ; (8001c00 ) 8001ad6: 4293 cmp r3, r2 8001ad8: d036 beq.n 8001b48 8001ada: 687b ldr r3, [r7, #4] 8001adc: 681b ldr r3, [r3, #0] 8001ade: 4a49 ldr r2, [pc, #292] ; (8001c04 ) 8001ae0: 4293 cmp r3, r2 8001ae2: d031 beq.n 8001b48 8001ae4: 687b ldr r3, [r7, #4] 8001ae6: 681b ldr r3, [r3, #0] 8001ae8: 4a47 ldr r2, [pc, #284] ; (8001c08 ) 8001aea: 4293 cmp r3, r2 8001aec: d02c beq.n 8001b48 8001aee: 687b ldr r3, [r7, #4] 8001af0: 681b ldr r3, [r3, #0] 8001af2: 4a46 ldr r2, [pc, #280] ; (8001c0c ) 8001af4: 4293 cmp r3, r2 8001af6: d027 beq.n 8001b48 8001af8: 687b ldr r3, [r7, #4] 8001afa: 681b ldr r3, [r3, #0] 8001afc: 4a44 ldr r2, [pc, #272] ; (8001c10 ) 8001afe: 4293 cmp r3, r2 8001b00: d022 beq.n 8001b48 8001b02: 687b ldr r3, [r7, #4] 8001b04: 681b ldr r3, [r3, #0] 8001b06: 4a43 ldr r2, [pc, #268] ; (8001c14 ) 8001b08: 4293 cmp r3, r2 8001b0a: d01d beq.n 8001b48 8001b0c: 687b ldr r3, [r7, #4] 8001b0e: 681b ldr r3, [r3, #0] 8001b10: 4a41 ldr r2, [pc, #260] ; (8001c18 ) 8001b12: 4293 cmp r3, r2 8001b14: d018 beq.n 8001b48 8001b16: 687b ldr r3, [r7, #4] 8001b18: 681b ldr r3, [r3, #0] 8001b1a: 4a40 ldr r2, [pc, #256] ; (8001c1c ) 8001b1c: 4293 cmp r3, r2 8001b1e: d013 beq.n 8001b48 8001b20: 687b ldr r3, [r7, #4] 8001b22: 681b ldr r3, [r3, #0] 8001b24: 4a3e ldr r2, [pc, #248] ; (8001c20 ) 8001b26: 4293 cmp r3, r2 8001b28: d00e beq.n 8001b48 8001b2a: 687b ldr r3, [r7, #4] 8001b2c: 681b ldr r3, [r3, #0] 8001b2e: 4a3d ldr r2, [pc, #244] ; (8001c24 ) 8001b30: 4293 cmp r3, r2 8001b32: d009 beq.n 8001b48 8001b34: 687b ldr r3, [r7, #4] 8001b36: 681b ldr r3, [r3, #0] 8001b38: 4a3b ldr r2, [pc, #236] ; (8001c28 ) 8001b3a: 4293 cmp r3, r2 8001b3c: d004 beq.n 8001b48 8001b3e: 687b ldr r3, [r7, #4] 8001b40: 681b ldr r3, [r3, #0] 8001b42: 4a3a ldr r2, [pc, #232] ; (8001c2c ) 8001b44: 4293 cmp r3, r2 8001b46: d101 bne.n 8001b4c 8001b48: 2301 movs r3, #1 8001b4a: e000 b.n 8001b4e 8001b4c: 2300 movs r3, #0 8001b4e: 2b00 cmp r3, #0 8001b50: d028 beq.n 8001ba4 { /* disable the DMAMUX sync overrun IT */ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 8001b52: 687b ldr r3, [r7, #4] 8001b54: 6e1b ldr r3, [r3, #96] ; 0x60 8001b56: 681a ldr r2, [r3, #0] 8001b58: 687b ldr r3, [r7, #4] 8001b5a: 6e1b ldr r3, [r3, #96] ; 0x60 8001b5c: f422 7280 bic.w r2, r2, #256 ; 0x100 8001b60: 601a str r2, [r3, #0] /* Clear all flags */ regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 8001b62: 687b ldr r3, [r7, #4] 8001b64: 6d9b ldr r3, [r3, #88] ; 0x58 8001b66: 60fb str r3, [r7, #12] regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 8001b68: 687b ldr r3, [r7, #4] 8001b6a: 6ddb ldr r3, [r3, #92] ; 0x5c 8001b6c: f003 031f and.w r3, r3, #31 8001b70: 2201 movs r2, #1 8001b72: 409a lsls r2, r3 8001b74: 68fb ldr r3, [r7, #12] 8001b76: 605a str r2, [r3, #4] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8001b78: 687b ldr r3, [r7, #4] 8001b7a: 6e5b ldr r3, [r3, #100] ; 0x64 8001b7c: 687a ldr r2, [r7, #4] 8001b7e: 6e92 ldr r2, [r2, #104] ; 0x68 8001b80: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 8001b82: 687b ldr r3, [r7, #4] 8001b84: 6edb ldr r3, [r3, #108] ; 0x6c 8001b86: 2b00 cmp r3, #0 8001b88: d00c beq.n 8001ba4 { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 8001b8a: 687b ldr r3, [r7, #4] 8001b8c: 6edb ldr r3, [r3, #108] ; 0x6c 8001b8e: 681a ldr r2, [r3, #0] 8001b90: 687b ldr r3, [r7, #4] 8001b92: 6edb ldr r3, [r3, #108] ; 0x6c 8001b94: f422 7280 bic.w r2, r2, #256 ; 0x100 8001b98: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8001b9a: 687b ldr r3, [r7, #4] 8001b9c: 6f1b ldr r3, [r3, #112] ; 0x70 8001b9e: 687a ldr r2, [r7, #4] 8001ba0: 6f52 ldr r2, [r2, #116] ; 0x74 8001ba2: 605a str r2, [r3, #4] } } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8001ba4: 687b ldr r3, [r7, #4] 8001ba6: 2201 movs r2, #1 8001ba8: f883 2035 strb.w r2, [r3, #53] ; 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001bac: 687b ldr r3, [r7, #4] 8001bae: 2200 movs r2, #0 8001bb0: f883 2034 strb.w r2, [r3, #52] ; 0x34 /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 8001bb4: 687b ldr r3, [r7, #4] 8001bb6: 6d1b ldr r3, [r3, #80] ; 0x50 8001bb8: 2b00 cmp r3, #0 8001bba: d003 beq.n 8001bc4 { hdma->XferAbortCallback(hdma); 8001bbc: 687b ldr r3, [r7, #4] 8001bbe: 6d1b ldr r3, [r3, #80] ; 0x50 8001bc0: 6878 ldr r0, [r7, #4] 8001bc2: 4798 blx r3 } } } return HAL_OK; 8001bc4: 2300 movs r3, #0 } 8001bc6: 4618 mov r0, r3 8001bc8: 3710 adds r7, #16 8001bca: 46bd mov sp, r7 8001bcc: bd80 pop {r7, pc} 8001bce: bf00 nop 8001bd0: 40020010 .word 0x40020010 8001bd4: 40020028 .word 0x40020028 8001bd8: 40020040 .word 0x40020040 8001bdc: 40020058 .word 0x40020058 8001be0: 40020070 .word 0x40020070 8001be4: 40020088 .word 0x40020088 8001be8: 400200a0 .word 0x400200a0 8001bec: 400200b8 .word 0x400200b8 8001bf0: 40020410 .word 0x40020410 8001bf4: 40020428 .word 0x40020428 8001bf8: 40020440 .word 0x40020440 8001bfc: 40020458 .word 0x40020458 8001c00: 40020470 .word 0x40020470 8001c04: 40020488 .word 0x40020488 8001c08: 400204a0 .word 0x400204a0 8001c0c: 400204b8 .word 0x400204b8 8001c10: 58025408 .word 0x58025408 8001c14: 5802541c .word 0x5802541c 8001c18: 58025430 .word 0x58025430 8001c1c: 58025444 .word 0x58025444 8001c20: 58025458 .word 0x58025458 8001c24: 5802546c .word 0x5802546c 8001c28: 58025480 .word 0x58025480 8001c2c: 58025494 .word 0x58025494 08001c30 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8001c30: b480 push {r7} 8001c32: b089 sub sp, #36 ; 0x24 8001c34: af00 add r7, sp, #0 8001c36: 6078 str r0, [r7, #4] 8001c38: 6039 str r1, [r7, #0] uint32_t position = 0x00U; 8001c3a: 2300 movs r3, #0 8001c3c: 61fb str r3, [r7, #28] EXTI_Core_TypeDef *EXTI_CurrentCPU; #if defined(DUAL_CORE) && defined(CORE_CM4) EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */ #else EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */ 8001c3e: 4b89 ldr r3, [pc, #548] ; (8001e64 ) 8001c40: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00U) 8001c42: e194 b.n 8001f6e { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1UL << position); 8001c44: 683b ldr r3, [r7, #0] 8001c46: 681a ldr r2, [r3, #0] 8001c48: 2101 movs r1, #1 8001c4a: 69fb ldr r3, [r7, #28] 8001c4c: fa01 f303 lsl.w r3, r1, r3 8001c50: 4013 ands r3, r2 8001c52: 613b str r3, [r7, #16] if (iocurrent != 0x00U) 8001c54: 693b ldr r3, [r7, #16] 8001c56: 2b00 cmp r3, #0 8001c58: f000 8186 beq.w 8001f68 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 8001c5c: 683b ldr r3, [r7, #0] 8001c5e: 685b ldr r3, [r3, #4] 8001c60: f003 0303 and.w r3, r3, #3 8001c64: 2b01 cmp r3, #1 8001c66: d005 beq.n 8001c74 8001c68: 683b ldr r3, [r7, #0] 8001c6a: 685b ldr r3, [r3, #4] 8001c6c: f003 0303 and.w r3, r3, #3 8001c70: 2b02 cmp r3, #2 8001c72: d130 bne.n 8001cd6 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8001c74: 687b ldr r3, [r7, #4] 8001c76: 689b ldr r3, [r3, #8] 8001c78: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 8001c7a: 69fb ldr r3, [r7, #28] 8001c7c: 005b lsls r3, r3, #1 8001c7e: 2203 movs r2, #3 8001c80: fa02 f303 lsl.w r3, r2, r3 8001c84: 43db mvns r3, r3 8001c86: 69ba ldr r2, [r7, #24] 8001c88: 4013 ands r3, r2 8001c8a: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 8001c8c: 683b ldr r3, [r7, #0] 8001c8e: 68da ldr r2, [r3, #12] 8001c90: 69fb ldr r3, [r7, #28] 8001c92: 005b lsls r3, r3, #1 8001c94: fa02 f303 lsl.w r3, r2, r3 8001c98: 69ba ldr r2, [r7, #24] 8001c9a: 4313 orrs r3, r2 8001c9c: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 8001c9e: 687b ldr r3, [r7, #4] 8001ca0: 69ba ldr r2, [r7, #24] 8001ca2: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8001ca4: 687b ldr r3, [r7, #4] 8001ca6: 685b ldr r3, [r3, #4] 8001ca8: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT0 << position) ; 8001caa: 2201 movs r2, #1 8001cac: 69fb ldr r3, [r7, #28] 8001cae: fa02 f303 lsl.w r3, r2, r3 8001cb2: 43db mvns r3, r3 8001cb4: 69ba ldr r2, [r7, #24] 8001cb6: 4013 ands r3, r2 8001cb8: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8001cba: 683b ldr r3, [r7, #0] 8001cbc: 685b ldr r3, [r3, #4] 8001cbe: 091b lsrs r3, r3, #4 8001cc0: f003 0201 and.w r2, r3, #1 8001cc4: 69fb ldr r3, [r7, #28] 8001cc6: fa02 f303 lsl.w r3, r2, r3 8001cca: 69ba ldr r2, [r7, #24] 8001ccc: 4313 orrs r3, r2 8001cce: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 8001cd0: 687b ldr r3, [r7, #4] 8001cd2: 69ba ldr r2, [r7, #24] 8001cd4: 605a str r2, [r3, #4] } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8001cd6: 683b ldr r3, [r7, #0] 8001cd8: 685b ldr r3, [r3, #4] 8001cda: f003 0303 and.w r3, r3, #3 8001cde: 2b03 cmp r3, #3 8001ce0: d017 beq.n 8001d12 { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8001ce2: 687b ldr r3, [r7, #4] 8001ce4: 68db ldr r3, [r3, #12] 8001ce6: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 8001ce8: 69fb ldr r3, [r7, #28] 8001cea: 005b lsls r3, r3, #1 8001cec: 2203 movs r2, #3 8001cee: fa02 f303 lsl.w r3, r2, r3 8001cf2: 43db mvns r3, r3 8001cf4: 69ba ldr r2, [r7, #24] 8001cf6: 4013 ands r3, r2 8001cf8: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 8001cfa: 683b ldr r3, [r7, #0] 8001cfc: 689a ldr r2, [r3, #8] 8001cfe: 69fb ldr r3, [r7, #28] 8001d00: 005b lsls r3, r3, #1 8001d02: fa02 f303 lsl.w r3, r2, r3 8001d06: 69ba ldr r2, [r7, #24] 8001d08: 4313 orrs r3, r2 8001d0a: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 8001d0c: 687b ldr r3, [r7, #4] 8001d0e: 69ba ldr r2, [r7, #24] 8001d10: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8001d12: 683b ldr r3, [r7, #0] 8001d14: 685b ldr r3, [r3, #4] 8001d16: f003 0303 and.w r3, r3, #3 8001d1a: 2b02 cmp r3, #2 8001d1c: d123 bne.n 8001d66 /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 8001d1e: 69fb ldr r3, [r7, #28] 8001d20: 08da lsrs r2, r3, #3 8001d22: 687b ldr r3, [r7, #4] 8001d24: 3208 adds r2, #8 8001d26: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8001d2a: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((position & 0x07U) * 4U)); 8001d2c: 69fb ldr r3, [r7, #28] 8001d2e: f003 0307 and.w r3, r3, #7 8001d32: 009b lsls r3, r3, #2 8001d34: 220f movs r2, #15 8001d36: fa02 f303 lsl.w r3, r2, r3 8001d3a: 43db mvns r3, r3 8001d3c: 69ba ldr r2, [r7, #24] 8001d3e: 4013 ands r3, r2 8001d40: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 8001d42: 683b ldr r3, [r7, #0] 8001d44: 691a ldr r2, [r3, #16] 8001d46: 69fb ldr r3, [r7, #28] 8001d48: f003 0307 and.w r3, r3, #7 8001d4c: 009b lsls r3, r3, #2 8001d4e: fa02 f303 lsl.w r3, r2, r3 8001d52: 69ba ldr r2, [r7, #24] 8001d54: 4313 orrs r3, r2 8001d56: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 8001d58: 69fb ldr r3, [r7, #28] 8001d5a: 08da lsrs r2, r3, #3 8001d5c: 687b ldr r3, [r7, #4] 8001d5e: 3208 adds r2, #8 8001d60: 69b9 ldr r1, [r7, #24] 8001d62: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8001d66: 687b ldr r3, [r7, #4] 8001d68: 681b ldr r3, [r3, #0] 8001d6a: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); 8001d6c: 69fb ldr r3, [r7, #28] 8001d6e: 005b lsls r3, r3, #1 8001d70: 2203 movs r2, #3 8001d72: fa02 f303 lsl.w r3, r2, r3 8001d76: 43db mvns r3, r3 8001d78: 69ba ldr r2, [r7, #24] 8001d7a: 4013 ands r3, r2 8001d7c: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 8001d7e: 683b ldr r3, [r7, #0] 8001d80: 685b ldr r3, [r3, #4] 8001d82: f003 0203 and.w r2, r3, #3 8001d86: 69fb ldr r3, [r7, #28] 8001d88: 005b lsls r3, r3, #1 8001d8a: fa02 f303 lsl.w r3, r2, r3 8001d8e: 69ba ldr r2, [r7, #24] 8001d90: 4313 orrs r3, r2 8001d92: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 8001d94: 687b ldr r3, [r7, #4] 8001d96: 69ba ldr r2, [r7, #24] 8001d98: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 8001d9a: 683b ldr r3, [r7, #0] 8001d9c: 685b ldr r3, [r3, #4] 8001d9e: f403 3340 and.w r3, r3, #196608 ; 0x30000 8001da2: 2b00 cmp r3, #0 8001da4: f000 80e0 beq.w 8001f68 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8001da8: 4b2f ldr r3, [pc, #188] ; (8001e68 ) 8001daa: f8d3 3154 ldr.w r3, [r3, #340] ; 0x154 8001dae: 4a2e ldr r2, [pc, #184] ; (8001e68 ) 8001db0: f043 0302 orr.w r3, r3, #2 8001db4: f8c2 3154 str.w r3, [r2, #340] ; 0x154 8001db8: 4b2b ldr r3, [pc, #172] ; (8001e68 ) 8001dba: f8d3 3154 ldr.w r3, [r3, #340] ; 0x154 8001dbe: f003 0302 and.w r3, r3, #2 8001dc2: 60fb str r3, [r7, #12] 8001dc4: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 8001dc6: 4a29 ldr r2, [pc, #164] ; (8001e6c ) 8001dc8: 69fb ldr r3, [r7, #28] 8001dca: 089b lsrs r3, r3, #2 8001dcc: 3302 adds r3, #2 8001dce: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8001dd2: 61bb str r3, [r7, #24] temp &= ~(0x0FUL << (4U * (position & 0x03U))); 8001dd4: 69fb ldr r3, [r7, #28] 8001dd6: f003 0303 and.w r3, r3, #3 8001dda: 009b lsls r3, r3, #2 8001ddc: 220f movs r2, #15 8001dde: fa02 f303 lsl.w r3, r2, r3 8001de2: 43db mvns r3, r3 8001de4: 69ba ldr r2, [r7, #24] 8001de6: 4013 ands r3, r2 8001de8: 61bb str r3, [r7, #24] temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 8001dea: 687b ldr r3, [r7, #4] 8001dec: 4a20 ldr r2, [pc, #128] ; (8001e70 ) 8001dee: 4293 cmp r3, r2 8001df0: d052 beq.n 8001e98 8001df2: 687b ldr r3, [r7, #4] 8001df4: 4a1f ldr r2, [pc, #124] ; (8001e74 ) 8001df6: 4293 cmp r3, r2 8001df8: d031 beq.n 8001e5e 8001dfa: 687b ldr r3, [r7, #4] 8001dfc: 4a1e ldr r2, [pc, #120] ; (8001e78 ) 8001dfe: 4293 cmp r3, r2 8001e00: d02b beq.n 8001e5a 8001e02: 687b ldr r3, [r7, #4] 8001e04: 4a1d ldr r2, [pc, #116] ; (8001e7c ) 8001e06: 4293 cmp r3, r2 8001e08: d025 beq.n 8001e56 8001e0a: 687b ldr r3, [r7, #4] 8001e0c: 4a1c ldr r2, [pc, #112] ; (8001e80 ) 8001e0e: 4293 cmp r3, r2 8001e10: d01f beq.n 8001e52 8001e12: 687b ldr r3, [r7, #4] 8001e14: 4a1b ldr r2, [pc, #108] ; (8001e84 ) 8001e16: 4293 cmp r3, r2 8001e18: d019 beq.n 8001e4e 8001e1a: 687b ldr r3, [r7, #4] 8001e1c: 4a1a ldr r2, [pc, #104] ; (8001e88 ) 8001e1e: 4293 cmp r3, r2 8001e20: d013 beq.n 8001e4a 8001e22: 687b ldr r3, [r7, #4] 8001e24: 4a19 ldr r2, [pc, #100] ; (8001e8c ) 8001e26: 4293 cmp r3, r2 8001e28: d00d beq.n 8001e46 8001e2a: 687b ldr r3, [r7, #4] 8001e2c: 4a18 ldr r2, [pc, #96] ; (8001e90 ) 8001e2e: 4293 cmp r3, r2 8001e30: d007 beq.n 8001e42 8001e32: 687b ldr r3, [r7, #4] 8001e34: 4a17 ldr r2, [pc, #92] ; (8001e94 ) 8001e36: 4293 cmp r3, r2 8001e38: d101 bne.n 8001e3e 8001e3a: 2309 movs r3, #9 8001e3c: e02d b.n 8001e9a 8001e3e: 230a movs r3, #10 8001e40: e02b b.n 8001e9a 8001e42: 2308 movs r3, #8 8001e44: e029 b.n 8001e9a 8001e46: 2307 movs r3, #7 8001e48: e027 b.n 8001e9a 8001e4a: 2306 movs r3, #6 8001e4c: e025 b.n 8001e9a 8001e4e: 2305 movs r3, #5 8001e50: e023 b.n 8001e9a 8001e52: 2304 movs r3, #4 8001e54: e021 b.n 8001e9a 8001e56: 2303 movs r3, #3 8001e58: e01f b.n 8001e9a 8001e5a: 2302 movs r3, #2 8001e5c: e01d b.n 8001e9a 8001e5e: 2301 movs r3, #1 8001e60: e01b b.n 8001e9a 8001e62: bf00 nop 8001e64: 58000080 .word 0x58000080 8001e68: 58024400 .word 0x58024400 8001e6c: 58000400 .word 0x58000400 8001e70: 58020000 .word 0x58020000 8001e74: 58020400 .word 0x58020400 8001e78: 58020800 .word 0x58020800 8001e7c: 58020c00 .word 0x58020c00 8001e80: 58021000 .word 0x58021000 8001e84: 58021400 .word 0x58021400 8001e88: 58021800 .word 0x58021800 8001e8c: 58021c00 .word 0x58021c00 8001e90: 58022000 .word 0x58022000 8001e94: 58022400 .word 0x58022400 8001e98: 2300 movs r3, #0 8001e9a: 69fa ldr r2, [r7, #28] 8001e9c: f002 0203 and.w r2, r2, #3 8001ea0: 0092 lsls r2, r2, #2 8001ea2: 4093 lsls r3, r2 8001ea4: 69ba ldr r2, [r7, #24] 8001ea6: 4313 orrs r3, r2 8001ea8: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 8001eaa: 4938 ldr r1, [pc, #224] ; (8001f8c ) 8001eac: 69fb ldr r3, [r7, #28] 8001eae: 089b lsrs r3, r3, #2 8001eb0: 3302 adds r3, #2 8001eb2: 69ba ldr r2, [r7, #24] 8001eb4: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 8001eb8: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 8001ebc: 681b ldr r3, [r3, #0] 8001ebe: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8001ec0: 693b ldr r3, [r7, #16] 8001ec2: 43db mvns r3, r3 8001ec4: 69ba ldr r2, [r7, #24] 8001ec6: 4013 ands r3, r2 8001ec8: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 8001eca: 683b ldr r3, [r7, #0] 8001ecc: 685b ldr r3, [r3, #4] 8001ece: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8001ed2: 2b00 cmp r3, #0 8001ed4: d003 beq.n 8001ede { temp |= iocurrent; 8001ed6: 69ba ldr r2, [r7, #24] 8001ed8: 693b ldr r3, [r7, #16] 8001eda: 4313 orrs r3, r2 8001edc: 61bb str r3, [r7, #24] } EXTI->RTSR1 = temp; 8001ede: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 8001ee2: 69bb ldr r3, [r7, #24] 8001ee4: 6013 str r3, [r2, #0] temp = EXTI->FTSR1; 8001ee6: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 8001eea: 685b ldr r3, [r3, #4] 8001eec: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8001eee: 693b ldr r3, [r7, #16] 8001ef0: 43db mvns r3, r3 8001ef2: 69ba ldr r2, [r7, #24] 8001ef4: 4013 ands r3, r2 8001ef6: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 8001ef8: 683b ldr r3, [r7, #0] 8001efa: 685b ldr r3, [r3, #4] 8001efc: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8001f00: 2b00 cmp r3, #0 8001f02: d003 beq.n 8001f0c { temp |= iocurrent; 8001f04: 69ba ldr r2, [r7, #24] 8001f06: 693b ldr r3, [r7, #16] 8001f08: 4313 orrs r3, r2 8001f0a: 61bb str r3, [r7, #24] } EXTI->FTSR1 = temp; 8001f0c: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 8001f10: 69bb ldr r3, [r7, #24] 8001f12: 6053 str r3, [r2, #4] temp = EXTI_CurrentCPU->EMR1; 8001f14: 697b ldr r3, [r7, #20] 8001f16: 685b ldr r3, [r3, #4] 8001f18: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8001f1a: 693b ldr r3, [r7, #16] 8001f1c: 43db mvns r3, r3 8001f1e: 69ba ldr r2, [r7, #24] 8001f20: 4013 ands r3, r2 8001f22: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 8001f24: 683b ldr r3, [r7, #0] 8001f26: 685b ldr r3, [r3, #4] 8001f28: f403 3300 and.w r3, r3, #131072 ; 0x20000 8001f2c: 2b00 cmp r3, #0 8001f2e: d003 beq.n 8001f38 { temp |= iocurrent; 8001f30: 69ba ldr r2, [r7, #24] 8001f32: 693b ldr r3, [r7, #16] 8001f34: 4313 orrs r3, r2 8001f36: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->EMR1 = temp; 8001f38: 697b ldr r3, [r7, #20] 8001f3a: 69ba ldr r2, [r7, #24] 8001f3c: 605a str r2, [r3, #4] /* Clear EXTI line configuration */ temp = EXTI_CurrentCPU->IMR1; 8001f3e: 697b ldr r3, [r7, #20] 8001f40: 681b ldr r3, [r3, #0] 8001f42: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8001f44: 693b ldr r3, [r7, #16] 8001f46: 43db mvns r3, r3 8001f48: 69ba ldr r2, [r7, #24] 8001f4a: 4013 ands r3, r2 8001f4c: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) 8001f4e: 683b ldr r3, [r7, #0] 8001f50: 685b ldr r3, [r3, #4] 8001f52: f403 3380 and.w r3, r3, #65536 ; 0x10000 8001f56: 2b00 cmp r3, #0 8001f58: d003 beq.n 8001f62 { temp |= iocurrent; 8001f5a: 69ba ldr r2, [r7, #24] 8001f5c: 693b ldr r3, [r7, #16] 8001f5e: 4313 orrs r3, r2 8001f60: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->IMR1 = temp; 8001f62: 697b ldr r3, [r7, #20] 8001f64: 69ba ldr r2, [r7, #24] 8001f66: 601a str r2, [r3, #0] } } position++; 8001f68: 69fb ldr r3, [r7, #28] 8001f6a: 3301 adds r3, #1 8001f6c: 61fb str r3, [r7, #28] while (((GPIO_Init->Pin) >> position) != 0x00U) 8001f6e: 683b ldr r3, [r7, #0] 8001f70: 681a ldr r2, [r3, #0] 8001f72: 69fb ldr r3, [r7, #28] 8001f74: fa22 f303 lsr.w r3, r2, r3 8001f78: 2b00 cmp r3, #0 8001f7a: f47f ae63 bne.w 8001c44 } } 8001f7e: bf00 nop 8001f80: bf00 nop 8001f82: 3724 adds r7, #36 ; 0x24 8001f84: 46bd mov sp, r7 8001f86: f85d 7b04 ldr.w r7, [sp], #4 8001f8a: 4770 bx lr 8001f8c: 58000400 .word 0x58000400 08001f90 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8001f90: b480 push {r7} 8001f92: b083 sub sp, #12 8001f94: af00 add r7, sp, #0 8001f96: 6078 str r0, [r7, #4] 8001f98: 460b mov r3, r1 8001f9a: 807b strh r3, [r7, #2] 8001f9c: 4613 mov r3, r2 8001f9e: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8001fa0: 787b ldrb r3, [r7, #1] 8001fa2: 2b00 cmp r3, #0 8001fa4: d003 beq.n 8001fae { GPIOx->BSRR = GPIO_Pin; 8001fa6: 887a ldrh r2, [r7, #2] 8001fa8: 687b ldr r3, [r7, #4] 8001faa: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; } } 8001fac: e003 b.n 8001fb6 GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; 8001fae: 887b ldrh r3, [r7, #2] 8001fb0: 041a lsls r2, r3, #16 8001fb2: 687b ldr r3, [r7, #4] 8001fb4: 619a str r2, [r3, #24] } 8001fb6: bf00 nop 8001fb8: 370c adds r7, #12 8001fba: 46bd mov sp, r7 8001fbc: f85d 7b04 ldr.w r7, [sp], #4 8001fc0: 4770 bx lr ... 08001fc4 : * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS * regulator. * @retval HAL status. */ HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource) { 8001fc4: b580 push {r7, lr} 8001fc6: b084 sub sp, #16 8001fc8: af00 add r7, sp, #0 8001fca: 6078 str r0, [r7, #4] /* Check if supply source was configured */ #if defined (PWR_FLAG_SCUEN) if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U) #else if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) 8001fcc: 4b29 ldr r3, [pc, #164] ; (8002074 ) 8001fce: 68db ldr r3, [r3, #12] 8001fd0: f003 0307 and.w r3, r3, #7 8001fd4: 2b06 cmp r3, #6 8001fd6: d00a beq.n 8001fee #endif /* defined (PWR_FLAG_SCUEN) */ { /* Check supply configuration */ if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) 8001fd8: 4b26 ldr r3, [pc, #152] ; (8002074 ) 8001fda: 68db ldr r3, [r3, #12] 8001fdc: f003 033f and.w r3, r3, #63 ; 0x3f 8001fe0: 687a ldr r2, [r7, #4] 8001fe2: 429a cmp r2, r3 8001fe4: d001 beq.n 8001fea { /* Supply configuration update locked, can't apply a new supply config */ return HAL_ERROR; 8001fe6: 2301 movs r3, #1 8001fe8: e040 b.n 800206c else { /* Supply configuration update locked, but new supply configuration matches with old supply configuration : nothing to do */ return HAL_OK; 8001fea: 2300 movs r3, #0 8001fec: e03e b.n 800206c } } /* Set the power supply configuration */ MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource); 8001fee: 4b21 ldr r3, [pc, #132] ; (8002074 ) 8001ff0: 68db ldr r3, [r3, #12] 8001ff2: f023 023f bic.w r2, r3, #63 ; 0x3f 8001ff6: 491f ldr r1, [pc, #124] ; (8002074 ) 8001ff8: 687b ldr r3, [r7, #4] 8001ffa: 4313 orrs r3, r2 8001ffc: 60cb str r3, [r1, #12] /* Get tick */ tickstart = HAL_GetTick (); 8001ffe: f7fe ff75 bl 8000eec 8002002: 60f8 str r0, [r7, #12] /* Wait till voltage level flag is set */ while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 8002004: e009 b.n 800201a { if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) 8002006: f7fe ff71 bl 8000eec 800200a: 4602 mov r2, r0 800200c: 68fb ldr r3, [r7, #12] 800200e: 1ad3 subs r3, r2, r3 8002010: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 8002014: d901 bls.n 800201a { return HAL_ERROR; 8002016: 2301 movs r3, #1 8002018: e028 b.n 800206c while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 800201a: 4b16 ldr r3, [pc, #88] ; (8002074 ) 800201c: 685b ldr r3, [r3, #4] 800201e: f403 5300 and.w r3, r3, #8192 ; 0x2000 8002022: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 8002026: d1ee bne.n 8002006 } } #if defined (SMPS) /* When the SMPS supplies external circuits verify that SDEXTRDY flag is set */ if ((SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) || 8002028: 687b ldr r3, [r7, #4] 800202a: 2b1e cmp r3, #30 800202c: d008 beq.n 8002040 800202e: 687b ldr r3, [r7, #4] 8002030: 2b2e cmp r3, #46 ; 0x2e 8002032: d005 beq.n 8002040 (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) || 8002034: 687b ldr r3, [r7, #4] 8002036: 2b1d cmp r3, #29 8002038: d002 beq.n 8002040 (SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT) || 800203a: 687b ldr r3, [r7, #4] 800203c: 2b2d cmp r3, #45 ; 0x2d 800203e: d114 bne.n 800206a (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT)) { /* Get the current tick number */ tickstart = HAL_GetTick (); 8002040: f7fe ff54 bl 8000eec 8002044: 60f8 str r0, [r7, #12] /* Wait till SMPS external supply ready flag is set */ while (__HAL_PWR_GET_FLAG (PWR_FLAG_SMPSEXTRDY) == 0U) 8002046: e009 b.n 800205c { if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) 8002048: f7fe ff50 bl 8000eec 800204c: 4602 mov r2, r0 800204e: 68fb ldr r3, [r7, #12] 8002050: 1ad3 subs r3, r2, r3 8002052: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 8002056: d901 bls.n 800205c { return HAL_ERROR; 8002058: 2301 movs r3, #1 800205a: e007 b.n 800206c while (__HAL_PWR_GET_FLAG (PWR_FLAG_SMPSEXTRDY) == 0U) 800205c: 4b05 ldr r3, [pc, #20] ; (8002074 ) 800205e: 68db ldr r3, [r3, #12] 8002060: f403 3380 and.w r3, r3, #65536 ; 0x10000 8002064: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8002068: d1ee bne.n 8002048 } } } #endif /* defined (SMPS) */ return HAL_OK; 800206a: 2300 movs r3, #0 } 800206c: 4618 mov r0, r3 800206e: 3710 adds r7, #16 8002070: 46bd mov sp, r7 8002072: bd80 pop {r7, pc} 8002074: 58024800 .word 0x58024800 08002078 : * supported by this function. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8002078: b580 push {r7, lr} 800207a: b08c sub sp, #48 ; 0x30 800207c: af00 add r7, sp, #0 800207e: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t temp1_pllckcfg, temp2_pllckcfg; /* Check Null pointer */ if(RCC_OscInitStruct == NULL) 8002080: 687b ldr r3, [r7, #4] 8002082: 2b00 cmp r3, #0 8002084: d101 bne.n 800208a { return HAL_ERROR; 8002086: 2301 movs r3, #1 8002088: e3f3 b.n 8002872 } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800208a: 687b ldr r3, [r7, #4] 800208c: 681b ldr r3, [r3, #0] 800208e: f003 0301 and.w r3, r3, #1 8002092: 2b00 cmp r3, #0 8002094: f000 80b3 beq.w 80021fe { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8002098: 4b9e ldr r3, [pc, #632] ; (8002314 ) 800209a: 691b ldr r3, [r3, #16] 800209c: f003 0338 and.w r3, r3, #56 ; 0x38 80020a0: 62fb str r3, [r7, #44] ; 0x2c const uint32_t temp_pllckselr = RCC->PLLCKSELR; 80020a2: 4b9c ldr r3, [pc, #624] ; (8002314 ) 80020a4: 6a9b ldr r3, [r3, #40] ; 0x28 80020a6: 62bb str r3, [r7, #40] ; 0x28 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ if((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE))) 80020a8: 6afb ldr r3, [r7, #44] ; 0x2c 80020aa: 2b10 cmp r3, #16 80020ac: d007 beq.n 80020be 80020ae: 6afb ldr r3, [r7, #44] ; 0x2c 80020b0: 2b18 cmp r3, #24 80020b2: d112 bne.n 80020da 80020b4: 6abb ldr r3, [r7, #40] ; 0x28 80020b6: f003 0303 and.w r3, r3, #3 80020ba: 2b02 cmp r3, #2 80020bc: d10d bne.n 80020da { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80020be: 4b95 ldr r3, [pc, #596] ; (8002314 ) 80020c0: 681b ldr r3, [r3, #0] 80020c2: f403 3300 and.w r3, r3, #131072 ; 0x20000 80020c6: 2b00 cmp r3, #0 80020c8: f000 8098 beq.w 80021fc 80020cc: 687b ldr r3, [r7, #4] 80020ce: 685b ldr r3, [r3, #4] 80020d0: 2b00 cmp r3, #0 80020d2: f040 8093 bne.w 80021fc { return HAL_ERROR; 80020d6: 2301 movs r3, #1 80020d8: e3cb b.n 8002872 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80020da: 687b ldr r3, [r7, #4] 80020dc: 685b ldr r3, [r3, #4] 80020de: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80020e2: d106 bne.n 80020f2 80020e4: 4b8b ldr r3, [pc, #556] ; (8002314 ) 80020e6: 681b ldr r3, [r3, #0] 80020e8: 4a8a ldr r2, [pc, #552] ; (8002314 ) 80020ea: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80020ee: 6013 str r3, [r2, #0] 80020f0: e058 b.n 80021a4 80020f2: 687b ldr r3, [r7, #4] 80020f4: 685b ldr r3, [r3, #4] 80020f6: 2b00 cmp r3, #0 80020f8: d112 bne.n 8002120 80020fa: 4b86 ldr r3, [pc, #536] ; (8002314 ) 80020fc: 681b ldr r3, [r3, #0] 80020fe: 4a85 ldr r2, [pc, #532] ; (8002314 ) 8002100: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8002104: 6013 str r3, [r2, #0] 8002106: 4b83 ldr r3, [pc, #524] ; (8002314 ) 8002108: 681b ldr r3, [r3, #0] 800210a: 4a82 ldr r2, [pc, #520] ; (8002314 ) 800210c: f423 1380 bic.w r3, r3, #1048576 ; 0x100000 8002110: 6013 str r3, [r2, #0] 8002112: 4b80 ldr r3, [pc, #512] ; (8002314 ) 8002114: 681b ldr r3, [r3, #0] 8002116: 4a7f ldr r2, [pc, #508] ; (8002314 ) 8002118: f423 2380 bic.w r3, r3, #262144 ; 0x40000 800211c: 6013 str r3, [r2, #0] 800211e: e041 b.n 80021a4 8002120: 687b ldr r3, [r7, #4] 8002122: 685b ldr r3, [r3, #4] 8002124: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8002128: d112 bne.n 8002150 800212a: 4b7a ldr r3, [pc, #488] ; (8002314 ) 800212c: 681b ldr r3, [r3, #0] 800212e: 4a79 ldr r2, [pc, #484] ; (8002314 ) 8002130: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8002134: 6013 str r3, [r2, #0] 8002136: 4b77 ldr r3, [pc, #476] ; (8002314 ) 8002138: 681b ldr r3, [r3, #0] 800213a: 4a76 ldr r2, [pc, #472] ; (8002314 ) 800213c: f423 1380 bic.w r3, r3, #1048576 ; 0x100000 8002140: 6013 str r3, [r2, #0] 8002142: 4b74 ldr r3, [pc, #464] ; (8002314 ) 8002144: 681b ldr r3, [r3, #0] 8002146: 4a73 ldr r2, [pc, #460] ; (8002314 ) 8002148: f443 3380 orr.w r3, r3, #65536 ; 0x10000 800214c: 6013 str r3, [r2, #0] 800214e: e029 b.n 80021a4 8002150: 687b ldr r3, [r7, #4] 8002152: 685b ldr r3, [r3, #4] 8002154: f5b3 1fa8 cmp.w r3, #1376256 ; 0x150000 8002158: d112 bne.n 8002180 800215a: 4b6e ldr r3, [pc, #440] ; (8002314 ) 800215c: 681b ldr r3, [r3, #0] 800215e: 4a6d ldr r2, [pc, #436] ; (8002314 ) 8002160: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8002164: 6013 str r3, [r2, #0] 8002166: 4b6b ldr r3, [pc, #428] ; (8002314 ) 8002168: 681b ldr r3, [r3, #0] 800216a: 4a6a ldr r2, [pc, #424] ; (8002314 ) 800216c: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 8002170: 6013 str r3, [r2, #0] 8002172: 4b68 ldr r3, [pc, #416] ; (8002314 ) 8002174: 681b ldr r3, [r3, #0] 8002176: 4a67 ldr r2, [pc, #412] ; (8002314 ) 8002178: f443 3380 orr.w r3, r3, #65536 ; 0x10000 800217c: 6013 str r3, [r2, #0] 800217e: e011 b.n 80021a4 8002180: 4b64 ldr r3, [pc, #400] ; (8002314 ) 8002182: 681b ldr r3, [r3, #0] 8002184: 4a63 ldr r2, [pc, #396] ; (8002314 ) 8002186: f423 3380 bic.w r3, r3, #65536 ; 0x10000 800218a: 6013 str r3, [r2, #0] 800218c: 4b61 ldr r3, [pc, #388] ; (8002314 ) 800218e: 681b ldr r3, [r3, #0] 8002190: 4a60 ldr r2, [pc, #384] ; (8002314 ) 8002192: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8002196: 6013 str r3, [r2, #0] 8002198: 4b5e ldr r3, [pc, #376] ; (8002314 ) 800219a: 681b ldr r3, [r3, #0] 800219c: 4a5d ldr r2, [pc, #372] ; (8002314 ) 800219e: f423 1380 bic.w r3, r3, #1048576 ; 0x100000 80021a2: 6013 str r3, [r2, #0] /* Check the HSE State */ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 80021a4: 687b ldr r3, [r7, #4] 80021a6: 685b ldr r3, [r3, #4] 80021a8: 2b00 cmp r3, #0 80021aa: d013 beq.n 80021d4 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80021ac: f7fe fe9e bl 8000eec 80021b0: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 80021b2: e008 b.n 80021c6 { if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 80021b4: f7fe fe9a bl 8000eec 80021b8: 4602 mov r2, r0 80021ba: 6a7b ldr r3, [r7, #36] ; 0x24 80021bc: 1ad3 subs r3, r2, r3 80021be: 2b64 cmp r3, #100 ; 0x64 80021c0: d901 bls.n 80021c6 { return HAL_TIMEOUT; 80021c2: 2303 movs r3, #3 80021c4: e355 b.n 8002872 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 80021c6: 4b53 ldr r3, [pc, #332] ; (8002314 ) 80021c8: 681b ldr r3, [r3, #0] 80021ca: f403 3300 and.w r3, r3, #131072 ; 0x20000 80021ce: 2b00 cmp r3, #0 80021d0: d0f0 beq.n 80021b4 80021d2: e014 b.n 80021fe } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80021d4: f7fe fe8a bl 8000eec 80021d8: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 80021da: e008 b.n 80021ee { if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 80021dc: f7fe fe86 bl 8000eec 80021e0: 4602 mov r2, r0 80021e2: 6a7b ldr r3, [r7, #36] ; 0x24 80021e4: 1ad3 subs r3, r2, r3 80021e6: 2b64 cmp r3, #100 ; 0x64 80021e8: d901 bls.n 80021ee { return HAL_TIMEOUT; 80021ea: 2303 movs r3, #3 80021ec: e341 b.n 8002872 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 80021ee: 4b49 ldr r3, [pc, #292] ; (8002314 ) 80021f0: 681b ldr r3, [r3, #0] 80021f2: f403 3300 and.w r3, r3, #131072 ; 0x20000 80021f6: 2b00 cmp r3, #0 80021f8: d1f0 bne.n 80021dc 80021fa: e000 b.n 80021fe if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80021fc: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 80021fe: 687b ldr r3, [r7, #4] 8002200: 681b ldr r3, [r3, #0] 8002202: f003 0302 and.w r3, r3, #2 8002206: 2b00 cmp r3, #0 8002208: f000 808c beq.w 8002324 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* When the HSI is used as system clock it will not be disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800220c: 4b41 ldr r3, [pc, #260] ; (8002314 ) 800220e: 691b ldr r3, [r3, #16] 8002210: f003 0338 and.w r3, r3, #56 ; 0x38 8002214: 623b str r3, [r7, #32] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 8002216: 4b3f ldr r3, [pc, #252] ; (8002314 ) 8002218: 6a9b ldr r3, [r3, #40] ; 0x28 800221a: 61fb str r3, [r7, #28] if((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI))) 800221c: 6a3b ldr r3, [r7, #32] 800221e: 2b00 cmp r3, #0 8002220: d007 beq.n 8002232 8002222: 6a3b ldr r3, [r7, #32] 8002224: 2b18 cmp r3, #24 8002226: d137 bne.n 8002298 8002228: 69fb ldr r3, [r7, #28] 800222a: f003 0303 and.w r3, r3, #3 800222e: 2b00 cmp r3, #0 8002230: d132 bne.n 8002298 { /* When HSI is used as system clock it will not be disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 8002232: 4b38 ldr r3, [pc, #224] ; (8002314 ) 8002234: 681b ldr r3, [r3, #0] 8002236: f003 0304 and.w r3, r3, #4 800223a: 2b00 cmp r3, #0 800223c: d005 beq.n 800224a 800223e: 687b ldr r3, [r7, #4] 8002240: 68db ldr r3, [r3, #12] 8002242: 2b00 cmp r3, #0 8002244: d101 bne.n 800224a { return HAL_ERROR; 8002246: 2301 movs r3, #1 8002248: e313 b.n 8002872 } /* Otherwise, only HSI division and calibration are allowed */ else { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 800224a: 4b32 ldr r3, [pc, #200] ; (8002314 ) 800224c: 681b ldr r3, [r3, #0] 800224e: f023 0219 bic.w r2, r3, #25 8002252: 687b ldr r3, [r7, #4] 8002254: 68db ldr r3, [r3, #12] 8002256: 492f ldr r1, [pc, #188] ; (8002314 ) 8002258: 4313 orrs r3, r2 800225a: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800225c: f7fe fe46 bl 8000eec 8002260: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 8002262: e008 b.n 8002276 { if((uint32_t) (HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8002264: f7fe fe42 bl 8000eec 8002268: 4602 mov r2, r0 800226a: 6a7b ldr r3, [r7, #36] ; 0x24 800226c: 1ad3 subs r3, r2, r3 800226e: 2b02 cmp r3, #2 8002270: d901 bls.n 8002276 { return HAL_TIMEOUT; 8002272: 2303 movs r3, #3 8002274: e2fd b.n 8002872 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 8002276: 4b27 ldr r3, [pc, #156] ; (8002314 ) 8002278: 681b ldr r3, [r3, #0] 800227a: f003 0304 and.w r3, r3, #4 800227e: 2b00 cmp r3, #0 8002280: d0f0 beq.n 8002264 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8002282: 4b24 ldr r3, [pc, #144] ; (8002314 ) 8002284: 685b ldr r3, [r3, #4] 8002286: f023 42fe bic.w r2, r3, #2130706432 ; 0x7f000000 800228a: 687b ldr r3, [r7, #4] 800228c: 691b ldr r3, [r3, #16] 800228e: 061b lsls r3, r3, #24 8002290: 4920 ldr r1, [pc, #128] ; (8002314 ) 8002292: 4313 orrs r3, r2 8002294: 604b str r3, [r1, #4] if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 8002296: e045 b.n 8002324 } else { /* Check the HSI State */ if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) 8002298: 687b ldr r3, [r7, #4] 800229a: 68db ldr r3, [r3, #12] 800229c: 2b00 cmp r3, #0 800229e: d026 beq.n 80022ee { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 80022a0: 4b1c ldr r3, [pc, #112] ; (8002314 ) 80022a2: 681b ldr r3, [r3, #0] 80022a4: f023 0219 bic.w r2, r3, #25 80022a8: 687b ldr r3, [r7, #4] 80022aa: 68db ldr r3, [r3, #12] 80022ac: 4919 ldr r1, [pc, #100] ; (8002314 ) 80022ae: 4313 orrs r3, r2 80022b0: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80022b2: f7fe fe1b bl 8000eec 80022b6: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 80022b8: e008 b.n 80022cc { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 80022ba: f7fe fe17 bl 8000eec 80022be: 4602 mov r2, r0 80022c0: 6a7b ldr r3, [r7, #36] ; 0x24 80022c2: 1ad3 subs r3, r2, r3 80022c4: 2b02 cmp r3, #2 80022c6: d901 bls.n 80022cc { return HAL_TIMEOUT; 80022c8: 2303 movs r3, #3 80022ca: e2d2 b.n 8002872 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 80022cc: 4b11 ldr r3, [pc, #68] ; (8002314 ) 80022ce: 681b ldr r3, [r3, #0] 80022d0: f003 0304 and.w r3, r3, #4 80022d4: 2b00 cmp r3, #0 80022d6: d0f0 beq.n 80022ba } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80022d8: 4b0e ldr r3, [pc, #56] ; (8002314 ) 80022da: 685b ldr r3, [r3, #4] 80022dc: f023 42fe bic.w r2, r3, #2130706432 ; 0x7f000000 80022e0: 687b ldr r3, [r7, #4] 80022e2: 691b ldr r3, [r3, #16] 80022e4: 061b lsls r3, r3, #24 80022e6: 490b ldr r1, [pc, #44] ; (8002314 ) 80022e8: 4313 orrs r3, r2 80022ea: 604b str r3, [r1, #4] 80022ec: e01a b.n 8002324 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 80022ee: 4b09 ldr r3, [pc, #36] ; (8002314 ) 80022f0: 681b ldr r3, [r3, #0] 80022f2: 4a08 ldr r2, [pc, #32] ; (8002314 ) 80022f4: f023 0301 bic.w r3, r3, #1 80022f8: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80022fa: f7fe fdf7 bl 8000eec 80022fe: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 8002300: e00a b.n 8002318 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8002302: f7fe fdf3 bl 8000eec 8002306: 4602 mov r2, r0 8002308: 6a7b ldr r3, [r7, #36] ; 0x24 800230a: 1ad3 subs r3, r2, r3 800230c: 2b02 cmp r3, #2 800230e: d903 bls.n 8002318 { return HAL_TIMEOUT; 8002310: 2303 movs r3, #3 8002312: e2ae b.n 8002872 8002314: 58024400 .word 0x58024400 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 8002318: 4b99 ldr r3, [pc, #612] ; (8002580 ) 800231a: 681b ldr r3, [r3, #0] 800231c: f003 0304 and.w r3, r3, #4 8002320: 2b00 cmp r3, #0 8002322: d1ee bne.n 8002302 } } } } /*----------------------------- CSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) 8002324: 687b ldr r3, [r7, #4] 8002326: 681b ldr r3, [r3, #0] 8002328: f003 0310 and.w r3, r3, #16 800232c: 2b00 cmp r3, #0 800232e: d06a beq.n 8002406 /* Check the parameters */ assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState)); assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue)); /* When the CSI is used as system clock it will not disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8002330: 4b93 ldr r3, [pc, #588] ; (8002580 ) 8002332: 691b ldr r3, [r3, #16] 8002334: f003 0338 and.w r3, r3, #56 ; 0x38 8002338: 61bb str r3, [r7, #24] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800233a: 4b91 ldr r3, [pc, #580] ; (8002580 ) 800233c: 6a9b ldr r3, [r3, #40] ; 0x28 800233e: 617b str r3, [r7, #20] if((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI))) 8002340: 69bb ldr r3, [r7, #24] 8002342: 2b08 cmp r3, #8 8002344: d007 beq.n 8002356 8002346: 69bb ldr r3, [r7, #24] 8002348: 2b18 cmp r3, #24 800234a: d11b bne.n 8002384 800234c: 697b ldr r3, [r7, #20] 800234e: f003 0303 and.w r3, r3, #3 8002352: 2b01 cmp r3, #1 8002354: d116 bne.n 8002384 { /* When CSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 8002356: 4b8a ldr r3, [pc, #552] ; (8002580 ) 8002358: 681b ldr r3, [r3, #0] 800235a: f403 7380 and.w r3, r3, #256 ; 0x100 800235e: 2b00 cmp r3, #0 8002360: d005 beq.n 800236e 8002362: 687b ldr r3, [r7, #4] 8002364: 69db ldr r3, [r3, #28] 8002366: 2b80 cmp r3, #128 ; 0x80 8002368: d001 beq.n 800236e { return HAL_ERROR; 800236a: 2301 movs r3, #1 800236c: e281 b.n 8002872 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800236e: 4b84 ldr r3, [pc, #528] ; (8002580 ) 8002370: 68db ldr r3, [r3, #12] 8002372: f023 527c bic.w r2, r3, #1056964608 ; 0x3f000000 8002376: 687b ldr r3, [r7, #4] 8002378: 6a1b ldr r3, [r3, #32] 800237a: 061b lsls r3, r3, #24 800237c: 4980 ldr r1, [pc, #512] ; (8002580 ) 800237e: 4313 orrs r3, r2 8002380: 60cb str r3, [r1, #12] if((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 8002382: e040 b.n 8002406 } } else { /* Check the CSI State */ if((RCC_OscInitStruct->CSIState)!= RCC_CSI_OFF) 8002384: 687b ldr r3, [r7, #4] 8002386: 69db ldr r3, [r3, #28] 8002388: 2b00 cmp r3, #0 800238a: d023 beq.n 80023d4 { /* Enable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_ENABLE(); 800238c: 4b7c ldr r3, [pc, #496] ; (8002580 ) 800238e: 681b ldr r3, [r3, #0] 8002390: 4a7b ldr r2, [pc, #492] ; (8002580 ) 8002392: f043 0380 orr.w r3, r3, #128 ; 0x80 8002396: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002398: f7fe fda8 bl 8000eec 800239c: 6278 str r0, [r7, #36] ; 0x24 /* Wait till CSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 800239e: e008 b.n 80023b2 { if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE) 80023a0: f7fe fda4 bl 8000eec 80023a4: 4602 mov r2, r0 80023a6: 6a7b ldr r3, [r7, #36] ; 0x24 80023a8: 1ad3 subs r3, r2, r3 80023aa: 2b02 cmp r3, #2 80023ac: d901 bls.n 80023b2 { return HAL_TIMEOUT; 80023ae: 2303 movs r3, #3 80023b0: e25f b.n 8002872 while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 80023b2: 4b73 ldr r3, [pc, #460] ; (8002580 ) 80023b4: 681b ldr r3, [r3, #0] 80023b6: f403 7380 and.w r3, r3, #256 ; 0x100 80023ba: 2b00 cmp r3, #0 80023bc: d0f0 beq.n 80023a0 } } /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 80023be: 4b70 ldr r3, [pc, #448] ; (8002580 ) 80023c0: 68db ldr r3, [r3, #12] 80023c2: f023 527c bic.w r2, r3, #1056964608 ; 0x3f000000 80023c6: 687b ldr r3, [r7, #4] 80023c8: 6a1b ldr r3, [r3, #32] 80023ca: 061b lsls r3, r3, #24 80023cc: 496c ldr r1, [pc, #432] ; (8002580 ) 80023ce: 4313 orrs r3, r2 80023d0: 60cb str r3, [r1, #12] 80023d2: e018 b.n 8002406 } else { /* Disable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_DISABLE(); 80023d4: 4b6a ldr r3, [pc, #424] ; (8002580 ) 80023d6: 681b ldr r3, [r3, #0] 80023d8: 4a69 ldr r2, [pc, #420] ; (8002580 ) 80023da: f023 0380 bic.w r3, r3, #128 ; 0x80 80023de: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80023e0: f7fe fd84 bl 8000eec 80023e4: 6278 str r0, [r7, #36] ; 0x24 /* Wait till CSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 80023e6: e008 b.n 80023fa { if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE) 80023e8: f7fe fd80 bl 8000eec 80023ec: 4602 mov r2, r0 80023ee: 6a7b ldr r3, [r7, #36] ; 0x24 80023f0: 1ad3 subs r3, r2, r3 80023f2: 2b02 cmp r3, #2 80023f4: d901 bls.n 80023fa { return HAL_TIMEOUT; 80023f6: 2303 movs r3, #3 80023f8: e23b b.n 8002872 while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 80023fa: 4b61 ldr r3, [pc, #388] ; (8002580 ) 80023fc: 681b ldr r3, [r3, #0] 80023fe: f403 7380 and.w r3, r3, #256 ; 0x100 8002402: 2b00 cmp r3, #0 8002404: d1f0 bne.n 80023e8 } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8002406: 687b ldr r3, [r7, #4] 8002408: 681b ldr r3, [r3, #0] 800240a: f003 0308 and.w r3, r3, #8 800240e: 2b00 cmp r3, #0 8002410: d036 beq.n 8002480 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) 8002412: 687b ldr r3, [r7, #4] 8002414: 695b ldr r3, [r3, #20] 8002416: 2b00 cmp r3, #0 8002418: d019 beq.n 800244e { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 800241a: 4b59 ldr r3, [pc, #356] ; (8002580 ) 800241c: 6f5b ldr r3, [r3, #116] ; 0x74 800241e: 4a58 ldr r2, [pc, #352] ; (8002580 ) 8002420: f043 0301 orr.w r3, r3, #1 8002424: 6753 str r3, [r2, #116] ; 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002426: f7fe fd61 bl 8000eec 800242a: 6278 str r0, [r7, #36] ; 0x24 /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 800242c: e008 b.n 8002440 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 800242e: f7fe fd5d bl 8000eec 8002432: 4602 mov r2, r0 8002434: 6a7b ldr r3, [r7, #36] ; 0x24 8002436: 1ad3 subs r3, r2, r3 8002438: 2b02 cmp r3, #2 800243a: d901 bls.n 8002440 { return HAL_TIMEOUT; 800243c: 2303 movs r3, #3 800243e: e218 b.n 8002872 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 8002440: 4b4f ldr r3, [pc, #316] ; (8002580 ) 8002442: 6f5b ldr r3, [r3, #116] ; 0x74 8002444: f003 0302 and.w r3, r3, #2 8002448: 2b00 cmp r3, #0 800244a: d0f0 beq.n 800242e 800244c: e018 b.n 8002480 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 800244e: 4b4c ldr r3, [pc, #304] ; (8002580 ) 8002450: 6f5b ldr r3, [r3, #116] ; 0x74 8002452: 4a4b ldr r2, [pc, #300] ; (8002580 ) 8002454: f023 0301 bic.w r3, r3, #1 8002458: 6753 str r3, [r2, #116] ; 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800245a: f7fe fd47 bl 8000eec 800245e: 6278 str r0, [r7, #36] ; 0x24 /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 8002460: e008 b.n 8002474 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8002462: f7fe fd43 bl 8000eec 8002466: 4602 mov r2, r0 8002468: 6a7b ldr r3, [r7, #36] ; 0x24 800246a: 1ad3 subs r3, r2, r3 800246c: 2b02 cmp r3, #2 800246e: d901 bls.n 8002474 { return HAL_TIMEOUT; 8002470: 2303 movs r3, #3 8002472: e1fe b.n 8002872 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 8002474: 4b42 ldr r3, [pc, #264] ; (8002580 ) 8002476: 6f5b ldr r3, [r3, #116] ; 0x74 8002478: f003 0302 and.w r3, r3, #2 800247c: 2b00 cmp r3, #0 800247e: d1f0 bne.n 8002462 } } } /*------------------------------ HSI48 Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 8002480: 687b ldr r3, [r7, #4] 8002482: 681b ldr r3, [r3, #0] 8002484: f003 0320 and.w r3, r3, #32 8002488: 2b00 cmp r3, #0 800248a: d036 beq.n 80024fa { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI48 State */ if((RCC_OscInitStruct->HSI48State)!= RCC_HSI48_OFF) 800248c: 687b ldr r3, [r7, #4] 800248e: 699b ldr r3, [r3, #24] 8002490: 2b00 cmp r3, #0 8002492: d019 beq.n 80024c8 { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); 8002494: 4b3a ldr r3, [pc, #232] ; (8002580 ) 8002496: 681b ldr r3, [r3, #0] 8002498: 4a39 ldr r2, [pc, #228] ; (8002580 ) 800249a: f443 5380 orr.w r3, r3, #4096 ; 0x1000 800249e: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 80024a0: f7fe fd24 bl 8000eec 80024a4: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI48 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 80024a6: e008 b.n 80024ba { if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE) 80024a8: f7fe fd20 bl 8000eec 80024ac: 4602 mov r2, r0 80024ae: 6a7b ldr r3, [r7, #36] ; 0x24 80024b0: 1ad3 subs r3, r2, r3 80024b2: 2b02 cmp r3, #2 80024b4: d901 bls.n 80024ba { return HAL_TIMEOUT; 80024b6: 2303 movs r3, #3 80024b8: e1db b.n 8002872 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 80024ba: 4b31 ldr r3, [pc, #196] ; (8002580 ) 80024bc: 681b ldr r3, [r3, #0] 80024be: f403 5300 and.w r3, r3, #8192 ; 0x2000 80024c2: 2b00 cmp r3, #0 80024c4: d0f0 beq.n 80024a8 80024c6: e018 b.n 80024fa } } else { /* Disable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); 80024c8: 4b2d ldr r3, [pc, #180] ; (8002580 ) 80024ca: 681b ldr r3, [r3, #0] 80024cc: 4a2c ldr r2, [pc, #176] ; (8002580 ) 80024ce: f423 5380 bic.w r3, r3, #4096 ; 0x1000 80024d2: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 80024d4: f7fe fd0a bl 8000eec 80024d8: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI48 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 80024da: e008 b.n 80024ee { if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE) 80024dc: f7fe fd06 bl 8000eec 80024e0: 4602 mov r2, r0 80024e2: 6a7b ldr r3, [r7, #36] ; 0x24 80024e4: 1ad3 subs r3, r2, r3 80024e6: 2b02 cmp r3, #2 80024e8: d901 bls.n 80024ee { return HAL_TIMEOUT; 80024ea: 2303 movs r3, #3 80024ec: e1c1 b.n 8002872 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 80024ee: 4b24 ldr r3, [pc, #144] ; (8002580 ) 80024f0: 681b ldr r3, [r3, #0] 80024f2: f403 5300 and.w r3, r3, #8192 ; 0x2000 80024f6: 2b00 cmp r3, #0 80024f8: d1f0 bne.n 80024dc } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 80024fa: 687b ldr r3, [r7, #4] 80024fc: 681b ldr r3, [r3, #0] 80024fe: f003 0304 and.w r3, r3, #4 8002502: 2b00 cmp r3, #0 8002504: f000 80af beq.w 8002666 { /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; 8002508: 4b1e ldr r3, [pc, #120] ; (8002584 ) 800250a: 681b ldr r3, [r3, #0] 800250c: 4a1d ldr r2, [pc, #116] ; (8002584 ) 800250e: f443 7380 orr.w r3, r3, #256 ; 0x100 8002512: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8002514: f7fe fcea bl 8000eec 8002518: 6278 str r0, [r7, #36] ; 0x24 while((PWR->CR1 & PWR_CR1_DBP) == 0U) 800251a: e008 b.n 800252e { if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) 800251c: f7fe fce6 bl 8000eec 8002520: 4602 mov r2, r0 8002522: 6a7b ldr r3, [r7, #36] ; 0x24 8002524: 1ad3 subs r3, r2, r3 8002526: 2b64 cmp r3, #100 ; 0x64 8002528: d901 bls.n 800252e { return HAL_TIMEOUT; 800252a: 2303 movs r3, #3 800252c: e1a1 b.n 8002872 while((PWR->CR1 & PWR_CR1_DBP) == 0U) 800252e: 4b15 ldr r3, [pc, #84] ; (8002584 ) 8002530: 681b ldr r3, [r3, #0] 8002532: f403 7380 and.w r3, r3, #256 ; 0x100 8002536: 2b00 cmp r3, #0 8002538: d0f0 beq.n 800251c } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 800253a: 687b ldr r3, [r7, #4] 800253c: 689b ldr r3, [r3, #8] 800253e: 2b01 cmp r3, #1 8002540: d106 bne.n 8002550 8002542: 4b0f ldr r3, [pc, #60] ; (8002580 ) 8002544: 6f1b ldr r3, [r3, #112] ; 0x70 8002546: 4a0e ldr r2, [pc, #56] ; (8002580 ) 8002548: f043 0301 orr.w r3, r3, #1 800254c: 6713 str r3, [r2, #112] ; 0x70 800254e: e05b b.n 8002608 8002550: 687b ldr r3, [r7, #4] 8002552: 689b ldr r3, [r3, #8] 8002554: 2b00 cmp r3, #0 8002556: d117 bne.n 8002588 8002558: 4b09 ldr r3, [pc, #36] ; (8002580 ) 800255a: 6f1b ldr r3, [r3, #112] ; 0x70 800255c: 4a08 ldr r2, [pc, #32] ; (8002580 ) 800255e: f023 0301 bic.w r3, r3, #1 8002562: 6713 str r3, [r2, #112] ; 0x70 8002564: 4b06 ldr r3, [pc, #24] ; (8002580 ) 8002566: 6f1b ldr r3, [r3, #112] ; 0x70 8002568: 4a05 ldr r2, [pc, #20] ; (8002580 ) 800256a: f023 0380 bic.w r3, r3, #128 ; 0x80 800256e: 6713 str r3, [r2, #112] ; 0x70 8002570: 4b03 ldr r3, [pc, #12] ; (8002580 ) 8002572: 6f1b ldr r3, [r3, #112] ; 0x70 8002574: 4a02 ldr r2, [pc, #8] ; (8002580 ) 8002576: f023 0304 bic.w r3, r3, #4 800257a: 6713 str r3, [r2, #112] ; 0x70 800257c: e044 b.n 8002608 800257e: bf00 nop 8002580: 58024400 .word 0x58024400 8002584: 58024800 .word 0x58024800 8002588: 687b ldr r3, [r7, #4] 800258a: 689b ldr r3, [r3, #8] 800258c: 2b05 cmp r3, #5 800258e: d112 bne.n 80025b6 8002590: 4b95 ldr r3, [pc, #596] ; (80027e8 ) 8002592: 6f1b ldr r3, [r3, #112] ; 0x70 8002594: 4a94 ldr r2, [pc, #592] ; (80027e8 ) 8002596: f043 0304 orr.w r3, r3, #4 800259a: 6713 str r3, [r2, #112] ; 0x70 800259c: 4b92 ldr r3, [pc, #584] ; (80027e8 ) 800259e: 6f1b ldr r3, [r3, #112] ; 0x70 80025a0: 4a91 ldr r2, [pc, #580] ; (80027e8 ) 80025a2: f023 0380 bic.w r3, r3, #128 ; 0x80 80025a6: 6713 str r3, [r2, #112] ; 0x70 80025a8: 4b8f ldr r3, [pc, #572] ; (80027e8 ) 80025aa: 6f1b ldr r3, [r3, #112] ; 0x70 80025ac: 4a8e ldr r2, [pc, #568] ; (80027e8 ) 80025ae: f043 0301 orr.w r3, r3, #1 80025b2: 6713 str r3, [r2, #112] ; 0x70 80025b4: e028 b.n 8002608 80025b6: 687b ldr r3, [r7, #4] 80025b8: 689b ldr r3, [r3, #8] 80025ba: 2b85 cmp r3, #133 ; 0x85 80025bc: d112 bne.n 80025e4 80025be: 4b8a ldr r3, [pc, #552] ; (80027e8 ) 80025c0: 6f1b ldr r3, [r3, #112] ; 0x70 80025c2: 4a89 ldr r2, [pc, #548] ; (80027e8 ) 80025c4: f043 0304 orr.w r3, r3, #4 80025c8: 6713 str r3, [r2, #112] ; 0x70 80025ca: 4b87 ldr r3, [pc, #540] ; (80027e8 ) 80025cc: 6f1b ldr r3, [r3, #112] ; 0x70 80025ce: 4a86 ldr r2, [pc, #536] ; (80027e8 ) 80025d0: f043 0380 orr.w r3, r3, #128 ; 0x80 80025d4: 6713 str r3, [r2, #112] ; 0x70 80025d6: 4b84 ldr r3, [pc, #528] ; (80027e8 ) 80025d8: 6f1b ldr r3, [r3, #112] ; 0x70 80025da: 4a83 ldr r2, [pc, #524] ; (80027e8 ) 80025dc: f043 0301 orr.w r3, r3, #1 80025e0: 6713 str r3, [r2, #112] ; 0x70 80025e2: e011 b.n 8002608 80025e4: 4b80 ldr r3, [pc, #512] ; (80027e8 ) 80025e6: 6f1b ldr r3, [r3, #112] ; 0x70 80025e8: 4a7f ldr r2, [pc, #508] ; (80027e8 ) 80025ea: f023 0301 bic.w r3, r3, #1 80025ee: 6713 str r3, [r2, #112] ; 0x70 80025f0: 4b7d ldr r3, [pc, #500] ; (80027e8 ) 80025f2: 6f1b ldr r3, [r3, #112] ; 0x70 80025f4: 4a7c ldr r2, [pc, #496] ; (80027e8 ) 80025f6: f023 0304 bic.w r3, r3, #4 80025fa: 6713 str r3, [r2, #112] ; 0x70 80025fc: 4b7a ldr r3, [pc, #488] ; (80027e8 ) 80025fe: 6f1b ldr r3, [r3, #112] ; 0x70 8002600: 4a79 ldr r2, [pc, #484] ; (80027e8 ) 8002602: f023 0380 bic.w r3, r3, #128 ; 0x80 8002606: 6713 str r3, [r2, #112] ; 0x70 /* Check the LSE State */ if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 8002608: 687b ldr r3, [r7, #4] 800260a: 689b ldr r3, [r3, #8] 800260c: 2b00 cmp r3, #0 800260e: d015 beq.n 800263c { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002610: f7fe fc6c bl 8000eec 8002614: 6278 str r0, [r7, #36] ; 0x24 /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 8002616: e00a b.n 800262e { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8002618: f7fe fc68 bl 8000eec 800261c: 4602 mov r2, r0 800261e: 6a7b ldr r3, [r7, #36] ; 0x24 8002620: 1ad3 subs r3, r2, r3 8002622: f241 3288 movw r2, #5000 ; 0x1388 8002626: 4293 cmp r3, r2 8002628: d901 bls.n 800262e { return HAL_TIMEOUT; 800262a: 2303 movs r3, #3 800262c: e121 b.n 8002872 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800262e: 4b6e ldr r3, [pc, #440] ; (80027e8 ) 8002630: 6f1b ldr r3, [r3, #112] ; 0x70 8002632: f003 0302 and.w r3, r3, #2 8002636: 2b00 cmp r3, #0 8002638: d0ee beq.n 8002618 800263a: e014 b.n 8002666 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800263c: f7fe fc56 bl 8000eec 8002640: 6278 str r0, [r7, #36] ; 0x24 /* Wait till LSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 8002642: e00a b.n 800265a { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8002644: f7fe fc52 bl 8000eec 8002648: 4602 mov r2, r0 800264a: 6a7b ldr r3, [r7, #36] ; 0x24 800264c: 1ad3 subs r3, r2, r3 800264e: f241 3288 movw r2, #5000 ; 0x1388 8002652: 4293 cmp r3, r2 8002654: d901 bls.n 800265a { return HAL_TIMEOUT; 8002656: 2303 movs r3, #3 8002658: e10b b.n 8002872 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 800265a: 4b63 ldr r3, [pc, #396] ; (80027e8 ) 800265c: 6f1b ldr r3, [r3, #112] ; 0x70 800265e: f003 0302 and.w r3, r3, #2 8002662: 2b00 cmp r3, #0 8002664: d1ee bne.n 8002644 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8002666: 687b ldr r3, [r7, #4] 8002668: 6a5b ldr r3, [r3, #36] ; 0x24 800266a: 2b00 cmp r3, #0 800266c: f000 8100 beq.w 8002870 { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) 8002670: 4b5d ldr r3, [pc, #372] ; (80027e8 ) 8002672: 691b ldr r3, [r3, #16] 8002674: f003 0338 and.w r3, r3, #56 ; 0x38 8002678: 2b18 cmp r3, #24 800267a: f000 80bb beq.w 80027f4 { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 800267e: 687b ldr r3, [r7, #4] 8002680: 6a5b ldr r3, [r3, #36] ; 0x24 8002682: 2b02 cmp r3, #2 8002684: f040 8095 bne.w 80027b2 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8002688: 4b57 ldr r3, [pc, #348] ; (80027e8 ) 800268a: 681b ldr r3, [r3, #0] 800268c: 4a56 ldr r2, [pc, #344] ; (80027e8 ) 800268e: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 8002692: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002694: f7fe fc2a bl 8000eec 8002698: 6278 str r0, [r7, #36] ; 0x24 /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800269a: e008 b.n 80026ae { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 800269c: f7fe fc26 bl 8000eec 80026a0: 4602 mov r2, r0 80026a2: 6a7b ldr r3, [r7, #36] ; 0x24 80026a4: 1ad3 subs r3, r2, r3 80026a6: 2b02 cmp r3, #2 80026a8: d901 bls.n 80026ae { return HAL_TIMEOUT; 80026aa: 2303 movs r3, #3 80026ac: e0e1 b.n 8002872 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 80026ae: 4b4e ldr r3, [pc, #312] ; (80027e8 ) 80026b0: 681b ldr r3, [r3, #0] 80026b2: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80026b6: 2b00 cmp r3, #0 80026b8: d1f0 bne.n 800269c } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 80026ba: 4b4b ldr r3, [pc, #300] ; (80027e8 ) 80026bc: 6a9a ldr r2, [r3, #40] ; 0x28 80026be: 4b4b ldr r3, [pc, #300] ; (80027ec ) 80026c0: 4013 ands r3, r2 80026c2: 687a ldr r2, [r7, #4] 80026c4: 6a91 ldr r1, [r2, #40] ; 0x28 80026c6: 687a ldr r2, [r7, #4] 80026c8: 6ad2 ldr r2, [r2, #44] ; 0x2c 80026ca: 0112 lsls r2, r2, #4 80026cc: 430a orrs r2, r1 80026ce: 4946 ldr r1, [pc, #280] ; (80027e8 ) 80026d0: 4313 orrs r3, r2 80026d2: 628b str r3, [r1, #40] ; 0x28 80026d4: 687b ldr r3, [r7, #4] 80026d6: 6b1b ldr r3, [r3, #48] ; 0x30 80026d8: 3b01 subs r3, #1 80026da: f3c3 0208 ubfx r2, r3, #0, #9 80026de: 687b ldr r3, [r7, #4] 80026e0: 6b5b ldr r3, [r3, #52] ; 0x34 80026e2: 3b01 subs r3, #1 80026e4: 025b lsls r3, r3, #9 80026e6: b29b uxth r3, r3 80026e8: 431a orrs r2, r3 80026ea: 687b ldr r3, [r7, #4] 80026ec: 6b9b ldr r3, [r3, #56] ; 0x38 80026ee: 3b01 subs r3, #1 80026f0: 041b lsls r3, r3, #16 80026f2: f403 03fe and.w r3, r3, #8323072 ; 0x7f0000 80026f6: 431a orrs r2, r3 80026f8: 687b ldr r3, [r7, #4] 80026fa: 6bdb ldr r3, [r3, #60] ; 0x3c 80026fc: 3b01 subs r3, #1 80026fe: 061b lsls r3, r3, #24 8002700: f003 43fe and.w r3, r3, #2130706432 ; 0x7f000000 8002704: 4938 ldr r1, [pc, #224] ; (80027e8 ) 8002706: 4313 orrs r3, r2 8002708: 630b str r3, [r1, #48] ; 0x30 RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); /* Disable PLLFRACN . */ __HAL_RCC_PLLFRACN_DISABLE(); 800270a: 4b37 ldr r3, [pc, #220] ; (80027e8 ) 800270c: 6adb ldr r3, [r3, #44] ; 0x2c 800270e: 4a36 ldr r2, [pc, #216] ; (80027e8 ) 8002710: f023 0301 bic.w r3, r3, #1 8002714: 62d3 str r3, [r2, #44] ; 0x2c /* Configure PLL PLL1FRACN */ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 8002716: 4b34 ldr r3, [pc, #208] ; (80027e8 ) 8002718: 6b5a ldr r2, [r3, #52] ; 0x34 800271a: 4b35 ldr r3, [pc, #212] ; (80027f0 ) 800271c: 4013 ands r3, r2 800271e: 687a ldr r2, [r7, #4] 8002720: 6c92 ldr r2, [r2, #72] ; 0x48 8002722: 00d2 lsls r2, r2, #3 8002724: 4930 ldr r1, [pc, #192] ; (80027e8 ) 8002726: 4313 orrs r3, r2 8002728: 634b str r3, [r1, #52] ; 0x34 /* Select PLL1 input reference frequency range: VCI */ __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ; 800272a: 4b2f ldr r3, [pc, #188] ; (80027e8 ) 800272c: 6adb ldr r3, [r3, #44] ; 0x2c 800272e: f023 020c bic.w r2, r3, #12 8002732: 687b ldr r3, [r7, #4] 8002734: 6c1b ldr r3, [r3, #64] ; 0x40 8002736: 492c ldr r1, [pc, #176] ; (80027e8 ) 8002738: 4313 orrs r3, r2 800273a: 62cb str r3, [r1, #44] ; 0x2c /* Select PLL1 output frequency range : VCO */ __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ; 800273c: 4b2a ldr r3, [pc, #168] ; (80027e8 ) 800273e: 6adb ldr r3, [r3, #44] ; 0x2c 8002740: f023 0202 bic.w r2, r3, #2 8002744: 687b ldr r3, [r7, #4] 8002746: 6c5b ldr r3, [r3, #68] ; 0x44 8002748: 4927 ldr r1, [pc, #156] ; (80027e8 ) 800274a: 4313 orrs r3, r2 800274c: 62cb str r3, [r1, #44] ; 0x2c /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); 800274e: 4b26 ldr r3, [pc, #152] ; (80027e8 ) 8002750: 6adb ldr r3, [r3, #44] ; 0x2c 8002752: 4a25 ldr r2, [pc, #148] ; (80027e8 ) 8002754: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8002758: 62d3 str r3, [r2, #44] ; 0x2c /* Enable PLL1Q Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800275a: 4b23 ldr r3, [pc, #140] ; (80027e8 ) 800275c: 6adb ldr r3, [r3, #44] ; 0x2c 800275e: 4a22 ldr r2, [pc, #136] ; (80027e8 ) 8002760: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8002764: 62d3 str r3, [r2, #44] ; 0x2c /* Enable PLL1R Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); 8002766: 4b20 ldr r3, [pc, #128] ; (80027e8 ) 8002768: 6adb ldr r3, [r3, #44] ; 0x2c 800276a: 4a1f ldr r2, [pc, #124] ; (80027e8 ) 800276c: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8002770: 62d3 str r3, [r2, #44] ; 0x2c /* Enable PLL1FRACN . */ __HAL_RCC_PLLFRACN_ENABLE(); 8002772: 4b1d ldr r3, [pc, #116] ; (80027e8 ) 8002774: 6adb ldr r3, [r3, #44] ; 0x2c 8002776: 4a1c ldr r2, [pc, #112] ; (80027e8 ) 8002778: f043 0301 orr.w r3, r3, #1 800277c: 62d3 str r3, [r2, #44] ; 0x2c /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 800277e: 4b1a ldr r3, [pc, #104] ; (80027e8 ) 8002780: 681b ldr r3, [r3, #0] 8002782: 4a19 ldr r2, [pc, #100] ; (80027e8 ) 8002784: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 8002788: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800278a: f7fe fbaf bl 8000eec 800278e: 6278 str r0, [r7, #36] ; 0x24 /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 8002790: e008 b.n 80027a4 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8002792: f7fe fbab bl 8000eec 8002796: 4602 mov r2, r0 8002798: 6a7b ldr r3, [r7, #36] ; 0x24 800279a: 1ad3 subs r3, r2, r3 800279c: 2b02 cmp r3, #2 800279e: d901 bls.n 80027a4 { return HAL_TIMEOUT; 80027a0: 2303 movs r3, #3 80027a2: e066 b.n 8002872 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 80027a4: 4b10 ldr r3, [pc, #64] ; (80027e8 ) 80027a6: 681b ldr r3, [r3, #0] 80027a8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80027ac: 2b00 cmp r3, #0 80027ae: d0f0 beq.n 8002792 80027b0: e05e b.n 8002870 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80027b2: 4b0d ldr r3, [pc, #52] ; (80027e8 ) 80027b4: 681b ldr r3, [r3, #0] 80027b6: 4a0c ldr r2, [pc, #48] ; (80027e8 ) 80027b8: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 80027bc: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80027be: f7fe fb95 bl 8000eec 80027c2: 6278 str r0, [r7, #36] ; 0x24 /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 80027c4: e008 b.n 80027d8 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 80027c6: f7fe fb91 bl 8000eec 80027ca: 4602 mov r2, r0 80027cc: 6a7b ldr r3, [r7, #36] ; 0x24 80027ce: 1ad3 subs r3, r2, r3 80027d0: 2b02 cmp r3, #2 80027d2: d901 bls.n 80027d8 { return HAL_TIMEOUT; 80027d4: 2303 movs r3, #3 80027d6: e04c b.n 8002872 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 80027d8: 4b03 ldr r3, [pc, #12] ; (80027e8 ) 80027da: 681b ldr r3, [r3, #0] 80027dc: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80027e0: 2b00 cmp r3, #0 80027e2: d1f0 bne.n 80027c6 80027e4: e044 b.n 8002870 80027e6: bf00 nop 80027e8: 58024400 .word 0x58024400 80027ec: fffffc0c .word 0xfffffc0c 80027f0: ffff0007 .word 0xffff0007 } } else { /* Do not return HAL_ERROR if request repeats the current configuration */ temp1_pllckcfg = RCC->PLLCKSELR; 80027f4: 4b21 ldr r3, [pc, #132] ; (800287c ) 80027f6: 6a9b ldr r3, [r3, #40] ; 0x28 80027f8: 613b str r3, [r7, #16] temp2_pllckcfg = RCC->PLL1DIVR; 80027fa: 4b20 ldr r3, [pc, #128] ; (800287c ) 80027fc: 6b1b ldr r3, [r3, #48] ; 0x30 80027fe: 60fb str r3, [r7, #12] if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 8002800: 687b ldr r3, [r7, #4] 8002802: 6a5b ldr r3, [r3, #36] ; 0x24 8002804: 2b01 cmp r3, #1 8002806: d031 beq.n 800286c (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8002808: 693b ldr r3, [r7, #16] 800280a: f003 0203 and.w r2, r3, #3 800280e: 687b ldr r3, [r7, #4] 8002810: 6a9b ldr r3, [r3, #40] ; 0x28 if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 8002812: 429a cmp r2, r3 8002814: d12a bne.n 800286c ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 8002816: 693b ldr r3, [r7, #16] 8002818: 091b lsrs r3, r3, #4 800281a: f003 023f and.w r2, r3, #63 ; 0x3f 800281e: 687b ldr r3, [r7, #4] 8002820: 6adb ldr r3, [r3, #44] ; 0x2c (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8002822: 429a cmp r2, r3 8002824: d122 bne.n 800286c (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 8002826: 68fb ldr r3, [r7, #12] 8002828: f3c3 0208 ubfx r2, r3, #0, #9 800282c: 687b ldr r3, [r7, #4] 800282e: 6b1b ldr r3, [r3, #48] ; 0x30 8002830: 3b01 subs r3, #1 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 8002832: 429a cmp r2, r3 8002834: d11a bne.n 800286c ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 8002836: 68fb ldr r3, [r7, #12] 8002838: 0a5b lsrs r3, r3, #9 800283a: f003 027f and.w r2, r3, #127 ; 0x7f 800283e: 687b ldr r3, [r7, #4] 8002840: 6b5b ldr r3, [r3, #52] ; 0x34 8002842: 3b01 subs r3, #1 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 8002844: 429a cmp r2, r3 8002846: d111 bne.n 800286c ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 8002848: 68fb ldr r3, [r7, #12] 800284a: 0c1b lsrs r3, r3, #16 800284c: f003 027f and.w r2, r3, #127 ; 0x7f 8002850: 687b ldr r3, [r7, #4] 8002852: 6b9b ldr r3, [r3, #56] ; 0x38 8002854: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 8002856: 429a cmp r2, r3 8002858: d108 bne.n 800286c ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U))) 800285a: 68fb ldr r3, [r7, #12] 800285c: 0e1b lsrs r3, r3, #24 800285e: f003 027f and.w r2, r3, #127 ; 0x7f 8002862: 687b ldr r3, [r7, #4] 8002864: 6bdb ldr r3, [r3, #60] ; 0x3c 8002866: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 8002868: 429a cmp r2, r3 800286a: d001 beq.n 8002870 { return HAL_ERROR; 800286c: 2301 movs r3, #1 800286e: e000 b.n 8002872 } } } return HAL_OK; 8002870: 2300 movs r3, #0 } 8002872: 4618 mov r0, r3 8002874: 3730 adds r7, #48 ; 0x30 8002876: 46bd mov sp, r7 8002878: bd80 pop {r7, pc} 800287a: bf00 nop 800287c: 58024400 .word 0x58024400 08002880 : * D1CPRE[3:0] bits to ensure that Domain1 core clock not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8002880: b580 push {r7, lr} 8002882: b086 sub sp, #24 8002884: af00 add r7, sp, #0 8002886: 6078 str r0, [r7, #4] 8002888: 6039 str r1, [r7, #0] HAL_StatusTypeDef halstatus; uint32_t tickstart; uint32_t common_system_clock; /* Check Null pointer */ if(RCC_ClkInitStruct == NULL) 800288a: 687b ldr r3, [r7, #4] 800288c: 2b00 cmp r3, #0 800288e: d101 bne.n 8002894 { return HAL_ERROR; 8002890: 2301 movs r3, #1 8002892: e19c b.n 8002bce /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the CPU frequency */ if(FLatency > __HAL_FLASH_GET_LATENCY()) 8002894: 4b8a ldr r3, [pc, #552] ; (8002ac0 ) 8002896: 681b ldr r3, [r3, #0] 8002898: f003 030f and.w r3, r3, #15 800289c: 683a ldr r2, [r7, #0] 800289e: 429a cmp r2, r3 80028a0: d910 bls.n 80028c4 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80028a2: 4b87 ldr r3, [pc, #540] ; (8002ac0 ) 80028a4: 681b ldr r3, [r3, #0] 80028a6: f023 020f bic.w r2, r3, #15 80028aa: 4985 ldr r1, [pc, #532] ; (8002ac0 ) 80028ac: 683b ldr r3, [r7, #0] 80028ae: 4313 orrs r3, r2 80028b0: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 80028b2: 4b83 ldr r3, [pc, #524] ; (8002ac0 ) 80028b4: 681b ldr r3, [r3, #0] 80028b6: f003 030f and.w r3, r3, #15 80028ba: 683a ldr r2, [r7, #0] 80028bc: 429a cmp r2, r3 80028be: d001 beq.n 80028c4 { return HAL_ERROR; 80028c0: 2301 movs r3, #1 80028c2: e184 b.n 8002bce } /* Increasing the BUS frequency divider */ /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 80028c4: 687b ldr r3, [r7, #4] 80028c6: 681b ldr r3, [r3, #0] 80028c8: f003 0304 and.w r3, r3, #4 80028cc: 2b00 cmp r3, #0 80028ce: d010 beq.n 80028f2 { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); } #else if((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)) 80028d0: 687b ldr r3, [r7, #4] 80028d2: 691a ldr r2, [r3, #16] 80028d4: 4b7b ldr r3, [pc, #492] ; (8002ac4 ) 80028d6: 699b ldr r3, [r3, #24] 80028d8: f003 0370 and.w r3, r3, #112 ; 0x70 80028dc: 429a cmp r2, r3 80028de: d908 bls.n 80028f2 { assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider); 80028e0: 4b78 ldr r3, [pc, #480] ; (8002ac4 ) 80028e2: 699b ldr r3, [r3, #24] 80028e4: f023 0270 bic.w r2, r3, #112 ; 0x70 80028e8: 687b ldr r3, [r7, #4] 80028ea: 691b ldr r3, [r3, #16] 80028ec: 4975 ldr r1, [pc, #468] ; (8002ac4 ) 80028ee: 4313 orrs r3, r2 80028f0: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80028f2: 687b ldr r3, [r7, #4] 80028f4: 681b ldr r3, [r3, #0] 80028f6: f003 0308 and.w r3, r3, #8 80028fa: 2b00 cmp r3, #0 80028fc: d010 beq.n 8002920 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); } #else if((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)) 80028fe: 687b ldr r3, [r7, #4] 8002900: 695a ldr r2, [r3, #20] 8002902: 4b70 ldr r3, [pc, #448] ; (8002ac4 ) 8002904: 69db ldr r3, [r3, #28] 8002906: f003 0370 and.w r3, r3, #112 ; 0x70 800290a: 429a cmp r2, r3 800290c: d908 bls.n 8002920 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 800290e: 4b6d ldr r3, [pc, #436] ; (8002ac4 ) 8002910: 69db ldr r3, [r3, #28] 8002912: f023 0270 bic.w r2, r3, #112 ; 0x70 8002916: 687b ldr r3, [r7, #4] 8002918: 695b ldr r3, [r3, #20] 800291a: 496a ldr r1, [pc, #424] ; (8002ac4 ) 800291c: 4313 orrs r3, r2 800291e: 61cb str r3, [r1, #28] } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8002920: 687b ldr r3, [r7, #4] 8002922: 681b ldr r3, [r3, #0] 8002924: f003 0310 and.w r3, r3, #16 8002928: 2b00 cmp r3, #0 800292a: d010 beq.n 800294e { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); } #else if((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)) 800292c: 687b ldr r3, [r7, #4] 800292e: 699a ldr r2, [r3, #24] 8002930: 4b64 ldr r3, [pc, #400] ; (8002ac4 ) 8002932: 69db ldr r3, [r3, #28] 8002934: f403 63e0 and.w r3, r3, #1792 ; 0x700 8002938: 429a cmp r2, r3 800293a: d908 bls.n 800294e { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 800293c: 4b61 ldr r3, [pc, #388] ; (8002ac4 ) 800293e: 69db ldr r3, [r3, #28] 8002940: f423 62e0 bic.w r2, r3, #1792 ; 0x700 8002944: 687b ldr r3, [r7, #4] 8002946: 699b ldr r3, [r3, #24] 8002948: 495e ldr r1, [pc, #376] ; (8002ac4 ) 800294a: 4313 orrs r3, r2 800294c: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 800294e: 687b ldr r3, [r7, #4] 8002950: 681b ldr r3, [r3, #0] 8002952: f003 0320 and.w r3, r3, #32 8002956: 2b00 cmp r3, #0 8002958: d010 beq.n 800297c { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) ); } #else if((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)) 800295a: 687b ldr r3, [r7, #4] 800295c: 69da ldr r2, [r3, #28] 800295e: 4b59 ldr r3, [pc, #356] ; (8002ac4 ) 8002960: 6a1b ldr r3, [r3, #32] 8002962: f003 0370 and.w r3, r3, #112 ; 0x70 8002966: 429a cmp r2, r3 8002968: d908 bls.n 800297c { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider) ); 800296a: 4b56 ldr r3, [pc, #344] ; (8002ac4 ) 800296c: 6a1b ldr r3, [r3, #32] 800296e: f023 0270 bic.w r2, r3, #112 ; 0x70 8002972: 687b ldr r3, [r7, #4] 8002974: 69db ldr r3, [r3, #28] 8002976: 4953 ldr r1, [pc, #332] ; (8002ac4 ) 8002978: 4313 orrs r3, r2 800297a: 620b str r3, [r1, #32] } #endif } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800297c: 687b ldr r3, [r7, #4] 800297e: 681b ldr r3, [r3, #0] 8002980: f003 0302 and.w r3, r3, #2 8002984: 2b00 cmp r3, #0 8002986: d010 beq.n 80029aa /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); } #else if((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)) 8002988: 687b ldr r3, [r7, #4] 800298a: 68da ldr r2, [r3, #12] 800298c: 4b4d ldr r3, [pc, #308] ; (8002ac4 ) 800298e: 699b ldr r3, [r3, #24] 8002990: f003 030f and.w r3, r3, #15 8002994: 429a cmp r2, r3 8002996: d908 bls.n 80029aa { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8002998: 4b4a ldr r3, [pc, #296] ; (8002ac4 ) 800299a: 699b ldr r3, [r3, #24] 800299c: f023 020f bic.w r2, r3, #15 80029a0: 687b ldr r3, [r7, #4] 80029a2: 68db ldr r3, [r3, #12] 80029a4: 4947 ldr r1, [pc, #284] ; (8002ac4 ) 80029a6: 4313 orrs r3, r2 80029a8: 618b str r3, [r1, #24] } #endif } /*------------------------- SYSCLK Configuration -------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 80029aa: 687b ldr r3, [r7, #4] 80029ac: 681b ldr r3, [r3, #0] 80029ae: f003 0301 and.w r3, r3, #1 80029b2: 2b00 cmp r3, #0 80029b4: d055 beq.n 8002a62 assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); #if defined(RCC_D1CFGR_D1CPRE) MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider); #else MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider); 80029b6: 4b43 ldr r3, [pc, #268] ; (8002ac4 ) 80029b8: 699b ldr r3, [r3, #24] 80029ba: f423 6270 bic.w r2, r3, #3840 ; 0xf00 80029be: 687b ldr r3, [r7, #4] 80029c0: 689b ldr r3, [r3, #8] 80029c2: 4940 ldr r1, [pc, #256] ; (8002ac4 ) 80029c4: 4313 orrs r3, r2 80029c6: 618b str r3, [r1, #24] #endif /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 80029c8: 687b ldr r3, [r7, #4] 80029ca: 685b ldr r3, [r3, #4] 80029cc: 2b02 cmp r3, #2 80029ce: d107 bne.n 80029e0 { /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 80029d0: 4b3c ldr r3, [pc, #240] ; (8002ac4 ) 80029d2: 681b ldr r3, [r3, #0] 80029d4: f403 3300 and.w r3, r3, #131072 ; 0x20000 80029d8: 2b00 cmp r3, #0 80029da: d121 bne.n 8002a20 { return HAL_ERROR; 80029dc: 2301 movs r3, #1 80029de: e0f6 b.n 8002bce } } /* PLL is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 80029e0: 687b ldr r3, [r7, #4] 80029e2: 685b ldr r3, [r3, #4] 80029e4: 2b03 cmp r3, #3 80029e6: d107 bne.n 80029f8 { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 80029e8: 4b36 ldr r3, [pc, #216] ; (8002ac4 ) 80029ea: 681b ldr r3, [r3, #0] 80029ec: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80029f0: 2b00 cmp r3, #0 80029f2: d115 bne.n 8002a20 { return HAL_ERROR; 80029f4: 2301 movs r3, #1 80029f6: e0ea b.n 8002bce } } /* CSI is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) 80029f8: 687b ldr r3, [r7, #4] 80029fa: 685b ldr r3, [r3, #4] 80029fc: 2b01 cmp r3, #1 80029fe: d107 bne.n 8002a10 { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 8002a00: 4b30 ldr r3, [pc, #192] ; (8002ac4 ) 8002a02: 681b ldr r3, [r3, #0] 8002a04: f403 7380 and.w r3, r3, #256 ; 0x100 8002a08: 2b00 cmp r3, #0 8002a0a: d109 bne.n 8002a20 { return HAL_ERROR; 8002a0c: 2301 movs r3, #1 8002a0e: e0de b.n 8002bce } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 8002a10: 4b2c ldr r3, [pc, #176] ; (8002ac4 ) 8002a12: 681b ldr r3, [r3, #0] 8002a14: f003 0304 and.w r3, r3, #4 8002a18: 2b00 cmp r3, #0 8002a1a: d101 bne.n 8002a20 { return HAL_ERROR; 8002a1c: 2301 movs r3, #1 8002a1e: e0d6 b.n 8002bce } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 8002a20: 4b28 ldr r3, [pc, #160] ; (8002ac4 ) 8002a22: 691b ldr r3, [r3, #16] 8002a24: f023 0207 bic.w r2, r3, #7 8002a28: 687b ldr r3, [r7, #4] 8002a2a: 685b ldr r3, [r3, #4] 8002a2c: 4925 ldr r1, [pc, #148] ; (8002ac4 ) 8002a2e: 4313 orrs r3, r2 8002a30: 610b str r3, [r1, #16] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002a32: f7fe fa5b bl 8000eec 8002a36: 6178 str r0, [r7, #20] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8002a38: e00a b.n 8002a50 { if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 8002a3a: f7fe fa57 bl 8000eec 8002a3e: 4602 mov r2, r0 8002a40: 697b ldr r3, [r7, #20] 8002a42: 1ad3 subs r3, r2, r3 8002a44: f241 3288 movw r2, #5000 ; 0x1388 8002a48: 4293 cmp r3, r2 8002a4a: d901 bls.n 8002a50 { return HAL_TIMEOUT; 8002a4c: 2303 movs r3, #3 8002a4e: e0be b.n 8002bce while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8002a50: 4b1c ldr r3, [pc, #112] ; (8002ac4 ) 8002a52: 691b ldr r3, [r3, #16] 8002a54: f003 0238 and.w r2, r3, #56 ; 0x38 8002a58: 687b ldr r3, [r7, #4] 8002a5a: 685b ldr r3, [r3, #4] 8002a5c: 00db lsls r3, r3, #3 8002a5e: 429a cmp r2, r3 8002a60: d1eb bne.n 8002a3a } /* Decreasing the BUS frequency divider */ /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8002a62: 687b ldr r3, [r7, #4] 8002a64: 681b ldr r3, [r3, #0] 8002a66: f003 0302 and.w r3, r3, #2 8002a6a: 2b00 cmp r3, #0 8002a6c: d010 beq.n 8002a90 /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); } #else if((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)) 8002a6e: 687b ldr r3, [r7, #4] 8002a70: 68da ldr r2, [r3, #12] 8002a72: 4b14 ldr r3, [pc, #80] ; (8002ac4 ) 8002a74: 699b ldr r3, [r3, #24] 8002a76: f003 030f and.w r3, r3, #15 8002a7a: 429a cmp r2, r3 8002a7c: d208 bcs.n 8002a90 { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8002a7e: 4b11 ldr r3, [pc, #68] ; (8002ac4 ) 8002a80: 699b ldr r3, [r3, #24] 8002a82: f023 020f bic.w r2, r3, #15 8002a86: 687b ldr r3, [r7, #4] 8002a88: 68db ldr r3, [r3, #12] 8002a8a: 490e ldr r1, [pc, #56] ; (8002ac4 ) 8002a8c: 4313 orrs r3, r2 8002a8e: 618b str r3, [r1, #24] } #endif } /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < __HAL_FLASH_GET_LATENCY()) 8002a90: 4b0b ldr r3, [pc, #44] ; (8002ac0 ) 8002a92: 681b ldr r3, [r3, #0] 8002a94: f003 030f and.w r3, r3, #15 8002a98: 683a ldr r2, [r7, #0] 8002a9a: 429a cmp r2, r3 8002a9c: d214 bcs.n 8002ac8 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8002a9e: 4b08 ldr r3, [pc, #32] ; (8002ac0 ) 8002aa0: 681b ldr r3, [r3, #0] 8002aa2: f023 020f bic.w r2, r3, #15 8002aa6: 4906 ldr r1, [pc, #24] ; (8002ac0 ) 8002aa8: 683b ldr r3, [r7, #0] 8002aaa: 4313 orrs r3, r2 8002aac: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8002aae: 4b04 ldr r3, [pc, #16] ; (8002ac0 ) 8002ab0: 681b ldr r3, [r3, #0] 8002ab2: f003 030f and.w r3, r3, #15 8002ab6: 683a ldr r2, [r7, #0] 8002ab8: 429a cmp r2, r3 8002aba: d005 beq.n 8002ac8 { return HAL_ERROR; 8002abc: 2301 movs r3, #1 8002abe: e086 b.n 8002bce 8002ac0: 52002000 .word 0x52002000 8002ac4: 58024400 .word 0x58024400 } } /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 8002ac8: 687b ldr r3, [r7, #4] 8002aca: 681b ldr r3, [r3, #0] 8002acc: f003 0304 and.w r3, r3, #4 8002ad0: 2b00 cmp r3, #0 8002ad2: d010 beq.n 8002af6 { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); } #else if((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)) 8002ad4: 687b ldr r3, [r7, #4] 8002ad6: 691a ldr r2, [r3, #16] 8002ad8: 4b3f ldr r3, [pc, #252] ; (8002bd8 ) 8002ada: 699b ldr r3, [r3, #24] 8002adc: f003 0370 and.w r3, r3, #112 ; 0x70 8002ae0: 429a cmp r2, r3 8002ae2: d208 bcs.n 8002af6 { assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider); 8002ae4: 4b3c ldr r3, [pc, #240] ; (8002bd8 ) 8002ae6: 699b ldr r3, [r3, #24] 8002ae8: f023 0270 bic.w r2, r3, #112 ; 0x70 8002aec: 687b ldr r3, [r7, #4] 8002aee: 691b ldr r3, [r3, #16] 8002af0: 4939 ldr r1, [pc, #228] ; (8002bd8 ) 8002af2: 4313 orrs r3, r2 8002af4: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8002af6: 687b ldr r3, [r7, #4] 8002af8: 681b ldr r3, [r3, #0] 8002afa: f003 0308 and.w r3, r3, #8 8002afe: 2b00 cmp r3, #0 8002b00: d010 beq.n 8002b24 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); } #else if((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)) 8002b02: 687b ldr r3, [r7, #4] 8002b04: 695a ldr r2, [r3, #20] 8002b06: 4b34 ldr r3, [pc, #208] ; (8002bd8 ) 8002b08: 69db ldr r3, [r3, #28] 8002b0a: f003 0370 and.w r3, r3, #112 ; 0x70 8002b0e: 429a cmp r2, r3 8002b10: d208 bcs.n 8002b24 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 8002b12: 4b31 ldr r3, [pc, #196] ; (8002bd8 ) 8002b14: 69db ldr r3, [r3, #28] 8002b16: f023 0270 bic.w r2, r3, #112 ; 0x70 8002b1a: 687b ldr r3, [r7, #4] 8002b1c: 695b ldr r3, [r3, #20] 8002b1e: 492e ldr r1, [pc, #184] ; (8002bd8 ) 8002b20: 4313 orrs r3, r2 8002b22: 61cb str r3, [r1, #28] } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8002b24: 687b ldr r3, [r7, #4] 8002b26: 681b ldr r3, [r3, #0] 8002b28: f003 0310 and.w r3, r3, #16 8002b2c: 2b00 cmp r3, #0 8002b2e: d010 beq.n 8002b52 { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); } #else if((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)) 8002b30: 687b ldr r3, [r7, #4] 8002b32: 699a ldr r2, [r3, #24] 8002b34: 4b28 ldr r3, [pc, #160] ; (8002bd8 ) 8002b36: 69db ldr r3, [r3, #28] 8002b38: f403 63e0 and.w r3, r3, #1792 ; 0x700 8002b3c: 429a cmp r2, r3 8002b3e: d208 bcs.n 8002b52 { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 8002b40: 4b25 ldr r3, [pc, #148] ; (8002bd8 ) 8002b42: 69db ldr r3, [r3, #28] 8002b44: f423 62e0 bic.w r2, r3, #1792 ; 0x700 8002b48: 687b ldr r3, [r7, #4] 8002b4a: 699b ldr r3, [r3, #24] 8002b4c: 4922 ldr r1, [pc, #136] ; (8002bd8 ) 8002b4e: 4313 orrs r3, r2 8002b50: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 8002b52: 687b ldr r3, [r7, #4] 8002b54: 681b ldr r3, [r3, #0] 8002b56: f003 0320 and.w r3, r3, #32 8002b5a: 2b00 cmp r3, #0 8002b5c: d010 beq.n 8002b80 { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) ); } #else if((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)) 8002b5e: 687b ldr r3, [r7, #4] 8002b60: 69da ldr r2, [r3, #28] 8002b62: 4b1d ldr r3, [pc, #116] ; (8002bd8 ) 8002b64: 6a1b ldr r3, [r3, #32] 8002b66: f003 0370 and.w r3, r3, #112 ; 0x70 8002b6a: 429a cmp r2, r3 8002b6c: d208 bcs.n 8002b80 { assert_param(IS_RCC_SRDPCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider) ); 8002b6e: 4b1a ldr r3, [pc, #104] ; (8002bd8 ) 8002b70: 6a1b ldr r3, [r3, #32] 8002b72: f023 0270 bic.w r2, r3, #112 ; 0x70 8002b76: 687b ldr r3, [r7, #4] 8002b78: 69db ldr r3, [r3, #28] 8002b7a: 4917 ldr r1, [pc, #92] ; (8002bd8 ) 8002b7c: 4313 orrs r3, r2 8002b7e: 620b str r3, [r1, #32] /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); #else common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); 8002b80: f000 f834 bl 8002bec 8002b84: 4602 mov r2, r0 8002b86: 4b14 ldr r3, [pc, #80] ; (8002bd8 ) 8002b88: 699b ldr r3, [r3, #24] 8002b8a: 0a1b lsrs r3, r3, #8 8002b8c: f003 030f and.w r3, r3, #15 8002b90: 4912 ldr r1, [pc, #72] ; (8002bdc ) 8002b92: 5ccb ldrb r3, [r1, r3] 8002b94: f003 031f and.w r3, r3, #31 8002b98: fa22 f303 lsr.w r3, r2, r3 8002b9c: 613b str r3, [r7, #16] #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); #else SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); 8002b9e: 4b0e ldr r3, [pc, #56] ; (8002bd8 ) 8002ba0: 699b ldr r3, [r3, #24] 8002ba2: f003 030f and.w r3, r3, #15 8002ba6: 4a0d ldr r2, [pc, #52] ; (8002bdc ) 8002ba8: 5cd3 ldrb r3, [r2, r3] 8002baa: f003 031f and.w r3, r3, #31 8002bae: 693a ldr r2, [r7, #16] 8002bb0: fa22 f303 lsr.w r3, r2, r3 8002bb4: 4a0a ldr r2, [pc, #40] ; (8002be0 ) 8002bb6: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 8002bb8: 4a0a ldr r2, [pc, #40] ; (8002be4 ) 8002bba: 693b ldr r3, [r7, #16] 8002bbc: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Configure the source of time base considering new system clocks settings*/ halstatus = HAL_InitTick (uwTickPrio); 8002bbe: 4b0a ldr r3, [pc, #40] ; (8002be8 ) 8002bc0: 681b ldr r3, [r3, #0] 8002bc2: 4618 mov r0, r3 8002bc4: f7fe f948 bl 8000e58 8002bc8: 4603 mov r3, r0 8002bca: 73fb strb r3, [r7, #15] return halstatus; 8002bcc: 7bfb ldrb r3, [r7, #15] } 8002bce: 4618 mov r0, r3 8002bd0: 3718 adds r7, #24 8002bd2: 46bd mov sp, r7 8002bd4: bd80 pop {r7, pc} 8002bd6: bf00 nop 8002bd8: 58024400 .word 0x58024400 8002bdc: 08007278 .word 0x08007278 8002be0: 24000018 .word 0x24000018 8002be4: 24000014 .word 0x24000014 8002be8: 2400001c .word 0x2400001c 08002bec : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8002bec: b480 push {r7} 8002bee: b089 sub sp, #36 ; 0x24 8002bf0: af00 add r7, sp, #0 float_t fracn1, pllvco; uint32_t sysclockfreq; /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 8002bf2: 4bb3 ldr r3, [pc, #716] ; (8002ec0 ) 8002bf4: 691b ldr r3, [r3, #16] 8002bf6: f003 0338 and.w r3, r3, #56 ; 0x38 8002bfa: 2b18 cmp r3, #24 8002bfc: f200 8155 bhi.w 8002eaa 8002c00: a201 add r2, pc, #4 ; (adr r2, 8002c08 ) 8002c02: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8002c06: bf00 nop 8002c08: 08002c6d .word 0x08002c6d 8002c0c: 08002eab .word 0x08002eab 8002c10: 08002eab .word 0x08002eab 8002c14: 08002eab .word 0x08002eab 8002c18: 08002eab .word 0x08002eab 8002c1c: 08002eab .word 0x08002eab 8002c20: 08002eab .word 0x08002eab 8002c24: 08002eab .word 0x08002eab 8002c28: 08002c93 .word 0x08002c93 8002c2c: 08002eab .word 0x08002eab 8002c30: 08002eab .word 0x08002eab 8002c34: 08002eab .word 0x08002eab 8002c38: 08002eab .word 0x08002eab 8002c3c: 08002eab .word 0x08002eab 8002c40: 08002eab .word 0x08002eab 8002c44: 08002eab .word 0x08002eab 8002c48: 08002c99 .word 0x08002c99 8002c4c: 08002eab .word 0x08002eab 8002c50: 08002eab .word 0x08002eab 8002c54: 08002eab .word 0x08002eab 8002c58: 08002eab .word 0x08002eab 8002c5c: 08002eab .word 0x08002eab 8002c60: 08002eab .word 0x08002eab 8002c64: 08002eab .word 0x08002eab 8002c68: 08002c9f .word 0x08002c9f { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8002c6c: 4b94 ldr r3, [pc, #592] ; (8002ec0 ) 8002c6e: 681b ldr r3, [r3, #0] 8002c70: f003 0320 and.w r3, r3, #32 8002c74: 2b00 cmp r3, #0 8002c76: d009 beq.n 8002c8c { sysclockfreq = (uint32_t) (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 8002c78: 4b91 ldr r3, [pc, #580] ; (8002ec0 ) 8002c7a: 681b ldr r3, [r3, #0] 8002c7c: 08db lsrs r3, r3, #3 8002c7e: f003 0303 and.w r3, r3, #3 8002c82: 4a90 ldr r2, [pc, #576] ; (8002ec4 ) 8002c84: fa22 f303 lsr.w r3, r2, r3 8002c88: 61bb str r3, [r7, #24] else { sysclockfreq = (uint32_t) HSI_VALUE; } break; 8002c8a: e111 b.n 8002eb0 sysclockfreq = (uint32_t) HSI_VALUE; 8002c8c: 4b8d ldr r3, [pc, #564] ; (8002ec4 ) 8002c8e: 61bb str r3, [r7, #24] break; 8002c90: e10e b.n 8002eb0 case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ sysclockfreq = CSI_VALUE; 8002c92: 4b8d ldr r3, [pc, #564] ; (8002ec8 ) 8002c94: 61bb str r3, [r7, #24] break; 8002c96: e10b b.n 8002eb0 case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; 8002c98: 4b8c ldr r3, [pc, #560] ; (8002ecc ) 8002c9a: 61bb str r3, [r7, #24] break; 8002c9c: e108 b.n 8002eb0 case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 8002c9e: 4b88 ldr r3, [pc, #544] ; (8002ec0 ) 8002ca0: 6a9b ldr r3, [r3, #40] ; 0x28 8002ca2: f003 0303 and.w r3, r3, #3 8002ca6: 617b str r3, [r7, #20] pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; 8002ca8: 4b85 ldr r3, [pc, #532] ; (8002ec0 ) 8002caa: 6a9b ldr r3, [r3, #40] ; 0x28 8002cac: 091b lsrs r3, r3, #4 8002cae: f003 033f and.w r3, r3, #63 ; 0x3f 8002cb2: 613b str r3, [r7, #16] pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos); 8002cb4: 4b82 ldr r3, [pc, #520] ; (8002ec0 ) 8002cb6: 6adb ldr r3, [r3, #44] ; 0x2c 8002cb8: f003 0301 and.w r3, r3, #1 8002cbc: 60fb str r3, [r7, #12] fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); 8002cbe: 4b80 ldr r3, [pc, #512] ; (8002ec0 ) 8002cc0: 6b5b ldr r3, [r3, #52] ; 0x34 8002cc2: 08db lsrs r3, r3, #3 8002cc4: f3c3 030c ubfx r3, r3, #0, #13 8002cc8: 68fa ldr r2, [r7, #12] 8002cca: fb02 f303 mul.w r3, r2, r3 8002cce: ee07 3a90 vmov s15, r3 8002cd2: eef8 7a67 vcvt.f32.u32 s15, s15 8002cd6: edc7 7a02 vstr s15, [r7, #8] if (pllm != 0U) 8002cda: 693b ldr r3, [r7, #16] 8002cdc: 2b00 cmp r3, #0 8002cde: f000 80e1 beq.w 8002ea4 8002ce2: 697b ldr r3, [r7, #20] 8002ce4: 2b02 cmp r3, #2 8002ce6: f000 8083 beq.w 8002df0 8002cea: 697b ldr r3, [r7, #20] 8002cec: 2b02 cmp r3, #2 8002cee: f200 80a1 bhi.w 8002e34 8002cf2: 697b ldr r3, [r7, #20] 8002cf4: 2b00 cmp r3, #0 8002cf6: d003 beq.n 8002d00 8002cf8: 697b ldr r3, [r7, #20] 8002cfa: 2b01 cmp r3, #1 8002cfc: d056 beq.n 8002dac 8002cfe: e099 b.n 8002e34 { switch (pllsource) { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8002d00: 4b6f ldr r3, [pc, #444] ; (8002ec0 ) 8002d02: 681b ldr r3, [r3, #0] 8002d04: f003 0320 and.w r3, r3, #32 8002d08: 2b00 cmp r3, #0 8002d0a: d02d beq.n 8002d68 { hsivalue= (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 8002d0c: 4b6c ldr r3, [pc, #432] ; (8002ec0 ) 8002d0e: 681b ldr r3, [r3, #0] 8002d10: 08db lsrs r3, r3, #3 8002d12: f003 0303 and.w r3, r3, #3 8002d16: 4a6b ldr r2, [pc, #428] ; (8002ec4 ) 8002d18: fa22 f303 lsr.w r3, r2, r3 8002d1c: 607b str r3, [r7, #4] pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 8002d1e: 687b ldr r3, [r7, #4] 8002d20: ee07 3a90 vmov s15, r3 8002d24: eef8 6a67 vcvt.f32.u32 s13, s15 8002d28: 693b ldr r3, [r7, #16] 8002d2a: ee07 3a90 vmov s15, r3 8002d2e: eef8 7a67 vcvt.f32.u32 s15, s15 8002d32: ee86 7aa7 vdiv.f32 s14, s13, s15 8002d36: 4b62 ldr r3, [pc, #392] ; (8002ec0 ) 8002d38: 6b1b ldr r3, [r3, #48] ; 0x30 8002d3a: f3c3 0308 ubfx r3, r3, #0, #9 8002d3e: ee07 3a90 vmov s15, r3 8002d42: eef8 6a67 vcvt.f32.u32 s13, s15 8002d46: ed97 6a02 vldr s12, [r7, #8] 8002d4a: eddf 5a61 vldr s11, [pc, #388] ; 8002ed0 8002d4e: eec6 7a25 vdiv.f32 s15, s12, s11 8002d52: ee76 7aa7 vadd.f32 s15, s13, s15 8002d56: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8002d5a: ee77 7aa6 vadd.f32 s15, s15, s13 8002d5e: ee67 7a27 vmul.f32 s15, s14, s15 8002d62: edc7 7a07 vstr s15, [r7, #28] } else { pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); } break; 8002d66: e087 b.n 8002e78 pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 8002d68: 693b ldr r3, [r7, #16] 8002d6a: ee07 3a90 vmov s15, r3 8002d6e: eef8 7a67 vcvt.f32.u32 s15, s15 8002d72: eddf 6a58 vldr s13, [pc, #352] ; 8002ed4 8002d76: ee86 7aa7 vdiv.f32 s14, s13, s15 8002d7a: 4b51 ldr r3, [pc, #324] ; (8002ec0 ) 8002d7c: 6b1b ldr r3, [r3, #48] ; 0x30 8002d7e: f3c3 0308 ubfx r3, r3, #0, #9 8002d82: ee07 3a90 vmov s15, r3 8002d86: eef8 6a67 vcvt.f32.u32 s13, s15 8002d8a: ed97 6a02 vldr s12, [r7, #8] 8002d8e: eddf 5a50 vldr s11, [pc, #320] ; 8002ed0 8002d92: eec6 7a25 vdiv.f32 s15, s12, s11 8002d96: ee76 7aa7 vadd.f32 s15, s13, s15 8002d9a: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8002d9e: ee77 7aa6 vadd.f32 s15, s15, s13 8002da2: ee67 7a27 vmul.f32 s15, s14, s15 8002da6: edc7 7a07 vstr s15, [r7, #28] break; 8002daa: e065 b.n 8002e78 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 8002dac: 693b ldr r3, [r7, #16] 8002dae: ee07 3a90 vmov s15, r3 8002db2: eef8 7a67 vcvt.f32.u32 s15, s15 8002db6: eddf 6a48 vldr s13, [pc, #288] ; 8002ed8 8002dba: ee86 7aa7 vdiv.f32 s14, s13, s15 8002dbe: 4b40 ldr r3, [pc, #256] ; (8002ec0 ) 8002dc0: 6b1b ldr r3, [r3, #48] ; 0x30 8002dc2: f3c3 0308 ubfx r3, r3, #0, #9 8002dc6: ee07 3a90 vmov s15, r3 8002dca: eef8 6a67 vcvt.f32.u32 s13, s15 8002dce: ed97 6a02 vldr s12, [r7, #8] 8002dd2: eddf 5a3f vldr s11, [pc, #252] ; 8002ed0 8002dd6: eec6 7a25 vdiv.f32 s15, s12, s11 8002dda: ee76 7aa7 vadd.f32 s15, s13, s15 8002dde: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8002de2: ee77 7aa6 vadd.f32 s15, s15, s13 8002de6: ee67 7a27 vmul.f32 s15, s14, s15 8002dea: edc7 7a07 vstr s15, [r7, #28] break; 8002dee: e043 b.n 8002e78 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 8002df0: 693b ldr r3, [r7, #16] 8002df2: ee07 3a90 vmov s15, r3 8002df6: eef8 7a67 vcvt.f32.u32 s15, s15 8002dfa: eddf 6a38 vldr s13, [pc, #224] ; 8002edc 8002dfe: ee86 7aa7 vdiv.f32 s14, s13, s15 8002e02: 4b2f ldr r3, [pc, #188] ; (8002ec0 ) 8002e04: 6b1b ldr r3, [r3, #48] ; 0x30 8002e06: f3c3 0308 ubfx r3, r3, #0, #9 8002e0a: ee07 3a90 vmov s15, r3 8002e0e: eef8 6a67 vcvt.f32.u32 s13, s15 8002e12: ed97 6a02 vldr s12, [r7, #8] 8002e16: eddf 5a2e vldr s11, [pc, #184] ; 8002ed0 8002e1a: eec6 7a25 vdiv.f32 s15, s12, s11 8002e1e: ee76 7aa7 vadd.f32 s15, s13, s15 8002e22: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8002e26: ee77 7aa6 vadd.f32 s15, s15, s13 8002e2a: ee67 7a27 vmul.f32 s15, s14, s15 8002e2e: edc7 7a07 vstr s15, [r7, #28] break; 8002e32: e021 b.n 8002e78 default: pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 8002e34: 693b ldr r3, [r7, #16] 8002e36: ee07 3a90 vmov s15, r3 8002e3a: eef8 7a67 vcvt.f32.u32 s15, s15 8002e3e: eddf 6a26 vldr s13, [pc, #152] ; 8002ed8 8002e42: ee86 7aa7 vdiv.f32 s14, s13, s15 8002e46: 4b1e ldr r3, [pc, #120] ; (8002ec0 ) 8002e48: 6b1b ldr r3, [r3, #48] ; 0x30 8002e4a: f3c3 0308 ubfx r3, r3, #0, #9 8002e4e: ee07 3a90 vmov s15, r3 8002e52: eef8 6a67 vcvt.f32.u32 s13, s15 8002e56: ed97 6a02 vldr s12, [r7, #8] 8002e5a: eddf 5a1d vldr s11, [pc, #116] ; 8002ed0 8002e5e: eec6 7a25 vdiv.f32 s15, s12, s11 8002e62: ee76 7aa7 vadd.f32 s15, s13, s15 8002e66: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8002e6a: ee77 7aa6 vadd.f32 s15, s15, s13 8002e6e: ee67 7a27 vmul.f32 s15, s14, s15 8002e72: edc7 7a07 vstr s15, [r7, #28] break; 8002e76: bf00 nop } pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; 8002e78: 4b11 ldr r3, [pc, #68] ; (8002ec0 ) 8002e7a: 6b1b ldr r3, [r3, #48] ; 0x30 8002e7c: 0a5b lsrs r3, r3, #9 8002e7e: f003 037f and.w r3, r3, #127 ; 0x7f 8002e82: 3301 adds r3, #1 8002e84: 603b str r3, [r7, #0] sysclockfreq = (uint32_t)(float_t)(pllvco/(float_t)pllp); 8002e86: 683b ldr r3, [r7, #0] 8002e88: ee07 3a90 vmov s15, r3 8002e8c: eeb8 7a67 vcvt.f32.u32 s14, s15 8002e90: edd7 6a07 vldr s13, [r7, #28] 8002e94: eec6 7a87 vdiv.f32 s15, s13, s14 8002e98: eefc 7ae7 vcvt.u32.f32 s15, s15 8002e9c: ee17 3a90 vmov r3, s15 8002ea0: 61bb str r3, [r7, #24] } else { sysclockfreq = 0U; } break; 8002ea2: e005 b.n 8002eb0 sysclockfreq = 0U; 8002ea4: 2300 movs r3, #0 8002ea6: 61bb str r3, [r7, #24] break; 8002ea8: e002 b.n 8002eb0 default: sysclockfreq = CSI_VALUE; 8002eaa: 4b07 ldr r3, [pc, #28] ; (8002ec8 ) 8002eac: 61bb str r3, [r7, #24] break; 8002eae: bf00 nop } return sysclockfreq; 8002eb0: 69bb ldr r3, [r7, #24] } 8002eb2: 4618 mov r0, r3 8002eb4: 3724 adds r7, #36 ; 0x24 8002eb6: 46bd mov sp, r7 8002eb8: f85d 7b04 ldr.w r7, [sp], #4 8002ebc: 4770 bx lr 8002ebe: bf00 nop 8002ec0: 58024400 .word 0x58024400 8002ec4: 03d09000 .word 0x03d09000 8002ec8: 003d0900 .word 0x003d0900 8002ecc: 007a1200 .word 0x007a1200 8002ed0: 46000000 .word 0x46000000 8002ed4: 4c742400 .word 0x4c742400 8002ed8: 4a742400 .word 0x4a742400 8002edc: 4af42400 .word 0x4af42400 08002ee0 : * @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8002ee0: b580 push {r7, lr} 8002ee2: b082 sub sp, #8 8002ee4: af00 add r7, sp, #0 uint32_t common_system_clock; #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); #else common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); 8002ee6: f7ff fe81 bl 8002bec 8002eea: 4602 mov r2, r0 8002eec: 4b10 ldr r3, [pc, #64] ; (8002f30 ) 8002eee: 699b ldr r3, [r3, #24] 8002ef0: 0a1b lsrs r3, r3, #8 8002ef2: f003 030f and.w r3, r3, #15 8002ef6: 490f ldr r1, [pc, #60] ; (8002f34 ) 8002ef8: 5ccb ldrb r3, [r1, r3] 8002efa: f003 031f and.w r3, r3, #31 8002efe: fa22 f303 lsr.w r3, r2, r3 8002f02: 607b str r3, [r7, #4] #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); #else SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); 8002f04: 4b0a ldr r3, [pc, #40] ; (8002f30 ) 8002f06: 699b ldr r3, [r3, #24] 8002f08: f003 030f and.w r3, r3, #15 8002f0c: 4a09 ldr r2, [pc, #36] ; (8002f34 ) 8002f0e: 5cd3 ldrb r3, [r2, r3] 8002f10: f003 031f and.w r3, r3, #31 8002f14: 687a ldr r2, [r7, #4] 8002f16: fa22 f303 lsr.w r3, r2, r3 8002f1a: 4a07 ldr r2, [pc, #28] ; (8002f38 ) 8002f1c: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 8002f1e: 4a07 ldr r2, [pc, #28] ; (8002f3c ) 8002f20: 687b ldr r3, [r7, #4] 8002f22: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ return SystemD2Clock; 8002f24: 4b04 ldr r3, [pc, #16] ; (8002f38 ) 8002f26: 681b ldr r3, [r3, #0] } 8002f28: 4618 mov r0, r3 8002f2a: 3708 adds r7, #8 8002f2c: 46bd mov sp, r7 8002f2e: bd80 pop {r7, pc} 8002f30: 58024400 .word 0x58024400 8002f34: 08007278 .word 0x08007278 8002f38: 24000018 .word 0x24000018 8002f3c: 24000014 .word 0x24000014 08002f40 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8002f40: b580 push {r7, lr} 8002f42: af00 add r7, sp, #0 #if defined (RCC_D2CFGR_D2PPRE1) /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)>> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU)); #else /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)>> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU)); 8002f44: f7ff ffcc bl 8002ee0 8002f48: 4602 mov r2, r0 8002f4a: 4b06 ldr r3, [pc, #24] ; (8002f64 ) 8002f4c: 69db ldr r3, [r3, #28] 8002f4e: 091b lsrs r3, r3, #4 8002f50: f003 0307 and.w r3, r3, #7 8002f54: 4904 ldr r1, [pc, #16] ; (8002f68 ) 8002f56: 5ccb ldrb r3, [r1, r3] 8002f58: f003 031f and.w r3, r3, #31 8002f5c: fa22 f303 lsr.w r3, r2, r3 #endif } 8002f60: 4618 mov r0, r3 8002f62: bd80 pop {r7, pc} 8002f64: 58024400 .word 0x58024400 8002f68: 08007278 .word 0x08007278 08002f6c : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8002f6c: b580 push {r7, lr} 8002f6e: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ #if defined(RCC_D2CFGR_D2PPRE2) return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)>> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU)); #else return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)>> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU)); 8002f70: f7ff ffb6 bl 8002ee0 8002f74: 4602 mov r2, r0 8002f76: 4b06 ldr r3, [pc, #24] ; (8002f90 ) 8002f78: 69db ldr r3, [r3, #28] 8002f7a: 0a1b lsrs r3, r3, #8 8002f7c: f003 0307 and.w r3, r3, #7 8002f80: 4904 ldr r1, [pc, #16] ; (8002f94 ) 8002f82: 5ccb ldrb r3, [r1, r3] 8002f84: f003 031f and.w r3, r3, #31 8002f88: fa22 f303 lsr.w r3, r2, r3 #endif } 8002f8c: 4618 mov r0, r3 8002f8e: bd80 pop {r7, pc} 8002f90: 58024400 .word 0x58024400 8002f94: 08007278 .word 0x08007278 08002f98 : * (*) : Available on some STM32H7 lines only. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8002f98: b580 push {r7, lr} 8002f9a: b086 sub sp, #24 8002f9c: af00 add r7, sp, #0 8002f9e: 6078 str r0, [r7, #4] uint32_t tmpreg; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 8002fa0: 2300 movs r3, #0 8002fa2: 75fb strb r3, [r7, #23] HAL_StatusTypeDef status = HAL_OK; /* Final status */ 8002fa4: 2300 movs r3, #0 8002fa6: 75bb strb r3, [r7, #22] /*---------------------------- SPDIFRX configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 8002fa8: 687b ldr r3, [r7, #4] 8002faa: 681b ldr r3, [r3, #0] 8002fac: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8002fb0: 2b00 cmp r3, #0 8002fb2: d03f beq.n 8003034 { switch(PeriphClkInit->SpdifrxClockSelection) 8002fb4: 687b ldr r3, [r7, #4] 8002fb6: 6e9b ldr r3, [r3, #104] ; 0x68 8002fb8: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000 8002fbc: d02a beq.n 8003014 8002fbe: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000 8002fc2: d824 bhi.n 800300e 8002fc4: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 8002fc8: d018 beq.n 8002ffc 8002fca: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 8002fce: d81e bhi.n 800300e 8002fd0: 2b00 cmp r3, #0 8002fd2: d003 beq.n 8002fdc 8002fd4: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 8002fd8: d007 beq.n 8002fea 8002fda: e018 b.n 800300e { case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/ /* Enable PLL1Q Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8002fdc: 4ba6 ldr r3, [pc, #664] ; (8003278 ) 8002fde: 6adb ldr r3, [r3, #44] ; 0x2c 8002fe0: 4aa5 ldr r2, [pc, #660] ; (8003278 ) 8002fe2: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8002fe6: 62d3 str r3, [r2, #44] ; 0x2c /* SPDIFRX clock source configuration done later after clock selection check */ break; 8002fe8: e015 b.n 8003016 case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); 8002fea: 687b ldr r3, [r7, #4] 8002fec: 3304 adds r3, #4 8002fee: 2102 movs r1, #2 8002ff0: 4618 mov r0, r3 8002ff2: f001 f99b bl 800432c 8002ff6: 4603 mov r3, r0 8002ff8: 75fb strb r3, [r7, #23] /* SPDIFRX clock source configuration done later after clock selection check */ break; 8002ffa: e00c b.n 8003016 case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 8002ffc: 687b ldr r3, [r7, #4] 8002ffe: 3324 adds r3, #36 ; 0x24 8003000: 2102 movs r1, #2 8003002: 4618 mov r0, r3 8003004: f001 fa44 bl 8004490 8003008: 4603 mov r3, r0 800300a: 75fb strb r3, [r7, #23] /* SPDIFRX clock source configuration done later after clock selection check */ break; 800300c: e003 b.n 8003016 /* Internal OSC clock is used as source of SPDIFRX clock*/ /* SPDIFRX clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800300e: 2301 movs r3, #1 8003010: 75fb strb r3, [r7, #23] break; 8003012: e000 b.n 8003016 break; 8003014: bf00 nop } if(ret == HAL_OK) 8003016: 7dfb ldrb r3, [r7, #23] 8003018: 2b00 cmp r3, #0 800301a: d109 bne.n 8003030 { /* Set the source of SPDIFRX clock*/ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); 800301c: 4b96 ldr r3, [pc, #600] ; (8003278 ) 800301e: 6d1b ldr r3, [r3, #80] ; 0x50 8003020: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 8003024: 687b ldr r3, [r7, #4] 8003026: 6e9b ldr r3, [r3, #104] ; 0x68 8003028: 4993 ldr r1, [pc, #588] ; (8003278 ) 800302a: 4313 orrs r3, r2 800302c: 650b str r3, [r1, #80] ; 0x50 800302e: e001 b.n 8003034 } else { /* set overall return value */ status = ret; 8003030: 7dfb ldrb r3, [r7, #23] 8003032: 75bb strb r3, [r7, #22] } } /*---------------------------- SAI1 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 8003034: 687b ldr r3, [r7, #4] 8003036: 681b ldr r3, [r3, #0] 8003038: f403 7380 and.w r3, r3, #256 ; 0x100 800303c: 2b00 cmp r3, #0 800303e: d03d beq.n 80030bc { switch(PeriphClkInit->Sai1ClockSelection) 8003040: 687b ldr r3, [r7, #4] 8003042: 6d5b ldr r3, [r3, #84] ; 0x54 8003044: 2b04 cmp r3, #4 8003046: d826 bhi.n 8003096 8003048: a201 add r2, pc, #4 ; (adr r2, 8003050 ) 800304a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800304e: bf00 nop 8003050: 08003065 .word 0x08003065 8003054: 08003073 .word 0x08003073 8003058: 08003085 .word 0x08003085 800305c: 0800309d .word 0x0800309d 8003060: 0800309d .word 0x0800309d { case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8003064: 4b84 ldr r3, [pc, #528] ; (8003278 ) 8003066: 6adb ldr r3, [r3, #44] ; 0x2c 8003068: 4a83 ldr r2, [pc, #524] ; (8003278 ) 800306a: f443 3300 orr.w r3, r3, #131072 ; 0x20000 800306e: 62d3 str r3, [r2, #44] ; 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 8003070: e015 b.n 800309e case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 8003072: 687b ldr r3, [r7, #4] 8003074: 3304 adds r3, #4 8003076: 2100 movs r1, #0 8003078: 4618 mov r0, r3 800307a: f001 f957 bl 800432c 800307e: 4603 mov r3, r0 8003080: 75fb strb r3, [r7, #23] /* SAI1 clock source configuration done later after clock selection check */ break; 8003082: e00c b.n 800309e case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); 8003084: 687b ldr r3, [r7, #4] 8003086: 3324 adds r3, #36 ; 0x24 8003088: 2100 movs r1, #0 800308a: 4618 mov r0, r3 800308c: f001 fa00 bl 8004490 8003090: 4603 mov r3, r0 8003092: 75fb strb r3, [r7, #23] /* SAI1 clock source configuration done later after clock selection check */ break; 8003094: e003 b.n 800309e /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */ /* SAI1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8003096: 2301 movs r3, #1 8003098: 75fb strb r3, [r7, #23] break; 800309a: e000 b.n 800309e break; 800309c: bf00 nop } if(ret == HAL_OK) 800309e: 7dfb ldrb r3, [r7, #23] 80030a0: 2b00 cmp r3, #0 80030a2: d109 bne.n 80030b8 { /* Set the source of SAI1 clock*/ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 80030a4: 4b74 ldr r3, [pc, #464] ; (8003278 ) 80030a6: 6d1b ldr r3, [r3, #80] ; 0x50 80030a8: f023 0207 bic.w r2, r3, #7 80030ac: 687b ldr r3, [r7, #4] 80030ae: 6d5b ldr r3, [r3, #84] ; 0x54 80030b0: 4971 ldr r1, [pc, #452] ; (8003278 ) 80030b2: 4313 orrs r3, r2 80030b4: 650b str r3, [r1, #80] ; 0x50 80030b6: e001 b.n 80030bc } else { /* set overall return value */ status = ret; 80030b8: 7dfb ldrb r3, [r7, #23] 80030ba: 75bb strb r3, [r7, #22] #endif /* SAI3 */ #if defined(RCC_CDCCIP1R_SAI2ASEL) /*---------------------------- SAI2A configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2A) == RCC_PERIPHCLK_SAI2A) 80030bc: 687b ldr r3, [r7, #4] 80030be: 681b ldr r3, [r3, #0] 80030c0: f403 7300 and.w r3, r3, #512 ; 0x200 80030c4: 2b00 cmp r3, #0 80030c6: d04a beq.n 800315e { switch(PeriphClkInit->Sai2AClockSelection) 80030c8: 687b ldr r3, [r7, #4] 80030ca: 6d9b ldr r3, [r3, #88] ; 0x58 80030cc: f5b3 7fa0 cmp.w r3, #320 ; 0x140 80030d0: d031 beq.n 8003136 80030d2: f5b3 7fa0 cmp.w r3, #320 ; 0x140 80030d6: d82b bhi.n 8003130 80030d8: f5b3 7f80 cmp.w r3, #256 ; 0x100 80030dc: d02d beq.n 800313a 80030de: f5b3 7f80 cmp.w r3, #256 ; 0x100 80030e2: d825 bhi.n 8003130 80030e4: 2bc0 cmp r3, #192 ; 0xc0 80030e6: d02a beq.n 800313e 80030e8: 2bc0 cmp r3, #192 ; 0xc0 80030ea: d821 bhi.n 8003130 80030ec: 2b80 cmp r3, #128 ; 0x80 80030ee: d016 beq.n 800311e 80030f0: 2b80 cmp r3, #128 ; 0x80 80030f2: d81d bhi.n 8003130 80030f4: 2b00 cmp r3, #0 80030f6: d002 beq.n 80030fe 80030f8: 2b40 cmp r3, #64 ; 0x40 80030fa: d007 beq.n 800310c 80030fc: e018 b.n 8003130 { case RCC_SAI2ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2A */ /* Enable SAI2A Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80030fe: 4b5e ldr r3, [pc, #376] ; (8003278 ) 8003100: 6adb ldr r3, [r3, #44] ; 0x2c 8003102: 4a5d ldr r2, [pc, #372] ; (8003278 ) 8003104: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8003108: 62d3 str r3, [r2, #44] ; 0x2c /* SAI2A clock source configuration done later after clock selection check */ break; 800310a: e019 b.n 8003140 case RCC_SAI2ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2A */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 800310c: 687b ldr r3, [r7, #4] 800310e: 3304 adds r3, #4 8003110: 2100 movs r1, #0 8003112: 4618 mov r0, r3 8003114: f001 f90a bl 800432c 8003118: 4603 mov r3, r0 800311a: 75fb strb r3, [r7, #23] /* SAI2A clock source configuration done later after clock selection check */ break; 800311c: e010 b.n 8003140 case RCC_SAI2ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2A */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); 800311e: 687b ldr r3, [r7, #4] 8003120: 3324 adds r3, #36 ; 0x24 8003122: 2100 movs r1, #0 8003124: 4618 mov r0, r3 8003126: f001 f9b3 bl 8004490 800312a: 4603 mov r3, r0 800312c: 75fb strb r3, [r7, #23] /* SAI2A clock source configuration done later after clock selection check */ break; 800312e: e007 b.n 8003140 /* SPDIF clock is used as source of SAI2A clock */ /* SAI2A clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8003130: 2301 movs r3, #1 8003132: 75fb strb r3, [r7, #23] break; 8003134: e004 b.n 8003140 break; 8003136: bf00 nop 8003138: e002 b.n 8003140 break; 800313a: bf00 nop 800313c: e000 b.n 8003140 break; 800313e: bf00 nop } if(ret == HAL_OK) 8003140: 7dfb ldrb r3, [r7, #23] 8003142: 2b00 cmp r3, #0 8003144: d109 bne.n 800315a { /* Set the source of SAI2A clock*/ __HAL_RCC_SAI2A_CONFIG(PeriphClkInit->Sai2AClockSelection); 8003146: 4b4c ldr r3, [pc, #304] ; (8003278 ) 8003148: 6d1b ldr r3, [r3, #80] ; 0x50 800314a: f423 72e0 bic.w r2, r3, #448 ; 0x1c0 800314e: 687b ldr r3, [r7, #4] 8003150: 6d9b ldr r3, [r3, #88] ; 0x58 8003152: 4949 ldr r1, [pc, #292] ; (8003278 ) 8003154: 4313 orrs r3, r2 8003156: 650b str r3, [r1, #80] ; 0x50 8003158: e001 b.n 800315e } else { /* set overall return value */ status = ret; 800315a: 7dfb ldrb r3, [r7, #23] 800315c: 75bb strb r3, [r7, #22] #endif /*SAI2A*/ #if defined(RCC_CDCCIP1R_SAI2BSEL) /*---------------------------- SAI2B configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2B) == RCC_PERIPHCLK_SAI2B) 800315e: 687b ldr r3, [r7, #4] 8003160: 681b ldr r3, [r3, #0] 8003162: f403 6380 and.w r3, r3, #1024 ; 0x400 8003166: 2b00 cmp r3, #0 8003168: d04f beq.n 800320a { switch(PeriphClkInit->Sai2BClockSelection) 800316a: 687b ldr r3, [r7, #4] 800316c: 6ddb ldr r3, [r3, #92] ; 0x5c 800316e: f5b3 6f20 cmp.w r3, #2560 ; 0xa00 8003172: d036 beq.n 80031e2 8003174: f5b3 6f20 cmp.w r3, #2560 ; 0xa00 8003178: d830 bhi.n 80031dc 800317a: f5b3 6f00 cmp.w r3, #2048 ; 0x800 800317e: d032 beq.n 80031e6 8003180: f5b3 6f00 cmp.w r3, #2048 ; 0x800 8003184: d82a bhi.n 80031dc 8003186: f5b3 6fc0 cmp.w r3, #1536 ; 0x600 800318a: d02e beq.n 80031ea 800318c: f5b3 6fc0 cmp.w r3, #1536 ; 0x600 8003190: d824 bhi.n 80031dc 8003192: f5b3 6f80 cmp.w r3, #1024 ; 0x400 8003196: d018 beq.n 80031ca 8003198: f5b3 6f80 cmp.w r3, #1024 ; 0x400 800319c: d81e bhi.n 80031dc 800319e: 2b00 cmp r3, #0 80031a0: d003 beq.n 80031aa 80031a2: f5b3 7f00 cmp.w r3, #512 ; 0x200 80031a6: d007 beq.n 80031b8 80031a8: e018 b.n 80031dc { case RCC_SAI2BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2B */ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80031aa: 4b33 ldr r3, [pc, #204] ; (8003278 ) 80031ac: 6adb ldr r3, [r3, #44] ; 0x2c 80031ae: 4a32 ldr r2, [pc, #200] ; (8003278 ) 80031b0: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80031b4: 62d3 str r3, [r2, #44] ; 0x2c /* SAI2B clock source configuration done later after clock selection check */ break; 80031b6: e019 b.n 80031ec case RCC_SAI2BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2B */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 80031b8: 687b ldr r3, [r7, #4] 80031ba: 3304 adds r3, #4 80031bc: 2100 movs r1, #0 80031be: 4618 mov r0, r3 80031c0: f001 f8b4 bl 800432c 80031c4: 4603 mov r3, r0 80031c6: 75fb strb r3, [r7, #23] /* SAI2B clock source configuration done later after clock selection check */ break; 80031c8: e010 b.n 80031ec case RCC_SAI2BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2B */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); 80031ca: 687b ldr r3, [r7, #4] 80031cc: 3324 adds r3, #36 ; 0x24 80031ce: 2100 movs r1, #0 80031d0: 4618 mov r0, r3 80031d2: f001 f95d bl 8004490 80031d6: 4603 mov r3, r0 80031d8: 75fb strb r3, [r7, #23] /* SAI2B clock source configuration done later after clock selection check */ break; 80031da: e007 b.n 80031ec /* SPDIF clock is used as source of SAI2B clock */ /* SAI2B clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80031dc: 2301 movs r3, #1 80031de: 75fb strb r3, [r7, #23] break; 80031e0: e004 b.n 80031ec break; 80031e2: bf00 nop 80031e4: e002 b.n 80031ec break; 80031e6: bf00 nop 80031e8: e000 b.n 80031ec break; 80031ea: bf00 nop } if(ret == HAL_OK) 80031ec: 7dfb ldrb r3, [r7, #23] 80031ee: 2b00 cmp r3, #0 80031f0: d109 bne.n 8003206 { /* Set the source of SAI2B clock*/ __HAL_RCC_SAI2B_CONFIG(PeriphClkInit->Sai2BClockSelection); 80031f2: 4b21 ldr r3, [pc, #132] ; (8003278 ) 80031f4: 6d1b ldr r3, [r3, #80] ; 0x50 80031f6: f423 6260 bic.w r2, r3, #3584 ; 0xe00 80031fa: 687b ldr r3, [r7, #4] 80031fc: 6ddb ldr r3, [r3, #92] ; 0x5c 80031fe: 491e ldr r1, [pc, #120] ; (8003278 ) 8003200: 4313 orrs r3, r2 8003202: 650b str r3, [r1, #80] ; 0x50 8003204: e001 b.n 800320a } else { /* set overall return value */ status = ret; 8003206: 7dfb ldrb r3, [r7, #23] 8003208: 75bb strb r3, [r7, #22] } #endif /*QUADSPI*/ #if defined(OCTOSPI1) || defined(OCTOSPI2) /*---------------------------- OCTOSPI configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) 800320a: 687b ldr r3, [r7, #4] 800320c: 681b ldr r3, [r3, #0] 800320e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8003212: 2b00 cmp r3, #0 8003214: d034 beq.n 8003280 { switch(PeriphClkInit->OspiClockSelection) 8003216: 687b ldr r3, [r7, #4] 8003218: 6c9b ldr r3, [r3, #72] ; 0x48 800321a: 2b30 cmp r3, #48 ; 0x30 800321c: d01c beq.n 8003258 800321e: 2b30 cmp r3, #48 ; 0x30 8003220: d817 bhi.n 8003252 8003222: 2b20 cmp r3, #32 8003224: d00c beq.n 8003240 8003226: 2b20 cmp r3, #32 8003228: d813 bhi.n 8003252 800322a: 2b00 cmp r3, #0 800322c: d016 beq.n 800325c 800322e: 2b10 cmp r3, #16 8003230: d10f bne.n 8003252 { case RCC_OSPICLKSOURCE_PLL: /* PLL is used as clock source for OSPI*/ /* Enable OSPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8003232: 4b11 ldr r3, [pc, #68] ; (8003278 ) 8003234: 6adb ldr r3, [r3, #44] ; 0x2c 8003236: 4a10 ldr r2, [pc, #64] ; (8003278 ) 8003238: f443 3300 orr.w r3, r3, #131072 ; 0x20000 800323c: 62d3 str r3, [r2, #44] ; 0x2c /* OSPI clock source configuration done later after clock selection check */ break; 800323e: e00e b.n 800325e case RCC_OSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for OSPI*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); 8003240: 687b ldr r3, [r7, #4] 8003242: 3304 adds r3, #4 8003244: 2102 movs r1, #2 8003246: 4618 mov r0, r3 8003248: f001 f870 bl 800432c 800324c: 4603 mov r3, r0 800324e: 75fb strb r3, [r7, #23] /* OSPI clock source configuration done later after clock selection check */ break; 8003250: e005 b.n 800325e case RCC_OSPICLKSOURCE_HCLK: /* HCLK clock selected as OSPI kernel peripheral clock */ break; default: ret = HAL_ERROR; 8003252: 2301 movs r3, #1 8003254: 75fb strb r3, [r7, #23] break; 8003256: e002 b.n 800325e break; 8003258: bf00 nop 800325a: e000 b.n 800325e break; 800325c: bf00 nop } if(ret == HAL_OK) 800325e: 7dfb ldrb r3, [r7, #23] 8003260: 2b00 cmp r3, #0 8003262: d10b bne.n 800327c { /* Set the source of OSPI clock*/ __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection); 8003264: 4b04 ldr r3, [pc, #16] ; (8003278 ) 8003266: 6cdb ldr r3, [r3, #76] ; 0x4c 8003268: f023 0230 bic.w r2, r3, #48 ; 0x30 800326c: 687b ldr r3, [r7, #4] 800326e: 6c9b ldr r3, [r3, #72] ; 0x48 8003270: 4901 ldr r1, [pc, #4] ; (8003278 ) 8003272: 4313 orrs r3, r2 8003274: 64cb str r3, [r1, #76] ; 0x4c 8003276: e003 b.n 8003280 8003278: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 800327c: 7dfb ldrb r3, [r7, #23] 800327e: 75bb strb r3, [r7, #22] } } #endif /*OCTOSPI*/ /*---------------------------- SPI1/2/3 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) 8003280: 687b ldr r3, [r7, #4] 8003282: 681b ldr r3, [r3, #0] 8003284: f403 5380 and.w r3, r3, #4096 ; 0x1000 8003288: 2b00 cmp r3, #0 800328a: d047 beq.n 800331c { switch(PeriphClkInit->Spi123ClockSelection) 800328c: 687b ldr r3, [r7, #4] 800328e: 6e1b ldr r3, [r3, #96] ; 0x60 8003290: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 8003294: d030 beq.n 80032f8 8003296: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 800329a: d82a bhi.n 80032f2 800329c: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 80032a0: d02c beq.n 80032fc 80032a2: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 80032a6: d824 bhi.n 80032f2 80032a8: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 80032ac: d018 beq.n 80032e0 80032ae: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 80032b2: d81e bhi.n 80032f2 80032b4: 2b00 cmp r3, #0 80032b6: d003 beq.n 80032c0 80032b8: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 80032bc: d007 beq.n 80032ce 80032be: e018 b.n 80032f2 { case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */ /* Enable SPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80032c0: 4bb0 ldr r3, [pc, #704] ; (8003584 ) 80032c2: 6adb ldr r3, [r3, #44] ; 0x2c 80032c4: 4aaf ldr r2, [pc, #700] ; (8003584 ) 80032c6: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80032ca: 62d3 str r3, [r2, #44] ; 0x2c /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 80032cc: e017 b.n 80032fe case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 80032ce: 687b ldr r3, [r7, #4] 80032d0: 3304 adds r3, #4 80032d2: 2100 movs r1, #0 80032d4: 4618 mov r0, r3 80032d6: f001 f829 bl 800432c 80032da: 4603 mov r3, r0 80032dc: 75fb strb r3, [r7, #23] /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 80032de: e00e b.n 80032fe case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); 80032e0: 687b ldr r3, [r7, #4] 80032e2: 3324 adds r3, #36 ; 0x24 80032e4: 2100 movs r1, #0 80032e6: 4618 mov r0, r3 80032e8: f001 f8d2 bl 8004490 80032ec: 4603 mov r3, r0 80032ee: 75fb strb r3, [r7, #23] /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 80032f0: e005 b.n 80032fe /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */ /* SPI1/2/3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80032f2: 2301 movs r3, #1 80032f4: 75fb strb r3, [r7, #23] break; 80032f6: e002 b.n 80032fe break; 80032f8: bf00 nop 80032fa: e000 b.n 80032fe break; 80032fc: bf00 nop } if(ret == HAL_OK) 80032fe: 7dfb ldrb r3, [r7, #23] 8003300: 2b00 cmp r3, #0 8003302: d109 bne.n 8003318 { /* Set the source of SPI1/2/3 clock*/ __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection); 8003304: 4b9f ldr r3, [pc, #636] ; (8003584 ) 8003306: 6d1b ldr r3, [r3, #80] ; 0x50 8003308: f423 42e0 bic.w r2, r3, #28672 ; 0x7000 800330c: 687b ldr r3, [r7, #4] 800330e: 6e1b ldr r3, [r3, #96] ; 0x60 8003310: 499c ldr r1, [pc, #624] ; (8003584 ) 8003312: 4313 orrs r3, r2 8003314: 650b str r3, [r1, #80] ; 0x50 8003316: e001 b.n 800331c } else { /* set overall return value */ status = ret; 8003318: 7dfb ldrb r3, [r7, #23] 800331a: 75bb strb r3, [r7, #22] } } /*---------------------------- SPI4/5 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) 800331c: 687b ldr r3, [r7, #4] 800331e: 681b ldr r3, [r3, #0] 8003320: f403 5300 and.w r3, r3, #8192 ; 0x2000 8003324: 2b00 cmp r3, #0 8003326: d049 beq.n 80033bc { switch(PeriphClkInit->Spi45ClockSelection) 8003328: 687b ldr r3, [r7, #4] 800332a: 6e5b ldr r3, [r3, #100] ; 0x64 800332c: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8003330: d02e beq.n 8003390 8003332: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8003336: d828 bhi.n 800338a 8003338: f5b3 2f80 cmp.w r3, #262144 ; 0x40000 800333c: d02a beq.n 8003394 800333e: f5b3 2f80 cmp.w r3, #262144 ; 0x40000 8003342: d822 bhi.n 800338a 8003344: f5b3 3f40 cmp.w r3, #196608 ; 0x30000 8003348: d026 beq.n 8003398 800334a: f5b3 3f40 cmp.w r3, #196608 ; 0x30000 800334e: d81c bhi.n 800338a 8003350: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 8003354: d010 beq.n 8003378 8003356: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 800335a: d816 bhi.n 800338a 800335c: 2b00 cmp r3, #0 800335e: d01d beq.n 800339c 8003360: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8003364: d111 bne.n 800338a /* SPI4/5 clock source configuration done later after clock selection check */ break; case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 8003366: 687b ldr r3, [r7, #4] 8003368: 3304 adds r3, #4 800336a: 2101 movs r1, #1 800336c: 4618 mov r0, r3 800336e: f000 ffdd bl 800432c 8003372: 4603 mov r3, r0 8003374: 75fb strb r3, [r7, #23] /* SPI4/5 clock source configuration done later after clock selection check */ break; 8003376: e012 b.n 800339e case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 8003378: 687b ldr r3, [r7, #4] 800337a: 3324 adds r3, #36 ; 0x24 800337c: 2101 movs r1, #1 800337e: 4618 mov r0, r3 8003380: f001 f886 bl 8004490 8003384: 4603 mov r3, r0 8003386: 75fb strb r3, [r7, #23] /* SPI4/5 clock source configuration done later after clock selection check */ break; 8003388: e009 b.n 800339e /* HSE, oscillator is used as source of SPI4/5 clock */ /* SPI4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800338a: 2301 movs r3, #1 800338c: 75fb strb r3, [r7, #23] break; 800338e: e006 b.n 800339e break; 8003390: bf00 nop 8003392: e004 b.n 800339e break; 8003394: bf00 nop 8003396: e002 b.n 800339e break; 8003398: bf00 nop 800339a: e000 b.n 800339e break; 800339c: bf00 nop } if(ret == HAL_OK) 800339e: 7dfb ldrb r3, [r7, #23] 80033a0: 2b00 cmp r3, #0 80033a2: d109 bne.n 80033b8 { /* Set the source of SPI4/5 clock*/ __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection); 80033a4: 4b77 ldr r3, [pc, #476] ; (8003584 ) 80033a6: 6d1b ldr r3, [r3, #80] ; 0x50 80033a8: f423 22e0 bic.w r2, r3, #458752 ; 0x70000 80033ac: 687b ldr r3, [r7, #4] 80033ae: 6e5b ldr r3, [r3, #100] ; 0x64 80033b0: 4974 ldr r1, [pc, #464] ; (8003584 ) 80033b2: 4313 orrs r3, r2 80033b4: 650b str r3, [r1, #80] ; 0x50 80033b6: e001 b.n 80033bc } else { /* set overall return value */ status = ret; 80033b8: 7dfb ldrb r3, [r7, #23] 80033ba: 75bb strb r3, [r7, #22] } } /*---------------------------- SPI6 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) 80033bc: 687b ldr r3, [r7, #4] 80033be: 681b ldr r3, [r3, #0] 80033c0: f403 4380 and.w r3, r3, #16384 ; 0x4000 80033c4: 2b00 cmp r3, #0 80033c6: d053 beq.n 8003470 { switch(PeriphClkInit->Spi6ClockSelection) 80033c8: 687b ldr r3, [r7, #4] 80033ca: f8d3 30ac ldr.w r3, [r3, #172] ; 0xac 80033ce: f1b3 4fc0 cmp.w r3, #1610612736 ; 0x60000000 80033d2: d034 beq.n 800343e 80033d4: f1b3 4fc0 cmp.w r3, #1610612736 ; 0x60000000 80033d8: d82e bhi.n 8003438 80033da: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 80033de: d030 beq.n 8003442 80033e0: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 80033e4: d828 bhi.n 8003438 80033e6: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 80033ea: d02c beq.n 8003446 80033ec: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 80033f0: d822 bhi.n 8003438 80033f2: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 80033f6: d028 beq.n 800344a 80033f8: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 80033fc: d81c bhi.n 8003438 80033fe: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8003402: d010 beq.n 8003426 8003404: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8003408: d816 bhi.n 8003438 800340a: 2b00 cmp r3, #0 800340c: d01f beq.n 800344e 800340e: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 8003412: d111 bne.n 8003438 /* SPI6 clock source configuration done later after clock selection check */ break; case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 8003414: 687b ldr r3, [r7, #4] 8003416: 3304 adds r3, #4 8003418: 2101 movs r1, #1 800341a: 4618 mov r0, r3 800341c: f000 ff86 bl 800432c 8003420: 4603 mov r3, r0 8003422: 75fb strb r3, [r7, #23] /* SPI6 clock source configuration done later after clock selection check */ break; 8003424: e014 b.n 8003450 case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 8003426: 687b ldr r3, [r7, #4] 8003428: 3324 adds r3, #36 ; 0x24 800342a: 2101 movs r1, #1 800342c: 4618 mov r0, r3 800342e: f001 f82f bl 8004490 8003432: 4603 mov r3, r0 8003434: 75fb strb r3, [r7, #23] /* SPI6 clock source configuration done later after clock selection check */ break; 8003436: e00b b.n 8003450 /* SPI6 clock source configuration done later after clock selection check */ break; #endif default: ret = HAL_ERROR; 8003438: 2301 movs r3, #1 800343a: 75fb strb r3, [r7, #23] break; 800343c: e008 b.n 8003450 break; 800343e: bf00 nop 8003440: e006 b.n 8003450 break; 8003442: bf00 nop 8003444: e004 b.n 8003450 break; 8003446: bf00 nop 8003448: e002 b.n 8003450 break; 800344a: bf00 nop 800344c: e000 b.n 8003450 break; 800344e: bf00 nop } if(ret == HAL_OK) 8003450: 7dfb ldrb r3, [r7, #23] 8003452: 2b00 cmp r3, #0 8003454: d10a bne.n 800346c { /* Set the source of SPI6 clock*/ __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection); 8003456: 4b4b ldr r3, [pc, #300] ; (8003584 ) 8003458: 6d9b ldr r3, [r3, #88] ; 0x58 800345a: f023 42e0 bic.w r2, r3, #1879048192 ; 0x70000000 800345e: 687b ldr r3, [r7, #4] 8003460: f8d3 30ac ldr.w r3, [r3, #172] ; 0xac 8003464: 4947 ldr r1, [pc, #284] ; (8003584 ) 8003466: 4313 orrs r3, r2 8003468: 658b str r3, [r1, #88] ; 0x58 800346a: e001 b.n 8003470 } else { /* set overall return value */ status = ret; 800346c: 7dfb ldrb r3, [r7, #23] 800346e: 75bb strb r3, [r7, #22] } #endif /*DSI*/ #if defined(FDCAN1) || defined(FDCAN2) /*---------------------------- FDCAN configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) 8003470: 687b ldr r3, [r7, #4] 8003472: 681b ldr r3, [r3, #0] 8003474: f403 4300 and.w r3, r3, #32768 ; 0x8000 8003478: 2b00 cmp r3, #0 800347a: d02f beq.n 80034dc { switch(PeriphClkInit->FdcanClockSelection) 800347c: 687b ldr r3, [r7, #4] 800347e: 6f5b ldr r3, [r3, #116] ; 0x74 8003480: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8003484: d00e beq.n 80034a4 8003486: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 800348a: d814 bhi.n 80034b6 800348c: 2b00 cmp r3, #0 800348e: d015 beq.n 80034bc 8003490: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 8003494: d10f bne.n 80034b6 { case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/ /* Enable FDCAN Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8003496: 4b3b ldr r3, [pc, #236] ; (8003584 ) 8003498: 6adb ldr r3, [r3, #44] ; 0x2c 800349a: 4a3a ldr r2, [pc, #232] ; (8003584 ) 800349c: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80034a0: 62d3 str r3, [r2, #44] ; 0x2c /* FDCAN clock source configuration done later after clock selection check */ break; 80034a2: e00c b.n 80034be case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 80034a4: 687b ldr r3, [r7, #4] 80034a6: 3304 adds r3, #4 80034a8: 2101 movs r1, #1 80034aa: 4618 mov r0, r3 80034ac: f000 ff3e bl 800432c 80034b0: 4603 mov r3, r0 80034b2: 75fb strb r3, [r7, #23] /* FDCAN clock source configuration done later after clock selection check */ break; 80034b4: e003 b.n 80034be /* HSE is used as clock source for FDCAN*/ /* FDCAN clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80034b6: 2301 movs r3, #1 80034b8: 75fb strb r3, [r7, #23] break; 80034ba: e000 b.n 80034be break; 80034bc: bf00 nop } if(ret == HAL_OK) 80034be: 7dfb ldrb r3, [r7, #23] 80034c0: 2b00 cmp r3, #0 80034c2: d109 bne.n 80034d8 { /* Set the source of FDCAN clock*/ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); 80034c4: 4b2f ldr r3, [pc, #188] ; (8003584 ) 80034c6: 6d1b ldr r3, [r3, #80] ; 0x50 80034c8: f023 5240 bic.w r2, r3, #805306368 ; 0x30000000 80034cc: 687b ldr r3, [r7, #4] 80034ce: 6f5b ldr r3, [r3, #116] ; 0x74 80034d0: 492c ldr r1, [pc, #176] ; (8003584 ) 80034d2: 4313 orrs r3, r2 80034d4: 650b str r3, [r1, #80] ; 0x50 80034d6: e001 b.n 80034dc } else { /* set overall return value */ status = ret; 80034d8: 7dfb ldrb r3, [r7, #23] 80034da: 75bb strb r3, [r7, #22] } } #endif /*FDCAN1 || FDCAN2*/ /*---------------------------- FMC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) 80034dc: 687b ldr r3, [r7, #4] 80034de: 681b ldr r3, [r3, #0] 80034e0: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 80034e4: 2b00 cmp r3, #0 80034e6: d032 beq.n 800354e { switch(PeriphClkInit->FmcClockSelection) 80034e8: 687b ldr r3, [r7, #4] 80034ea: 6c5b ldr r3, [r3, #68] ; 0x44 80034ec: 2b03 cmp r3, #3 80034ee: d81b bhi.n 8003528 80034f0: a201 add r2, pc, #4 ; (adr r2, 80034f8 ) 80034f2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80034f6: bf00 nop 80034f8: 0800352f .word 0x0800352f 80034fc: 08003509 .word 0x08003509 8003500: 08003517 .word 0x08003517 8003504: 0800352f .word 0x0800352f { case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/ /* Enable FMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8003508: 4b1e ldr r3, [pc, #120] ; (8003584 ) 800350a: 6adb ldr r3, [r3, #44] ; 0x2c 800350c: 4a1d ldr r2, [pc, #116] ; (8003584 ) 800350e: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8003512: 62d3 str r3, [r2, #44] ; 0x2c /* FMC clock source configuration done later after clock selection check */ break; 8003514: e00c b.n 8003530 case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); 8003516: 687b ldr r3, [r7, #4] 8003518: 3304 adds r3, #4 800351a: 2102 movs r1, #2 800351c: 4618 mov r0, r3 800351e: f000 ff05 bl 800432c 8003522: 4603 mov r3, r0 8003524: 75fb strb r3, [r7, #23] /* FMC clock source configuration done later after clock selection check */ break; 8003526: e003 b.n 8003530 case RCC_FMCCLKSOURCE_HCLK: /* D1/CD HCLK clock selected as FMC kernel peripheral clock */ break; default: ret = HAL_ERROR; 8003528: 2301 movs r3, #1 800352a: 75fb strb r3, [r7, #23] break; 800352c: e000 b.n 8003530 break; 800352e: bf00 nop } if(ret == HAL_OK) 8003530: 7dfb ldrb r3, [r7, #23] 8003532: 2b00 cmp r3, #0 8003534: d109 bne.n 800354a { /* Set the source of FMC clock*/ __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection); 8003536: 4b13 ldr r3, [pc, #76] ; (8003584 ) 8003538: 6cdb ldr r3, [r3, #76] ; 0x4c 800353a: f023 0203 bic.w r2, r3, #3 800353e: 687b ldr r3, [r7, #4] 8003540: 6c5b ldr r3, [r3, #68] ; 0x44 8003542: 4910 ldr r1, [pc, #64] ; (8003584 ) 8003544: 4313 orrs r3, r2 8003546: 64cb str r3, [r1, #76] ; 0x4c 8003548: e001 b.n 800354e } else { /* set overall return value */ status = ret; 800354a: 7dfb ldrb r3, [r7, #23] 800354c: 75bb strb r3, [r7, #22] } } /*---------------------------- RTC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 800354e: 687b ldr r3, [r7, #4] 8003550: 681b ldr r3, [r3, #0] 8003552: f403 0380 and.w r3, r3, #4194304 ; 0x400000 8003556: 2b00 cmp r3, #0 8003558: f000 808a beq.w 8003670 { /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 800355c: 4b0a ldr r3, [pc, #40] ; (8003588 ) 800355e: 681b ldr r3, [r3, #0] 8003560: 4a09 ldr r2, [pc, #36] ; (8003588 ) 8003562: f443 7380 orr.w r3, r3, #256 ; 0x100 8003566: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8003568: f7fd fcc0 bl 8000eec 800356c: 6138 str r0, [r7, #16] while((PWR->CR1 & PWR_CR1_DBP) == 0U) 800356e: e00d b.n 800358c { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8003570: f7fd fcbc bl 8000eec 8003574: 4602 mov r2, r0 8003576: 693b ldr r3, [r7, #16] 8003578: 1ad3 subs r3, r2, r3 800357a: 2b64 cmp r3, #100 ; 0x64 800357c: d906 bls.n 800358c { ret = HAL_TIMEOUT; 800357e: 2303 movs r3, #3 8003580: 75fb strb r3, [r7, #23] break; 8003582: e009 b.n 8003598 8003584: 58024400 .word 0x58024400 8003588: 58024800 .word 0x58024800 while((PWR->CR1 & PWR_CR1_DBP) == 0U) 800358c: 4bba ldr r3, [pc, #744] ; (8003878 ) 800358e: 681b ldr r3, [r3, #0] 8003590: f403 7380 and.w r3, r3, #256 ; 0x100 8003594: 2b00 cmp r3, #0 8003596: d0eb beq.n 8003570 } } if(ret == HAL_OK) 8003598: 7dfb ldrb r3, [r7, #23] 800359a: 2b00 cmp r3, #0 800359c: d166 bne.n 800366c { /* Reset the Backup domain only if the RTC Clock source selection is modified */ if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) 800359e: 4bb7 ldr r3, [pc, #732] ; (800387c ) 80035a0: 6f1a ldr r2, [r3, #112] ; 0x70 80035a2: 687b ldr r3, [r7, #4] 80035a4: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 80035a8: 4053 eors r3, r2 80035aa: f403 7340 and.w r3, r3, #768 ; 0x300 80035ae: 2b00 cmp r3, #0 80035b0: d013 beq.n 80035da { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 80035b2: 4bb2 ldr r3, [pc, #712] ; (800387c ) 80035b4: 6f1b ldr r3, [r3, #112] ; 0x70 80035b6: f423 7340 bic.w r3, r3, #768 ; 0x300 80035ba: 60fb str r3, [r7, #12] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 80035bc: 4baf ldr r3, [pc, #700] ; (800387c ) 80035be: 6f1b ldr r3, [r3, #112] ; 0x70 80035c0: 4aae ldr r2, [pc, #696] ; (800387c ) 80035c2: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80035c6: 6713 str r3, [r2, #112] ; 0x70 __HAL_RCC_BACKUPRESET_RELEASE(); 80035c8: 4bac ldr r3, [pc, #688] ; (800387c ) 80035ca: 6f1b ldr r3, [r3, #112] ; 0x70 80035cc: 4aab ldr r2, [pc, #684] ; (800387c ) 80035ce: f423 3380 bic.w r3, r3, #65536 ; 0x10000 80035d2: 6713 str r3, [r2, #112] ; 0x70 /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg; 80035d4: 4aa9 ldr r2, [pc, #676] ; (800387c ) 80035d6: 68fb ldr r3, [r7, #12] 80035d8: 6713 str r3, [r2, #112] ; 0x70 } /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */ if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) 80035da: 687b ldr r3, [r7, #4] 80035dc: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 80035e0: f5b3 7f80 cmp.w r3, #256 ; 0x100 80035e4: d115 bne.n 8003612 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80035e6: f7fd fc81 bl 8000eec 80035ea: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 80035ec: e00b b.n 8003606 { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80035ee: f7fd fc7d bl 8000eec 80035f2: 4602 mov r2, r0 80035f4: 693b ldr r3, [r7, #16] 80035f6: 1ad3 subs r3, r2, r3 80035f8: f241 3288 movw r2, #5000 ; 0x1388 80035fc: 4293 cmp r3, r2 80035fe: d902 bls.n 8003606 { ret = HAL_TIMEOUT; 8003600: 2303 movs r3, #3 8003602: 75fb strb r3, [r7, #23] break; 8003604: e005 b.n 8003612 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 8003606: 4b9d ldr r3, [pc, #628] ; (800387c ) 8003608: 6f1b ldr r3, [r3, #112] ; 0x70 800360a: f003 0302 and.w r3, r3, #2 800360e: 2b00 cmp r3, #0 8003610: d0ed beq.n 80035ee } } } if(ret == HAL_OK) 8003612: 7dfb ldrb r3, [r7, #23] 8003614: 2b00 cmp r3, #0 8003616: d126 bne.n 8003666 { __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8003618: 687b ldr r3, [r7, #4] 800361a: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 800361e: f403 7340 and.w r3, r3, #768 ; 0x300 8003622: f5b3 7f40 cmp.w r3, #768 ; 0x300 8003626: d10d bne.n 8003644 8003628: 4b94 ldr r3, [pc, #592] ; (800387c ) 800362a: 691b ldr r3, [r3, #16] 800362c: f423 527c bic.w r2, r3, #16128 ; 0x3f00 8003630: 687b ldr r3, [r7, #4] 8003632: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 8003636: 0919 lsrs r1, r3, #4 8003638: 4b91 ldr r3, [pc, #580] ; (8003880 ) 800363a: 400b ands r3, r1 800363c: 498f ldr r1, [pc, #572] ; (800387c ) 800363e: 4313 orrs r3, r2 8003640: 610b str r3, [r1, #16] 8003642: e005 b.n 8003650 8003644: 4b8d ldr r3, [pc, #564] ; (800387c ) 8003646: 691b ldr r3, [r3, #16] 8003648: 4a8c ldr r2, [pc, #560] ; (800387c ) 800364a: f423 537c bic.w r3, r3, #16128 ; 0x3f00 800364e: 6113 str r3, [r2, #16] 8003650: 4b8a ldr r3, [pc, #552] ; (800387c ) 8003652: 6f1a ldr r2, [r3, #112] ; 0x70 8003654: 687b ldr r3, [r7, #4] 8003656: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 800365a: f3c3 030b ubfx r3, r3, #0, #12 800365e: 4987 ldr r1, [pc, #540] ; (800387c ) 8003660: 4313 orrs r3, r2 8003662: 670b str r3, [r1, #112] ; 0x70 8003664: e004 b.n 8003670 } else { /* set overall return value */ status = ret; 8003666: 7dfb ldrb r3, [r7, #23] 8003668: 75bb strb r3, [r7, #22] 800366a: e001 b.n 8003670 } } else { /* set overall return value */ status = ret; 800366c: 7dfb ldrb r3, [r7, #23] 800366e: 75bb strb r3, [r7, #22] } } /*-------------------------- USART1/6 configuration --------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) 8003670: 687b ldr r3, [r7, #4] 8003672: 681b ldr r3, [r3, #0] 8003674: f003 0301 and.w r3, r3, #1 8003678: 2b00 cmp r3, #0 800367a: d07f beq.n 800377c { switch(PeriphClkInit->Usart16ClockSelection) 800367c: 687b ldr r3, [r7, #4] 800367e: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 8003682: 2b28 cmp r3, #40 ; 0x28 8003684: d866 bhi.n 8003754 8003686: a201 add r2, pc, #4 ; (adr r2, 800368c ) 8003688: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800368c: 0800375b .word 0x0800375b 8003690: 08003755 .word 0x08003755 8003694: 08003755 .word 0x08003755 8003698: 08003755 .word 0x08003755 800369c: 08003755 .word 0x08003755 80036a0: 08003755 .word 0x08003755 80036a4: 08003755 .word 0x08003755 80036a8: 08003755 .word 0x08003755 80036ac: 08003731 .word 0x08003731 80036b0: 08003755 .word 0x08003755 80036b4: 08003755 .word 0x08003755 80036b8: 08003755 .word 0x08003755 80036bc: 08003755 .word 0x08003755 80036c0: 08003755 .word 0x08003755 80036c4: 08003755 .word 0x08003755 80036c8: 08003755 .word 0x08003755 80036cc: 08003743 .word 0x08003743 80036d0: 08003755 .word 0x08003755 80036d4: 08003755 .word 0x08003755 80036d8: 08003755 .word 0x08003755 80036dc: 08003755 .word 0x08003755 80036e0: 08003755 .word 0x08003755 80036e4: 08003755 .word 0x08003755 80036e8: 08003755 .word 0x08003755 80036ec: 0800375b .word 0x0800375b 80036f0: 08003755 .word 0x08003755 80036f4: 08003755 .word 0x08003755 80036f8: 08003755 .word 0x08003755 80036fc: 08003755 .word 0x08003755 8003700: 08003755 .word 0x08003755 8003704: 08003755 .word 0x08003755 8003708: 08003755 .word 0x08003755 800370c: 0800375b .word 0x0800375b 8003710: 08003755 .word 0x08003755 8003714: 08003755 .word 0x08003755 8003718: 08003755 .word 0x08003755 800371c: 08003755 .word 0x08003755 8003720: 08003755 .word 0x08003755 8003724: 08003755 .word 0x08003755 8003728: 08003755 .word 0x08003755 800372c: 0800375b .word 0x0800375b case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */ /* USART1/6 clock source configuration done later after clock selection check */ break; case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 8003730: 687b ldr r3, [r7, #4] 8003732: 3304 adds r3, #4 8003734: 2101 movs r1, #1 8003736: 4618 mov r0, r3 8003738: f000 fdf8 bl 800432c 800373c: 4603 mov r3, r0 800373e: 75fb strb r3, [r7, #23] /* USART1/6 clock source configuration done later after clock selection check */ break; 8003740: e00c b.n 800375c case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 8003742: 687b ldr r3, [r7, #4] 8003744: 3324 adds r3, #36 ; 0x24 8003746: 2101 movs r1, #1 8003748: 4618 mov r0, r3 800374a: f000 fea1 bl 8004490 800374e: 4603 mov r3, r0 8003750: 75fb strb r3, [r7, #23] /* USART1/6 clock source configuration done later after clock selection check */ break; 8003752: e003 b.n 800375c /* LSE, oscillator is used as source of USART1/6 clock */ /* USART1/6 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8003754: 2301 movs r3, #1 8003756: 75fb strb r3, [r7, #23] break; 8003758: e000 b.n 800375c break; 800375a: bf00 nop } if(ret == HAL_OK) 800375c: 7dfb ldrb r3, [r7, #23] 800375e: 2b00 cmp r3, #0 8003760: d10a bne.n 8003778 { /* Set the source of USART1/6 clock */ __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection); 8003762: 4b46 ldr r3, [pc, #280] ; (800387c ) 8003764: 6d5b ldr r3, [r3, #84] ; 0x54 8003766: f023 0238 bic.w r2, r3, #56 ; 0x38 800376a: 687b ldr r3, [r7, #4] 800376c: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 8003770: 4942 ldr r1, [pc, #264] ; (800387c ) 8003772: 4313 orrs r3, r2 8003774: 654b str r3, [r1, #84] ; 0x54 8003776: e001 b.n 800377c } else { /* set overall return value */ status = ret; 8003778: 7dfb ldrb r3, [r7, #23] 800377a: 75bb strb r3, [r7, #22] } } /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) 800377c: 687b ldr r3, [r7, #4] 800377e: 681b ldr r3, [r3, #0] 8003780: f003 0302 and.w r3, r3, #2 8003784: 2b00 cmp r3, #0 8003786: d038 beq.n 80037fa { switch(PeriphClkInit->Usart234578ClockSelection) 8003788: 687b ldr r3, [r7, #4] 800378a: 6fdb ldr r3, [r3, #124] ; 0x7c 800378c: 2b05 cmp r3, #5 800378e: d821 bhi.n 80037d4 8003790: a201 add r2, pc, #4 ; (adr r2, 8003798 ) 8003792: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003796: bf00 nop 8003798: 080037db .word 0x080037db 800379c: 080037b1 .word 0x080037b1 80037a0: 080037c3 .word 0x080037c3 80037a4: 080037db .word 0x080037db 80037a8: 080037db .word 0x080037db 80037ac: 080037db .word 0x080037db case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 80037b0: 687b ldr r3, [r7, #4] 80037b2: 3304 adds r3, #4 80037b4: 2101 movs r1, #1 80037b6: 4618 mov r0, r3 80037b8: f000 fdb8 bl 800432c 80037bc: 4603 mov r3, r0 80037be: 75fb strb r3, [r7, #23] /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 80037c0: e00c b.n 80037dc case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 80037c2: 687b ldr r3, [r7, #4] 80037c4: 3324 adds r3, #36 ; 0x24 80037c6: 2101 movs r1, #1 80037c8: 4618 mov r0, r3 80037ca: f000 fe61 bl 8004490 80037ce: 4603 mov r3, r0 80037d0: 75fb strb r3, [r7, #23] /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 80037d2: e003 b.n 80037dc /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80037d4: 2301 movs r3, #1 80037d6: 75fb strb r3, [r7, #23] break; 80037d8: e000 b.n 80037dc break; 80037da: bf00 nop } if(ret == HAL_OK) 80037dc: 7dfb ldrb r3, [r7, #23] 80037de: 2b00 cmp r3, #0 80037e0: d109 bne.n 80037f6 { /* Set the source of USART2/3/4/5/7/8 clock */ __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection); 80037e2: 4b26 ldr r3, [pc, #152] ; (800387c ) 80037e4: 6d5b ldr r3, [r3, #84] ; 0x54 80037e6: f023 0207 bic.w r2, r3, #7 80037ea: 687b ldr r3, [r7, #4] 80037ec: 6fdb ldr r3, [r3, #124] ; 0x7c 80037ee: 4923 ldr r1, [pc, #140] ; (800387c ) 80037f0: 4313 orrs r3, r2 80037f2: 654b str r3, [r1, #84] ; 0x54 80037f4: e001 b.n 80037fa } else { /* set overall return value */ status = ret; 80037f6: 7dfb ldrb r3, [r7, #23] 80037f8: 75bb strb r3, [r7, #22] } } /*-------------------------- LPUART1 Configuration -------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 80037fa: 687b ldr r3, [r7, #4] 80037fc: 681b ldr r3, [r3, #0] 80037fe: f003 0304 and.w r3, r3, #4 8003802: 2b00 cmp r3, #0 8003804: d040 beq.n 8003888 { switch(PeriphClkInit->Lpuart1ClockSelection) 8003806: 687b ldr r3, [r7, #4] 8003808: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98 800380c: 2b05 cmp r3, #5 800380e: d821 bhi.n 8003854 8003810: a201 add r2, pc, #4 ; (adr r2, 8003818 ) 8003812: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003816: bf00 nop 8003818: 0800385b .word 0x0800385b 800381c: 08003831 .word 0x08003831 8003820: 08003843 .word 0x08003843 8003824: 0800385b .word 0x0800385b 8003828: 0800385b .word 0x0800385b 800382c: 0800385b .word 0x0800385b case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */ /* LPUART1 clock source configuration done later after clock selection check */ break; case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 8003830: 687b ldr r3, [r7, #4] 8003832: 3304 adds r3, #4 8003834: 2101 movs r1, #1 8003836: 4618 mov r0, r3 8003838: f000 fd78 bl 800432c 800383c: 4603 mov r3, r0 800383e: 75fb strb r3, [r7, #23] /* LPUART1 clock source configuration done later after clock selection check */ break; 8003840: e00c b.n 800385c case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 8003842: 687b ldr r3, [r7, #4] 8003844: 3324 adds r3, #36 ; 0x24 8003846: 2101 movs r1, #1 8003848: 4618 mov r0, r3 800384a: f000 fe21 bl 8004490 800384e: 4603 mov r3, r0 8003850: 75fb strb r3, [r7, #23] /* LPUART1 clock source configuration done later after clock selection check */ break; 8003852: e003 b.n 800385c /* LSE, oscillator is used as source of LPUART1 clock */ /* LPUART1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8003854: 2301 movs r3, #1 8003856: 75fb strb r3, [r7, #23] break; 8003858: e000 b.n 800385c break; 800385a: bf00 nop } if(ret == HAL_OK) 800385c: 7dfb ldrb r3, [r7, #23] 800385e: 2b00 cmp r3, #0 8003860: d110 bne.n 8003884 { /* Set the source of LPUART1 clock */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 8003862: 4b06 ldr r3, [pc, #24] ; (800387c ) 8003864: 6d9b ldr r3, [r3, #88] ; 0x58 8003866: f023 0207 bic.w r2, r3, #7 800386a: 687b ldr r3, [r7, #4] 800386c: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98 8003870: 4902 ldr r1, [pc, #8] ; (800387c ) 8003872: 4313 orrs r3, r2 8003874: 658b str r3, [r1, #88] ; 0x58 8003876: e007 b.n 8003888 8003878: 58024800 .word 0x58024800 800387c: 58024400 .word 0x58024400 8003880: 00ffffcf .word 0x00ffffcf } else { /* set overall return value */ status = ret; 8003884: 7dfb ldrb r3, [r7, #23] 8003886: 75bb strb r3, [r7, #22] } } /*---------------------------- LPTIM1 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) 8003888: 687b ldr r3, [r7, #4] 800388a: 681b ldr r3, [r3, #0] 800388c: f003 0320 and.w r3, r3, #32 8003890: 2b00 cmp r3, #0 8003892: d04b beq.n 800392c { switch(PeriphClkInit->Lptim1ClockSelection) 8003894: 687b ldr r3, [r7, #4] 8003896: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 800389a: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 800389e: d02e beq.n 80038fe 80038a0: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 80038a4: d828 bhi.n 80038f8 80038a6: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 80038aa: d02a beq.n 8003902 80038ac: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 80038b0: d822 bhi.n 80038f8 80038b2: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 80038b6: d026 beq.n 8003906 80038b8: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 80038bc: d81c bhi.n 80038f8 80038be: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 80038c2: d010 beq.n 80038e6 80038c4: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 80038c8: d816 bhi.n 80038f8 80038ca: 2b00 cmp r3, #0 80038cc: d01d beq.n 800390a 80038ce: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 80038d2: d111 bne.n 80038f8 /* LPTIM1 clock source configuration done later after clock selection check */ break; case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 80038d4: 687b ldr r3, [r7, #4] 80038d6: 3304 adds r3, #4 80038d8: 2100 movs r1, #0 80038da: 4618 mov r0, r3 80038dc: f000 fd26 bl 800432c 80038e0: 4603 mov r3, r0 80038e2: 75fb strb r3, [r7, #23] /* LPTIM1 clock source configuration done later after clock selection check */ break; 80038e4: e012 b.n 800390c case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 80038e6: 687b ldr r3, [r7, #4] 80038e8: 3324 adds r3, #36 ; 0x24 80038ea: 2102 movs r1, #2 80038ec: 4618 mov r0, r3 80038ee: f000 fdcf bl 8004490 80038f2: 4603 mov r3, r0 80038f4: 75fb strb r3, [r7, #23] /* LPTIM1 clock source configuration done later after clock selection check */ break; 80038f6: e009 b.n 800390c /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */ /* LPTIM1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80038f8: 2301 movs r3, #1 80038fa: 75fb strb r3, [r7, #23] break; 80038fc: e006 b.n 800390c break; 80038fe: bf00 nop 8003900: e004 b.n 800390c break; 8003902: bf00 nop 8003904: e002 b.n 800390c break; 8003906: bf00 nop 8003908: e000 b.n 800390c break; 800390a: bf00 nop } if(ret == HAL_OK) 800390c: 7dfb ldrb r3, [r7, #23] 800390e: 2b00 cmp r3, #0 8003910: d10a bne.n 8003928 { /* Set the source of LPTIM1 clock*/ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 8003912: 4bb3 ldr r3, [pc, #716] ; (8003be0 ) 8003914: 6d5b ldr r3, [r3, #84] ; 0x54 8003916: f023 42e0 bic.w r2, r3, #1879048192 ; 0x70000000 800391a: 687b ldr r3, [r7, #4] 800391c: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 8003920: 49af ldr r1, [pc, #700] ; (8003be0 ) 8003922: 4313 orrs r3, r2 8003924: 654b str r3, [r1, #84] ; 0x54 8003926: e001 b.n 800392c } else { /* set overall return value */ status = ret; 8003928: 7dfb ldrb r3, [r7, #23] 800392a: 75bb strb r3, [r7, #22] } } /*---------------------------- LPTIM2 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) 800392c: 687b ldr r3, [r7, #4] 800392e: 681b ldr r3, [r3, #0] 8003930: f003 0340 and.w r3, r3, #64 ; 0x40 8003934: 2b00 cmp r3, #0 8003936: d04b beq.n 80039d0 { switch(PeriphClkInit->Lptim2ClockSelection) 8003938: 687b ldr r3, [r7, #4] 800393a: f8d3 30a0 ldr.w r3, [r3, #160] ; 0xa0 800393e: f5b3 5fa0 cmp.w r3, #5120 ; 0x1400 8003942: d02e beq.n 80039a2 8003944: f5b3 5fa0 cmp.w r3, #5120 ; 0x1400 8003948: d828 bhi.n 800399c 800394a: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 800394e: d02a beq.n 80039a6 8003950: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8003954: d822 bhi.n 800399c 8003956: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 800395a: d026 beq.n 80039aa 800395c: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 8003960: d81c bhi.n 800399c 8003962: f5b3 6f00 cmp.w r3, #2048 ; 0x800 8003966: d010 beq.n 800398a 8003968: f5b3 6f00 cmp.w r3, #2048 ; 0x800 800396c: d816 bhi.n 800399c 800396e: 2b00 cmp r3, #0 8003970: d01d beq.n 80039ae 8003972: f5b3 6f80 cmp.w r3, #1024 ; 0x400 8003976: d111 bne.n 800399c /* LPTIM2 clock source configuration done later after clock selection check */ break; case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 8003978: 687b ldr r3, [r7, #4] 800397a: 3304 adds r3, #4 800397c: 2100 movs r1, #0 800397e: 4618 mov r0, r3 8003980: f000 fcd4 bl 800432c 8003984: 4603 mov r3, r0 8003986: 75fb strb r3, [r7, #23] /* LPTIM2 clock source configuration done later after clock selection check */ break; 8003988: e012 b.n 80039b0 case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 800398a: 687b ldr r3, [r7, #4] 800398c: 3324 adds r3, #36 ; 0x24 800398e: 2102 movs r1, #2 8003990: 4618 mov r0, r3 8003992: f000 fd7d bl 8004490 8003996: 4603 mov r3, r0 8003998: 75fb strb r3, [r7, #23] /* LPTIM2 clock source configuration done later after clock selection check */ break; 800399a: e009 b.n 80039b0 /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */ /* LPTIM2 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800399c: 2301 movs r3, #1 800399e: 75fb strb r3, [r7, #23] break; 80039a0: e006 b.n 80039b0 break; 80039a2: bf00 nop 80039a4: e004 b.n 80039b0 break; 80039a6: bf00 nop 80039a8: e002 b.n 80039b0 break; 80039aa: bf00 nop 80039ac: e000 b.n 80039b0 break; 80039ae: bf00 nop } if(ret == HAL_OK) 80039b0: 7dfb ldrb r3, [r7, #23] 80039b2: 2b00 cmp r3, #0 80039b4: d10a bne.n 80039cc { /* Set the source of LPTIM2 clock*/ __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); 80039b6: 4b8a ldr r3, [pc, #552] ; (8003be0 ) 80039b8: 6d9b ldr r3, [r3, #88] ; 0x58 80039ba: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00 80039be: 687b ldr r3, [r7, #4] 80039c0: f8d3 30a0 ldr.w r3, [r3, #160] ; 0xa0 80039c4: 4986 ldr r1, [pc, #536] ; (8003be0 ) 80039c6: 4313 orrs r3, r2 80039c8: 658b str r3, [r1, #88] ; 0x58 80039ca: e001 b.n 80039d0 } else { /* set overall return value */ status = ret; 80039cc: 7dfb ldrb r3, [r7, #23] 80039ce: 75bb strb r3, [r7, #22] } } /*---------------------------- LPTIM345 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345) 80039d0: 687b ldr r3, [r7, #4] 80039d2: 681b ldr r3, [r3, #0] 80039d4: f003 0380 and.w r3, r3, #128 ; 0x80 80039d8: 2b00 cmp r3, #0 80039da: d04b beq.n 8003a74 { switch(PeriphClkInit->Lptim345ClockSelection) 80039dc: 687b ldr r3, [r7, #4] 80039de: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4 80039e2: f5b3 4f20 cmp.w r3, #40960 ; 0xa000 80039e6: d02e beq.n 8003a46 80039e8: f5b3 4f20 cmp.w r3, #40960 ; 0xa000 80039ec: d828 bhi.n 8003a40 80039ee: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 80039f2: d02a beq.n 8003a4a 80039f4: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 80039f8: d822 bhi.n 8003a40 80039fa: f5b3 4fc0 cmp.w r3, #24576 ; 0x6000 80039fe: d026 beq.n 8003a4e 8003a00: f5b3 4fc0 cmp.w r3, #24576 ; 0x6000 8003a04: d81c bhi.n 8003a40 8003a06: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 8003a0a: d010 beq.n 8003a2e 8003a0c: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 8003a10: d816 bhi.n 8003a40 8003a12: 2b00 cmp r3, #0 8003a14: d01d beq.n 8003a52 8003a16: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 8003a1a: d111 bne.n 8003a40 case RCC_LPTIM345CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 8003a1c: 687b ldr r3, [r7, #4] 8003a1e: 3304 adds r3, #4 8003a20: 2100 movs r1, #0 8003a22: 4618 mov r0, r3 8003a24: f000 fc82 bl 800432c 8003a28: 4603 mov r3, r0 8003a2a: 75fb strb r3, [r7, #23] /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 8003a2c: e012 b.n 8003a54 case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 8003a2e: 687b ldr r3, [r7, #4] 8003a30: 3324 adds r3, #36 ; 0x24 8003a32: 2102 movs r1, #2 8003a34: 4618 mov r0, r3 8003a36: f000 fd2b bl 8004490 8003a3a: 4603 mov r3, r0 8003a3c: 75fb strb r3, [r7, #23] /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 8003a3e: e009 b.n 8003a54 /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8003a40: 2301 movs r3, #1 8003a42: 75fb strb r3, [r7, #23] break; 8003a44: e006 b.n 8003a54 break; 8003a46: bf00 nop 8003a48: e004 b.n 8003a54 break; 8003a4a: bf00 nop 8003a4c: e002 b.n 8003a54 break; 8003a4e: bf00 nop 8003a50: e000 b.n 8003a54 break; 8003a52: bf00 nop } if(ret == HAL_OK) 8003a54: 7dfb ldrb r3, [r7, #23] 8003a56: 2b00 cmp r3, #0 8003a58: d10a bne.n 8003a70 { /* Set the source of LPTIM3/4/5 clock */ __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection); 8003a5a: 4b61 ldr r3, [pc, #388] ; (8003be0 ) 8003a5c: 6d9b ldr r3, [r3, #88] ; 0x58 8003a5e: f423 4260 bic.w r2, r3, #57344 ; 0xe000 8003a62: 687b ldr r3, [r7, #4] 8003a64: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4 8003a68: 495d ldr r1, [pc, #372] ; (8003be0 ) 8003a6a: 4313 orrs r3, r2 8003a6c: 658b str r3, [r1, #88] ; 0x58 8003a6e: e001 b.n 8003a74 } else { /* set overall return value */ status = ret; 8003a70: 7dfb ldrb r3, [r7, #23] 8003a72: 75bb strb r3, [r7, #22] __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection); } #else if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123) 8003a74: 687b ldr r3, [r7, #4] 8003a76: 681b ldr r3, [r3, #0] 8003a78: f003 0308 and.w r3, r3, #8 8003a7c: 2b00 cmp r3, #0 8003a7e: d01a beq.n 8003ab6 { /* Check the parameters */ assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection)); if ((PeriphClkInit->I2c123ClockSelection )== RCC_I2C123CLKSOURCE_PLL3 ) 8003a80: 687b ldr r3, [r7, #4] 8003a82: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8003a86: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8003a8a: d10a bne.n 8003aa2 { if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK) 8003a8c: 687b ldr r3, [r7, #4] 8003a8e: 3324 adds r3, #36 ; 0x24 8003a90: 2102 movs r1, #2 8003a92: 4618 mov r0, r3 8003a94: f000 fcfc bl 8004490 8003a98: 4603 mov r3, r0 8003a9a: 2b00 cmp r3, #0 8003a9c: d001 beq.n 8003aa2 { status = HAL_ERROR; 8003a9e: 2301 movs r3, #1 8003aa0: 75bb strb r3, [r7, #22] } } __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection); 8003aa2: 4b4f ldr r3, [pc, #316] ; (8003be0 ) 8003aa4: 6d5b ldr r3, [r3, #84] ; 0x54 8003aa6: f423 5240 bic.w r2, r3, #12288 ; 0x3000 8003aaa: 687b ldr r3, [r7, #4] 8003aac: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8003ab0: 494b ldr r1, [pc, #300] ; (8003be0 ) 8003ab2: 4313 orrs r3, r2 8003ab4: 654b str r3, [r1, #84] ; 0x54 } #endif /* I2C5 */ /*------------------------------ I2C4 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) 8003ab6: 687b ldr r3, [r7, #4] 8003ab8: 681b ldr r3, [r3, #0] 8003aba: f003 0310 and.w r3, r3, #16 8003abe: 2b00 cmp r3, #0 8003ac0: d01a beq.n 8003af8 { /* Check the parameters */ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3 ) 8003ac2: 687b ldr r3, [r7, #4] 8003ac4: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 8003ac8: f5b3 7f80 cmp.w r3, #256 ; 0x100 8003acc: d10a bne.n 8003ae4 { if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK) 8003ace: 687b ldr r3, [r7, #4] 8003ad0: 3324 adds r3, #36 ; 0x24 8003ad2: 2102 movs r1, #2 8003ad4: 4618 mov r0, r3 8003ad6: f000 fcdb bl 8004490 8003ada: 4603 mov r3, r0 8003adc: 2b00 cmp r3, #0 8003ade: d001 beq.n 8003ae4 { status = HAL_ERROR; 8003ae0: 2301 movs r3, #1 8003ae2: 75bb strb r3, [r7, #22] } } __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); 8003ae4: 4b3e ldr r3, [pc, #248] ; (8003be0 ) 8003ae6: 6d9b ldr r3, [r3, #88] ; 0x58 8003ae8: f423 7240 bic.w r2, r3, #768 ; 0x300 8003aec: 687b ldr r3, [r7, #4] 8003aee: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 8003af2: 493b ldr r1, [pc, #236] ; (8003be0 ) 8003af4: 4313 orrs r3, r2 8003af6: 658b str r3, [r1, #88] ; 0x58 } /*---------------------------- ADC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 8003af8: 687b ldr r3, [r7, #4] 8003afa: 681b ldr r3, [r3, #0] 8003afc: f403 2300 and.w r3, r3, #524288 ; 0x80000 8003b00: 2b00 cmp r3, #0 8003b02: d034 beq.n 8003b6e { switch(PeriphClkInit->AdcClockSelection) 8003b04: 687b ldr r3, [r7, #4] 8003b06: f8d3 30a8 ldr.w r3, [r3, #168] ; 0xa8 8003b0a: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 8003b0e: d01d beq.n 8003b4c 8003b10: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 8003b14: d817 bhi.n 8003b46 8003b16: 2b00 cmp r3, #0 8003b18: d003 beq.n 8003b22 8003b1a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8003b1e: d009 beq.n 8003b34 8003b20: e011 b.n 8003b46 { case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 8003b22: 687b ldr r3, [r7, #4] 8003b24: 3304 adds r3, #4 8003b26: 2100 movs r1, #0 8003b28: 4618 mov r0, r3 8003b2a: f000 fbff bl 800432c 8003b2e: 4603 mov r3, r0 8003b30: 75fb strb r3, [r7, #23] /* ADC clock source configuration done later after clock selection check */ break; 8003b32: e00c b.n 8003b4e case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 8003b34: 687b ldr r3, [r7, #4] 8003b36: 3324 adds r3, #36 ; 0x24 8003b38: 2102 movs r1, #2 8003b3a: 4618 mov r0, r3 8003b3c: f000 fca8 bl 8004490 8003b40: 4603 mov r3, r0 8003b42: 75fb strb r3, [r7, #23] /* ADC clock source configuration done later after clock selection check */ break; 8003b44: e003 b.n 8003b4e /* HSI, HSE, or CSI oscillator is used as source of ADC clock */ /* ADC clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8003b46: 2301 movs r3, #1 8003b48: 75fb strb r3, [r7, #23] break; 8003b4a: e000 b.n 8003b4e break; 8003b4c: bf00 nop } if(ret == HAL_OK) 8003b4e: 7dfb ldrb r3, [r7, #23] 8003b50: 2b00 cmp r3, #0 8003b52: d10a bne.n 8003b6a { /* Set the source of ADC clock*/ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 8003b54: 4b22 ldr r3, [pc, #136] ; (8003be0 ) 8003b56: 6d9b ldr r3, [r3, #88] ; 0x58 8003b58: f423 3240 bic.w r2, r3, #196608 ; 0x30000 8003b5c: 687b ldr r3, [r7, #4] 8003b5e: f8d3 30a8 ldr.w r3, [r3, #168] ; 0xa8 8003b62: 491f ldr r1, [pc, #124] ; (8003be0 ) 8003b64: 4313 orrs r3, r2 8003b66: 658b str r3, [r1, #88] ; 0x58 8003b68: e001 b.n 8003b6e } else { /* set overall return value */ status = ret; 8003b6a: 7dfb ldrb r3, [r7, #23] 8003b6c: 75bb strb r3, [r7, #22] } } /*------------------------------ USB Configuration -------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 8003b6e: 687b ldr r3, [r7, #4] 8003b70: 681b ldr r3, [r3, #0] 8003b72: f403 2380 and.w r3, r3, #262144 ; 0x40000 8003b76: 2b00 cmp r3, #0 8003b78: d036 beq.n 8003be8 { switch(PeriphClkInit->UsbClockSelection) 8003b7a: 687b ldr r3, [r7, #4] 8003b7c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 8003b80: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000 8003b84: d01c beq.n 8003bc0 8003b86: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000 8003b8a: d816 bhi.n 8003bba 8003b8c: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 8003b90: d003 beq.n 8003b9a 8003b92: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 8003b96: d007 beq.n 8003ba8 8003b98: e00f b.n 8003bba { case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/ /* Enable USB Clock output generated form System USB . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8003b9a: 4b11 ldr r3, [pc, #68] ; (8003be0 ) 8003b9c: 6adb ldr r3, [r3, #44] ; 0x2c 8003b9e: 4a10 ldr r2, [pc, #64] ; (8003be0 ) 8003ba0: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8003ba4: 62d3 str r3, [r2, #44] ; 0x2c /* USB clock source configuration done later after clock selection check */ break; 8003ba6: e00c b.n 8003bc2 case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 8003ba8: 687b ldr r3, [r7, #4] 8003baa: 3324 adds r3, #36 ; 0x24 8003bac: 2101 movs r1, #1 8003bae: 4618 mov r0, r3 8003bb0: f000 fc6e bl 8004490 8003bb4: 4603 mov r3, r0 8003bb6: 75fb strb r3, [r7, #23] /* USB clock source configuration done later after clock selection check */ break; 8003bb8: e003 b.n 8003bc2 /* HSI48 oscillator is used as source of USB clock */ /* USB clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8003bba: 2301 movs r3, #1 8003bbc: 75fb strb r3, [r7, #23] break; 8003bbe: e000 b.n 8003bc2 break; 8003bc0: bf00 nop } if(ret == HAL_OK) 8003bc2: 7dfb ldrb r3, [r7, #23] 8003bc4: 2b00 cmp r3, #0 8003bc6: d10d bne.n 8003be4 { /* Set the source of USB clock*/ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 8003bc8: 4b05 ldr r3, [pc, #20] ; (8003be0 ) 8003bca: 6d5b ldr r3, [r3, #84] ; 0x54 8003bcc: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 8003bd0: 687b ldr r3, [r7, #4] 8003bd2: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 8003bd6: 4902 ldr r1, [pc, #8] ; (8003be0 ) 8003bd8: 4313 orrs r3, r2 8003bda: 654b str r3, [r1, #84] ; 0x54 8003bdc: e004 b.n 8003be8 8003bde: bf00 nop 8003be0: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 8003be4: 7dfb ldrb r3, [r7, #23] 8003be6: 75bb strb r3, [r7, #22] } } /*------------------------------------- SDMMC Configuration ------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC) 8003be8: 687b ldr r3, [r7, #4] 8003bea: 681b ldr r3, [r3, #0] 8003bec: f403 3380 and.w r3, r3, #65536 ; 0x10000 8003bf0: 2b00 cmp r3, #0 8003bf2: d029 beq.n 8003c48 { /* Check the parameters */ assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection)); switch(PeriphClkInit->SdmmcClockSelection) 8003bf4: 687b ldr r3, [r7, #4] 8003bf6: 6cdb ldr r3, [r3, #76] ; 0x4c 8003bf8: 2b00 cmp r3, #0 8003bfa: d003 beq.n 8003c04 8003bfc: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8003c00: d007 beq.n 8003c12 8003c02: e00f b.n 8003c24 { case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/ /* Enable SDMMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8003c04: 4b69 ldr r3, [pc, #420] ; (8003dac ) 8003c06: 6adb ldr r3, [r3, #44] ; 0x2c 8003c08: 4a68 ldr r2, [pc, #416] ; (8003dac ) 8003c0a: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8003c0e: 62d3 str r3, [r2, #44] ; 0x2c /* SDMMC clock source configuration done later after clock selection check */ break; 8003c10: e00b b.n 8003c2a case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); 8003c12: 687b ldr r3, [r7, #4] 8003c14: 3304 adds r3, #4 8003c16: 2102 movs r1, #2 8003c18: 4618 mov r0, r3 8003c1a: f000 fb87 bl 800432c 8003c1e: 4603 mov r3, r0 8003c20: 75fb strb r3, [r7, #23] /* SDMMC clock source configuration done later after clock selection check */ break; 8003c22: e002 b.n 8003c2a default: ret = HAL_ERROR; 8003c24: 2301 movs r3, #1 8003c26: 75fb strb r3, [r7, #23] break; 8003c28: bf00 nop } if(ret == HAL_OK) 8003c2a: 7dfb ldrb r3, [r7, #23] 8003c2c: 2b00 cmp r3, #0 8003c2e: d109 bne.n 8003c44 { /* Set the source of SDMMC clock*/ __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection); 8003c30: 4b5e ldr r3, [pc, #376] ; (8003dac ) 8003c32: 6cdb ldr r3, [r3, #76] ; 0x4c 8003c34: f423 3280 bic.w r2, r3, #65536 ; 0x10000 8003c38: 687b ldr r3, [r7, #4] 8003c3a: 6cdb ldr r3, [r3, #76] ; 0x4c 8003c3c: 495b ldr r1, [pc, #364] ; (8003dac ) 8003c3e: 4313 orrs r3, r2 8003c40: 64cb str r3, [r1, #76] ; 0x4c 8003c42: e001 b.n 8003c48 } else { /* set overall return value */ status = ret; 8003c44: 7dfb ldrb r3, [r7, #23] 8003c46: 75bb strb r3, [r7, #22] } } #if defined(LTDC) /*-------------------------------------- LTDC Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) 8003c48: 687b ldr r3, [r7, #4] 8003c4a: 681b ldr r3, [r3, #0] 8003c4c: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 8003c50: 2b00 cmp r3, #0 8003c52: d00a beq.n 8003c6a { if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!=HAL_OK) 8003c54: 687b ldr r3, [r7, #4] 8003c56: 3324 adds r3, #36 ; 0x24 8003c58: 2102 movs r1, #2 8003c5a: 4618 mov r0, r3 8003c5c: f000 fc18 bl 8004490 8003c60: 4603 mov r3, r0 8003c62: 2b00 cmp r3, #0 8003c64: d001 beq.n 8003c6a { status=HAL_ERROR; 8003c66: 2301 movs r3, #1 8003c68: 75bb strb r3, [r7, #22] } } #endif /* LTDC */ /*------------------------------ RNG Configuration -------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) 8003c6a: 687b ldr r3, [r7, #4] 8003c6c: 681b ldr r3, [r3, #0] 8003c6e: f403 3300 and.w r3, r3, #131072 ; 0x20000 8003c72: 2b00 cmp r3, #0 8003c74: d032 beq.n 8003cdc { switch(PeriphClkInit->RngClockSelection) 8003c76: 687b ldr r3, [r7, #4] 8003c78: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 8003c7c: f5b3 7f40 cmp.w r3, #768 ; 0x300 8003c80: d017 beq.n 8003cb2 8003c82: f5b3 7f40 cmp.w r3, #768 ; 0x300 8003c86: d811 bhi.n 8003cac 8003c88: f5b3 7f00 cmp.w r3, #512 ; 0x200 8003c8c: d013 beq.n 8003cb6 8003c8e: f5b3 7f00 cmp.w r3, #512 ; 0x200 8003c92: d80b bhi.n 8003cac 8003c94: 2b00 cmp r3, #0 8003c96: d010 beq.n 8003cba 8003c98: f5b3 7f80 cmp.w r3, #256 ; 0x100 8003c9c: d106 bne.n 8003cac { case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/ /* Enable RNG Clock output generated form System RNG . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8003c9e: 4b43 ldr r3, [pc, #268] ; (8003dac ) 8003ca0: 6adb ldr r3, [r3, #44] ; 0x2c 8003ca2: 4a42 ldr r2, [pc, #264] ; (8003dac ) 8003ca4: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8003ca8: 62d3 str r3, [r2, #44] ; 0x2c /* RNG clock source configuration done later after clock selection check */ break; 8003caa: e007 b.n 8003cbc /* HSI48 oscillator is used as source of RNG clock */ /* RNG clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8003cac: 2301 movs r3, #1 8003cae: 75fb strb r3, [r7, #23] break; 8003cb0: e004 b.n 8003cbc break; 8003cb2: bf00 nop 8003cb4: e002 b.n 8003cbc break; 8003cb6: bf00 nop 8003cb8: e000 b.n 8003cbc break; 8003cba: bf00 nop } if(ret == HAL_OK) 8003cbc: 7dfb ldrb r3, [r7, #23] 8003cbe: 2b00 cmp r3, #0 8003cc0: d10a bne.n 8003cd8 { /* Set the source of RNG clock*/ __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 8003cc2: 4b3a ldr r3, [pc, #232] ; (8003dac ) 8003cc4: 6d5b ldr r3, [r3, #84] ; 0x54 8003cc6: f423 7240 bic.w r2, r3, #768 ; 0x300 8003cca: 687b ldr r3, [r7, #4] 8003ccc: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 8003cd0: 4936 ldr r1, [pc, #216] ; (8003dac ) 8003cd2: 4313 orrs r3, r2 8003cd4: 654b str r3, [r1, #84] ; 0x54 8003cd6: e001 b.n 8003cdc } else { /* set overall return value */ status = ret; 8003cd8: 7dfb ldrb r3, [r7, #23] 8003cda: 75bb strb r3, [r7, #22] } } /*------------------------------ SWPMI1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) 8003cdc: 687b ldr r3, [r7, #4] 8003cde: 681b ldr r3, [r3, #0] 8003ce0: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8003ce4: 2b00 cmp r3, #0 8003ce6: d008 beq.n 8003cfa { /* Check the parameters */ assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); /* Configure the SWPMI1 interface clock source */ __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); 8003ce8: 4b30 ldr r3, [pc, #192] ; (8003dac ) 8003cea: 6d1b ldr r3, [r3, #80] ; 0x50 8003cec: f023 4200 bic.w r2, r3, #2147483648 ; 0x80000000 8003cf0: 687b ldr r3, [r7, #4] 8003cf2: 6f9b ldr r3, [r3, #120] ; 0x78 8003cf4: 492d ldr r1, [pc, #180] ; (8003dac ) 8003cf6: 4313 orrs r3, r2 8003cf8: 650b str r3, [r1, #80] ; 0x50 /* Configure the HRTIM1 clock source */ __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); } #endif /*HRTIM1*/ /*------------------------------ DFSDM1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) 8003cfa: 687b ldr r3, [r7, #4] 8003cfc: 681b ldr r3, [r3, #0] 8003cfe: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8003d02: 2b00 cmp r3, #0 8003d04: d008 beq.n 8003d18 { /* Check the parameters */ assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); /* Configure the DFSDM1 interface clock source */ __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); 8003d06: 4b29 ldr r3, [pc, #164] ; (8003dac ) 8003d08: 6d1b ldr r3, [r3, #80] ; 0x50 8003d0a: f023 7280 bic.w r2, r3, #16777216 ; 0x1000000 8003d0e: 687b ldr r3, [r7, #4] 8003d10: 6edb ldr r3, [r3, #108] ; 0x6c 8003d12: 4926 ldr r1, [pc, #152] ; (8003dac ) 8003d14: 4313 orrs r3, r2 8003d16: 650b str r3, [r1, #80] ; 0x50 } #if defined(DFSDM2_BASE) /*------------------------------ DFSDM2 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2) 8003d18: 687b ldr r3, [r7, #4] 8003d1a: 681b ldr r3, [r3, #0] 8003d1c: f403 6300 and.w r3, r3, #2048 ; 0x800 8003d20: 2b00 cmp r3, #0 8003d22: d008 beq.n 8003d36 { /* Check the parameters */ assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection)); /* Configure the DFSDM2 interface clock source */ __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); 8003d24: 4b21 ldr r3, [pc, #132] ; (8003dac ) 8003d26: 6d9b ldr r3, [r3, #88] ; 0x58 8003d28: f023 6200 bic.w r2, r3, #134217728 ; 0x8000000 8003d2c: 687b ldr r3, [r7, #4] 8003d2e: 6f1b ldr r3, [r3, #112] ; 0x70 8003d30: 491e ldr r1, [pc, #120] ; (8003dac ) 8003d32: 4313 orrs r3, r2 8003d34: 658b str r3, [r1, #88] ; 0x58 } #endif /* DFSDM2 */ /*------------------------------------ TIM configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) 8003d36: 687b ldr r3, [r7, #4] 8003d38: 681b ldr r3, [r3, #0] 8003d3a: f003 4380 and.w r3, r3, #1073741824 ; 0x40000000 8003d3e: 2b00 cmp r3, #0 8003d40: d00d beq.n 8003d5e { /* Check the parameters */ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 8003d42: 4b1a ldr r3, [pc, #104] ; (8003dac ) 8003d44: 691b ldr r3, [r3, #16] 8003d46: 4a19 ldr r2, [pc, #100] ; (8003dac ) 8003d48: f423 4300 bic.w r3, r3, #32768 ; 0x8000 8003d4c: 6113 str r3, [r2, #16] 8003d4e: 4b17 ldr r3, [pc, #92] ; (8003dac ) 8003d50: 691a ldr r2, [r3, #16] 8003d52: 687b ldr r3, [r7, #4] 8003d54: f8d3 30b4 ldr.w r3, [r3, #180] ; 0xb4 8003d58: 4914 ldr r1, [pc, #80] ; (8003dac ) 8003d5a: 4313 orrs r3, r2 8003d5c: 610b str r3, [r1, #16] } /*------------------------------------ CKPER configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) 8003d5e: 687b ldr r3, [r7, #4] 8003d60: 681b ldr r3, [r3, #0] 8003d62: 2b00 cmp r3, #0 8003d64: da08 bge.n 8003d78 { /* Check the parameters */ assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection)); /* Configure the CKPER clock source */ __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); 8003d66: 4b11 ldr r3, [pc, #68] ; (8003dac ) 8003d68: 6cdb ldr r3, [r3, #76] ; 0x4c 8003d6a: f023 5240 bic.w r2, r3, #805306368 ; 0x30000000 8003d6e: 687b ldr r3, [r7, #4] 8003d70: 6d1b ldr r3, [r3, #80] ; 0x50 8003d72: 490e ldr r1, [pc, #56] ; (8003dac ) 8003d74: 4313 orrs r3, r2 8003d76: 64cb str r3, [r1, #76] ; 0x4c } /*------------------------------ CEC Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 8003d78: 687b ldr r3, [r7, #4] 8003d7a: 681b ldr r3, [r3, #0] 8003d7c: f403 0300 and.w r3, r3, #8388608 ; 0x800000 8003d80: 2b00 cmp r3, #0 8003d82: d009 beq.n 8003d98 { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC interface clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 8003d84: 4b09 ldr r3, [pc, #36] ; (8003dac ) 8003d86: 6d5b ldr r3, [r3, #84] ; 0x54 8003d88: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 8003d8c: 687b ldr r3, [r7, #4] 8003d8e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8003d92: 4906 ldr r1, [pc, #24] ; (8003dac ) 8003d94: 4313 orrs r3, r2 8003d96: 654b str r3, [r1, #84] ; 0x54 } if (status == HAL_OK) 8003d98: 7dbb ldrb r3, [r7, #22] 8003d9a: 2b00 cmp r3, #0 8003d9c: d101 bne.n 8003da2 { return HAL_OK; 8003d9e: 2300 movs r3, #0 8003da0: e000 b.n 8003da4 } return HAL_ERROR; 8003da2: 2301 movs r3, #1 } 8003da4: 4618 mov r0, r3 8003da6: 3718 adds r7, #24 8003da8: 46bd mov sp, r7 8003daa: bd80 pop {r7, pc} 8003dac: 58024400 .word 0x58024400 08003db0 : * @note Each time D3PCLK1 changes, this function must be called to update the * right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval D3PCLK1 frequency */ uint32_t HAL_RCCEx_GetD3PCLK1Freq(void) { 8003db0: b580 push {r7, lr} 8003db2: af00 add r7, sp, #0 #if defined(RCC_D3CFGR_D3PPRE) /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE)>> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU)); #else /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)>> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU)); 8003db4: f7ff f894 bl 8002ee0 8003db8: 4602 mov r2, r0 8003dba: 4b06 ldr r3, [pc, #24] ; (8003dd4 ) 8003dbc: 6a1b ldr r3, [r3, #32] 8003dbe: 091b lsrs r3, r3, #4 8003dc0: f003 0307 and.w r3, r3, #7 8003dc4: 4904 ldr r1, [pc, #16] ; (8003dd8 ) 8003dc6: 5ccb ldrb r3, [r1, r3] 8003dc8: f003 031f and.w r3, r3, #31 8003dcc: fa22 f303 lsr.w r3, r2, r3 #endif } 8003dd0: 4618 mov r0, r3 8003dd2: bd80 pop {r7, pc} 8003dd4: 58024400 .word 0x58024400 8003dd8: 08007278 .word 0x08007278 08003ddc : * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL2_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks) { 8003ddc: b480 push {r7} 8003dde: b089 sub sp, #36 ; 0x24 8003de0: af00 add r7, sp, #0 8003de2: 6078 str r0, [r7, #4] float_t fracn2, pll2vco; /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N PLL2xCLK = PLL2_VCO / PLL2x */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 8003de4: 4ba1 ldr r3, [pc, #644] ; (800406c ) 8003de6: 6a9b ldr r3, [r3, #40] ; 0x28 8003de8: f003 0303 and.w r3, r3, #3 8003dec: 61bb str r3, [r7, #24] pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> 12); 8003dee: 4b9f ldr r3, [pc, #636] ; (800406c ) 8003df0: 6a9b ldr r3, [r3, #40] ; 0x28 8003df2: 0b1b lsrs r3, r3, #12 8003df4: f003 033f and.w r3, r3, #63 ; 0x3f 8003df8: 617b str r3, [r7, #20] pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos; 8003dfa: 4b9c ldr r3, [pc, #624] ; (800406c ) 8003dfc: 6adb ldr r3, [r3, #44] ; 0x2c 8003dfe: 091b lsrs r3, r3, #4 8003e00: f003 0301 and.w r3, r3, #1 8003e04: 613b str r3, [r7, #16] fracn2 =(float_t)(uint32_t)(pll2fracen* ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2)>> 3)); 8003e06: 4b99 ldr r3, [pc, #612] ; (800406c ) 8003e08: 6bdb ldr r3, [r3, #60] ; 0x3c 8003e0a: 08db lsrs r3, r3, #3 8003e0c: f3c3 030c ubfx r3, r3, #0, #13 8003e10: 693a ldr r2, [r7, #16] 8003e12: fb02 f303 mul.w r3, r2, r3 8003e16: ee07 3a90 vmov s15, r3 8003e1a: eef8 7a67 vcvt.f32.u32 s15, s15 8003e1e: edc7 7a03 vstr s15, [r7, #12] if (pll2m != 0U) 8003e22: 697b ldr r3, [r7, #20] 8003e24: 2b00 cmp r3, #0 8003e26: f000 8111 beq.w 800404c { switch (pllsource) 8003e2a: 69bb ldr r3, [r7, #24] 8003e2c: 2b02 cmp r3, #2 8003e2e: f000 8083 beq.w 8003f38 8003e32: 69bb ldr r3, [r7, #24] 8003e34: 2b02 cmp r3, #2 8003e36: f200 80a1 bhi.w 8003f7c 8003e3a: 69bb ldr r3, [r7, #24] 8003e3c: 2b00 cmp r3, #0 8003e3e: d003 beq.n 8003e48 8003e40: 69bb ldr r3, [r7, #24] 8003e42: 2b01 cmp r3, #1 8003e44: d056 beq.n 8003ef4 8003e46: e099 b.n 8003f7c { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8003e48: 4b88 ldr r3, [pc, #544] ; (800406c ) 8003e4a: 681b ldr r3, [r3, #0] 8003e4c: f003 0320 and.w r3, r3, #32 8003e50: 2b00 cmp r3, #0 8003e52: d02d beq.n 8003eb0 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 8003e54: 4b85 ldr r3, [pc, #532] ; (800406c ) 8003e56: 681b ldr r3, [r3, #0] 8003e58: 08db lsrs r3, r3, #3 8003e5a: f003 0303 and.w r3, r3, #3 8003e5e: 4a84 ldr r2, [pc, #528] ; (8004070 ) 8003e60: fa22 f303 lsr.w r3, r2, r3 8003e64: 60bb str r3, [r7, #8] pll2vco = ( (float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 ); 8003e66: 68bb ldr r3, [r7, #8] 8003e68: ee07 3a90 vmov s15, r3 8003e6c: eef8 6a67 vcvt.f32.u32 s13, s15 8003e70: 697b ldr r3, [r7, #20] 8003e72: ee07 3a90 vmov s15, r3 8003e76: eef8 7a67 vcvt.f32.u32 s15, s15 8003e7a: ee86 7aa7 vdiv.f32 s14, s13, s15 8003e7e: 4b7b ldr r3, [pc, #492] ; (800406c ) 8003e80: 6b9b ldr r3, [r3, #56] ; 0x38 8003e82: f3c3 0308 ubfx r3, r3, #0, #9 8003e86: ee07 3a90 vmov s15, r3 8003e8a: eef8 6a67 vcvt.f32.u32 s13, s15 8003e8e: ed97 6a03 vldr s12, [r7, #12] 8003e92: eddf 5a78 vldr s11, [pc, #480] ; 8004074 8003e96: eec6 7a25 vdiv.f32 s15, s12, s11 8003e9a: ee76 7aa7 vadd.f32 s15, s13, s15 8003e9e: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8003ea2: ee77 7aa6 vadd.f32 s15, s15, s13 8003ea6: ee67 7a27 vmul.f32 s15, s14, s15 8003eaa: edc7 7a07 vstr s15, [r7, #28] } else { pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 ); } break; 8003eae: e087 b.n 8003fc0 pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 ); 8003eb0: 697b ldr r3, [r7, #20] 8003eb2: ee07 3a90 vmov s15, r3 8003eb6: eef8 7a67 vcvt.f32.u32 s15, s15 8003eba: eddf 6a6f vldr s13, [pc, #444] ; 8004078 8003ebe: ee86 7aa7 vdiv.f32 s14, s13, s15 8003ec2: 4b6a ldr r3, [pc, #424] ; (800406c ) 8003ec4: 6b9b ldr r3, [r3, #56] ; 0x38 8003ec6: f3c3 0308 ubfx r3, r3, #0, #9 8003eca: ee07 3a90 vmov s15, r3 8003ece: eef8 6a67 vcvt.f32.u32 s13, s15 8003ed2: ed97 6a03 vldr s12, [r7, #12] 8003ed6: eddf 5a67 vldr s11, [pc, #412] ; 8004074 8003eda: eec6 7a25 vdiv.f32 s15, s12, s11 8003ede: ee76 7aa7 vadd.f32 s15, s13, s15 8003ee2: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8003ee6: ee77 7aa6 vadd.f32 s15, s15, s13 8003eea: ee67 7a27 vmul.f32 s15, s14, s15 8003eee: edc7 7a07 vstr s15, [r7, #28] break; 8003ef2: e065 b.n 8003fc0 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 ); 8003ef4: 697b ldr r3, [r7, #20] 8003ef6: ee07 3a90 vmov s15, r3 8003efa: eef8 7a67 vcvt.f32.u32 s15, s15 8003efe: eddf 6a5f vldr s13, [pc, #380] ; 800407c 8003f02: ee86 7aa7 vdiv.f32 s14, s13, s15 8003f06: 4b59 ldr r3, [pc, #356] ; (800406c ) 8003f08: 6b9b ldr r3, [r3, #56] ; 0x38 8003f0a: f3c3 0308 ubfx r3, r3, #0, #9 8003f0e: ee07 3a90 vmov s15, r3 8003f12: eef8 6a67 vcvt.f32.u32 s13, s15 8003f16: ed97 6a03 vldr s12, [r7, #12] 8003f1a: eddf 5a56 vldr s11, [pc, #344] ; 8004074 8003f1e: eec6 7a25 vdiv.f32 s15, s12, s11 8003f22: ee76 7aa7 vadd.f32 s15, s13, s15 8003f26: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8003f2a: ee77 7aa6 vadd.f32 s15, s15, s13 8003f2e: ee67 7a27 vmul.f32 s15, s14, s15 8003f32: edc7 7a07 vstr s15, [r7, #28] break; 8003f36: e043 b.n 8003fc0 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 ); 8003f38: 697b ldr r3, [r7, #20] 8003f3a: ee07 3a90 vmov s15, r3 8003f3e: eef8 7a67 vcvt.f32.u32 s15, s15 8003f42: eddf 6a4f vldr s13, [pc, #316] ; 8004080 8003f46: ee86 7aa7 vdiv.f32 s14, s13, s15 8003f4a: 4b48 ldr r3, [pc, #288] ; (800406c ) 8003f4c: 6b9b ldr r3, [r3, #56] ; 0x38 8003f4e: f3c3 0308 ubfx r3, r3, #0, #9 8003f52: ee07 3a90 vmov s15, r3 8003f56: eef8 6a67 vcvt.f32.u32 s13, s15 8003f5a: ed97 6a03 vldr s12, [r7, #12] 8003f5e: eddf 5a45 vldr s11, [pc, #276] ; 8004074 8003f62: eec6 7a25 vdiv.f32 s15, s12, s11 8003f66: ee76 7aa7 vadd.f32 s15, s13, s15 8003f6a: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8003f6e: ee77 7aa6 vadd.f32 s15, s15, s13 8003f72: ee67 7a27 vmul.f32 s15, s14, s15 8003f76: edc7 7a07 vstr s15, [r7, #28] break; 8003f7a: e021 b.n 8003fc0 default: pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 ); 8003f7c: 697b ldr r3, [r7, #20] 8003f7e: ee07 3a90 vmov s15, r3 8003f82: eef8 7a67 vcvt.f32.u32 s15, s15 8003f86: eddf 6a3d vldr s13, [pc, #244] ; 800407c 8003f8a: ee86 7aa7 vdiv.f32 s14, s13, s15 8003f8e: 4b37 ldr r3, [pc, #220] ; (800406c ) 8003f90: 6b9b ldr r3, [r3, #56] ; 0x38 8003f92: f3c3 0308 ubfx r3, r3, #0, #9 8003f96: ee07 3a90 vmov s15, r3 8003f9a: eef8 6a67 vcvt.f32.u32 s13, s15 8003f9e: ed97 6a03 vldr s12, [r7, #12] 8003fa2: eddf 5a34 vldr s11, [pc, #208] ; 8004074 8003fa6: eec6 7a25 vdiv.f32 s15, s12, s11 8003faa: ee76 7aa7 vadd.f32 s15, s13, s15 8003fae: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8003fb2: ee77 7aa6 vadd.f32 s15, s15, s13 8003fb6: ee67 7a27 vmul.f32 s15, s14, s15 8003fba: edc7 7a07 vstr s15, [r7, #28] break; 8003fbe: bf00 nop } PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >>9) + (float_t)1 )) ; 8003fc0: 4b2a ldr r3, [pc, #168] ; (800406c ) 8003fc2: 6b9b ldr r3, [r3, #56] ; 0x38 8003fc4: 0a5b lsrs r3, r3, #9 8003fc6: f003 037f and.w r3, r3, #127 ; 0x7f 8003fca: ee07 3a90 vmov s15, r3 8003fce: eef8 7a67 vcvt.f32.u32 s15, s15 8003fd2: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 8003fd6: ee37 7a87 vadd.f32 s14, s15, s14 8003fda: edd7 6a07 vldr s13, [r7, #28] 8003fde: eec6 7a87 vdiv.f32 s15, s13, s14 8003fe2: eefc 7ae7 vcvt.u32.f32 s15, s15 8003fe6: ee17 2a90 vmov r2, s15 8003fea: 687b ldr r3, [r7, #4] 8003fec: 601a str r2, [r3, #0] PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >>16) + (float_t)1 )) ; 8003fee: 4b1f ldr r3, [pc, #124] ; (800406c ) 8003ff0: 6b9b ldr r3, [r3, #56] ; 0x38 8003ff2: 0c1b lsrs r3, r3, #16 8003ff4: f003 037f and.w r3, r3, #127 ; 0x7f 8003ff8: ee07 3a90 vmov s15, r3 8003ffc: eef8 7a67 vcvt.f32.u32 s15, s15 8004000: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 8004004: ee37 7a87 vadd.f32 s14, s15, s14 8004008: edd7 6a07 vldr s13, [r7, #28] 800400c: eec6 7a87 vdiv.f32 s15, s13, s14 8004010: eefc 7ae7 vcvt.u32.f32 s15, s15 8004014: ee17 2a90 vmov r2, s15 8004018: 687b ldr r3, [r7, #4] 800401a: 605a str r2, [r3, #4] PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >>24) + (float_t)1 )) ; 800401c: 4b13 ldr r3, [pc, #76] ; (800406c ) 800401e: 6b9b ldr r3, [r3, #56] ; 0x38 8004020: 0e1b lsrs r3, r3, #24 8004022: f003 037f and.w r3, r3, #127 ; 0x7f 8004026: ee07 3a90 vmov s15, r3 800402a: eef8 7a67 vcvt.f32.u32 s15, s15 800402e: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 8004032: ee37 7a87 vadd.f32 s14, s15, s14 8004036: edd7 6a07 vldr s13, [r7, #28] 800403a: eec6 7a87 vdiv.f32 s15, s13, s14 800403e: eefc 7ae7 vcvt.u32.f32 s15, s15 8004042: ee17 2a90 vmov r2, s15 8004046: 687b ldr r3, [r7, #4] 8004048: 609a str r2, [r3, #8] { PLL2_Clocks->PLL2_P_Frequency = 0U; PLL2_Clocks->PLL2_Q_Frequency = 0U; PLL2_Clocks->PLL2_R_Frequency = 0U; } } 800404a: e008 b.n 800405e PLL2_Clocks->PLL2_P_Frequency = 0U; 800404c: 687b ldr r3, [r7, #4] 800404e: 2200 movs r2, #0 8004050: 601a str r2, [r3, #0] PLL2_Clocks->PLL2_Q_Frequency = 0U; 8004052: 687b ldr r3, [r7, #4] 8004054: 2200 movs r2, #0 8004056: 605a str r2, [r3, #4] PLL2_Clocks->PLL2_R_Frequency = 0U; 8004058: 687b ldr r3, [r7, #4] 800405a: 2200 movs r2, #0 800405c: 609a str r2, [r3, #8] } 800405e: bf00 nop 8004060: 3724 adds r7, #36 ; 0x24 8004062: 46bd mov sp, r7 8004064: f85d 7b04 ldr.w r7, [sp], #4 8004068: 4770 bx lr 800406a: bf00 nop 800406c: 58024400 .word 0x58024400 8004070: 03d09000 .word 0x03d09000 8004074: 46000000 .word 0x46000000 8004078: 4c742400 .word 0x4c742400 800407c: 4a742400 .word 0x4a742400 8004080: 4af42400 .word 0x4af42400 08004084 : * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL3_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks) { 8004084: b480 push {r7} 8004086: b089 sub sp, #36 ; 0x24 8004088: af00 add r7, sp, #0 800408a: 6078 str r0, [r7, #4] float_t fracn3, pll3vco; /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N PLL3xCLK = PLL3_VCO / PLLxR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800408c: 4ba1 ldr r3, [pc, #644] ; (8004314 ) 800408e: 6a9b ldr r3, [r3, #40] ; 0x28 8004090: f003 0303 and.w r3, r3, #3 8004094: 61bb str r3, [r7, #24] pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> 20) ; 8004096: 4b9f ldr r3, [pc, #636] ; (8004314 ) 8004098: 6a9b ldr r3, [r3, #40] ; 0x28 800409a: 0d1b lsrs r3, r3, #20 800409c: f003 033f and.w r3, r3, #63 ; 0x3f 80040a0: 617b str r3, [r7, #20] pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos; 80040a2: 4b9c ldr r3, [pc, #624] ; (8004314 ) 80040a4: 6adb ldr r3, [r3, #44] ; 0x2c 80040a6: 0a1b lsrs r3, r3, #8 80040a8: f003 0301 and.w r3, r3, #1 80040ac: 613b str r3, [r7, #16] fracn3 = (float_t)(uint32_t)(pll3fracen* ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3)>> 3)); 80040ae: 4b99 ldr r3, [pc, #612] ; (8004314 ) 80040b0: 6c5b ldr r3, [r3, #68] ; 0x44 80040b2: 08db lsrs r3, r3, #3 80040b4: f3c3 030c ubfx r3, r3, #0, #13 80040b8: 693a ldr r2, [r7, #16] 80040ba: fb02 f303 mul.w r3, r2, r3 80040be: ee07 3a90 vmov s15, r3 80040c2: eef8 7a67 vcvt.f32.u32 s15, s15 80040c6: edc7 7a03 vstr s15, [r7, #12] if (pll3m != 0U) 80040ca: 697b ldr r3, [r7, #20] 80040cc: 2b00 cmp r3, #0 80040ce: f000 8111 beq.w 80042f4 { switch (pllsource) 80040d2: 69bb ldr r3, [r7, #24] 80040d4: 2b02 cmp r3, #2 80040d6: f000 8083 beq.w 80041e0 80040da: 69bb ldr r3, [r7, #24] 80040dc: 2b02 cmp r3, #2 80040de: f200 80a1 bhi.w 8004224 80040e2: 69bb ldr r3, [r7, #24] 80040e4: 2b00 cmp r3, #0 80040e6: d003 beq.n 80040f0 80040e8: 69bb ldr r3, [r7, #24] 80040ea: 2b01 cmp r3, #1 80040ec: d056 beq.n 800419c 80040ee: e099 b.n 8004224 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 80040f0: 4b88 ldr r3, [pc, #544] ; (8004314 ) 80040f2: 681b ldr r3, [r3, #0] 80040f4: f003 0320 and.w r3, r3, #32 80040f8: 2b00 cmp r3, #0 80040fa: d02d beq.n 8004158 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 80040fc: 4b85 ldr r3, [pc, #532] ; (8004314 ) 80040fe: 681b ldr r3, [r3, #0] 8004100: 08db lsrs r3, r3, #3 8004102: f003 0303 and.w r3, r3, #3 8004106: 4a84 ldr r2, [pc, #528] ; (8004318 ) 8004108: fa22 f303 lsr.w r3, r2, r3 800410c: 60bb str r3, [r7, #8] pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 ); 800410e: 68bb ldr r3, [r7, #8] 8004110: ee07 3a90 vmov s15, r3 8004114: eef8 6a67 vcvt.f32.u32 s13, s15 8004118: 697b ldr r3, [r7, #20] 800411a: ee07 3a90 vmov s15, r3 800411e: eef8 7a67 vcvt.f32.u32 s15, s15 8004122: ee86 7aa7 vdiv.f32 s14, s13, s15 8004126: 4b7b ldr r3, [pc, #492] ; (8004314 ) 8004128: 6c1b ldr r3, [r3, #64] ; 0x40 800412a: f3c3 0308 ubfx r3, r3, #0, #9 800412e: ee07 3a90 vmov s15, r3 8004132: eef8 6a67 vcvt.f32.u32 s13, s15 8004136: ed97 6a03 vldr s12, [r7, #12] 800413a: eddf 5a78 vldr s11, [pc, #480] ; 800431c 800413e: eec6 7a25 vdiv.f32 s15, s12, s11 8004142: ee76 7aa7 vadd.f32 s15, s13, s15 8004146: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 800414a: ee77 7aa6 vadd.f32 s15, s15, s13 800414e: ee67 7a27 vmul.f32 s15, s14, s15 8004152: edc7 7a07 vstr s15, [r7, #28] } else { pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 ); } break; 8004156: e087 b.n 8004268 pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 ); 8004158: 697b ldr r3, [r7, #20] 800415a: ee07 3a90 vmov s15, r3 800415e: eef8 7a67 vcvt.f32.u32 s15, s15 8004162: eddf 6a6f vldr s13, [pc, #444] ; 8004320 8004166: ee86 7aa7 vdiv.f32 s14, s13, s15 800416a: 4b6a ldr r3, [pc, #424] ; (8004314 ) 800416c: 6c1b ldr r3, [r3, #64] ; 0x40 800416e: f3c3 0308 ubfx r3, r3, #0, #9 8004172: ee07 3a90 vmov s15, r3 8004176: eef8 6a67 vcvt.f32.u32 s13, s15 800417a: ed97 6a03 vldr s12, [r7, #12] 800417e: eddf 5a67 vldr s11, [pc, #412] ; 800431c 8004182: eec6 7a25 vdiv.f32 s15, s12, s11 8004186: ee76 7aa7 vadd.f32 s15, s13, s15 800418a: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 800418e: ee77 7aa6 vadd.f32 s15, s15, s13 8004192: ee67 7a27 vmul.f32 s15, s14, s15 8004196: edc7 7a07 vstr s15, [r7, #28] break; 800419a: e065 b.n 8004268 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 ); 800419c: 697b ldr r3, [r7, #20] 800419e: ee07 3a90 vmov s15, r3 80041a2: eef8 7a67 vcvt.f32.u32 s15, s15 80041a6: eddf 6a5f vldr s13, [pc, #380] ; 8004324 80041aa: ee86 7aa7 vdiv.f32 s14, s13, s15 80041ae: 4b59 ldr r3, [pc, #356] ; (8004314 ) 80041b0: 6c1b ldr r3, [r3, #64] ; 0x40 80041b2: f3c3 0308 ubfx r3, r3, #0, #9 80041b6: ee07 3a90 vmov s15, r3 80041ba: eef8 6a67 vcvt.f32.u32 s13, s15 80041be: ed97 6a03 vldr s12, [r7, #12] 80041c2: eddf 5a56 vldr s11, [pc, #344] ; 800431c 80041c6: eec6 7a25 vdiv.f32 s15, s12, s11 80041ca: ee76 7aa7 vadd.f32 s15, s13, s15 80041ce: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 80041d2: ee77 7aa6 vadd.f32 s15, s15, s13 80041d6: ee67 7a27 vmul.f32 s15, s14, s15 80041da: edc7 7a07 vstr s15, [r7, #28] break; 80041de: e043 b.n 8004268 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 ); 80041e0: 697b ldr r3, [r7, #20] 80041e2: ee07 3a90 vmov s15, r3 80041e6: eef8 7a67 vcvt.f32.u32 s15, s15 80041ea: eddf 6a4f vldr s13, [pc, #316] ; 8004328 80041ee: ee86 7aa7 vdiv.f32 s14, s13, s15 80041f2: 4b48 ldr r3, [pc, #288] ; (8004314 ) 80041f4: 6c1b ldr r3, [r3, #64] ; 0x40 80041f6: f3c3 0308 ubfx r3, r3, #0, #9 80041fa: ee07 3a90 vmov s15, r3 80041fe: eef8 6a67 vcvt.f32.u32 s13, s15 8004202: ed97 6a03 vldr s12, [r7, #12] 8004206: eddf 5a45 vldr s11, [pc, #276] ; 800431c 800420a: eec6 7a25 vdiv.f32 s15, s12, s11 800420e: ee76 7aa7 vadd.f32 s15, s13, s15 8004212: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8004216: ee77 7aa6 vadd.f32 s15, s15, s13 800421a: ee67 7a27 vmul.f32 s15, s14, s15 800421e: edc7 7a07 vstr s15, [r7, #28] break; 8004222: e021 b.n 8004268 default: pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 ); 8004224: 697b ldr r3, [r7, #20] 8004226: ee07 3a90 vmov s15, r3 800422a: eef8 7a67 vcvt.f32.u32 s15, s15 800422e: eddf 6a3d vldr s13, [pc, #244] ; 8004324 8004232: ee86 7aa7 vdiv.f32 s14, s13, s15 8004236: 4b37 ldr r3, [pc, #220] ; (8004314 ) 8004238: 6c1b ldr r3, [r3, #64] ; 0x40 800423a: f3c3 0308 ubfx r3, r3, #0, #9 800423e: ee07 3a90 vmov s15, r3 8004242: eef8 6a67 vcvt.f32.u32 s13, s15 8004246: ed97 6a03 vldr s12, [r7, #12] 800424a: eddf 5a34 vldr s11, [pc, #208] ; 800431c 800424e: eec6 7a25 vdiv.f32 s15, s12, s11 8004252: ee76 7aa7 vadd.f32 s15, s13, s15 8004256: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 800425a: ee77 7aa6 vadd.f32 s15, s15, s13 800425e: ee67 7a27 vmul.f32 s15, s14, s15 8004262: edc7 7a07 vstr s15, [r7, #28] break; 8004266: bf00 nop } PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >>9) + (float_t)1 )) ; 8004268: 4b2a ldr r3, [pc, #168] ; (8004314 ) 800426a: 6c1b ldr r3, [r3, #64] ; 0x40 800426c: 0a5b lsrs r3, r3, #9 800426e: f003 037f and.w r3, r3, #127 ; 0x7f 8004272: ee07 3a90 vmov s15, r3 8004276: eef8 7a67 vcvt.f32.u32 s15, s15 800427a: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 800427e: ee37 7a87 vadd.f32 s14, s15, s14 8004282: edd7 6a07 vldr s13, [r7, #28] 8004286: eec6 7a87 vdiv.f32 s15, s13, s14 800428a: eefc 7ae7 vcvt.u32.f32 s15, s15 800428e: ee17 2a90 vmov r2, s15 8004292: 687b ldr r3, [r7, #4] 8004294: 601a str r2, [r3, #0] PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >>16) + (float_t)1 )) ; 8004296: 4b1f ldr r3, [pc, #124] ; (8004314 ) 8004298: 6c1b ldr r3, [r3, #64] ; 0x40 800429a: 0c1b lsrs r3, r3, #16 800429c: f003 037f and.w r3, r3, #127 ; 0x7f 80042a0: ee07 3a90 vmov s15, r3 80042a4: eef8 7a67 vcvt.f32.u32 s15, s15 80042a8: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 80042ac: ee37 7a87 vadd.f32 s14, s15, s14 80042b0: edd7 6a07 vldr s13, [r7, #28] 80042b4: eec6 7a87 vdiv.f32 s15, s13, s14 80042b8: eefc 7ae7 vcvt.u32.f32 s15, s15 80042bc: ee17 2a90 vmov r2, s15 80042c0: 687b ldr r3, [r7, #4] 80042c2: 605a str r2, [r3, #4] PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >>24) + (float_t)1 )) ; 80042c4: 4b13 ldr r3, [pc, #76] ; (8004314 ) 80042c6: 6c1b ldr r3, [r3, #64] ; 0x40 80042c8: 0e1b lsrs r3, r3, #24 80042ca: f003 037f and.w r3, r3, #127 ; 0x7f 80042ce: ee07 3a90 vmov s15, r3 80042d2: eef8 7a67 vcvt.f32.u32 s15, s15 80042d6: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 80042da: ee37 7a87 vadd.f32 s14, s15, s14 80042de: edd7 6a07 vldr s13, [r7, #28] 80042e2: eec6 7a87 vdiv.f32 s15, s13, s14 80042e6: eefc 7ae7 vcvt.u32.f32 s15, s15 80042ea: ee17 2a90 vmov r2, s15 80042ee: 687b ldr r3, [r7, #4] 80042f0: 609a str r2, [r3, #8] PLL3_Clocks->PLL3_P_Frequency = 0U; PLL3_Clocks->PLL3_Q_Frequency = 0U; PLL3_Clocks->PLL3_R_Frequency = 0U; } } 80042f2: e008 b.n 8004306 PLL3_Clocks->PLL3_P_Frequency = 0U; 80042f4: 687b ldr r3, [r7, #4] 80042f6: 2200 movs r2, #0 80042f8: 601a str r2, [r3, #0] PLL3_Clocks->PLL3_Q_Frequency = 0U; 80042fa: 687b ldr r3, [r7, #4] 80042fc: 2200 movs r2, #0 80042fe: 605a str r2, [r3, #4] PLL3_Clocks->PLL3_R_Frequency = 0U; 8004300: 687b ldr r3, [r7, #4] 8004302: 2200 movs r2, #0 8004304: 609a str r2, [r3, #8] } 8004306: bf00 nop 8004308: 3724 adds r7, #36 ; 0x24 800430a: 46bd mov sp, r7 800430c: f85d 7b04 ldr.w r7, [sp], #4 8004310: 4770 bx lr 8004312: bf00 nop 8004314: 58024400 .word 0x58024400 8004318: 03d09000 .word 0x03d09000 800431c: 46000000 .word 0x46000000 8004320: 4c742400 .word 0x4c742400 8004324: 4a742400 .word 0x4a742400 8004328: 4af42400 .word 0x4af42400 0800432c : * @note PLL2 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider) { 800432c: b580 push {r7, lr} 800432e: b084 sub sp, #16 8004330: af00 add r7, sp, #0 8004332: 6078 str r0, [r7, #4] 8004334: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 8004336: 2300 movs r3, #0 8004338: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE)); assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN)); /* Check that PLL2 OSC clock source is already set */ if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 800433a: 4b53 ldr r3, [pc, #332] ; (8004488 ) 800433c: 6a9b ldr r3, [r3, #40] ; 0x28 800433e: f003 0303 and.w r3, r3, #3 8004342: 2b03 cmp r3, #3 8004344: d101 bne.n 800434a { return HAL_ERROR; 8004346: 2301 movs r3, #1 8004348: e099 b.n 800447e else { /* Disable PLL2. */ __HAL_RCC_PLL2_DISABLE(); 800434a: 4b4f ldr r3, [pc, #316] ; (8004488 ) 800434c: 681b ldr r3, [r3, #0] 800434e: 4a4e ldr r2, [pc, #312] ; (8004488 ) 8004350: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000 8004354: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004356: f7fc fdc9 bl 8000eec 800435a: 60b8 str r0, [r7, #8] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 800435c: e008 b.n 8004370 { if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE) 800435e: f7fc fdc5 bl 8000eec 8004362: 4602 mov r2, r0 8004364: 68bb ldr r3, [r7, #8] 8004366: 1ad3 subs r3, r2, r3 8004368: 2b02 cmp r3, #2 800436a: d901 bls.n 8004370 { return HAL_TIMEOUT; 800436c: 2303 movs r3, #3 800436e: e086 b.n 800447e while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 8004370: 4b45 ldr r3, [pc, #276] ; (8004488 ) 8004372: 681b ldr r3, [r3, #0] 8004374: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8004378: 2b00 cmp r3, #0 800437a: d1f0 bne.n 800435e } } /* Configure PLL2 multiplication and division factors. */ __HAL_RCC_PLL2_CONFIG(pll2->PLL2M, 800437c: 4b42 ldr r3, [pc, #264] ; (8004488 ) 800437e: 6a9b ldr r3, [r3, #40] ; 0x28 8004380: f423 327c bic.w r2, r3, #258048 ; 0x3f000 8004384: 687b ldr r3, [r7, #4] 8004386: 681b ldr r3, [r3, #0] 8004388: 031b lsls r3, r3, #12 800438a: 493f ldr r1, [pc, #252] ; (8004488 ) 800438c: 4313 orrs r3, r2 800438e: 628b str r3, [r1, #40] ; 0x28 8004390: 687b ldr r3, [r7, #4] 8004392: 685b ldr r3, [r3, #4] 8004394: 3b01 subs r3, #1 8004396: f3c3 0208 ubfx r2, r3, #0, #9 800439a: 687b ldr r3, [r7, #4] 800439c: 689b ldr r3, [r3, #8] 800439e: 3b01 subs r3, #1 80043a0: 025b lsls r3, r3, #9 80043a2: b29b uxth r3, r3 80043a4: 431a orrs r2, r3 80043a6: 687b ldr r3, [r7, #4] 80043a8: 68db ldr r3, [r3, #12] 80043aa: 3b01 subs r3, #1 80043ac: 041b lsls r3, r3, #16 80043ae: f403 03fe and.w r3, r3, #8323072 ; 0x7f0000 80043b2: 431a orrs r2, r3 80043b4: 687b ldr r3, [r7, #4] 80043b6: 691b ldr r3, [r3, #16] 80043b8: 3b01 subs r3, #1 80043ba: 061b lsls r3, r3, #24 80043bc: f003 43fe and.w r3, r3, #2130706432 ; 0x7f000000 80043c0: 4931 ldr r1, [pc, #196] ; (8004488 ) 80043c2: 4313 orrs r3, r2 80043c4: 638b str r3, [r1, #56] ; 0x38 pll2->PLL2P, pll2->PLL2Q, pll2->PLL2R); /* Select PLL2 input reference frequency range: VCI */ __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ; 80043c6: 4b30 ldr r3, [pc, #192] ; (8004488 ) 80043c8: 6adb ldr r3, [r3, #44] ; 0x2c 80043ca: f023 02c0 bic.w r2, r3, #192 ; 0xc0 80043ce: 687b ldr r3, [r7, #4] 80043d0: 695b ldr r3, [r3, #20] 80043d2: 492d ldr r1, [pc, #180] ; (8004488 ) 80043d4: 4313 orrs r3, r2 80043d6: 62cb str r3, [r1, #44] ; 0x2c /* Select PLL2 output frequency range : VCO */ __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ; 80043d8: 4b2b ldr r3, [pc, #172] ; (8004488 ) 80043da: 6adb ldr r3, [r3, #44] ; 0x2c 80043dc: f023 0220 bic.w r2, r3, #32 80043e0: 687b ldr r3, [r7, #4] 80043e2: 699b ldr r3, [r3, #24] 80043e4: 4928 ldr r1, [pc, #160] ; (8004488 ) 80043e6: 4313 orrs r3, r2 80043e8: 62cb str r3, [r1, #44] ; 0x2c /* Disable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_DISABLE(); 80043ea: 4b27 ldr r3, [pc, #156] ; (8004488 ) 80043ec: 6adb ldr r3, [r3, #44] ; 0x2c 80043ee: 4a26 ldr r2, [pc, #152] ; (8004488 ) 80043f0: f023 0310 bic.w r3, r3, #16 80043f4: 62d3 str r3, [r2, #44] ; 0x2c /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN); 80043f6: 4b24 ldr r3, [pc, #144] ; (8004488 ) 80043f8: 6bda ldr r2, [r3, #60] ; 0x3c 80043fa: 4b24 ldr r3, [pc, #144] ; (800448c ) 80043fc: 4013 ands r3, r2 80043fe: 687a ldr r2, [r7, #4] 8004400: 69d2 ldr r2, [r2, #28] 8004402: 00d2 lsls r2, r2, #3 8004404: 4920 ldr r1, [pc, #128] ; (8004488 ) 8004406: 4313 orrs r3, r2 8004408: 63cb str r3, [r1, #60] ; 0x3c /* Enable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_ENABLE(); 800440a: 4b1f ldr r3, [pc, #124] ; (8004488 ) 800440c: 6adb ldr r3, [r3, #44] ; 0x2c 800440e: 4a1e ldr r2, [pc, #120] ; (8004488 ) 8004410: f043 0310 orr.w r3, r3, #16 8004414: 62d3 str r3, [r2, #44] ; 0x2c /* Enable the PLL2 clock output */ if(Divider == DIVIDER_P_UPDATE) 8004416: 683b ldr r3, [r7, #0] 8004418: 2b00 cmp r3, #0 800441a: d106 bne.n 800442a { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP); 800441c: 4b1a ldr r3, [pc, #104] ; (8004488 ) 800441e: 6adb ldr r3, [r3, #44] ; 0x2c 8004420: 4a19 ldr r2, [pc, #100] ; (8004488 ) 8004422: f443 2300 orr.w r3, r3, #524288 ; 0x80000 8004426: 62d3 str r3, [r2, #44] ; 0x2c 8004428: e00f b.n 800444a } else if(Divider == DIVIDER_Q_UPDATE) 800442a: 683b ldr r3, [r7, #0] 800442c: 2b01 cmp r3, #1 800442e: d106 bne.n 800443e { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ); 8004430: 4b15 ldr r3, [pc, #84] ; (8004488 ) 8004432: 6adb ldr r3, [r3, #44] ; 0x2c 8004434: 4a14 ldr r2, [pc, #80] ; (8004488 ) 8004436: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 800443a: 62d3 str r3, [r2, #44] ; 0x2c 800443c: e005 b.n 800444a } else { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR); 800443e: 4b12 ldr r3, [pc, #72] ; (8004488 ) 8004440: 6adb ldr r3, [r3, #44] ; 0x2c 8004442: 4a11 ldr r2, [pc, #68] ; (8004488 ) 8004444: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 8004448: 62d3 str r3, [r2, #44] ; 0x2c } /* Enable PLL2. */ __HAL_RCC_PLL2_ENABLE(); 800444a: 4b0f ldr r3, [pc, #60] ; (8004488 ) 800444c: 681b ldr r3, [r3, #0] 800444e: 4a0e ldr r2, [pc, #56] ; (8004488 ) 8004450: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 8004454: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004456: f7fc fd49 bl 8000eec 800445a: 60b8 str r0, [r7, #8] /* Wait till PLL2 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 800445c: e008 b.n 8004470 { if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE) 800445e: f7fc fd45 bl 8000eec 8004462: 4602 mov r2, r0 8004464: 68bb ldr r3, [r7, #8] 8004466: 1ad3 subs r3, r2, r3 8004468: 2b02 cmp r3, #2 800446a: d901 bls.n 8004470 { return HAL_TIMEOUT; 800446c: 2303 movs r3, #3 800446e: e006 b.n 800447e while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 8004470: 4b05 ldr r3, [pc, #20] ; (8004488 ) 8004472: 681b ldr r3, [r3, #0] 8004474: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8004478: 2b00 cmp r3, #0 800447a: d0f0 beq.n 800445e } } return status; 800447c: 7bfb ldrb r3, [r7, #15] } 800447e: 4618 mov r0, r3 8004480: 3710 adds r7, #16 8004482: 46bd mov sp, r7 8004484: bd80 pop {r7, pc} 8004486: bf00 nop 8004488: 58024400 .word 0x58024400 800448c: ffff0007 .word 0xffff0007 08004490 : * @note PLL3 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider) { 8004490: b580 push {r7, lr} 8004492: b084 sub sp, #16 8004494: af00 add r7, sp, #0 8004496: 6078 str r0, [r7, #4] 8004498: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 800449a: 2300 movs r3, #0 800449c: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE)); assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN)); /* Check that PLL3 OSC clock source is already set */ if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 800449e: 4b53 ldr r3, [pc, #332] ; (80045ec ) 80044a0: 6a9b ldr r3, [r3, #40] ; 0x28 80044a2: f003 0303 and.w r3, r3, #3 80044a6: 2b03 cmp r3, #3 80044a8: d101 bne.n 80044ae { return HAL_ERROR; 80044aa: 2301 movs r3, #1 80044ac: e099 b.n 80045e2 else { /* Disable PLL3. */ __HAL_RCC_PLL3_DISABLE(); 80044ae: 4b4f ldr r3, [pc, #316] ; (80045ec ) 80044b0: 681b ldr r3, [r3, #0] 80044b2: 4a4e ldr r2, [pc, #312] ; (80045ec ) 80044b4: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 80044b8: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80044ba: f7fc fd17 bl 8000eec 80044be: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 80044c0: e008 b.n 80044d4 { if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE) 80044c2: f7fc fd13 bl 8000eec 80044c6: 4602 mov r2, r0 80044c8: 68bb ldr r3, [r7, #8] 80044ca: 1ad3 subs r3, r2, r3 80044cc: 2b02 cmp r3, #2 80044ce: d901 bls.n 80044d4 { return HAL_TIMEOUT; 80044d0: 2303 movs r3, #3 80044d2: e086 b.n 80045e2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 80044d4: 4b45 ldr r3, [pc, #276] ; (80045ec ) 80044d6: 681b ldr r3, [r3, #0] 80044d8: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 80044dc: 2b00 cmp r3, #0 80044de: d1f0 bne.n 80044c2 } } /* Configure the PLL3 multiplication and division factors. */ __HAL_RCC_PLL3_CONFIG(pll3->PLL3M, 80044e0: 4b42 ldr r3, [pc, #264] ; (80045ec ) 80044e2: 6a9b ldr r3, [r3, #40] ; 0x28 80044e4: f023 727c bic.w r2, r3, #66060288 ; 0x3f00000 80044e8: 687b ldr r3, [r7, #4] 80044ea: 681b ldr r3, [r3, #0] 80044ec: 051b lsls r3, r3, #20 80044ee: 493f ldr r1, [pc, #252] ; (80045ec ) 80044f0: 4313 orrs r3, r2 80044f2: 628b str r3, [r1, #40] ; 0x28 80044f4: 687b ldr r3, [r7, #4] 80044f6: 685b ldr r3, [r3, #4] 80044f8: 3b01 subs r3, #1 80044fa: f3c3 0208 ubfx r2, r3, #0, #9 80044fe: 687b ldr r3, [r7, #4] 8004500: 689b ldr r3, [r3, #8] 8004502: 3b01 subs r3, #1 8004504: 025b lsls r3, r3, #9 8004506: b29b uxth r3, r3 8004508: 431a orrs r2, r3 800450a: 687b ldr r3, [r7, #4] 800450c: 68db ldr r3, [r3, #12] 800450e: 3b01 subs r3, #1 8004510: 041b lsls r3, r3, #16 8004512: f403 03fe and.w r3, r3, #8323072 ; 0x7f0000 8004516: 431a orrs r2, r3 8004518: 687b ldr r3, [r7, #4] 800451a: 691b ldr r3, [r3, #16] 800451c: 3b01 subs r3, #1 800451e: 061b lsls r3, r3, #24 8004520: f003 43fe and.w r3, r3, #2130706432 ; 0x7f000000 8004524: 4931 ldr r1, [pc, #196] ; (80045ec ) 8004526: 4313 orrs r3, r2 8004528: 640b str r3, [r1, #64] ; 0x40 pll3->PLL3P, pll3->PLL3Q, pll3->PLL3R); /* Select PLL3 input reference frequency range: VCI */ __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ; 800452a: 4b30 ldr r3, [pc, #192] ; (80045ec ) 800452c: 6adb ldr r3, [r3, #44] ; 0x2c 800452e: f423 6240 bic.w r2, r3, #3072 ; 0xc00 8004532: 687b ldr r3, [r7, #4] 8004534: 695b ldr r3, [r3, #20] 8004536: 492d ldr r1, [pc, #180] ; (80045ec ) 8004538: 4313 orrs r3, r2 800453a: 62cb str r3, [r1, #44] ; 0x2c /* Select PLL3 output frequency range : VCO */ __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ; 800453c: 4b2b ldr r3, [pc, #172] ; (80045ec ) 800453e: 6adb ldr r3, [r3, #44] ; 0x2c 8004540: f423 7200 bic.w r2, r3, #512 ; 0x200 8004544: 687b ldr r3, [r7, #4] 8004546: 699b ldr r3, [r3, #24] 8004548: 4928 ldr r1, [pc, #160] ; (80045ec ) 800454a: 4313 orrs r3, r2 800454c: 62cb str r3, [r1, #44] ; 0x2c /* Disable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_DISABLE(); 800454e: 4b27 ldr r3, [pc, #156] ; (80045ec ) 8004550: 6adb ldr r3, [r3, #44] ; 0x2c 8004552: 4a26 ldr r2, [pc, #152] ; (80045ec ) 8004554: f423 7380 bic.w r3, r3, #256 ; 0x100 8004558: 62d3 str r3, [r2, #44] ; 0x2c /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN); 800455a: 4b24 ldr r3, [pc, #144] ; (80045ec ) 800455c: 6c5a ldr r2, [r3, #68] ; 0x44 800455e: 4b24 ldr r3, [pc, #144] ; (80045f0 ) 8004560: 4013 ands r3, r2 8004562: 687a ldr r2, [r7, #4] 8004564: 69d2 ldr r2, [r2, #28] 8004566: 00d2 lsls r2, r2, #3 8004568: 4920 ldr r1, [pc, #128] ; (80045ec ) 800456a: 4313 orrs r3, r2 800456c: 644b str r3, [r1, #68] ; 0x44 /* Enable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_ENABLE(); 800456e: 4b1f ldr r3, [pc, #124] ; (80045ec ) 8004570: 6adb ldr r3, [r3, #44] ; 0x2c 8004572: 4a1e ldr r2, [pc, #120] ; (80045ec ) 8004574: f443 7380 orr.w r3, r3, #256 ; 0x100 8004578: 62d3 str r3, [r2, #44] ; 0x2c /* Enable the PLL3 clock output */ if(Divider == DIVIDER_P_UPDATE) 800457a: 683b ldr r3, [r7, #0] 800457c: 2b00 cmp r3, #0 800457e: d106 bne.n 800458e { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP); 8004580: 4b1a ldr r3, [pc, #104] ; (80045ec ) 8004582: 6adb ldr r3, [r3, #44] ; 0x2c 8004584: 4a19 ldr r2, [pc, #100] ; (80045ec ) 8004586: f443 0380 orr.w r3, r3, #4194304 ; 0x400000 800458a: 62d3 str r3, [r2, #44] ; 0x2c 800458c: e00f b.n 80045ae } else if(Divider == DIVIDER_Q_UPDATE) 800458e: 683b ldr r3, [r7, #0] 8004590: 2b01 cmp r3, #1 8004592: d106 bne.n 80045a2 { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ); 8004594: 4b15 ldr r3, [pc, #84] ; (80045ec ) 8004596: 6adb ldr r3, [r3, #44] ; 0x2c 8004598: 4a14 ldr r2, [pc, #80] ; (80045ec ) 800459a: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 800459e: 62d3 str r3, [r2, #44] ; 0x2c 80045a0: e005 b.n 80045ae } else { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR); 80045a2: 4b12 ldr r3, [pc, #72] ; (80045ec ) 80045a4: 6adb ldr r3, [r3, #44] ; 0x2c 80045a6: 4a11 ldr r2, [pc, #68] ; (80045ec ) 80045a8: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 80045ac: 62d3 str r3, [r2, #44] ; 0x2c } /* Enable PLL3. */ __HAL_RCC_PLL3_ENABLE(); 80045ae: 4b0f ldr r3, [pc, #60] ; (80045ec ) 80045b0: 681b ldr r3, [r3, #0] 80045b2: 4a0e ldr r2, [pc, #56] ; (80045ec ) 80045b4: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80045b8: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80045ba: f7fc fc97 bl 8000eec 80045be: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 80045c0: e008 b.n 80045d4 { if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE) 80045c2: f7fc fc93 bl 8000eec 80045c6: 4602 mov r2, r0 80045c8: 68bb ldr r3, [r7, #8] 80045ca: 1ad3 subs r3, r2, r3 80045cc: 2b02 cmp r3, #2 80045ce: d901 bls.n 80045d4 { return HAL_TIMEOUT; 80045d0: 2303 movs r3, #3 80045d2: e006 b.n 80045e2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 80045d4: 4b05 ldr r3, [pc, #20] ; (80045ec ) 80045d6: 681b ldr r3, [r3, #0] 80045d8: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 80045dc: 2b00 cmp r3, #0 80045de: d0f0 beq.n 80045c2 } } return status; 80045e0: 7bfb ldrb r3, [r7, #15] } 80045e2: 4618 mov r0, r3 80045e4: 3710 adds r7, #16 80045e6: 46bd mov sp, r7 80045e8: bd80 pop {r7, pc} 80045ea: bf00 nop 80045ec: 58024400 .word 0x58024400 80045f0: ffff0007 .word 0xffff0007 080045f4 : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 80045f4: b580 push {r7, lr} 80045f6: b082 sub sp, #8 80045f8: af00 add r7, sp, #0 80045fa: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 80045fc: 687b ldr r3, [r7, #4] 80045fe: 2b00 cmp r3, #0 8004600: d101 bne.n 8004606 { return HAL_ERROR; 8004602: 2301 movs r3, #1 8004604: e042 b.n 800468c { /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); } if (huart->gState == HAL_UART_STATE_RESET) 8004606: 687b ldr r3, [r7, #4] 8004608: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 800460c: 2b00 cmp r3, #0 800460e: d106 bne.n 800461e { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8004610: 687b ldr r3, [r7, #4] 8004612: 2200 movs r2, #0 8004614: f883 2080 strb.w r2, [r3, #128] ; 0x80 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8004618: 6878 ldr r0, [r7, #4] 800461a: f7fc fa53 bl 8000ac4 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 800461e: 687b ldr r3, [r7, #4] 8004620: 2224 movs r2, #36 ; 0x24 8004622: f8c3 2084 str.w r2, [r3, #132] ; 0x84 __HAL_UART_DISABLE(huart); 8004626: 687b ldr r3, [r7, #4] 8004628: 681b ldr r3, [r3, #0] 800462a: 681a ldr r2, [r3, #0] 800462c: 687b ldr r3, [r7, #4] 800462e: 681b ldr r3, [r3, #0] 8004630: f022 0201 bic.w r2, r2, #1 8004634: 601a str r2, [r3, #0] /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) 8004636: 6878 ldr r0, [r7, #4] 8004638: f000 fcde bl 8004ff8 800463c: 4603 mov r3, r0 800463e: 2b01 cmp r3, #1 8004640: d101 bne.n 8004646 { return HAL_ERROR; 8004642: 2301 movs r3, #1 8004644: e022 b.n 800468c } if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) 8004646: 687b ldr r3, [r7, #4] 8004648: 6a9b ldr r3, [r3, #40] ; 0x28 800464a: 2b00 cmp r3, #0 800464c: d002 beq.n 8004654 { UART_AdvFeatureConfig(huart); 800464e: 6878 ldr r0, [r7, #4] 8004650: f001 fb30 bl 8005cb4 } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8004654: 687b ldr r3, [r7, #4] 8004656: 681b ldr r3, [r3, #0] 8004658: 685a ldr r2, [r3, #4] 800465a: 687b ldr r3, [r7, #4] 800465c: 681b ldr r3, [r3, #0] 800465e: f422 4290 bic.w r2, r2, #18432 ; 0x4800 8004662: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8004664: 687b ldr r3, [r7, #4] 8004666: 681b ldr r3, [r3, #0] 8004668: 689a ldr r2, [r3, #8] 800466a: 687b ldr r3, [r7, #4] 800466c: 681b ldr r3, [r3, #0] 800466e: f022 022a bic.w r2, r2, #42 ; 0x2a 8004672: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); 8004674: 687b ldr r3, [r7, #4] 8004676: 681b ldr r3, [r3, #0] 8004678: 681a ldr r2, [r3, #0] 800467a: 687b ldr r3, [r7, #4] 800467c: 681b ldr r3, [r3, #0] 800467e: f042 0201 orr.w r2, r2, #1 8004682: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); 8004684: 6878 ldr r0, [r7, #4] 8004686: f001 fbb7 bl 8005df8 800468a: 4603 mov r3, r0 } 800468c: 4618 mov r0, r3 800468e: 3708 adds r7, #8 8004690: 46bd mov sp, r7 8004692: bd80 pop {r7, pc} 08004694 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 8004694: b480 push {r7} 8004696: b091 sub sp, #68 ; 0x44 8004698: af00 add r7, sp, #0 800469a: 60f8 str r0, [r7, #12] 800469c: 60b9 str r1, [r7, #8] 800469e: 4613 mov r3, r2 80046a0: 80fb strh r3, [r7, #6] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 80046a2: 68fb ldr r3, [r7, #12] 80046a4: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 80046a8: 2b20 cmp r3, #32 80046aa: f040 808c bne.w 80047c6 { if ((pData == NULL) || (Size == 0U)) 80046ae: 68bb ldr r3, [r7, #8] 80046b0: 2b00 cmp r3, #0 80046b2: d002 beq.n 80046ba 80046b4: 88fb ldrh r3, [r7, #6] 80046b6: 2b00 cmp r3, #0 80046b8: d101 bne.n 80046be { return HAL_ERROR; 80046ba: 2301 movs r3, #1 80046bc: e084 b.n 80047c8 } __HAL_LOCK(huart); 80046be: 68fb ldr r3, [r7, #12] 80046c0: f893 3080 ldrb.w r3, [r3, #128] ; 0x80 80046c4: 2b01 cmp r3, #1 80046c6: d101 bne.n 80046cc 80046c8: 2302 movs r3, #2 80046ca: e07d b.n 80047c8 80046cc: 68fb ldr r3, [r7, #12] 80046ce: 2201 movs r2, #1 80046d0: f883 2080 strb.w r2, [r3, #128] ; 0x80 huart->pTxBuffPtr = pData; 80046d4: 68fb ldr r3, [r7, #12] 80046d6: 68ba ldr r2, [r7, #8] 80046d8: 651a str r2, [r3, #80] ; 0x50 huart->TxXferSize = Size; 80046da: 68fb ldr r3, [r7, #12] 80046dc: 88fa ldrh r2, [r7, #6] 80046de: f8a3 2054 strh.w r2, [r3, #84] ; 0x54 huart->TxXferCount = Size; 80046e2: 68fb ldr r3, [r7, #12] 80046e4: 88fa ldrh r2, [r7, #6] 80046e6: f8a3 2056 strh.w r2, [r3, #86] ; 0x56 huart->TxISR = NULL; 80046ea: 68fb ldr r3, [r7, #12] 80046ec: 2200 movs r2, #0 80046ee: 675a str r2, [r3, #116] ; 0x74 huart->ErrorCode = HAL_UART_ERROR_NONE; 80046f0: 68fb ldr r3, [r7, #12] 80046f2: 2200 movs r2, #0 80046f4: f8c3 208c str.w r2, [r3, #140] ; 0x8c huart->gState = HAL_UART_STATE_BUSY_TX; 80046f8: 68fb ldr r3, [r7, #12] 80046fa: 2221 movs r2, #33 ; 0x21 80046fc: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Configure Tx interrupt processing */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) 8004700: 68fb ldr r3, [r7, #12] 8004702: 6e5b ldr r3, [r3, #100] ; 0x64 8004704: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8004708: d12e bne.n 8004768 { /* Set the Tx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800470a: 68fb ldr r3, [r7, #12] 800470c: 689b ldr r3, [r3, #8] 800470e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8004712: d107 bne.n 8004724 8004714: 68fb ldr r3, [r7, #12] 8004716: 691b ldr r3, [r3, #16] 8004718: 2b00 cmp r3, #0 800471a: d103 bne.n 8004724 { huart->TxISR = UART_TxISR_16BIT_FIFOEN; 800471c: 68fb ldr r3, [r7, #12] 800471e: 4a2d ldr r2, [pc, #180] ; (80047d4 ) 8004720: 675a str r2, [r3, #116] ; 0x74 8004722: e002 b.n 800472a } else { huart->TxISR = UART_TxISR_8BIT_FIFOEN; 8004724: 68fb ldr r3, [r7, #12] 8004726: 4a2c ldr r2, [pc, #176] ; (80047d8 ) 8004728: 675a str r2, [r3, #116] ; 0x74 } __HAL_UNLOCK(huart); 800472a: 68fb ldr r3, [r7, #12] 800472c: 2200 movs r2, #0 800472e: f883 2080 strb.w r2, [r3, #128] ; 0x80 /* Enable the TX FIFO threshold interrupt */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 8004732: 68fb ldr r3, [r7, #12] 8004734: 681b ldr r3, [r3, #0] 8004736: 3308 adds r3, #8 8004738: 62bb str r3, [r7, #40] ; 0x28 */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800473a: 6abb ldr r3, [r7, #40] ; 0x28 800473c: e853 3f00 ldrex r3, [r3] 8004740: 627b str r3, [r7, #36] ; 0x24 return(result); 8004742: 6a7b ldr r3, [r7, #36] ; 0x24 8004744: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 8004748: 63bb str r3, [r7, #56] ; 0x38 800474a: 68fb ldr r3, [r7, #12] 800474c: 681b ldr r3, [r3, #0] 800474e: 3308 adds r3, #8 8004750: 6bba ldr r2, [r7, #56] ; 0x38 8004752: 637a str r2, [r7, #52] ; 0x34 8004754: 633b str r3, [r7, #48] ; 0x30 */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004756: 6b39 ldr r1, [r7, #48] ; 0x30 8004758: 6b7a ldr r2, [r7, #52] ; 0x34 800475a: e841 2300 strex r3, r2, [r1] 800475e: 62fb str r3, [r7, #44] ; 0x2c return(result); 8004760: 6afb ldr r3, [r7, #44] ; 0x2c 8004762: 2b00 cmp r3, #0 8004764: d1e5 bne.n 8004732 8004766: e02c b.n 80047c2 } else { /* Set the Tx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8004768: 68fb ldr r3, [r7, #12] 800476a: 689b ldr r3, [r3, #8] 800476c: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8004770: d107 bne.n 8004782 8004772: 68fb ldr r3, [r7, #12] 8004774: 691b ldr r3, [r3, #16] 8004776: 2b00 cmp r3, #0 8004778: d103 bne.n 8004782 { huart->TxISR = UART_TxISR_16BIT; 800477a: 68fb ldr r3, [r7, #12] 800477c: 4a17 ldr r2, [pc, #92] ; (80047dc ) 800477e: 675a str r2, [r3, #116] ; 0x74 8004780: e002 b.n 8004788 } else { huart->TxISR = UART_TxISR_8BIT; 8004782: 68fb ldr r3, [r7, #12] 8004784: 4a16 ldr r2, [pc, #88] ; (80047e0 ) 8004786: 675a str r2, [r3, #116] ; 0x74 } __HAL_UNLOCK(huart); 8004788: 68fb ldr r3, [r7, #12] 800478a: 2200 movs r2, #0 800478c: f883 2080 strb.w r2, [r3, #128] ; 0x80 /* Enable the Transmit Data Register Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 8004790: 68fb ldr r3, [r7, #12] 8004792: 681b ldr r3, [r3, #0] 8004794: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004796: 697b ldr r3, [r7, #20] 8004798: e853 3f00 ldrex r3, [r3] 800479c: 613b str r3, [r7, #16] return(result); 800479e: 693b ldr r3, [r7, #16] 80047a0: f043 0380 orr.w r3, r3, #128 ; 0x80 80047a4: 63fb str r3, [r7, #60] ; 0x3c 80047a6: 68fb ldr r3, [r7, #12] 80047a8: 681b ldr r3, [r3, #0] 80047aa: 461a mov r2, r3 80047ac: 6bfb ldr r3, [r7, #60] ; 0x3c 80047ae: 623b str r3, [r7, #32] 80047b0: 61fa str r2, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80047b2: 69f9 ldr r1, [r7, #28] 80047b4: 6a3a ldr r2, [r7, #32] 80047b6: e841 2300 strex r3, r2, [r1] 80047ba: 61bb str r3, [r7, #24] return(result); 80047bc: 69bb ldr r3, [r7, #24] 80047be: 2b00 cmp r3, #0 80047c0: d1e6 bne.n 8004790 } return HAL_OK; 80047c2: 2300 movs r3, #0 80047c4: e000 b.n 80047c8 } else { return HAL_BUSY; 80047c6: 2302 movs r3, #2 } } 80047c8: 4618 mov r0, r3 80047ca: 3744 adds r7, #68 ; 0x44 80047cc: 46bd mov sp, r7 80047ce: f85d 7b04 ldr.w r7, [sp], #4 80047d2: 4770 bx lr 80047d4: 080065c7 .word 0x080065c7 80047d8: 080064e7 .word 0x080064e7 80047dc: 08006425 .word 0x08006425 80047e0: 0800636d .word 0x0800636d 080047e4 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 80047e4: b580 push {r7, lr} 80047e6: b08a sub sp, #40 ; 0x28 80047e8: af00 add r7, sp, #0 80047ea: 60f8 str r0, [r7, #12] 80047ec: 60b9 str r1, [r7, #8] 80047ee: 4613 mov r3, r2 80047f0: 80fb strh r3, [r7, #6] /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 80047f2: 68fb ldr r3, [r7, #12] 80047f4: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 80047f8: 2b20 cmp r3, #32 80047fa: d142 bne.n 8004882 { if ((pData == NULL) || (Size == 0U)) 80047fc: 68bb ldr r3, [r7, #8] 80047fe: 2b00 cmp r3, #0 8004800: d002 beq.n 8004808 8004802: 88fb ldrh r3, [r7, #6] 8004804: 2b00 cmp r3, #0 8004806: d101 bne.n 800480c { return HAL_ERROR; 8004808: 2301 movs r3, #1 800480a: e03b b.n 8004884 } __HAL_LOCK(huart); 800480c: 68fb ldr r3, [r7, #12] 800480e: f893 3080 ldrb.w r3, [r3, #128] ; 0x80 8004812: 2b01 cmp r3, #1 8004814: d101 bne.n 800481a 8004816: 2302 movs r3, #2 8004818: e034 b.n 8004884 800481a: 68fb ldr r3, [r7, #12] 800481c: 2201 movs r2, #1 800481e: f883 2080 strb.w r2, [r3, #128] ; 0x80 /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8004822: 68fb ldr r3, [r7, #12] 8004824: 2200 movs r2, #0 8004826: 66da str r2, [r3, #108] ; 0x6c if (!(IS_LPUART_INSTANCE(huart->Instance))) 8004828: 68fb ldr r3, [r7, #12] 800482a: 681b ldr r3, [r3, #0] 800482c: 4a17 ldr r2, [pc, #92] ; (800488c ) 800482e: 4293 cmp r3, r2 8004830: d01f beq.n 8004872 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8004832: 68fb ldr r3, [r7, #12] 8004834: 681b ldr r3, [r3, #0] 8004836: 685b ldr r3, [r3, #4] 8004838: f403 0300 and.w r3, r3, #8388608 ; 0x800000 800483c: 2b00 cmp r3, #0 800483e: d018 beq.n 8004872 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 8004840: 68fb ldr r3, [r7, #12] 8004842: 681b ldr r3, [r3, #0] 8004844: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004846: 697b ldr r3, [r7, #20] 8004848: e853 3f00 ldrex r3, [r3] 800484c: 613b str r3, [r7, #16] return(result); 800484e: 693b ldr r3, [r7, #16] 8004850: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 8004854: 627b str r3, [r7, #36] ; 0x24 8004856: 68fb ldr r3, [r7, #12] 8004858: 681b ldr r3, [r3, #0] 800485a: 461a mov r2, r3 800485c: 6a7b ldr r3, [r7, #36] ; 0x24 800485e: 623b str r3, [r7, #32] 8004860: 61fa str r2, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004862: 69f9 ldr r1, [r7, #28] 8004864: 6a3a ldr r2, [r7, #32] 8004866: e841 2300 strex r3, r2, [r1] 800486a: 61bb str r3, [r7, #24] return(result); 800486c: 69bb ldr r3, [r7, #24] 800486e: 2b00 cmp r3, #0 8004870: d1e6 bne.n 8004840 } } return (UART_Start_Receive_IT(huart, pData, Size)); 8004872: 88fb ldrh r3, [r7, #6] 8004874: 461a mov r2, r3 8004876: 68b9 ldr r1, [r7, #8] 8004878: 68f8 ldr r0, [r7, #12] 800487a: f001 fbd1 bl 8006020 800487e: 4603 mov r3, r0 8004880: e000 b.n 8004884 } else { return HAL_BUSY; 8004882: 2302 movs r3, #2 } } 8004884: 4618 mov r0, r3 8004886: 3728 adds r7, #40 ; 0x28 8004888: 46bd mov sp, r7 800488a: bd80 pop {r7, pc} 800488c: 58000c00 .word 0x58000c00 08004890 : * @brief Handle UART interrupt request. * @param huart UART handle. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8004890: b580 push {r7, lr} 8004892: b0ba sub sp, #232 ; 0xe8 8004894: af00 add r7, sp, #0 8004896: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->ISR); 8004898: 687b ldr r3, [r7, #4] 800489a: 681b ldr r3, [r3, #0] 800489c: 69db ldr r3, [r3, #28] 800489e: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 80048a2: 687b ldr r3, [r7, #4] 80048a4: 681b ldr r3, [r3, #0] 80048a6: 681b ldr r3, [r3, #0] 80048a8: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 80048ac: 687b ldr r3, [r7, #4] 80048ae: 681b ldr r3, [r3, #0] 80048b0: 689b ldr r3, [r3, #8] 80048b2: f8c7 30dc str.w r3, [r7, #220] ; 0xdc uint32_t errorflags; uint32_t errorcode; /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); 80048b6: f8d7 20e4 ldr.w r2, [r7, #228] ; 0xe4 80048ba: f640 030f movw r3, #2063 ; 0x80f 80048be: 4013 ands r3, r2 80048c0: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8 if (errorflags == 0U) 80048c4: f8d7 30d8 ldr.w r3, [r7, #216] ; 0xd8 80048c8: 2b00 cmp r3, #0 80048ca: d11b bne.n 8004904 { /* UART in mode Receiver ---------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 80048cc: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 80048d0: f003 0320 and.w r3, r3, #32 80048d4: 2b00 cmp r3, #0 80048d6: d015 beq.n 8004904 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 80048d8: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 80048dc: f003 0320 and.w r3, r3, #32 80048e0: 2b00 cmp r3, #0 80048e2: d105 bne.n 80048f0 || ((cr3its & USART_CR3_RXFTIE) != 0U))) 80048e4: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc 80048e8: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80048ec: 2b00 cmp r3, #0 80048ee: d009 beq.n 8004904 { if (huart->RxISR != NULL) 80048f0: 687b ldr r3, [r7, #4] 80048f2: 6f1b ldr r3, [r3, #112] ; 0x70 80048f4: 2b00 cmp r3, #0 80048f6: f000 835a beq.w 8004fae { huart->RxISR(huart); 80048fa: 687b ldr r3, [r7, #4] 80048fc: 6f1b ldr r3, [r3, #112] ; 0x70 80048fe: 6878 ldr r0, [r7, #4] 8004900: 4798 blx r3 } return; 8004902: e354 b.n 8004fae } } /* If some errors occur */ if ((errorflags != 0U) 8004904: f8d7 30d8 ldr.w r3, [r7, #216] ; 0xd8 8004908: 2b00 cmp r3, #0 800490a: f000 811f beq.w 8004b4c && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) 800490e: f8d7 20dc ldr.w r2, [r7, #220] ; 0xdc 8004912: 4b8b ldr r3, [pc, #556] ; (8004b40 ) 8004914: 4013 ands r3, r2 8004916: 2b00 cmp r3, #0 8004918: d106 bne.n 8004928 || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) 800491a: f8d7 20e0 ldr.w r2, [r7, #224] ; 0xe0 800491e: 4b89 ldr r3, [pc, #548] ; (8004b44 ) 8004920: 4013 ands r3, r2 8004922: 2b00 cmp r3, #0 8004924: f000 8112 beq.w 8004b4c { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 8004928: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 800492c: f003 0301 and.w r3, r3, #1 8004930: 2b00 cmp r3, #0 8004932: d011 beq.n 8004958 8004934: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 8004938: f403 7380 and.w r3, r3, #256 ; 0x100 800493c: 2b00 cmp r3, #0 800493e: d00b beq.n 8004958 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 8004940: 687b ldr r3, [r7, #4] 8004942: 681b ldr r3, [r3, #0] 8004944: 2201 movs r2, #1 8004946: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 8004948: 687b ldr r3, [r7, #4] 800494a: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 800494e: f043 0201 orr.w r2, r3, #1 8004952: 687b ldr r3, [r7, #4] 8004954: f8c3 208c str.w r2, [r3, #140] ; 0x8c } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8004958: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 800495c: f003 0302 and.w r3, r3, #2 8004960: 2b00 cmp r3, #0 8004962: d011 beq.n 8004988 8004964: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc 8004968: f003 0301 and.w r3, r3, #1 800496c: 2b00 cmp r3, #0 800496e: d00b beq.n 8004988 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 8004970: 687b ldr r3, [r7, #4] 8004972: 681b ldr r3, [r3, #0] 8004974: 2202 movs r2, #2 8004976: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 8004978: 687b ldr r3, [r7, #4] 800497a: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 800497e: f043 0204 orr.w r2, r3, #4 8004982: 687b ldr r3, [r7, #4] 8004984: f8c3 208c str.w r2, [r3, #140] ; 0x8c } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8004988: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 800498c: f003 0304 and.w r3, r3, #4 8004990: 2b00 cmp r3, #0 8004992: d011 beq.n 80049b8 8004994: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc 8004998: f003 0301 and.w r3, r3, #1 800499c: 2b00 cmp r3, #0 800499e: d00b beq.n 80049b8 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 80049a0: 687b ldr r3, [r7, #4] 80049a2: 681b ldr r3, [r3, #0] 80049a4: 2204 movs r2, #4 80049a6: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 80049a8: 687b ldr r3, [r7, #4] 80049aa: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 80049ae: f043 0202 orr.w r2, r3, #2 80049b2: 687b ldr r3, [r7, #4] 80049b4: f8c3 208c str.w r2, [r3, #140] ; 0x8c } /* UART Over-Run interrupt occurred -----------------------------------------*/ if (((isrflags & USART_ISR_ORE) != 0U) 80049b8: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 80049bc: f003 0308 and.w r3, r3, #8 80049c0: 2b00 cmp r3, #0 80049c2: d017 beq.n 80049f4 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 80049c4: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 80049c8: f003 0320 and.w r3, r3, #32 80049cc: 2b00 cmp r3, #0 80049ce: d105 bne.n 80049dc ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) 80049d0: f8d7 20dc ldr.w r2, [r7, #220] ; 0xdc 80049d4: 4b5a ldr r3, [pc, #360] ; (8004b40 ) 80049d6: 4013 ands r3, r2 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 80049d8: 2b00 cmp r3, #0 80049da: d00b beq.n 80049f4 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 80049dc: 687b ldr r3, [r7, #4] 80049de: 681b ldr r3, [r3, #0] 80049e0: 2208 movs r2, #8 80049e2: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_ORE; 80049e4: 687b ldr r3, [r7, #4] 80049e6: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 80049ea: f043 0208 orr.w r2, r3, #8 80049ee: 687b ldr r3, [r7, #4] 80049f0: f8c3 208c str.w r2, [r3, #140] ; 0x8c } /* UART Receiver Timeout interrupt occurred ---------------------------------*/ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) 80049f4: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 80049f8: f403 6300 and.w r3, r3, #2048 ; 0x800 80049fc: 2b00 cmp r3, #0 80049fe: d012 beq.n 8004a26 8004a00: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 8004a04: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 8004a08: 2b00 cmp r3, #0 8004a0a: d00c beq.n 8004a26 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 8004a0c: 687b ldr r3, [r7, #4] 8004a0e: 681b ldr r3, [r3, #0] 8004a10: f44f 6200 mov.w r2, #2048 ; 0x800 8004a14: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_RTO; 8004a16: 687b ldr r3, [r7, #4] 8004a18: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 8004a1c: f043 0220 orr.w r2, r3, #32 8004a20: 687b ldr r3, [r7, #4] 8004a22: f8c3 208c str.w r2, [r3, #140] ; 0x8c } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8004a26: 687b ldr r3, [r7, #4] 8004a28: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 8004a2c: 2b00 cmp r3, #0 8004a2e: f000 82c0 beq.w 8004fb2 { /* UART in mode Receiver --------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 8004a32: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 8004a36: f003 0320 and.w r3, r3, #32 8004a3a: 2b00 cmp r3, #0 8004a3c: d013 beq.n 8004a66 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 8004a3e: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 8004a42: f003 0320 and.w r3, r3, #32 8004a46: 2b00 cmp r3, #0 8004a48: d105 bne.n 8004a56 || ((cr3its & USART_CR3_RXFTIE) != 0U))) 8004a4a: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc 8004a4e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8004a52: 2b00 cmp r3, #0 8004a54: d007 beq.n 8004a66 { if (huart->RxISR != NULL) 8004a56: 687b ldr r3, [r7, #4] 8004a58: 6f1b ldr r3, [r3, #112] ; 0x70 8004a5a: 2b00 cmp r3, #0 8004a5c: d003 beq.n 8004a66 { huart->RxISR(huart); 8004a5e: 687b ldr r3, [r7, #4] 8004a60: 6f1b ldr r3, [r3, #112] ; 0x70 8004a62: 6878 ldr r0, [r7, #4] 8004a64: 4798 blx r3 /* If Error is to be considered as blocking : - Receiver Timeout error in Reception - Overrun error in Reception - any error occurs in DMA mode reception */ errorcode = huart->ErrorCode; 8004a66: 687b ldr r3, [r7, #4] 8004a68: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 8004a6c: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 8004a70: 687b ldr r3, [r7, #4] 8004a72: 681b ldr r3, [r3, #0] 8004a74: 689b ldr r3, [r3, #8] 8004a76: f003 0340 and.w r3, r3, #64 ; 0x40 8004a7a: 2b40 cmp r3, #64 ; 0x40 8004a7c: d005 beq.n 8004a8a ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) 8004a7e: f8d7 30d4 ldr.w r3, [r7, #212] ; 0xd4 8004a82: f003 0328 and.w r3, r3, #40 ; 0x28 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 8004a86: 2b00 cmp r3, #0 8004a88: d04f beq.n 8004b2a { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 8004a8a: 6878 ldr r0, [r7, #4] 8004a8c: f001 fbf2 bl 8006274 /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8004a90: 687b ldr r3, [r7, #4] 8004a92: 681b ldr r3, [r3, #0] 8004a94: 689b ldr r3, [r3, #8] 8004a96: f003 0340 and.w r3, r3, #64 ; 0x40 8004a9a: 2b40 cmp r3, #64 ; 0x40 8004a9c: d141 bne.n 8004b22 { /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8004a9e: 687b ldr r3, [r7, #4] 8004aa0: 681b ldr r3, [r3, #0] 8004aa2: 3308 adds r3, #8 8004aa4: f8c7 309c str.w r3, [r7, #156] ; 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004aa8: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c 8004aac: e853 3f00 ldrex r3, [r3] 8004ab0: f8c7 3098 str.w r3, [r7, #152] ; 0x98 return(result); 8004ab4: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98 8004ab8: f023 0340 bic.w r3, r3, #64 ; 0x40 8004abc: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 8004ac0: 687b ldr r3, [r7, #4] 8004ac2: 681b ldr r3, [r3, #0] 8004ac4: 3308 adds r3, #8 8004ac6: f8d7 20d0 ldr.w r2, [r7, #208] ; 0xd0 8004aca: f8c7 20a8 str.w r2, [r7, #168] ; 0xa8 8004ace: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004ad2: f8d7 10a4 ldr.w r1, [r7, #164] ; 0xa4 8004ad6: f8d7 20a8 ldr.w r2, [r7, #168] ; 0xa8 8004ada: e841 2300 strex r3, r2, [r1] 8004ade: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0 return(result); 8004ae2: f8d7 30a0 ldr.w r3, [r7, #160] ; 0xa0 8004ae6: 2b00 cmp r3, #0 8004ae8: d1d9 bne.n 8004a9e /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 8004aea: 687b ldr r3, [r7, #4] 8004aec: 6fdb ldr r3, [r3, #124] ; 0x7c 8004aee: 2b00 cmp r3, #0 8004af0: d013 beq.n 8004b1a { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 8004af2: 687b ldr r3, [r7, #4] 8004af4: 6fdb ldr r3, [r3, #124] ; 0x7c 8004af6: 4a14 ldr r2, [pc, #80] ; (8004b48 ) 8004af8: 651a str r2, [r3, #80] ; 0x50 /* Abort DMA RX */ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 8004afa: 687b ldr r3, [r7, #4] 8004afc: 6fdb ldr r3, [r3, #124] ; 0x7c 8004afe: 4618 mov r0, r3 8004b00: f7fc fe52 bl 80017a8 8004b04: 4603 mov r3, r0 8004b06: 2b00 cmp r3, #0 8004b08: d017 beq.n 8004b3a { /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 8004b0a: 687b ldr r3, [r7, #4] 8004b0c: 6fdb ldr r3, [r3, #124] ; 0x7c 8004b0e: 6d1b ldr r3, [r3, #80] ; 0x50 8004b10: 687a ldr r2, [r7, #4] 8004b12: 6fd2 ldr r2, [r2, #124] ; 0x7c 8004b14: 4610 mov r0, r2 8004b16: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8004b18: e00f b.n 8004b3a #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8004b1a: 6878 ldr r0, [r7, #4] 8004b1c: f000 fa56 bl 8004fcc if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8004b20: e00b b.n 8004b3a #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8004b22: 6878 ldr r0, [r7, #4] 8004b24: f000 fa52 bl 8004fcc if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8004b28: e007 b.n 8004b3a #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8004b2a: 6878 ldr r0, [r7, #4] 8004b2c: f000 fa4e bl 8004fcc #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8004b30: 687b ldr r3, [r7, #4] 8004b32: 2200 movs r2, #0 8004b34: f8c3 208c str.w r2, [r3, #140] ; 0x8c } } return; 8004b38: e23b b.n 8004fb2 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8004b3a: bf00 nop return; 8004b3c: e239 b.n 8004fb2 8004b3e: bf00 nop 8004b40: 10000001 .word 0x10000001 8004b44: 04000120 .word 0x04000120 8004b48: 08006341 .word 0x08006341 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8004b4c: 687b ldr r3, [r7, #4] 8004b4e: 6edb ldr r3, [r3, #108] ; 0x6c 8004b50: 2b01 cmp r3, #1 8004b52: f040 81ce bne.w 8004ef2 && ((isrflags & USART_ISR_IDLE) != 0U) 8004b56: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 8004b5a: f003 0310 and.w r3, r3, #16 8004b5e: 2b00 cmp r3, #0 8004b60: f000 81c7 beq.w 8004ef2 && ((cr1its & USART_ISR_IDLE) != 0U)) 8004b64: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 8004b68: f003 0310 and.w r3, r3, #16 8004b6c: 2b00 cmp r3, #0 8004b6e: f000 81c0 beq.w 8004ef2 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8004b72: 687b ldr r3, [r7, #4] 8004b74: 681b ldr r3, [r3, #0] 8004b76: 2210 movs r2, #16 8004b78: 621a str r2, [r3, #32] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8004b7a: 687b ldr r3, [r7, #4] 8004b7c: 681b ldr r3, [r3, #0] 8004b7e: 689b ldr r3, [r3, #8] 8004b80: f003 0340 and.w r3, r3, #64 ; 0x40 8004b84: 2b40 cmp r3, #64 ; 0x40 8004b86: f040 813b bne.w 8004e00 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 8004b8a: 687b ldr r3, [r7, #4] 8004b8c: 6fdb ldr r3, [r3, #124] ; 0x7c 8004b8e: 681b ldr r3, [r3, #0] 8004b90: 4a8b ldr r2, [pc, #556] ; (8004dc0 ) 8004b92: 4293 cmp r3, r2 8004b94: d059 beq.n 8004c4a 8004b96: 687b ldr r3, [r7, #4] 8004b98: 6fdb ldr r3, [r3, #124] ; 0x7c 8004b9a: 681b ldr r3, [r3, #0] 8004b9c: 4a89 ldr r2, [pc, #548] ; (8004dc4 ) 8004b9e: 4293 cmp r3, r2 8004ba0: d053 beq.n 8004c4a 8004ba2: 687b ldr r3, [r7, #4] 8004ba4: 6fdb ldr r3, [r3, #124] ; 0x7c 8004ba6: 681b ldr r3, [r3, #0] 8004ba8: 4a87 ldr r2, [pc, #540] ; (8004dc8 ) 8004baa: 4293 cmp r3, r2 8004bac: d04d beq.n 8004c4a 8004bae: 687b ldr r3, [r7, #4] 8004bb0: 6fdb ldr r3, [r3, #124] ; 0x7c 8004bb2: 681b ldr r3, [r3, #0] 8004bb4: 4a85 ldr r2, [pc, #532] ; (8004dcc ) 8004bb6: 4293 cmp r3, r2 8004bb8: d047 beq.n 8004c4a 8004bba: 687b ldr r3, [r7, #4] 8004bbc: 6fdb ldr r3, [r3, #124] ; 0x7c 8004bbe: 681b ldr r3, [r3, #0] 8004bc0: 4a83 ldr r2, [pc, #524] ; (8004dd0 ) 8004bc2: 4293 cmp r3, r2 8004bc4: d041 beq.n 8004c4a 8004bc6: 687b ldr r3, [r7, #4] 8004bc8: 6fdb ldr r3, [r3, #124] ; 0x7c 8004bca: 681b ldr r3, [r3, #0] 8004bcc: 4a81 ldr r2, [pc, #516] ; (8004dd4 ) 8004bce: 4293 cmp r3, r2 8004bd0: d03b beq.n 8004c4a 8004bd2: 687b ldr r3, [r7, #4] 8004bd4: 6fdb ldr r3, [r3, #124] ; 0x7c 8004bd6: 681b ldr r3, [r3, #0] 8004bd8: 4a7f ldr r2, [pc, #508] ; (8004dd8 ) 8004bda: 4293 cmp r3, r2 8004bdc: d035 beq.n 8004c4a 8004bde: 687b ldr r3, [r7, #4] 8004be0: 6fdb ldr r3, [r3, #124] ; 0x7c 8004be2: 681b ldr r3, [r3, #0] 8004be4: 4a7d ldr r2, [pc, #500] ; (8004ddc ) 8004be6: 4293 cmp r3, r2 8004be8: d02f beq.n 8004c4a 8004bea: 687b ldr r3, [r7, #4] 8004bec: 6fdb ldr r3, [r3, #124] ; 0x7c 8004bee: 681b ldr r3, [r3, #0] 8004bf0: 4a7b ldr r2, [pc, #492] ; (8004de0 ) 8004bf2: 4293 cmp r3, r2 8004bf4: d029 beq.n 8004c4a 8004bf6: 687b ldr r3, [r7, #4] 8004bf8: 6fdb ldr r3, [r3, #124] ; 0x7c 8004bfa: 681b ldr r3, [r3, #0] 8004bfc: 4a79 ldr r2, [pc, #484] ; (8004de4 ) 8004bfe: 4293 cmp r3, r2 8004c00: d023 beq.n 8004c4a 8004c02: 687b ldr r3, [r7, #4] 8004c04: 6fdb ldr r3, [r3, #124] ; 0x7c 8004c06: 681b ldr r3, [r3, #0] 8004c08: 4a77 ldr r2, [pc, #476] ; (8004de8 ) 8004c0a: 4293 cmp r3, r2 8004c0c: d01d beq.n 8004c4a 8004c0e: 687b ldr r3, [r7, #4] 8004c10: 6fdb ldr r3, [r3, #124] ; 0x7c 8004c12: 681b ldr r3, [r3, #0] 8004c14: 4a75 ldr r2, [pc, #468] ; (8004dec ) 8004c16: 4293 cmp r3, r2 8004c18: d017 beq.n 8004c4a 8004c1a: 687b ldr r3, [r7, #4] 8004c1c: 6fdb ldr r3, [r3, #124] ; 0x7c 8004c1e: 681b ldr r3, [r3, #0] 8004c20: 4a73 ldr r2, [pc, #460] ; (8004df0 ) 8004c22: 4293 cmp r3, r2 8004c24: d011 beq.n 8004c4a 8004c26: 687b ldr r3, [r7, #4] 8004c28: 6fdb ldr r3, [r3, #124] ; 0x7c 8004c2a: 681b ldr r3, [r3, #0] 8004c2c: 4a71 ldr r2, [pc, #452] ; (8004df4 ) 8004c2e: 4293 cmp r3, r2 8004c30: d00b beq.n 8004c4a 8004c32: 687b ldr r3, [r7, #4] 8004c34: 6fdb ldr r3, [r3, #124] ; 0x7c 8004c36: 681b ldr r3, [r3, #0] 8004c38: 4a6f ldr r2, [pc, #444] ; (8004df8 ) 8004c3a: 4293 cmp r3, r2 8004c3c: d005 beq.n 8004c4a 8004c3e: 687b ldr r3, [r7, #4] 8004c40: 6fdb ldr r3, [r3, #124] ; 0x7c 8004c42: 681b ldr r3, [r3, #0] 8004c44: 4a6d ldr r2, [pc, #436] ; (8004dfc ) 8004c46: 4293 cmp r3, r2 8004c48: d105 bne.n 8004c56 8004c4a: 687b ldr r3, [r7, #4] 8004c4c: 6fdb ldr r3, [r3, #124] ; 0x7c 8004c4e: 681b ldr r3, [r3, #0] 8004c50: 685b ldr r3, [r3, #4] 8004c52: b29b uxth r3, r3 8004c54: e004 b.n 8004c60 8004c56: 687b ldr r3, [r7, #4] 8004c58: 6fdb ldr r3, [r3, #124] ; 0x7c 8004c5a: 681b ldr r3, [r3, #0] 8004c5c: 685b ldr r3, [r3, #4] 8004c5e: b29b uxth r3, r3 8004c60: f8a7 30be strh.w r3, [r7, #190] ; 0xbe if ((nb_remaining_rx_data > 0U) 8004c64: f8b7 30be ldrh.w r3, [r7, #190] ; 0xbe 8004c68: 2b00 cmp r3, #0 8004c6a: f000 81a4 beq.w 8004fb6 && (nb_remaining_rx_data < huart->RxXferSize)) 8004c6e: 687b ldr r3, [r7, #4] 8004c70: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c 8004c74: f8b7 20be ldrh.w r2, [r7, #190] ; 0xbe 8004c78: 429a cmp r2, r3 8004c7a: f080 819c bcs.w 8004fb6 { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 8004c7e: 687b ldr r3, [r7, #4] 8004c80: f8b7 20be ldrh.w r2, [r7, #190] ; 0xbe 8004c84: f8a3 205e strh.w r2, [r3, #94] ; 0x5e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 8004c88: 687b ldr r3, [r7, #4] 8004c8a: 6fdb ldr r3, [r3, #124] ; 0x7c 8004c8c: 69db ldr r3, [r3, #28] 8004c8e: f5b3 7f80 cmp.w r3, #256 ; 0x100 8004c92: f000 8086 beq.w 8004da2 { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8004c96: 687b ldr r3, [r7, #4] 8004c98: 681b ldr r3, [r3, #0] 8004c9a: f8c7 3088 str.w r3, [r7, #136] ; 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004c9e: f8d7 3088 ldr.w r3, [r7, #136] ; 0x88 8004ca2: e853 3f00 ldrex r3, [r3] 8004ca6: f8c7 3084 str.w r3, [r7, #132] ; 0x84 return(result); 8004caa: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84 8004cae: f423 7380 bic.w r3, r3, #256 ; 0x100 8004cb2: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8 8004cb6: 687b ldr r3, [r7, #4] 8004cb8: 681b ldr r3, [r3, #0] 8004cba: 461a mov r2, r3 8004cbc: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8 8004cc0: f8c7 3094 str.w r3, [r7, #148] ; 0x94 8004cc4: f8c7 2090 str.w r2, [r7, #144] ; 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004cc8: f8d7 1090 ldr.w r1, [r7, #144] ; 0x90 8004ccc: f8d7 2094 ldr.w r2, [r7, #148] ; 0x94 8004cd0: e841 2300 strex r3, r2, [r1] 8004cd4: f8c7 308c str.w r3, [r7, #140] ; 0x8c return(result); 8004cd8: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c 8004cdc: 2b00 cmp r3, #0 8004cde: d1da bne.n 8004c96 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8004ce0: 687b ldr r3, [r7, #4] 8004ce2: 681b ldr r3, [r3, #0] 8004ce4: 3308 adds r3, #8 8004ce6: 677b str r3, [r7, #116] ; 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004ce8: 6f7b ldr r3, [r7, #116] ; 0x74 8004cea: e853 3f00 ldrex r3, [r3] 8004cee: 673b str r3, [r7, #112] ; 0x70 return(result); 8004cf0: 6f3b ldr r3, [r7, #112] ; 0x70 8004cf2: f023 0301 bic.w r3, r3, #1 8004cf6: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4 8004cfa: 687b ldr r3, [r7, #4] 8004cfc: 681b ldr r3, [r3, #0] 8004cfe: 3308 adds r3, #8 8004d00: f8d7 20b4 ldr.w r2, [r7, #180] ; 0xb4 8004d04: f8c7 2080 str.w r2, [r7, #128] ; 0x80 8004d08: 67fb str r3, [r7, #124] ; 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004d0a: 6ff9 ldr r1, [r7, #124] ; 0x7c 8004d0c: f8d7 2080 ldr.w r2, [r7, #128] ; 0x80 8004d10: e841 2300 strex r3, r2, [r1] 8004d14: 67bb str r3, [r7, #120] ; 0x78 return(result); 8004d16: 6fbb ldr r3, [r7, #120] ; 0x78 8004d18: 2b00 cmp r3, #0 8004d1a: d1e1 bne.n 8004ce0 /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8004d1c: 687b ldr r3, [r7, #4] 8004d1e: 681b ldr r3, [r3, #0] 8004d20: 3308 adds r3, #8 8004d22: 663b str r3, [r7, #96] ; 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004d24: 6e3b ldr r3, [r7, #96] ; 0x60 8004d26: e853 3f00 ldrex r3, [r3] 8004d2a: 65fb str r3, [r7, #92] ; 0x5c return(result); 8004d2c: 6dfb ldr r3, [r7, #92] ; 0x5c 8004d2e: f023 0340 bic.w r3, r3, #64 ; 0x40 8004d32: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0 8004d36: 687b ldr r3, [r7, #4] 8004d38: 681b ldr r3, [r3, #0] 8004d3a: 3308 adds r3, #8 8004d3c: f8d7 20b0 ldr.w r2, [r7, #176] ; 0xb0 8004d40: 66fa str r2, [r7, #108] ; 0x6c 8004d42: 66bb str r3, [r7, #104] ; 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004d44: 6eb9 ldr r1, [r7, #104] ; 0x68 8004d46: 6efa ldr r2, [r7, #108] ; 0x6c 8004d48: e841 2300 strex r3, r2, [r1] 8004d4c: 667b str r3, [r7, #100] ; 0x64 return(result); 8004d4e: 6e7b ldr r3, [r7, #100] ; 0x64 8004d50: 2b00 cmp r3, #0 8004d52: d1e3 bne.n 8004d1c /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8004d54: 687b ldr r3, [r7, #4] 8004d56: 2220 movs r2, #32 8004d58: f8c3 2088 str.w r2, [r3, #136] ; 0x88 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8004d5c: 687b ldr r3, [r7, #4] 8004d5e: 2200 movs r2, #0 8004d60: 66da str r2, [r3, #108] ; 0x6c ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8004d62: 687b ldr r3, [r7, #4] 8004d64: 681b ldr r3, [r3, #0] 8004d66: 64fb str r3, [r7, #76] ; 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004d68: 6cfb ldr r3, [r7, #76] ; 0x4c 8004d6a: e853 3f00 ldrex r3, [r3] 8004d6e: 64bb str r3, [r7, #72] ; 0x48 return(result); 8004d70: 6cbb ldr r3, [r7, #72] ; 0x48 8004d72: f023 0310 bic.w r3, r3, #16 8004d76: f8c7 30ac str.w r3, [r7, #172] ; 0xac 8004d7a: 687b ldr r3, [r7, #4] 8004d7c: 681b ldr r3, [r3, #0] 8004d7e: 461a mov r2, r3 8004d80: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac 8004d84: 65bb str r3, [r7, #88] ; 0x58 8004d86: 657a str r2, [r7, #84] ; 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004d88: 6d79 ldr r1, [r7, #84] ; 0x54 8004d8a: 6dba ldr r2, [r7, #88] ; 0x58 8004d8c: e841 2300 strex r3, r2, [r1] 8004d90: 653b str r3, [r7, #80] ; 0x50 return(result); 8004d92: 6d3b ldr r3, [r7, #80] ; 0x50 8004d94: 2b00 cmp r3, #0 8004d96: d1e4 bne.n 8004d62 /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 8004d98: 687b ldr r3, [r7, #4] 8004d9a: 6fdb ldr r3, [r3, #124] ; 0x7c 8004d9c: 4618 mov r0, r3 8004d9e: f7fc f9e5 bl 800116c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 8004da2: 687b ldr r3, [r7, #4] 8004da4: f8b3 205c ldrh.w r2, [r3, #92] ; 0x5c 8004da8: 687b ldr r3, [r7, #4] 8004daa: f8b3 305e ldrh.w r3, [r3, #94] ; 0x5e 8004dae: b29b uxth r3, r3 8004db0: 1ad3 subs r3, r2, r3 8004db2: b29b uxth r3, r3 8004db4: 4619 mov r1, r3 8004db6: 6878 ldr r0, [r7, #4] 8004db8: f000 f912 bl 8004fe0 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; 8004dbc: e0fb b.n 8004fb6 8004dbe: bf00 nop 8004dc0: 40020010 .word 0x40020010 8004dc4: 40020028 .word 0x40020028 8004dc8: 40020040 .word 0x40020040 8004dcc: 40020058 .word 0x40020058 8004dd0: 40020070 .word 0x40020070 8004dd4: 40020088 .word 0x40020088 8004dd8: 400200a0 .word 0x400200a0 8004ddc: 400200b8 .word 0x400200b8 8004de0: 40020410 .word 0x40020410 8004de4: 40020428 .word 0x40020428 8004de8: 40020440 .word 0x40020440 8004dec: 40020458 .word 0x40020458 8004df0: 40020470 .word 0x40020470 8004df4: 40020488 .word 0x40020488 8004df8: 400204a0 .word 0x400204a0 8004dfc: 400204b8 .word 0x400204b8 else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 8004e00: 687b ldr r3, [r7, #4] 8004e02: f8b3 205c ldrh.w r2, [r3, #92] ; 0x5c 8004e06: 687b ldr r3, [r7, #4] 8004e08: f8b3 305e ldrh.w r3, [r3, #94] ; 0x5e 8004e0c: b29b uxth r3, r3 8004e0e: 1ad3 subs r3, r2, r3 8004e10: f8a7 30ce strh.w r3, [r7, #206] ; 0xce if ((huart->RxXferCount > 0U) 8004e14: 687b ldr r3, [r7, #4] 8004e16: f8b3 305e ldrh.w r3, [r3, #94] ; 0x5e 8004e1a: b29b uxth r3, r3 8004e1c: 2b00 cmp r3, #0 8004e1e: f000 80cc beq.w 8004fba && (nb_rx_data > 0U)) 8004e22: f8b7 30ce ldrh.w r3, [r7, #206] ; 0xce 8004e26: 2b00 cmp r3, #0 8004e28: f000 80c7 beq.w 8004fba { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8004e2c: 687b ldr r3, [r7, #4] 8004e2e: 681b ldr r3, [r3, #0] 8004e30: 63bb str r3, [r7, #56] ; 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004e32: 6bbb ldr r3, [r7, #56] ; 0x38 8004e34: e853 3f00 ldrex r3, [r3] 8004e38: 637b str r3, [r7, #52] ; 0x34 return(result); 8004e3a: 6b7b ldr r3, [r7, #52] ; 0x34 8004e3c: f423 7390 bic.w r3, r3, #288 ; 0x120 8004e40: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8 8004e44: 687b ldr r3, [r7, #4] 8004e46: 681b ldr r3, [r3, #0] 8004e48: 461a mov r2, r3 8004e4a: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 8004e4e: 647b str r3, [r7, #68] ; 0x44 8004e50: 643a str r2, [r7, #64] ; 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004e52: 6c39 ldr r1, [r7, #64] ; 0x40 8004e54: 6c7a ldr r2, [r7, #68] ; 0x44 8004e56: e841 2300 strex r3, r2, [r1] 8004e5a: 63fb str r3, [r7, #60] ; 0x3c return(result); 8004e5c: 6bfb ldr r3, [r7, #60] ; 0x3c 8004e5e: 2b00 cmp r3, #0 8004e60: d1e4 bne.n 8004e2c /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8004e62: 687b ldr r3, [r7, #4] 8004e64: 681b ldr r3, [r3, #0] 8004e66: 3308 adds r3, #8 8004e68: 627b str r3, [r7, #36] ; 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004e6a: 6a7b ldr r3, [r7, #36] ; 0x24 8004e6c: e853 3f00 ldrex r3, [r3] 8004e70: 623b str r3, [r7, #32] return(result); 8004e72: 6a3a ldr r2, [r7, #32] 8004e74: 4b54 ldr r3, [pc, #336] ; (8004fc8 ) 8004e76: 4013 ands r3, r2 8004e78: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 8004e7c: 687b ldr r3, [r7, #4] 8004e7e: 681b ldr r3, [r3, #0] 8004e80: 3308 adds r3, #8 8004e82: f8d7 20c4 ldr.w r2, [r7, #196] ; 0xc4 8004e86: 633a str r2, [r7, #48] ; 0x30 8004e88: 62fb str r3, [r7, #44] ; 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004e8a: 6af9 ldr r1, [r7, #44] ; 0x2c 8004e8c: 6b3a ldr r2, [r7, #48] ; 0x30 8004e8e: e841 2300 strex r3, r2, [r1] 8004e92: 62bb str r3, [r7, #40] ; 0x28 return(result); 8004e94: 6abb ldr r3, [r7, #40] ; 0x28 8004e96: 2b00 cmp r3, #0 8004e98: d1e3 bne.n 8004e62 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8004e9a: 687b ldr r3, [r7, #4] 8004e9c: 2220 movs r2, #32 8004e9e: f8c3 2088 str.w r2, [r3, #136] ; 0x88 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8004ea2: 687b ldr r3, [r7, #4] 8004ea4: 2200 movs r2, #0 8004ea6: 66da str r2, [r3, #108] ; 0x6c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8004ea8: 687b ldr r3, [r7, #4] 8004eaa: 2200 movs r2, #0 8004eac: 671a str r2, [r3, #112] ; 0x70 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8004eae: 687b ldr r3, [r7, #4] 8004eb0: 681b ldr r3, [r3, #0] 8004eb2: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004eb4: 693b ldr r3, [r7, #16] 8004eb6: e853 3f00 ldrex r3, [r3] 8004eba: 60fb str r3, [r7, #12] return(result); 8004ebc: 68fb ldr r3, [r7, #12] 8004ebe: f023 0310 bic.w r3, r3, #16 8004ec2: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0 8004ec6: 687b ldr r3, [r7, #4] 8004ec8: 681b ldr r3, [r3, #0] 8004eca: 461a mov r2, r3 8004ecc: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0 8004ed0: 61fb str r3, [r7, #28] 8004ed2: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004ed4: 69b9 ldr r1, [r7, #24] 8004ed6: 69fa ldr r2, [r7, #28] 8004ed8: e841 2300 strex r3, r2, [r1] 8004edc: 617b str r3, [r7, #20] return(result); 8004ede: 697b ldr r3, [r7, #20] 8004ee0: 2b00 cmp r3, #0 8004ee2: d1e4 bne.n 8004eae #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 8004ee4: f8b7 30ce ldrh.w r3, [r7, #206] ; 0xce 8004ee8: 4619 mov r1, r3 8004eea: 6878 ldr r0, [r7, #4] 8004eec: f000 f878 bl 8004fe0 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; 8004ef0: e063 b.n 8004fba } } /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) 8004ef2: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 8004ef6: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8004efa: 2b00 cmp r3, #0 8004efc: d00e beq.n 8004f1c 8004efe: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc 8004f02: f403 0380 and.w r3, r3, #4194304 ; 0x400000 8004f06: 2b00 cmp r3, #0 8004f08: d008 beq.n 8004f1c { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); 8004f0a: 687b ldr r3, [r7, #4] 8004f0c: 681b ldr r3, [r3, #0] 8004f0e: f44f 1280 mov.w r2, #1048576 ; 0x100000 8004f12: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Wakeup Callback */ huart->WakeupCallback(huart); #else /* Call legacy weak Wakeup Callback */ HAL_UARTEx_WakeupCallback(huart); 8004f14: 6878 ldr r0, [r7, #4] 8004f16: f002 f853 bl 8006fc0 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 8004f1a: e051 b.n 8004fc0 } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) 8004f1c: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 8004f20: f003 0380 and.w r3, r3, #128 ; 0x80 8004f24: 2b00 cmp r3, #0 8004f26: d014 beq.n 8004f52 && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) 8004f28: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 8004f2c: f003 0380 and.w r3, r3, #128 ; 0x80 8004f30: 2b00 cmp r3, #0 8004f32: d105 bne.n 8004f40 || ((cr3its & USART_CR3_TXFTIE) != 0U))) 8004f34: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc 8004f38: f403 0300 and.w r3, r3, #8388608 ; 0x800000 8004f3c: 2b00 cmp r3, #0 8004f3e: d008 beq.n 8004f52 { if (huart->TxISR != NULL) 8004f40: 687b ldr r3, [r7, #4] 8004f42: 6f5b ldr r3, [r3, #116] ; 0x74 8004f44: 2b00 cmp r3, #0 8004f46: d03a beq.n 8004fbe { huart->TxISR(huart); 8004f48: 687b ldr r3, [r7, #4] 8004f4a: 6f5b ldr r3, [r3, #116] ; 0x74 8004f4c: 6878 ldr r0, [r7, #4] 8004f4e: 4798 blx r3 } return; 8004f50: e035 b.n 8004fbe } /* UART in mode Transmitter (transmission end) -----------------------------*/ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) 8004f52: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 8004f56: f003 0340 and.w r3, r3, #64 ; 0x40 8004f5a: 2b00 cmp r3, #0 8004f5c: d009 beq.n 8004f72 8004f5e: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 8004f62: f003 0340 and.w r3, r3, #64 ; 0x40 8004f66: 2b00 cmp r3, #0 8004f68: d003 beq.n 8004f72 { UART_EndTransmit_IT(huart); 8004f6a: 6878 ldr r0, [r7, #4] 8004f6c: f001 fba0 bl 80066b0 return; 8004f70: e026 b.n 8004fc0 } /* UART TX Fifo Empty occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) 8004f72: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 8004f76: f403 0300 and.w r3, r3, #8388608 ; 0x800000 8004f7a: 2b00 cmp r3, #0 8004f7c: d009 beq.n 8004f92 8004f7e: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 8004f82: f003 4380 and.w r3, r3, #1073741824 ; 0x40000000 8004f86: 2b00 cmp r3, #0 8004f88: d003 beq.n 8004f92 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Tx Fifo Empty Callback */ huart->TxFifoEmptyCallback(huart); #else /* Call legacy weak Tx Fifo Empty Callback */ HAL_UARTEx_TxFifoEmptyCallback(huart); 8004f8a: 6878 ldr r0, [r7, #4] 8004f8c: f002 f82c bl 8006fe8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 8004f90: e016 b.n 8004fc0 } /* UART RX Fifo Full occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) 8004f92: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 8004f96: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 8004f9a: 2b00 cmp r3, #0 8004f9c: d010 beq.n 8004fc0 8004f9e: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 8004fa2: 2b00 cmp r3, #0 8004fa4: da0c bge.n 8004fc0 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Rx Fifo Full Callback */ huart->RxFifoFullCallback(huart); #else /* Call legacy weak Rx Fifo Full Callback */ HAL_UARTEx_RxFifoFullCallback(huart); 8004fa6: 6878 ldr r0, [r7, #4] 8004fa8: f002 f814 bl 8006fd4 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 8004fac: e008 b.n 8004fc0 return; 8004fae: bf00 nop 8004fb0: e006 b.n 8004fc0 return; 8004fb2: bf00 nop 8004fb4: e004 b.n 8004fc0 return; 8004fb6: bf00 nop 8004fb8: e002 b.n 8004fc0 return; 8004fba: bf00 nop 8004fbc: e000 b.n 8004fc0 return; 8004fbe: bf00 nop } } 8004fc0: 37e8 adds r7, #232 ; 0xe8 8004fc2: 46bd mov sp, r7 8004fc4: bd80 pop {r7, pc} 8004fc6: bf00 nop 8004fc8: effffffe .word 0xeffffffe 08004fcc : * @brief UART error callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 8004fcc: b480 push {r7} 8004fce: b083 sub sp, #12 8004fd0: af00 add r7, sp, #0 8004fd2: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback can be implemented in the user file. */ } 8004fd4: bf00 nop 8004fd6: 370c adds r7, #12 8004fd8: 46bd mov sp, r7 8004fda: f85d 7b04 ldr.w r7, [sp], #4 8004fde: 4770 bx lr 08004fe0 : * @param Size Number of data available in application reception buffer (indicates a position in * reception buffer until which, data are available) * @retval None */ __weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 8004fe0: b480 push {r7} 8004fe2: b083 sub sp, #12 8004fe4: af00 add r7, sp, #0 8004fe6: 6078 str r0, [r7, #4] 8004fe8: 460b mov r3, r1 8004fea: 807b strh r3, [r7, #2] UNUSED(Size); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxEventCallback can be implemented in the user file. */ } 8004fec: bf00 nop 8004fee: 370c adds r7, #12 8004ff0: 46bd mov sp, r7 8004ff2: f85d 7b04 ldr.w r7, [sp], #4 8004ff6: 4770 bx lr 08004ff8 : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { 8004ff8: b5b0 push {r4, r5, r7, lr} 8004ffa: b08e sub sp, #56 ; 0x38 8004ffc: af00 add r7, sp, #0 8004ffe: 6078 str r0, [r7, #4] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; 8005000: 2300 movs r3, #0 8005002: f887 3032 strb.w r3, [r7, #50] ; 0x32 * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 8005006: 687b ldr r3, [r7, #4] 8005008: 689a ldr r2, [r3, #8] 800500a: 687b ldr r3, [r7, #4] 800500c: 691b ldr r3, [r3, #16] 800500e: 431a orrs r2, r3 8005010: 687b ldr r3, [r7, #4] 8005012: 695b ldr r3, [r3, #20] 8005014: 431a orrs r2, r3 8005016: 687b ldr r3, [r7, #4] 8005018: 69db ldr r3, [r3, #28] 800501a: 4313 orrs r3, r2 800501c: 637b str r3, [r7, #52] ; 0x34 MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 800501e: 687b ldr r3, [r7, #4] 8005020: 681b ldr r3, [r3, #0] 8005022: 681a ldr r2, [r3, #0] 8005024: 4bbf ldr r3, [pc, #764] ; (8005324 ) 8005026: 4013 ands r3, r2 8005028: 687a ldr r2, [r7, #4] 800502a: 6812 ldr r2, [r2, #0] 800502c: 6b79 ldr r1, [r7, #52] ; 0x34 800502e: 430b orrs r3, r1 8005030: 6013 str r3, [r2, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8005032: 687b ldr r3, [r7, #4] 8005034: 681b ldr r3, [r3, #0] 8005036: 685b ldr r3, [r3, #4] 8005038: f423 5140 bic.w r1, r3, #12288 ; 0x3000 800503c: 687b ldr r3, [r7, #4] 800503e: 68da ldr r2, [r3, #12] 8005040: 687b ldr r3, [r7, #4] 8005042: 681b ldr r3, [r3, #0] 8005044: 430a orrs r2, r1 8005046: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; 8005048: 687b ldr r3, [r7, #4] 800504a: 699b ldr r3, [r3, #24] 800504c: 637b str r3, [r7, #52] ; 0x34 if (!(UART_INSTANCE_LOWPOWER(huart))) 800504e: 687b ldr r3, [r7, #4] 8005050: 681b ldr r3, [r3, #0] 8005052: 4ab5 ldr r2, [pc, #724] ; (8005328 ) 8005054: 4293 cmp r3, r2 8005056: d004 beq.n 8005062 { tmpreg |= huart->Init.OneBitSampling; 8005058: 687b ldr r3, [r7, #4] 800505a: 6a1b ldr r3, [r3, #32] 800505c: 6b7a ldr r2, [r7, #52] ; 0x34 800505e: 4313 orrs r3, r2 8005060: 637b str r3, [r7, #52] ; 0x34 } MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); 8005062: 687b ldr r3, [r7, #4] 8005064: 681b ldr r3, [r3, #0] 8005066: 689a ldr r2, [r3, #8] 8005068: 4bb0 ldr r3, [pc, #704] ; (800532c ) 800506a: 4013 ands r3, r2 800506c: 687a ldr r2, [r7, #4] 800506e: 6812 ldr r2, [r2, #0] 8005070: 6b79 ldr r1, [r7, #52] ; 0x34 8005072: 430b orrs r3, r1 8005074: 6093 str r3, [r2, #8] /*-------------------------- USART PRESC Configuration -----------------------*/ /* Configure * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); 8005076: 687b ldr r3, [r7, #4] 8005078: 681b ldr r3, [r3, #0] 800507a: 6adb ldr r3, [r3, #44] ; 0x2c 800507c: f023 010f bic.w r1, r3, #15 8005080: 687b ldr r3, [r7, #4] 8005082: 6a5a ldr r2, [r3, #36] ; 0x24 8005084: 687b ldr r3, [r7, #4] 8005086: 681b ldr r3, [r3, #0] 8005088: 430a orrs r2, r1 800508a: 62da str r2, [r3, #44] ; 0x2c /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); 800508c: 687b ldr r3, [r7, #4] 800508e: 681b ldr r3, [r3, #0] 8005090: 4aa7 ldr r2, [pc, #668] ; (8005330 ) 8005092: 4293 cmp r3, r2 8005094: d176 bne.n 8005184 8005096: 4ba7 ldr r3, [pc, #668] ; (8005334 ) 8005098: 6d5b ldr r3, [r3, #84] ; 0x54 800509a: f003 0338 and.w r3, r3, #56 ; 0x38 800509e: 2b28 cmp r3, #40 ; 0x28 80050a0: d86c bhi.n 800517c 80050a2: a201 add r2, pc, #4 ; (adr r2, 80050a8 ) 80050a4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80050a8: 0800514d .word 0x0800514d 80050ac: 0800517d .word 0x0800517d 80050b0: 0800517d .word 0x0800517d 80050b4: 0800517d .word 0x0800517d 80050b8: 0800517d .word 0x0800517d 80050bc: 0800517d .word 0x0800517d 80050c0: 0800517d .word 0x0800517d 80050c4: 0800517d .word 0x0800517d 80050c8: 08005155 .word 0x08005155 80050cc: 0800517d .word 0x0800517d 80050d0: 0800517d .word 0x0800517d 80050d4: 0800517d .word 0x0800517d 80050d8: 0800517d .word 0x0800517d 80050dc: 0800517d .word 0x0800517d 80050e0: 0800517d .word 0x0800517d 80050e4: 0800517d .word 0x0800517d 80050e8: 0800515d .word 0x0800515d 80050ec: 0800517d .word 0x0800517d 80050f0: 0800517d .word 0x0800517d 80050f4: 0800517d .word 0x0800517d 80050f8: 0800517d .word 0x0800517d 80050fc: 0800517d .word 0x0800517d 8005100: 0800517d .word 0x0800517d 8005104: 0800517d .word 0x0800517d 8005108: 08005165 .word 0x08005165 800510c: 0800517d .word 0x0800517d 8005110: 0800517d .word 0x0800517d 8005114: 0800517d .word 0x0800517d 8005118: 0800517d .word 0x0800517d 800511c: 0800517d .word 0x0800517d 8005120: 0800517d .word 0x0800517d 8005124: 0800517d .word 0x0800517d 8005128: 0800516d .word 0x0800516d 800512c: 0800517d .word 0x0800517d 8005130: 0800517d .word 0x0800517d 8005134: 0800517d .word 0x0800517d 8005138: 0800517d .word 0x0800517d 800513c: 0800517d .word 0x0800517d 8005140: 0800517d .word 0x0800517d 8005144: 0800517d .word 0x0800517d 8005148: 08005175 .word 0x08005175 800514c: 2301 movs r3, #1 800514e: f887 3033 strb.w r3, [r7, #51] ; 0x33 8005152: e326 b.n 80057a2 8005154: 2304 movs r3, #4 8005156: f887 3033 strb.w r3, [r7, #51] ; 0x33 800515a: e322 b.n 80057a2 800515c: 2308 movs r3, #8 800515e: f887 3033 strb.w r3, [r7, #51] ; 0x33 8005162: e31e b.n 80057a2 8005164: 2310 movs r3, #16 8005166: f887 3033 strb.w r3, [r7, #51] ; 0x33 800516a: e31a b.n 80057a2 800516c: 2320 movs r3, #32 800516e: f887 3033 strb.w r3, [r7, #51] ; 0x33 8005172: e316 b.n 80057a2 8005174: 2340 movs r3, #64 ; 0x40 8005176: f887 3033 strb.w r3, [r7, #51] ; 0x33 800517a: e312 b.n 80057a2 800517c: 2380 movs r3, #128 ; 0x80 800517e: f887 3033 strb.w r3, [r7, #51] ; 0x33 8005182: e30e b.n 80057a2 8005184: 687b ldr r3, [r7, #4] 8005186: 681b ldr r3, [r3, #0] 8005188: 4a6b ldr r2, [pc, #428] ; (8005338 ) 800518a: 4293 cmp r3, r2 800518c: d130 bne.n 80051f0 800518e: 4b69 ldr r3, [pc, #420] ; (8005334 ) 8005190: 6d5b ldr r3, [r3, #84] ; 0x54 8005192: f003 0307 and.w r3, r3, #7 8005196: 2b05 cmp r3, #5 8005198: d826 bhi.n 80051e8 800519a: a201 add r2, pc, #4 ; (adr r2, 80051a0 ) 800519c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80051a0: 080051b9 .word 0x080051b9 80051a4: 080051c1 .word 0x080051c1 80051a8: 080051c9 .word 0x080051c9 80051ac: 080051d1 .word 0x080051d1 80051b0: 080051d9 .word 0x080051d9 80051b4: 080051e1 .word 0x080051e1 80051b8: 2300 movs r3, #0 80051ba: f887 3033 strb.w r3, [r7, #51] ; 0x33 80051be: e2f0 b.n 80057a2 80051c0: 2304 movs r3, #4 80051c2: f887 3033 strb.w r3, [r7, #51] ; 0x33 80051c6: e2ec b.n 80057a2 80051c8: 2308 movs r3, #8 80051ca: f887 3033 strb.w r3, [r7, #51] ; 0x33 80051ce: e2e8 b.n 80057a2 80051d0: 2310 movs r3, #16 80051d2: f887 3033 strb.w r3, [r7, #51] ; 0x33 80051d6: e2e4 b.n 80057a2 80051d8: 2320 movs r3, #32 80051da: f887 3033 strb.w r3, [r7, #51] ; 0x33 80051de: e2e0 b.n 80057a2 80051e0: 2340 movs r3, #64 ; 0x40 80051e2: f887 3033 strb.w r3, [r7, #51] ; 0x33 80051e6: e2dc b.n 80057a2 80051e8: 2380 movs r3, #128 ; 0x80 80051ea: f887 3033 strb.w r3, [r7, #51] ; 0x33 80051ee: e2d8 b.n 80057a2 80051f0: 687b ldr r3, [r7, #4] 80051f2: 681b ldr r3, [r3, #0] 80051f4: 4a51 ldr r2, [pc, #324] ; (800533c ) 80051f6: 4293 cmp r3, r2 80051f8: d130 bne.n 800525c 80051fa: 4b4e ldr r3, [pc, #312] ; (8005334 ) 80051fc: 6d5b ldr r3, [r3, #84] ; 0x54 80051fe: f003 0307 and.w r3, r3, #7 8005202: 2b05 cmp r3, #5 8005204: d826 bhi.n 8005254 8005206: a201 add r2, pc, #4 ; (adr r2, 800520c ) 8005208: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800520c: 08005225 .word 0x08005225 8005210: 0800522d .word 0x0800522d 8005214: 08005235 .word 0x08005235 8005218: 0800523d .word 0x0800523d 800521c: 08005245 .word 0x08005245 8005220: 0800524d .word 0x0800524d 8005224: 2300 movs r3, #0 8005226: f887 3033 strb.w r3, [r7, #51] ; 0x33 800522a: e2ba b.n 80057a2 800522c: 2304 movs r3, #4 800522e: f887 3033 strb.w r3, [r7, #51] ; 0x33 8005232: e2b6 b.n 80057a2 8005234: 2308 movs r3, #8 8005236: f887 3033 strb.w r3, [r7, #51] ; 0x33 800523a: e2b2 b.n 80057a2 800523c: 2310 movs r3, #16 800523e: f887 3033 strb.w r3, [r7, #51] ; 0x33 8005242: e2ae b.n 80057a2 8005244: 2320 movs r3, #32 8005246: f887 3033 strb.w r3, [r7, #51] ; 0x33 800524a: e2aa b.n 80057a2 800524c: 2340 movs r3, #64 ; 0x40 800524e: f887 3033 strb.w r3, [r7, #51] ; 0x33 8005252: e2a6 b.n 80057a2 8005254: 2380 movs r3, #128 ; 0x80 8005256: f887 3033 strb.w r3, [r7, #51] ; 0x33 800525a: e2a2 b.n 80057a2 800525c: 687b ldr r3, [r7, #4] 800525e: 681b ldr r3, [r3, #0] 8005260: 4a37 ldr r2, [pc, #220] ; (8005340 ) 8005262: 4293 cmp r3, r2 8005264: d130 bne.n 80052c8 8005266: 4b33 ldr r3, [pc, #204] ; (8005334 ) 8005268: 6d5b ldr r3, [r3, #84] ; 0x54 800526a: f003 0307 and.w r3, r3, #7 800526e: 2b05 cmp r3, #5 8005270: d826 bhi.n 80052c0 8005272: a201 add r2, pc, #4 ; (adr r2, 8005278 ) 8005274: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8005278: 08005291 .word 0x08005291 800527c: 08005299 .word 0x08005299 8005280: 080052a1 .word 0x080052a1 8005284: 080052a9 .word 0x080052a9 8005288: 080052b1 .word 0x080052b1 800528c: 080052b9 .word 0x080052b9 8005290: 2300 movs r3, #0 8005292: f887 3033 strb.w r3, [r7, #51] ; 0x33 8005296: e284 b.n 80057a2 8005298: 2304 movs r3, #4 800529a: f887 3033 strb.w r3, [r7, #51] ; 0x33 800529e: e280 b.n 80057a2 80052a0: 2308 movs r3, #8 80052a2: f887 3033 strb.w r3, [r7, #51] ; 0x33 80052a6: e27c b.n 80057a2 80052a8: 2310 movs r3, #16 80052aa: f887 3033 strb.w r3, [r7, #51] ; 0x33 80052ae: e278 b.n 80057a2 80052b0: 2320 movs r3, #32 80052b2: f887 3033 strb.w r3, [r7, #51] ; 0x33 80052b6: e274 b.n 80057a2 80052b8: 2340 movs r3, #64 ; 0x40 80052ba: f887 3033 strb.w r3, [r7, #51] ; 0x33 80052be: e270 b.n 80057a2 80052c0: 2380 movs r3, #128 ; 0x80 80052c2: f887 3033 strb.w r3, [r7, #51] ; 0x33 80052c6: e26c b.n 80057a2 80052c8: 687b ldr r3, [r7, #4] 80052ca: 681b ldr r3, [r3, #0] 80052cc: 4a1d ldr r2, [pc, #116] ; (8005344 ) 80052ce: 4293 cmp r3, r2 80052d0: d142 bne.n 8005358 80052d2: 4b18 ldr r3, [pc, #96] ; (8005334 ) 80052d4: 6d5b ldr r3, [r3, #84] ; 0x54 80052d6: f003 0307 and.w r3, r3, #7 80052da: 2b05 cmp r3, #5 80052dc: d838 bhi.n 8005350 80052de: a201 add r2, pc, #4 ; (adr r2, 80052e4 ) 80052e0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80052e4: 080052fd .word 0x080052fd 80052e8: 08005305 .word 0x08005305 80052ec: 0800530d .word 0x0800530d 80052f0: 08005315 .word 0x08005315 80052f4: 0800531d .word 0x0800531d 80052f8: 08005349 .word 0x08005349 80052fc: 2300 movs r3, #0 80052fe: f887 3033 strb.w r3, [r7, #51] ; 0x33 8005302: e24e b.n 80057a2 8005304: 2304 movs r3, #4 8005306: f887 3033 strb.w r3, [r7, #51] ; 0x33 800530a: e24a b.n 80057a2 800530c: 2308 movs r3, #8 800530e: f887 3033 strb.w r3, [r7, #51] ; 0x33 8005312: e246 b.n 80057a2 8005314: 2310 movs r3, #16 8005316: f887 3033 strb.w r3, [r7, #51] ; 0x33 800531a: e242 b.n 80057a2 800531c: 2320 movs r3, #32 800531e: f887 3033 strb.w r3, [r7, #51] ; 0x33 8005322: e23e b.n 80057a2 8005324: cfff69f3 .word 0xcfff69f3 8005328: 58000c00 .word 0x58000c00 800532c: 11fff4ff .word 0x11fff4ff 8005330: 40011000 .word 0x40011000 8005334: 58024400 .word 0x58024400 8005338: 40004400 .word 0x40004400 800533c: 40004800 .word 0x40004800 8005340: 40004c00 .word 0x40004c00 8005344: 40005000 .word 0x40005000 8005348: 2340 movs r3, #64 ; 0x40 800534a: f887 3033 strb.w r3, [r7, #51] ; 0x33 800534e: e228 b.n 80057a2 8005350: 2380 movs r3, #128 ; 0x80 8005352: f887 3033 strb.w r3, [r7, #51] ; 0x33 8005356: e224 b.n 80057a2 8005358: 687b ldr r3, [r7, #4] 800535a: 681b ldr r3, [r3, #0] 800535c: 4ab1 ldr r2, [pc, #708] ; (8005624 ) 800535e: 4293 cmp r3, r2 8005360: d176 bne.n 8005450 8005362: 4bb1 ldr r3, [pc, #708] ; (8005628 ) 8005364: 6d5b ldr r3, [r3, #84] ; 0x54 8005366: f003 0338 and.w r3, r3, #56 ; 0x38 800536a: 2b28 cmp r3, #40 ; 0x28 800536c: d86c bhi.n 8005448 800536e: a201 add r2, pc, #4 ; (adr r2, 8005374 ) 8005370: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8005374: 08005419 .word 0x08005419 8005378: 08005449 .word 0x08005449 800537c: 08005449 .word 0x08005449 8005380: 08005449 .word 0x08005449 8005384: 08005449 .word 0x08005449 8005388: 08005449 .word 0x08005449 800538c: 08005449 .word 0x08005449 8005390: 08005449 .word 0x08005449 8005394: 08005421 .word 0x08005421 8005398: 08005449 .word 0x08005449 800539c: 08005449 .word 0x08005449 80053a0: 08005449 .word 0x08005449 80053a4: 08005449 .word 0x08005449 80053a8: 08005449 .word 0x08005449 80053ac: 08005449 .word 0x08005449 80053b0: 08005449 .word 0x08005449 80053b4: 08005429 .word 0x08005429 80053b8: 08005449 .word 0x08005449 80053bc: 08005449 .word 0x08005449 80053c0: 08005449 .word 0x08005449 80053c4: 08005449 .word 0x08005449 80053c8: 08005449 .word 0x08005449 80053cc: 08005449 .word 0x08005449 80053d0: 08005449 .word 0x08005449 80053d4: 08005431 .word 0x08005431 80053d8: 08005449 .word 0x08005449 80053dc: 08005449 .word 0x08005449 80053e0: 08005449 .word 0x08005449 80053e4: 08005449 .word 0x08005449 80053e8: 08005449 .word 0x08005449 80053ec: 08005449 .word 0x08005449 80053f0: 08005449 .word 0x08005449 80053f4: 08005439 .word 0x08005439 80053f8: 08005449 .word 0x08005449 80053fc: 08005449 .word 0x08005449 8005400: 08005449 .word 0x08005449 8005404: 08005449 .word 0x08005449 8005408: 08005449 .word 0x08005449 800540c: 08005449 .word 0x08005449 8005410: 08005449 .word 0x08005449 8005414: 08005441 .word 0x08005441 8005418: 2301 movs r3, #1 800541a: f887 3033 strb.w r3, [r7, #51] ; 0x33 800541e: e1c0 b.n 80057a2 8005420: 2304 movs r3, #4 8005422: f887 3033 strb.w r3, [r7, #51] ; 0x33 8005426: e1bc b.n 80057a2 8005428: 2308 movs r3, #8 800542a: f887 3033 strb.w r3, [r7, #51] ; 0x33 800542e: e1b8 b.n 80057a2 8005430: 2310 movs r3, #16 8005432: f887 3033 strb.w r3, [r7, #51] ; 0x33 8005436: e1b4 b.n 80057a2 8005438: 2320 movs r3, #32 800543a: f887 3033 strb.w r3, [r7, #51] ; 0x33 800543e: e1b0 b.n 80057a2 8005440: 2340 movs r3, #64 ; 0x40 8005442: f887 3033 strb.w r3, [r7, #51] ; 0x33 8005446: e1ac b.n 80057a2 8005448: 2380 movs r3, #128 ; 0x80 800544a: f887 3033 strb.w r3, [r7, #51] ; 0x33 800544e: e1a8 b.n 80057a2 8005450: 687b ldr r3, [r7, #4] 8005452: 681b ldr r3, [r3, #0] 8005454: 4a75 ldr r2, [pc, #468] ; (800562c ) 8005456: 4293 cmp r3, r2 8005458: d130 bne.n 80054bc 800545a: 4b73 ldr r3, [pc, #460] ; (8005628 ) 800545c: 6d5b ldr r3, [r3, #84] ; 0x54 800545e: f003 0307 and.w r3, r3, #7 8005462: 2b05 cmp r3, #5 8005464: d826 bhi.n 80054b4 8005466: a201 add r2, pc, #4 ; (adr r2, 800546c ) 8005468: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800546c: 08005485 .word 0x08005485 8005470: 0800548d .word 0x0800548d 8005474: 08005495 .word 0x08005495 8005478: 0800549d .word 0x0800549d 800547c: 080054a5 .word 0x080054a5 8005480: 080054ad .word 0x080054ad 8005484: 2300 movs r3, #0 8005486: f887 3033 strb.w r3, [r7, #51] ; 0x33 800548a: e18a b.n 80057a2 800548c: 2304 movs r3, #4 800548e: f887 3033 strb.w r3, [r7, #51] ; 0x33 8005492: e186 b.n 80057a2 8005494: 2308 movs r3, #8 8005496: f887 3033 strb.w r3, [r7, #51] ; 0x33 800549a: e182 b.n 80057a2 800549c: 2310 movs r3, #16 800549e: f887 3033 strb.w r3, [r7, #51] ; 0x33 80054a2: e17e b.n 80057a2 80054a4: 2320 movs r3, #32 80054a6: f887 3033 strb.w r3, [r7, #51] ; 0x33 80054aa: e17a b.n 80057a2 80054ac: 2340 movs r3, #64 ; 0x40 80054ae: f887 3033 strb.w r3, [r7, #51] ; 0x33 80054b2: e176 b.n 80057a2 80054b4: 2380 movs r3, #128 ; 0x80 80054b6: f887 3033 strb.w r3, [r7, #51] ; 0x33 80054ba: e172 b.n 80057a2 80054bc: 687b ldr r3, [r7, #4] 80054be: 681b ldr r3, [r3, #0] 80054c0: 4a5b ldr r2, [pc, #364] ; (8005630 ) 80054c2: 4293 cmp r3, r2 80054c4: d130 bne.n 8005528 80054c6: 4b58 ldr r3, [pc, #352] ; (8005628 ) 80054c8: 6d5b ldr r3, [r3, #84] ; 0x54 80054ca: f003 0307 and.w r3, r3, #7 80054ce: 2b05 cmp r3, #5 80054d0: d826 bhi.n 8005520 80054d2: a201 add r2, pc, #4 ; (adr r2, 80054d8 ) 80054d4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80054d8: 080054f1 .word 0x080054f1 80054dc: 080054f9 .word 0x080054f9 80054e0: 08005501 .word 0x08005501 80054e4: 08005509 .word 0x08005509 80054e8: 08005511 .word 0x08005511 80054ec: 08005519 .word 0x08005519 80054f0: 2300 movs r3, #0 80054f2: f887 3033 strb.w r3, [r7, #51] ; 0x33 80054f6: e154 b.n 80057a2 80054f8: 2304 movs r3, #4 80054fa: f887 3033 strb.w r3, [r7, #51] ; 0x33 80054fe: e150 b.n 80057a2 8005500: 2308 movs r3, #8 8005502: f887 3033 strb.w r3, [r7, #51] ; 0x33 8005506: e14c b.n 80057a2 8005508: 2310 movs r3, #16 800550a: f887 3033 strb.w r3, [r7, #51] ; 0x33 800550e: e148 b.n 80057a2 8005510: 2320 movs r3, #32 8005512: f887 3033 strb.w r3, [r7, #51] ; 0x33 8005516: e144 b.n 80057a2 8005518: 2340 movs r3, #64 ; 0x40 800551a: f887 3033 strb.w r3, [r7, #51] ; 0x33 800551e: e140 b.n 80057a2 8005520: 2380 movs r3, #128 ; 0x80 8005522: f887 3033 strb.w r3, [r7, #51] ; 0x33 8005526: e13c b.n 80057a2 8005528: 687b ldr r3, [r7, #4] 800552a: 681b ldr r3, [r3, #0] 800552c: 4a41 ldr r2, [pc, #260] ; (8005634 ) 800552e: 4293 cmp r3, r2 8005530: f040 8082 bne.w 8005638 8005534: 4b3c ldr r3, [pc, #240] ; (8005628 ) 8005536: 6d5b ldr r3, [r3, #84] ; 0x54 8005538: f003 0338 and.w r3, r3, #56 ; 0x38 800553c: 2b28 cmp r3, #40 ; 0x28 800553e: d86d bhi.n 800561c 8005540: a201 add r2, pc, #4 ; (adr r2, 8005548 ) 8005542: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8005546: bf00 nop 8005548: 080055ed .word 0x080055ed 800554c: 0800561d .word 0x0800561d 8005550: 0800561d .word 0x0800561d 8005554: 0800561d .word 0x0800561d 8005558: 0800561d .word 0x0800561d 800555c: 0800561d .word 0x0800561d 8005560: 0800561d .word 0x0800561d 8005564: 0800561d .word 0x0800561d 8005568: 080055f5 .word 0x080055f5 800556c: 0800561d .word 0x0800561d 8005570: 0800561d .word 0x0800561d 8005574: 0800561d .word 0x0800561d 8005578: 0800561d .word 0x0800561d 800557c: 0800561d .word 0x0800561d 8005580: 0800561d .word 0x0800561d 8005584: 0800561d .word 0x0800561d 8005588: 080055fd .word 0x080055fd 800558c: 0800561d .word 0x0800561d 8005590: 0800561d .word 0x0800561d 8005594: 0800561d .word 0x0800561d 8005598: 0800561d .word 0x0800561d 800559c: 0800561d .word 0x0800561d 80055a0: 0800561d .word 0x0800561d 80055a4: 0800561d .word 0x0800561d 80055a8: 08005605 .word 0x08005605 80055ac: 0800561d .word 0x0800561d 80055b0: 0800561d .word 0x0800561d 80055b4: 0800561d .word 0x0800561d 80055b8: 0800561d .word 0x0800561d 80055bc: 0800561d .word 0x0800561d 80055c0: 0800561d .word 0x0800561d 80055c4: 0800561d .word 0x0800561d 80055c8: 0800560d .word 0x0800560d 80055cc: 0800561d .word 0x0800561d 80055d0: 0800561d .word 0x0800561d 80055d4: 0800561d .word 0x0800561d 80055d8: 0800561d .word 0x0800561d 80055dc: 0800561d .word 0x0800561d 80055e0: 0800561d .word 0x0800561d 80055e4: 0800561d .word 0x0800561d 80055e8: 08005615 .word 0x08005615 80055ec: 2301 movs r3, #1 80055ee: f887 3033 strb.w r3, [r7, #51] ; 0x33 80055f2: e0d6 b.n 80057a2 80055f4: 2304 movs r3, #4 80055f6: f887 3033 strb.w r3, [r7, #51] ; 0x33 80055fa: e0d2 b.n 80057a2 80055fc: 2308 movs r3, #8 80055fe: f887 3033 strb.w r3, [r7, #51] ; 0x33 8005602: e0ce b.n 80057a2 8005604: 2310 movs r3, #16 8005606: f887 3033 strb.w r3, [r7, #51] ; 0x33 800560a: e0ca b.n 80057a2 800560c: 2320 movs r3, #32 800560e: f887 3033 strb.w r3, [r7, #51] ; 0x33 8005612: e0c6 b.n 80057a2 8005614: 2340 movs r3, #64 ; 0x40 8005616: f887 3033 strb.w r3, [r7, #51] ; 0x33 800561a: e0c2 b.n 80057a2 800561c: 2380 movs r3, #128 ; 0x80 800561e: f887 3033 strb.w r3, [r7, #51] ; 0x33 8005622: e0be b.n 80057a2 8005624: 40011400 .word 0x40011400 8005628: 58024400 .word 0x58024400 800562c: 40007800 .word 0x40007800 8005630: 40007c00 .word 0x40007c00 8005634: 40011800 .word 0x40011800 8005638: 687b ldr r3, [r7, #4] 800563a: 681b ldr r3, [r3, #0] 800563c: 4aad ldr r2, [pc, #692] ; (80058f4 ) 800563e: 4293 cmp r3, r2 8005640: d176 bne.n 8005730 8005642: 4bad ldr r3, [pc, #692] ; (80058f8 ) 8005644: 6d5b ldr r3, [r3, #84] ; 0x54 8005646: f003 0338 and.w r3, r3, #56 ; 0x38 800564a: 2b28 cmp r3, #40 ; 0x28 800564c: d86c bhi.n 8005728 800564e: a201 add r2, pc, #4 ; (adr r2, 8005654 ) 8005650: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8005654: 080056f9 .word 0x080056f9 8005658: 08005729 .word 0x08005729 800565c: 08005729 .word 0x08005729 8005660: 08005729 .word 0x08005729 8005664: 08005729 .word 0x08005729 8005668: 08005729 .word 0x08005729 800566c: 08005729 .word 0x08005729 8005670: 08005729 .word 0x08005729 8005674: 08005701 .word 0x08005701 8005678: 08005729 .word 0x08005729 800567c: 08005729 .word 0x08005729 8005680: 08005729 .word 0x08005729 8005684: 08005729 .word 0x08005729 8005688: 08005729 .word 0x08005729 800568c: 08005729 .word 0x08005729 8005690: 08005729 .word 0x08005729 8005694: 08005709 .word 0x08005709 8005698: 08005729 .word 0x08005729 800569c: 08005729 .word 0x08005729 80056a0: 08005729 .word 0x08005729 80056a4: 08005729 .word 0x08005729 80056a8: 08005729 .word 0x08005729 80056ac: 08005729 .word 0x08005729 80056b0: 08005729 .word 0x08005729 80056b4: 08005711 .word 0x08005711 80056b8: 08005729 .word 0x08005729 80056bc: 08005729 .word 0x08005729 80056c0: 08005729 .word 0x08005729 80056c4: 08005729 .word 0x08005729 80056c8: 08005729 .word 0x08005729 80056cc: 08005729 .word 0x08005729 80056d0: 08005729 .word 0x08005729 80056d4: 08005719 .word 0x08005719 80056d8: 08005729 .word 0x08005729 80056dc: 08005729 .word 0x08005729 80056e0: 08005729 .word 0x08005729 80056e4: 08005729 .word 0x08005729 80056e8: 08005729 .word 0x08005729 80056ec: 08005729 .word 0x08005729 80056f0: 08005729 .word 0x08005729 80056f4: 08005721 .word 0x08005721 80056f8: 2301 movs r3, #1 80056fa: f887 3033 strb.w r3, [r7, #51] ; 0x33 80056fe: e050 b.n 80057a2 8005700: 2304 movs r3, #4 8005702: f887 3033 strb.w r3, [r7, #51] ; 0x33 8005706: e04c b.n 80057a2 8005708: 2308 movs r3, #8 800570a: f887 3033 strb.w r3, [r7, #51] ; 0x33 800570e: e048 b.n 80057a2 8005710: 2310 movs r3, #16 8005712: f887 3033 strb.w r3, [r7, #51] ; 0x33 8005716: e044 b.n 80057a2 8005718: 2320 movs r3, #32 800571a: f887 3033 strb.w r3, [r7, #51] ; 0x33 800571e: e040 b.n 80057a2 8005720: 2340 movs r3, #64 ; 0x40 8005722: f887 3033 strb.w r3, [r7, #51] ; 0x33 8005726: e03c b.n 80057a2 8005728: 2380 movs r3, #128 ; 0x80 800572a: f887 3033 strb.w r3, [r7, #51] ; 0x33 800572e: e038 b.n 80057a2 8005730: 687b ldr r3, [r7, #4] 8005732: 681b ldr r3, [r3, #0] 8005734: 4a71 ldr r2, [pc, #452] ; (80058fc ) 8005736: 4293 cmp r3, r2 8005738: d130 bne.n 800579c 800573a: 4b6f ldr r3, [pc, #444] ; (80058f8 ) 800573c: 6d9b ldr r3, [r3, #88] ; 0x58 800573e: f003 0307 and.w r3, r3, #7 8005742: 2b05 cmp r3, #5 8005744: d826 bhi.n 8005794 8005746: a201 add r2, pc, #4 ; (adr r2, 800574c ) 8005748: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800574c: 08005765 .word 0x08005765 8005750: 0800576d .word 0x0800576d 8005754: 08005775 .word 0x08005775 8005758: 0800577d .word 0x0800577d 800575c: 08005785 .word 0x08005785 8005760: 0800578d .word 0x0800578d 8005764: 2302 movs r3, #2 8005766: f887 3033 strb.w r3, [r7, #51] ; 0x33 800576a: e01a b.n 80057a2 800576c: 2304 movs r3, #4 800576e: f887 3033 strb.w r3, [r7, #51] ; 0x33 8005772: e016 b.n 80057a2 8005774: 2308 movs r3, #8 8005776: f887 3033 strb.w r3, [r7, #51] ; 0x33 800577a: e012 b.n 80057a2 800577c: 2310 movs r3, #16 800577e: f887 3033 strb.w r3, [r7, #51] ; 0x33 8005782: e00e b.n 80057a2 8005784: 2320 movs r3, #32 8005786: f887 3033 strb.w r3, [r7, #51] ; 0x33 800578a: e00a b.n 80057a2 800578c: 2340 movs r3, #64 ; 0x40 800578e: f887 3033 strb.w r3, [r7, #51] ; 0x33 8005792: e006 b.n 80057a2 8005794: 2380 movs r3, #128 ; 0x80 8005796: f887 3033 strb.w r3, [r7, #51] ; 0x33 800579a: e002 b.n 80057a2 800579c: 2380 movs r3, #128 ; 0x80 800579e: f887 3033 strb.w r3, [r7, #51] ; 0x33 /* Check LPUART instance */ if (UART_INSTANCE_LOWPOWER(huart)) 80057a2: 687b ldr r3, [r7, #4] 80057a4: 681b ldr r3, [r3, #0] 80057a6: 4a55 ldr r2, [pc, #340] ; (80058fc ) 80057a8: 4293 cmp r3, r2 80057aa: f040 80f0 bne.w 800598e { /* Retrieve frequency clock */ switch (clocksource) 80057ae: f897 3033 ldrb.w r3, [r7, #51] ; 0x33 80057b2: 2b20 cmp r3, #32 80057b4: dc46 bgt.n 8005844 80057b6: 2b02 cmp r3, #2 80057b8: db75 blt.n 80058a6 80057ba: 3b02 subs r3, #2 80057bc: 2b1e cmp r3, #30 80057be: d872 bhi.n 80058a6 80057c0: a201 add r2, pc, #4 ; (adr r2, 80057c8 ) 80057c2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80057c6: bf00 nop 80057c8: 0800584b .word 0x0800584b 80057cc: 080058a7 .word 0x080058a7 80057d0: 08005853 .word 0x08005853 80057d4: 080058a7 .word 0x080058a7 80057d8: 080058a7 .word 0x080058a7 80057dc: 080058a7 .word 0x080058a7 80057e0: 08005863 .word 0x08005863 80057e4: 080058a7 .word 0x080058a7 80057e8: 080058a7 .word 0x080058a7 80057ec: 080058a7 .word 0x080058a7 80057f0: 080058a7 .word 0x080058a7 80057f4: 080058a7 .word 0x080058a7 80057f8: 080058a7 .word 0x080058a7 80057fc: 080058a7 .word 0x080058a7 8005800: 08005873 .word 0x08005873 8005804: 080058a7 .word 0x080058a7 8005808: 080058a7 .word 0x080058a7 800580c: 080058a7 .word 0x080058a7 8005810: 080058a7 .word 0x080058a7 8005814: 080058a7 .word 0x080058a7 8005818: 080058a7 .word 0x080058a7 800581c: 080058a7 .word 0x080058a7 8005820: 080058a7 .word 0x080058a7 8005824: 080058a7 .word 0x080058a7 8005828: 080058a7 .word 0x080058a7 800582c: 080058a7 .word 0x080058a7 8005830: 080058a7 .word 0x080058a7 8005834: 080058a7 .word 0x080058a7 8005838: 080058a7 .word 0x080058a7 800583c: 080058a7 .word 0x080058a7 8005840: 08005899 .word 0x08005899 8005844: 2b40 cmp r3, #64 ; 0x40 8005846: d02a beq.n 800589e 8005848: e02d b.n 80058a6 { case UART_CLOCKSOURCE_D3PCLK1: pclk = HAL_RCCEx_GetD3PCLK1Freq(); 800584a: f7fe fab1 bl 8003db0 800584e: 62f8 str r0, [r7, #44] ; 0x2c break; 8005850: e02f b.n 80058b2 case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8005852: f107 0314 add.w r3, r7, #20 8005856: 4618 mov r0, r3 8005858: f7fe fac0 bl 8003ddc pclk = pll2_clocks.PLL2_Q_Frequency; 800585c: 69bb ldr r3, [r7, #24] 800585e: 62fb str r3, [r7, #44] ; 0x2c break; 8005860: e027 b.n 80058b2 case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8005862: f107 0308 add.w r3, r7, #8 8005866: 4618 mov r0, r3 8005868: f7fe fc0c bl 8004084 pclk = pll3_clocks.PLL3_Q_Frequency; 800586c: 68fb ldr r3, [r7, #12] 800586e: 62fb str r3, [r7, #44] ; 0x2c break; 8005870: e01f b.n 80058b2 case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8005872: 4b21 ldr r3, [pc, #132] ; (80058f8 ) 8005874: 681b ldr r3, [r3, #0] 8005876: f003 0320 and.w r3, r3, #32 800587a: 2b00 cmp r3, #0 800587c: d009 beq.n 8005892 { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 800587e: 4b1e ldr r3, [pc, #120] ; (80058f8 ) 8005880: 681b ldr r3, [r3, #0] 8005882: 08db lsrs r3, r3, #3 8005884: f003 0303 and.w r3, r3, #3 8005888: 4a1d ldr r2, [pc, #116] ; (8005900 ) 800588a: fa22 f303 lsr.w r3, r2, r3 800588e: 62fb str r3, [r7, #44] ; 0x2c } else { pclk = (uint32_t) HSI_VALUE; } break; 8005890: e00f b.n 80058b2 pclk = (uint32_t) HSI_VALUE; 8005892: 4b1b ldr r3, [pc, #108] ; (8005900 ) 8005894: 62fb str r3, [r7, #44] ; 0x2c break; 8005896: e00c b.n 80058b2 case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 8005898: 4b1a ldr r3, [pc, #104] ; (8005904 ) 800589a: 62fb str r3, [r7, #44] ; 0x2c break; 800589c: e009 b.n 80058b2 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 800589e: f44f 4300 mov.w r3, #32768 ; 0x8000 80058a2: 62fb str r3, [r7, #44] ; 0x2c break; 80058a4: e005 b.n 80058b2 default: pclk = 0U; 80058a6: 2300 movs r3, #0 80058a8: 62fb str r3, [r7, #44] ; 0x2c ret = HAL_ERROR; 80058aa: 2301 movs r3, #1 80058ac: f887 3032 strb.w r3, [r7, #50] ; 0x32 break; 80058b0: bf00 nop } /* If proper clock source reported */ if (pclk != 0U) 80058b2: 6afb ldr r3, [r7, #44] ; 0x2c 80058b4: 2b00 cmp r3, #0 80058b6: f000 81e6 beq.w 8005c86 { /* Compute clock after Prescaler */ lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); 80058ba: 687b ldr r3, [r7, #4] 80058bc: 6a5b ldr r3, [r3, #36] ; 0x24 80058be: 4a12 ldr r2, [pc, #72] ; (8005908 ) 80058c0: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 80058c4: 461a mov r2, r3 80058c6: 6afb ldr r3, [r7, #44] ; 0x2c 80058c8: fbb3 f3f2 udiv r3, r3, r2 80058cc: 623b str r3, [r7, #32] /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 80058ce: 687b ldr r3, [r7, #4] 80058d0: 685a ldr r2, [r3, #4] 80058d2: 4613 mov r3, r2 80058d4: 005b lsls r3, r3, #1 80058d6: 4413 add r3, r2 80058d8: 6a3a ldr r2, [r7, #32] 80058da: 429a cmp r2, r3 80058dc: d305 bcc.n 80058ea (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) 80058de: 687b ldr r3, [r7, #4] 80058e0: 685b ldr r3, [r3, #4] 80058e2: 031b lsls r3, r3, #12 if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 80058e4: 6a3a ldr r2, [r7, #32] 80058e6: 429a cmp r2, r3 80058e8: d910 bls.n 800590c { ret = HAL_ERROR; 80058ea: 2301 movs r3, #1 80058ec: f887 3032 strb.w r3, [r7, #50] ; 0x32 80058f0: e1c9 b.n 8005c86 80058f2: bf00 nop 80058f4: 40011c00 .word 0x40011c00 80058f8: 58024400 .word 0x58024400 80058fc: 58000c00 .word 0x58000c00 8005900: 03d09000 .word 0x03d09000 8005904: 003d0900 .word 0x003d0900 8005908: 08007288 .word 0x08007288 } else { /* Check computed UsartDiv value is in allocated range (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 800590c: 6afb ldr r3, [r7, #44] ; 0x2c 800590e: 4618 mov r0, r3 8005910: f04f 0100 mov.w r1, #0 8005914: 687b ldr r3, [r7, #4] 8005916: 6a5b ldr r3, [r3, #36] ; 0x24 8005918: 4ac1 ldr r2, [pc, #772] ; (8005c20 ) 800591a: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 800591e: b29a uxth r2, r3 8005920: f04f 0300 mov.w r3, #0 8005924: f7fa fce2 bl 80002ec <__aeabi_uldivmod> 8005928: 4602 mov r2, r0 800592a: 460b mov r3, r1 800592c: 4610 mov r0, r2 800592e: 4619 mov r1, r3 8005930: f04f 0200 mov.w r2, #0 8005934: f04f 0300 mov.w r3, #0 8005938: 020b lsls r3, r1, #8 800593a: ea43 6310 orr.w r3, r3, r0, lsr #24 800593e: 0202 lsls r2, r0, #8 8005940: 6879 ldr r1, [r7, #4] 8005942: 6849 ldr r1, [r1, #4] 8005944: 0849 lsrs r1, r1, #1 8005946: 4608 mov r0, r1 8005948: f04f 0100 mov.w r1, #0 800594c: 1814 adds r4, r2, r0 800594e: eb43 0501 adc.w r5, r3, r1 8005952: 687b ldr r3, [r7, #4] 8005954: 685b ldr r3, [r3, #4] 8005956: 461a mov r2, r3 8005958: f04f 0300 mov.w r3, #0 800595c: 4620 mov r0, r4 800595e: 4629 mov r1, r5 8005960: f7fa fcc4 bl 80002ec <__aeabi_uldivmod> 8005964: 4602 mov r2, r0 8005966: 460b mov r3, r1 8005968: 4613 mov r3, r2 800596a: 62bb str r3, [r7, #40] ; 0x28 if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) 800596c: 6abb ldr r3, [r7, #40] ; 0x28 800596e: f5b3 7f40 cmp.w r3, #768 ; 0x300 8005972: d308 bcc.n 8005986 8005974: 6abb ldr r3, [r7, #40] ; 0x28 8005976: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 800597a: d204 bcs.n 8005986 { huart->Instance->BRR = usartdiv; 800597c: 687b ldr r3, [r7, #4] 800597e: 681b ldr r3, [r3, #0] 8005980: 6aba ldr r2, [r7, #40] ; 0x28 8005982: 60da str r2, [r3, #12] 8005984: e17f b.n 8005c86 } else { ret = HAL_ERROR; 8005986: 2301 movs r3, #1 8005988: f887 3032 strb.w r3, [r7, #50] ; 0x32 800598c: e17b b.n 8005c86 } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 800598e: 687b ldr r3, [r7, #4] 8005990: 69db ldr r3, [r3, #28] 8005992: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 8005996: f040 80bd bne.w 8005b14 { switch (clocksource) 800599a: f897 3033 ldrb.w r3, [r7, #51] ; 0x33 800599e: 2b20 cmp r3, #32 80059a0: dc48 bgt.n 8005a34 80059a2: 2b00 cmp r3, #0 80059a4: db7b blt.n 8005a9e 80059a6: 2b20 cmp r3, #32 80059a8: d879 bhi.n 8005a9e 80059aa: a201 add r2, pc, #4 ; (adr r2, 80059b0 ) 80059ac: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80059b0: 08005a3b .word 0x08005a3b 80059b4: 08005a43 .word 0x08005a43 80059b8: 08005a9f .word 0x08005a9f 80059bc: 08005a9f .word 0x08005a9f 80059c0: 08005a4b .word 0x08005a4b 80059c4: 08005a9f .word 0x08005a9f 80059c8: 08005a9f .word 0x08005a9f 80059cc: 08005a9f .word 0x08005a9f 80059d0: 08005a5b .word 0x08005a5b 80059d4: 08005a9f .word 0x08005a9f 80059d8: 08005a9f .word 0x08005a9f 80059dc: 08005a9f .word 0x08005a9f 80059e0: 08005a9f .word 0x08005a9f 80059e4: 08005a9f .word 0x08005a9f 80059e8: 08005a9f .word 0x08005a9f 80059ec: 08005a9f .word 0x08005a9f 80059f0: 08005a6b .word 0x08005a6b 80059f4: 08005a9f .word 0x08005a9f 80059f8: 08005a9f .word 0x08005a9f 80059fc: 08005a9f .word 0x08005a9f 8005a00: 08005a9f .word 0x08005a9f 8005a04: 08005a9f .word 0x08005a9f 8005a08: 08005a9f .word 0x08005a9f 8005a0c: 08005a9f .word 0x08005a9f 8005a10: 08005a9f .word 0x08005a9f 8005a14: 08005a9f .word 0x08005a9f 8005a18: 08005a9f .word 0x08005a9f 8005a1c: 08005a9f .word 0x08005a9f 8005a20: 08005a9f .word 0x08005a9f 8005a24: 08005a9f .word 0x08005a9f 8005a28: 08005a9f .word 0x08005a9f 8005a2c: 08005a9f .word 0x08005a9f 8005a30: 08005a91 .word 0x08005a91 8005a34: 2b40 cmp r3, #64 ; 0x40 8005a36: d02e beq.n 8005a96 8005a38: e031 b.n 8005a9e { case UART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8005a3a: f7fd fa81 bl 8002f40 8005a3e: 62f8 str r0, [r7, #44] ; 0x2c break; 8005a40: e033 b.n 8005aaa case UART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 8005a42: f7fd fa93 bl 8002f6c 8005a46: 62f8 str r0, [r7, #44] ; 0x2c break; 8005a48: e02f b.n 8005aaa case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8005a4a: f107 0314 add.w r3, r7, #20 8005a4e: 4618 mov r0, r3 8005a50: f7fe f9c4 bl 8003ddc pclk = pll2_clocks.PLL2_Q_Frequency; 8005a54: 69bb ldr r3, [r7, #24] 8005a56: 62fb str r3, [r7, #44] ; 0x2c break; 8005a58: e027 b.n 8005aaa case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8005a5a: f107 0308 add.w r3, r7, #8 8005a5e: 4618 mov r0, r3 8005a60: f7fe fb10 bl 8004084 pclk = pll3_clocks.PLL3_Q_Frequency; 8005a64: 68fb ldr r3, [r7, #12] 8005a66: 62fb str r3, [r7, #44] ; 0x2c break; 8005a68: e01f b.n 8005aaa case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8005a6a: 4b6e ldr r3, [pc, #440] ; (8005c24 ) 8005a6c: 681b ldr r3, [r3, #0] 8005a6e: f003 0320 and.w r3, r3, #32 8005a72: 2b00 cmp r3, #0 8005a74: d009 beq.n 8005a8a { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 8005a76: 4b6b ldr r3, [pc, #428] ; (8005c24 ) 8005a78: 681b ldr r3, [r3, #0] 8005a7a: 08db lsrs r3, r3, #3 8005a7c: f003 0303 and.w r3, r3, #3 8005a80: 4a69 ldr r2, [pc, #420] ; (8005c28 ) 8005a82: fa22 f303 lsr.w r3, r2, r3 8005a86: 62fb str r3, [r7, #44] ; 0x2c } else { pclk = (uint32_t) HSI_VALUE; } break; 8005a88: e00f b.n 8005aaa pclk = (uint32_t) HSI_VALUE; 8005a8a: 4b67 ldr r3, [pc, #412] ; (8005c28 ) 8005a8c: 62fb str r3, [r7, #44] ; 0x2c break; 8005a8e: e00c b.n 8005aaa case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 8005a90: 4b66 ldr r3, [pc, #408] ; (8005c2c ) 8005a92: 62fb str r3, [r7, #44] ; 0x2c break; 8005a94: e009 b.n 8005aaa case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8005a96: f44f 4300 mov.w r3, #32768 ; 0x8000 8005a9a: 62fb str r3, [r7, #44] ; 0x2c break; 8005a9c: e005 b.n 8005aaa default: pclk = 0U; 8005a9e: 2300 movs r3, #0 8005aa0: 62fb str r3, [r7, #44] ; 0x2c ret = HAL_ERROR; 8005aa2: 2301 movs r3, #1 8005aa4: f887 3032 strb.w r3, [r7, #50] ; 0x32 break; 8005aa8: bf00 nop } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) 8005aaa: 6afb ldr r3, [r7, #44] ; 0x2c 8005aac: 2b00 cmp r3, #0 8005aae: f000 80ea beq.w 8005c86 { usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 8005ab2: 687b ldr r3, [r7, #4] 8005ab4: 6a5b ldr r3, [r3, #36] ; 0x24 8005ab6: 4a5a ldr r2, [pc, #360] ; (8005c20 ) 8005ab8: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8005abc: 461a mov r2, r3 8005abe: 6afb ldr r3, [r7, #44] ; 0x2c 8005ac0: fbb3 f3f2 udiv r3, r3, r2 8005ac4: 005a lsls r2, r3, #1 8005ac6: 687b ldr r3, [r7, #4] 8005ac8: 685b ldr r3, [r3, #4] 8005aca: 085b lsrs r3, r3, #1 8005acc: 441a add r2, r3 8005ace: 687b ldr r3, [r7, #4] 8005ad0: 685b ldr r3, [r3, #4] 8005ad2: fbb2 f3f3 udiv r3, r2, r3 8005ad6: 62bb str r3, [r7, #40] ; 0x28 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8005ad8: 6abb ldr r3, [r7, #40] ; 0x28 8005ada: 2b0f cmp r3, #15 8005adc: d916 bls.n 8005b0c 8005ade: 6abb ldr r3, [r7, #40] ; 0x28 8005ae0: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8005ae4: d212 bcs.n 8005b0c { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); 8005ae6: 6abb ldr r3, [r7, #40] ; 0x28 8005ae8: b29b uxth r3, r3 8005aea: f023 030f bic.w r3, r3, #15 8005aee: 84fb strh r3, [r7, #38] ; 0x26 brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 8005af0: 6abb ldr r3, [r7, #40] ; 0x28 8005af2: 085b lsrs r3, r3, #1 8005af4: b29b uxth r3, r3 8005af6: f003 0307 and.w r3, r3, #7 8005afa: b29a uxth r2, r3 8005afc: 8cfb ldrh r3, [r7, #38] ; 0x26 8005afe: 4313 orrs r3, r2 8005b00: 84fb strh r3, [r7, #38] ; 0x26 huart->Instance->BRR = brrtemp; 8005b02: 687b ldr r3, [r7, #4] 8005b04: 681b ldr r3, [r3, #0] 8005b06: 8cfa ldrh r2, [r7, #38] ; 0x26 8005b08: 60da str r2, [r3, #12] 8005b0a: e0bc b.n 8005c86 } else { ret = HAL_ERROR; 8005b0c: 2301 movs r3, #1 8005b0e: f887 3032 strb.w r3, [r7, #50] ; 0x32 8005b12: e0b8 b.n 8005c86 } } } else { switch (clocksource) 8005b14: f897 3033 ldrb.w r3, [r7, #51] ; 0x33 8005b18: 2b20 cmp r3, #32 8005b1a: dc4b bgt.n 8005bb4 8005b1c: 2b00 cmp r3, #0 8005b1e: f2c0 8087 blt.w 8005c30 8005b22: 2b20 cmp r3, #32 8005b24: f200 8084 bhi.w 8005c30 8005b28: a201 add r2, pc, #4 ; (adr r2, 8005b30 ) 8005b2a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8005b2e: bf00 nop 8005b30: 08005bbb .word 0x08005bbb 8005b34: 08005bc3 .word 0x08005bc3 8005b38: 08005c31 .word 0x08005c31 8005b3c: 08005c31 .word 0x08005c31 8005b40: 08005bcb .word 0x08005bcb 8005b44: 08005c31 .word 0x08005c31 8005b48: 08005c31 .word 0x08005c31 8005b4c: 08005c31 .word 0x08005c31 8005b50: 08005bdb .word 0x08005bdb 8005b54: 08005c31 .word 0x08005c31 8005b58: 08005c31 .word 0x08005c31 8005b5c: 08005c31 .word 0x08005c31 8005b60: 08005c31 .word 0x08005c31 8005b64: 08005c31 .word 0x08005c31 8005b68: 08005c31 .word 0x08005c31 8005b6c: 08005c31 .word 0x08005c31 8005b70: 08005beb .word 0x08005beb 8005b74: 08005c31 .word 0x08005c31 8005b78: 08005c31 .word 0x08005c31 8005b7c: 08005c31 .word 0x08005c31 8005b80: 08005c31 .word 0x08005c31 8005b84: 08005c31 .word 0x08005c31 8005b88: 08005c31 .word 0x08005c31 8005b8c: 08005c31 .word 0x08005c31 8005b90: 08005c31 .word 0x08005c31 8005b94: 08005c31 .word 0x08005c31 8005b98: 08005c31 .word 0x08005c31 8005b9c: 08005c31 .word 0x08005c31 8005ba0: 08005c31 .word 0x08005c31 8005ba4: 08005c31 .word 0x08005c31 8005ba8: 08005c31 .word 0x08005c31 8005bac: 08005c31 .word 0x08005c31 8005bb0: 08005c11 .word 0x08005c11 8005bb4: 2b40 cmp r3, #64 ; 0x40 8005bb6: d02e beq.n 8005c16 8005bb8: e03a b.n 8005c30 { case UART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8005bba: f7fd f9c1 bl 8002f40 8005bbe: 62f8 str r0, [r7, #44] ; 0x2c break; 8005bc0: e03c b.n 8005c3c case UART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 8005bc2: f7fd f9d3 bl 8002f6c 8005bc6: 62f8 str r0, [r7, #44] ; 0x2c break; 8005bc8: e038 b.n 8005c3c case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8005bca: f107 0314 add.w r3, r7, #20 8005bce: 4618 mov r0, r3 8005bd0: f7fe f904 bl 8003ddc pclk = pll2_clocks.PLL2_Q_Frequency; 8005bd4: 69bb ldr r3, [r7, #24] 8005bd6: 62fb str r3, [r7, #44] ; 0x2c break; 8005bd8: e030 b.n 8005c3c case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8005bda: f107 0308 add.w r3, r7, #8 8005bde: 4618 mov r0, r3 8005be0: f7fe fa50 bl 8004084 pclk = pll3_clocks.PLL3_Q_Frequency; 8005be4: 68fb ldr r3, [r7, #12] 8005be6: 62fb str r3, [r7, #44] ; 0x2c break; 8005be8: e028 b.n 8005c3c case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8005bea: 4b0e ldr r3, [pc, #56] ; (8005c24 ) 8005bec: 681b ldr r3, [r3, #0] 8005bee: f003 0320 and.w r3, r3, #32 8005bf2: 2b00 cmp r3, #0 8005bf4: d009 beq.n 8005c0a { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 8005bf6: 4b0b ldr r3, [pc, #44] ; (8005c24 ) 8005bf8: 681b ldr r3, [r3, #0] 8005bfa: 08db lsrs r3, r3, #3 8005bfc: f003 0303 and.w r3, r3, #3 8005c00: 4a09 ldr r2, [pc, #36] ; (8005c28 ) 8005c02: fa22 f303 lsr.w r3, r2, r3 8005c06: 62fb str r3, [r7, #44] ; 0x2c } else { pclk = (uint32_t) HSI_VALUE; } break; 8005c08: e018 b.n 8005c3c pclk = (uint32_t) HSI_VALUE; 8005c0a: 4b07 ldr r3, [pc, #28] ; (8005c28 ) 8005c0c: 62fb str r3, [r7, #44] ; 0x2c break; 8005c0e: e015 b.n 8005c3c case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 8005c10: 4b06 ldr r3, [pc, #24] ; (8005c2c ) 8005c12: 62fb str r3, [r7, #44] ; 0x2c break; 8005c14: e012 b.n 8005c3c case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8005c16: f44f 4300 mov.w r3, #32768 ; 0x8000 8005c1a: 62fb str r3, [r7, #44] ; 0x2c break; 8005c1c: e00e b.n 8005c3c 8005c1e: bf00 nop 8005c20: 08007288 .word 0x08007288 8005c24: 58024400 .word 0x58024400 8005c28: 03d09000 .word 0x03d09000 8005c2c: 003d0900 .word 0x003d0900 default: pclk = 0U; 8005c30: 2300 movs r3, #0 8005c32: 62fb str r3, [r7, #44] ; 0x2c ret = HAL_ERROR; 8005c34: 2301 movs r3, #1 8005c36: f887 3032 strb.w r3, [r7, #50] ; 0x32 break; 8005c3a: bf00 nop } if (pclk != 0U) 8005c3c: 6afb ldr r3, [r7, #44] ; 0x2c 8005c3e: 2b00 cmp r3, #0 8005c40: d021 beq.n 8005c86 { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 8005c42: 687b ldr r3, [r7, #4] 8005c44: 6a5b ldr r3, [r3, #36] ; 0x24 8005c46: 4a1a ldr r2, [pc, #104] ; (8005cb0 ) 8005c48: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8005c4c: 461a mov r2, r3 8005c4e: 6afb ldr r3, [r7, #44] ; 0x2c 8005c50: fbb3 f2f2 udiv r2, r3, r2 8005c54: 687b ldr r3, [r7, #4] 8005c56: 685b ldr r3, [r3, #4] 8005c58: 085b lsrs r3, r3, #1 8005c5a: 441a add r2, r3 8005c5c: 687b ldr r3, [r7, #4] 8005c5e: 685b ldr r3, [r3, #4] 8005c60: fbb2 f3f3 udiv r3, r2, r3 8005c64: 62bb str r3, [r7, #40] ; 0x28 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8005c66: 6abb ldr r3, [r7, #40] ; 0x28 8005c68: 2b0f cmp r3, #15 8005c6a: d909 bls.n 8005c80 8005c6c: 6abb ldr r3, [r7, #40] ; 0x28 8005c6e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8005c72: d205 bcs.n 8005c80 { huart->Instance->BRR = (uint16_t)usartdiv; 8005c74: 6abb ldr r3, [r7, #40] ; 0x28 8005c76: b29a uxth r2, r3 8005c78: 687b ldr r3, [r7, #4] 8005c7a: 681b ldr r3, [r3, #0] 8005c7c: 60da str r2, [r3, #12] 8005c7e: e002 b.n 8005c86 } else { ret = HAL_ERROR; 8005c80: 2301 movs r3, #1 8005c82: f887 3032 strb.w r3, [r7, #50] ; 0x32 } } } /* Initialize the number of data to process during RX/TX ISR execution */ huart->NbTxDataToProcess = 1; 8005c86: 687b ldr r3, [r7, #4] 8005c88: 2201 movs r2, #1 8005c8a: f8a3 206a strh.w r2, [r3, #106] ; 0x6a huart->NbRxDataToProcess = 1; 8005c8e: 687b ldr r3, [r7, #4] 8005c90: 2201 movs r2, #1 8005c92: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 /* Clear ISR function pointers */ huart->RxISR = NULL; 8005c96: 687b ldr r3, [r7, #4] 8005c98: 2200 movs r2, #0 8005c9a: 671a str r2, [r3, #112] ; 0x70 huart->TxISR = NULL; 8005c9c: 687b ldr r3, [r7, #4] 8005c9e: 2200 movs r2, #0 8005ca0: 675a str r2, [r3, #116] ; 0x74 return ret; 8005ca2: f897 3032 ldrb.w r3, [r7, #50] ; 0x32 } 8005ca6: 4618 mov r0, r3 8005ca8: 3738 adds r7, #56 ; 0x38 8005caa: 46bd mov sp, r7 8005cac: bdb0 pop {r4, r5, r7, pc} 8005cae: bf00 nop 8005cb0: 08007288 .word 0x08007288 08005cb4 : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { 8005cb4: b480 push {r7} 8005cb6: b083 sub sp, #12 8005cb8: af00 add r7, sp, #0 8005cba: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) 8005cbc: 687b ldr r3, [r7, #4] 8005cbe: 6a9b ldr r3, [r3, #40] ; 0x28 8005cc0: f003 0301 and.w r3, r3, #1 8005cc4: 2b00 cmp r3, #0 8005cc6: d00a beq.n 8005cde { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); 8005cc8: 687b ldr r3, [r7, #4] 8005cca: 681b ldr r3, [r3, #0] 8005ccc: 685b ldr r3, [r3, #4] 8005cce: f423 3100 bic.w r1, r3, #131072 ; 0x20000 8005cd2: 687b ldr r3, [r7, #4] 8005cd4: 6ada ldr r2, [r3, #44] ; 0x2c 8005cd6: 687b ldr r3, [r7, #4] 8005cd8: 681b ldr r3, [r3, #0] 8005cda: 430a orrs r2, r1 8005cdc: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) 8005cde: 687b ldr r3, [r7, #4] 8005ce0: 6a9b ldr r3, [r3, #40] ; 0x28 8005ce2: f003 0302 and.w r3, r3, #2 8005ce6: 2b00 cmp r3, #0 8005ce8: d00a beq.n 8005d00 { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); 8005cea: 687b ldr r3, [r7, #4] 8005cec: 681b ldr r3, [r3, #0] 8005cee: 685b ldr r3, [r3, #4] 8005cf0: f423 3180 bic.w r1, r3, #65536 ; 0x10000 8005cf4: 687b ldr r3, [r7, #4] 8005cf6: 6b1a ldr r2, [r3, #48] ; 0x30 8005cf8: 687b ldr r3, [r7, #4] 8005cfa: 681b ldr r3, [r3, #0] 8005cfc: 430a orrs r2, r1 8005cfe: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) 8005d00: 687b ldr r3, [r7, #4] 8005d02: 6a9b ldr r3, [r3, #40] ; 0x28 8005d04: f003 0304 and.w r3, r3, #4 8005d08: 2b00 cmp r3, #0 8005d0a: d00a beq.n 8005d22 { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); 8005d0c: 687b ldr r3, [r7, #4] 8005d0e: 681b ldr r3, [r3, #0] 8005d10: 685b ldr r3, [r3, #4] 8005d12: f423 2180 bic.w r1, r3, #262144 ; 0x40000 8005d16: 687b ldr r3, [r7, #4] 8005d18: 6b5a ldr r2, [r3, #52] ; 0x34 8005d1a: 687b ldr r3, [r7, #4] 8005d1c: 681b ldr r3, [r3, #0] 8005d1e: 430a orrs r2, r1 8005d20: 605a str r2, [r3, #4] } /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) 8005d22: 687b ldr r3, [r7, #4] 8005d24: 6a9b ldr r3, [r3, #40] ; 0x28 8005d26: f003 0308 and.w r3, r3, #8 8005d2a: 2b00 cmp r3, #0 8005d2c: d00a beq.n 8005d44 { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); 8005d2e: 687b ldr r3, [r7, #4] 8005d30: 681b ldr r3, [r3, #0] 8005d32: 685b ldr r3, [r3, #4] 8005d34: f423 4100 bic.w r1, r3, #32768 ; 0x8000 8005d38: 687b ldr r3, [r7, #4] 8005d3a: 6b9a ldr r2, [r3, #56] ; 0x38 8005d3c: 687b ldr r3, [r7, #4] 8005d3e: 681b ldr r3, [r3, #0] 8005d40: 430a orrs r2, r1 8005d42: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) 8005d44: 687b ldr r3, [r7, #4] 8005d46: 6a9b ldr r3, [r3, #40] ; 0x28 8005d48: f003 0310 and.w r3, r3, #16 8005d4c: 2b00 cmp r3, #0 8005d4e: d00a beq.n 8005d66 { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); 8005d50: 687b ldr r3, [r7, #4] 8005d52: 681b ldr r3, [r3, #0] 8005d54: 689b ldr r3, [r3, #8] 8005d56: f423 5180 bic.w r1, r3, #4096 ; 0x1000 8005d5a: 687b ldr r3, [r7, #4] 8005d5c: 6bda ldr r2, [r3, #60] ; 0x3c 8005d5e: 687b ldr r3, [r7, #4] 8005d60: 681b ldr r3, [r3, #0] 8005d62: 430a orrs r2, r1 8005d64: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) 8005d66: 687b ldr r3, [r7, #4] 8005d68: 6a9b ldr r3, [r3, #40] ; 0x28 8005d6a: f003 0320 and.w r3, r3, #32 8005d6e: 2b00 cmp r3, #0 8005d70: d00a beq.n 8005d88 { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); 8005d72: 687b ldr r3, [r7, #4] 8005d74: 681b ldr r3, [r3, #0] 8005d76: 689b ldr r3, [r3, #8] 8005d78: f423 5100 bic.w r1, r3, #8192 ; 0x2000 8005d7c: 687b ldr r3, [r7, #4] 8005d7e: 6c1a ldr r2, [r3, #64] ; 0x40 8005d80: 687b ldr r3, [r7, #4] 8005d82: 681b ldr r3, [r3, #0] 8005d84: 430a orrs r2, r1 8005d86: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) 8005d88: 687b ldr r3, [r7, #4] 8005d8a: 6a9b ldr r3, [r3, #40] ; 0x28 8005d8c: f003 0340 and.w r3, r3, #64 ; 0x40 8005d90: 2b00 cmp r3, #0 8005d92: d01a beq.n 8005dca { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); 8005d94: 687b ldr r3, [r7, #4] 8005d96: 681b ldr r3, [r3, #0] 8005d98: 685b ldr r3, [r3, #4] 8005d9a: f423 1180 bic.w r1, r3, #1048576 ; 0x100000 8005d9e: 687b ldr r3, [r7, #4] 8005da0: 6c5a ldr r2, [r3, #68] ; 0x44 8005da2: 687b ldr r3, [r7, #4] 8005da4: 681b ldr r3, [r3, #0] 8005da6: 430a orrs r2, r1 8005da8: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) 8005daa: 687b ldr r3, [r7, #4] 8005dac: 6c5b ldr r3, [r3, #68] ; 0x44 8005dae: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 8005db2: d10a bne.n 8005dca { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); 8005db4: 687b ldr r3, [r7, #4] 8005db6: 681b ldr r3, [r3, #0] 8005db8: 685b ldr r3, [r3, #4] 8005dba: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000 8005dbe: 687b ldr r3, [r7, #4] 8005dc0: 6c9a ldr r2, [r3, #72] ; 0x48 8005dc2: 687b ldr r3, [r7, #4] 8005dc4: 681b ldr r3, [r3, #0] 8005dc6: 430a orrs r2, r1 8005dc8: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) 8005dca: 687b ldr r3, [r7, #4] 8005dcc: 6a9b ldr r3, [r3, #40] ; 0x28 8005dce: f003 0380 and.w r3, r3, #128 ; 0x80 8005dd2: 2b00 cmp r3, #0 8005dd4: d00a beq.n 8005dec { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); 8005dd6: 687b ldr r3, [r7, #4] 8005dd8: 681b ldr r3, [r3, #0] 8005dda: 685b ldr r3, [r3, #4] 8005ddc: f423 2100 bic.w r1, r3, #524288 ; 0x80000 8005de0: 687b ldr r3, [r7, #4] 8005de2: 6cda ldr r2, [r3, #76] ; 0x4c 8005de4: 687b ldr r3, [r7, #4] 8005de6: 681b ldr r3, [r3, #0] 8005de8: 430a orrs r2, r1 8005dea: 605a str r2, [r3, #4] } } 8005dec: bf00 nop 8005dee: 370c adds r7, #12 8005df0: 46bd mov sp, r7 8005df2: f85d 7b04 ldr.w r7, [sp], #4 8005df6: 4770 bx lr 08005df8 : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { 8005df8: b580 push {r7, lr} 8005dfa: b086 sub sp, #24 8005dfc: af02 add r7, sp, #8 8005dfe: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8005e00: 687b ldr r3, [r7, #4] 8005e02: 2200 movs r2, #0 8005e04: f8c3 208c str.w r2, [r3, #140] ; 0x8c /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8005e08: f7fb f870 bl 8000eec 8005e0c: 60f8 str r0, [r7, #12] /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) 8005e0e: 687b ldr r3, [r7, #4] 8005e10: 681b ldr r3, [r3, #0] 8005e12: 681b ldr r3, [r3, #0] 8005e14: f003 0308 and.w r3, r3, #8 8005e18: 2b08 cmp r3, #8 8005e1a: d10e bne.n 8005e3a { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8005e1c: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 8005e20: 9300 str r3, [sp, #0] 8005e22: 68fb ldr r3, [r7, #12] 8005e24: 2200 movs r2, #0 8005e26: f44f 1100 mov.w r1, #2097152 ; 0x200000 8005e2a: 6878 ldr r0, [r7, #4] 8005e2c: f000 f82f bl 8005e8e 8005e30: 4603 mov r3, r0 8005e32: 2b00 cmp r3, #0 8005e34: d001 beq.n 8005e3a { /* Timeout occurred */ return HAL_TIMEOUT; 8005e36: 2303 movs r3, #3 8005e38: e025 b.n 8005e86 } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) 8005e3a: 687b ldr r3, [r7, #4] 8005e3c: 681b ldr r3, [r3, #0] 8005e3e: 681b ldr r3, [r3, #0] 8005e40: f003 0304 and.w r3, r3, #4 8005e44: 2b04 cmp r3, #4 8005e46: d10e bne.n 8005e66 { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8005e48: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 8005e4c: 9300 str r3, [sp, #0] 8005e4e: 68fb ldr r3, [r7, #12] 8005e50: 2200 movs r2, #0 8005e52: f44f 0180 mov.w r1, #4194304 ; 0x400000 8005e56: 6878 ldr r0, [r7, #4] 8005e58: f000 f819 bl 8005e8e 8005e5c: 4603 mov r3, r0 8005e5e: 2b00 cmp r3, #0 8005e60: d001 beq.n 8005e66 { /* Timeout occurred */ return HAL_TIMEOUT; 8005e62: 2303 movs r3, #3 8005e64: e00f b.n 8005e86 } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; 8005e66: 687b ldr r3, [r7, #4] 8005e68: 2220 movs r2, #32 8005e6a: f8c3 2084 str.w r2, [r3, #132] ; 0x84 huart->RxState = HAL_UART_STATE_READY; 8005e6e: 687b ldr r3, [r7, #4] 8005e70: 2220 movs r2, #32 8005e72: f8c3 2088 str.w r2, [r3, #136] ; 0x88 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8005e76: 687b ldr r3, [r7, #4] 8005e78: 2200 movs r2, #0 8005e7a: 66da str r2, [r3, #108] ; 0x6c __HAL_UNLOCK(huart); 8005e7c: 687b ldr r3, [r7, #4] 8005e7e: 2200 movs r2, #0 8005e80: f883 2080 strb.w r2, [r3, #128] ; 0x80 return HAL_OK; 8005e84: 2300 movs r3, #0 } 8005e86: 4618 mov r0, r3 8005e88: 3710 adds r7, #16 8005e8a: 46bd mov sp, r7 8005e8c: bd80 pop {r7, pc} 08005e8e : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 8005e8e: b580 push {r7, lr} 8005e90: b09c sub sp, #112 ; 0x70 8005e92: af00 add r7, sp, #0 8005e94: 60f8 str r0, [r7, #12] 8005e96: 60b9 str r1, [r7, #8] 8005e98: 603b str r3, [r7, #0] 8005e9a: 4613 mov r3, r2 8005e9c: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8005e9e: e0a9 b.n 8005ff4 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8005ea0: 6fbb ldr r3, [r7, #120] ; 0x78 8005ea2: f1b3 3fff cmp.w r3, #4294967295 8005ea6: f000 80a5 beq.w 8005ff4 { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8005eaa: f7fb f81f bl 8000eec 8005eae: 4602 mov r2, r0 8005eb0: 683b ldr r3, [r7, #0] 8005eb2: 1ad3 subs r3, r2, r3 8005eb4: 6fba ldr r2, [r7, #120] ; 0x78 8005eb6: 429a cmp r2, r3 8005eb8: d302 bcc.n 8005ec0 8005eba: 6fbb ldr r3, [r7, #120] ; 0x78 8005ebc: 2b00 cmp r3, #0 8005ebe: d140 bne.n 8005f42 { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | 8005ec0: 68fb ldr r3, [r7, #12] 8005ec2: 681b ldr r3, [r3, #0] 8005ec4: 653b str r3, [r7, #80] ; 0x50 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005ec6: 6d3b ldr r3, [r7, #80] ; 0x50 8005ec8: e853 3f00 ldrex r3, [r3] 8005ecc: 64fb str r3, [r7, #76] ; 0x4c return(result); 8005ece: 6cfb ldr r3, [r7, #76] ; 0x4c 8005ed0: f423 73d0 bic.w r3, r3, #416 ; 0x1a0 8005ed4: 667b str r3, [r7, #100] ; 0x64 8005ed6: 68fb ldr r3, [r7, #12] 8005ed8: 681b ldr r3, [r3, #0] 8005eda: 461a mov r2, r3 8005edc: 6e7b ldr r3, [r7, #100] ; 0x64 8005ede: 65fb str r3, [r7, #92] ; 0x5c 8005ee0: 65ba str r2, [r7, #88] ; 0x58 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005ee2: 6db9 ldr r1, [r7, #88] ; 0x58 8005ee4: 6dfa ldr r2, [r7, #92] ; 0x5c 8005ee6: e841 2300 strex r3, r2, [r1] 8005eea: 657b str r3, [r7, #84] ; 0x54 return(result); 8005eec: 6d7b ldr r3, [r7, #84] ; 0x54 8005eee: 2b00 cmp r3, #0 8005ef0: d1e6 bne.n 8005ec0 USART_CR1_TXEIE_TXFNFIE)); ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8005ef2: 68fb ldr r3, [r7, #12] 8005ef4: 681b ldr r3, [r3, #0] 8005ef6: 3308 adds r3, #8 8005ef8: 63fb str r3, [r7, #60] ; 0x3c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005efa: 6bfb ldr r3, [r7, #60] ; 0x3c 8005efc: e853 3f00 ldrex r3, [r3] 8005f00: 63bb str r3, [r7, #56] ; 0x38 return(result); 8005f02: 6bbb ldr r3, [r7, #56] ; 0x38 8005f04: f023 0301 bic.w r3, r3, #1 8005f08: 663b str r3, [r7, #96] ; 0x60 8005f0a: 68fb ldr r3, [r7, #12] 8005f0c: 681b ldr r3, [r3, #0] 8005f0e: 3308 adds r3, #8 8005f10: 6e3a ldr r2, [r7, #96] ; 0x60 8005f12: 64ba str r2, [r7, #72] ; 0x48 8005f14: 647b str r3, [r7, #68] ; 0x44 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005f16: 6c79 ldr r1, [r7, #68] ; 0x44 8005f18: 6cba ldr r2, [r7, #72] ; 0x48 8005f1a: e841 2300 strex r3, r2, [r1] 8005f1e: 643b str r3, [r7, #64] ; 0x40 return(result); 8005f20: 6c3b ldr r3, [r7, #64] ; 0x40 8005f22: 2b00 cmp r3, #0 8005f24: d1e5 bne.n 8005ef2 huart->gState = HAL_UART_STATE_READY; 8005f26: 68fb ldr r3, [r7, #12] 8005f28: 2220 movs r2, #32 8005f2a: f8c3 2084 str.w r2, [r3, #132] ; 0x84 huart->RxState = HAL_UART_STATE_READY; 8005f2e: 68fb ldr r3, [r7, #12] 8005f30: 2220 movs r2, #32 8005f32: f8c3 2088 str.w r2, [r3, #136] ; 0x88 __HAL_UNLOCK(huart); 8005f36: 68fb ldr r3, [r7, #12] 8005f38: 2200 movs r2, #0 8005f3a: f883 2080 strb.w r2, [r3, #128] ; 0x80 return HAL_TIMEOUT; 8005f3e: 2303 movs r3, #3 8005f40: e069 b.n 8006016 } if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) 8005f42: 68fb ldr r3, [r7, #12] 8005f44: 681b ldr r3, [r3, #0] 8005f46: 681b ldr r3, [r3, #0] 8005f48: f003 0304 and.w r3, r3, #4 8005f4c: 2b00 cmp r3, #0 8005f4e: d051 beq.n 8005ff4 { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) 8005f50: 68fb ldr r3, [r7, #12] 8005f52: 681b ldr r3, [r3, #0] 8005f54: 69db ldr r3, [r3, #28] 8005f56: f403 6300 and.w r3, r3, #2048 ; 0x800 8005f5a: f5b3 6f00 cmp.w r3, #2048 ; 0x800 8005f5e: d149 bne.n 8005ff4 { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 8005f60: 68fb ldr r3, [r7, #12] 8005f62: 681b ldr r3, [r3, #0] 8005f64: f44f 6200 mov.w r2, #2048 ; 0x800 8005f68: 621a str r2, [r3, #32] /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | 8005f6a: 68fb ldr r3, [r7, #12] 8005f6c: 681b ldr r3, [r3, #0] 8005f6e: 62bb str r3, [r7, #40] ; 0x28 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005f70: 6abb ldr r3, [r7, #40] ; 0x28 8005f72: e853 3f00 ldrex r3, [r3] 8005f76: 627b str r3, [r7, #36] ; 0x24 return(result); 8005f78: 6a7b ldr r3, [r7, #36] ; 0x24 8005f7a: f423 73d0 bic.w r3, r3, #416 ; 0x1a0 8005f7e: 66fb str r3, [r7, #108] ; 0x6c 8005f80: 68fb ldr r3, [r7, #12] 8005f82: 681b ldr r3, [r3, #0] 8005f84: 461a mov r2, r3 8005f86: 6efb ldr r3, [r7, #108] ; 0x6c 8005f88: 637b str r3, [r7, #52] ; 0x34 8005f8a: 633a str r2, [r7, #48] ; 0x30 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005f8c: 6b39 ldr r1, [r7, #48] ; 0x30 8005f8e: 6b7a ldr r2, [r7, #52] ; 0x34 8005f90: e841 2300 strex r3, r2, [r1] 8005f94: 62fb str r3, [r7, #44] ; 0x2c return(result); 8005f96: 6afb ldr r3, [r7, #44] ; 0x2c 8005f98: 2b00 cmp r3, #0 8005f9a: d1e6 bne.n 8005f6a USART_CR1_TXEIE_TXFNFIE)); ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8005f9c: 68fb ldr r3, [r7, #12] 8005f9e: 681b ldr r3, [r3, #0] 8005fa0: 3308 adds r3, #8 8005fa2: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005fa4: 697b ldr r3, [r7, #20] 8005fa6: e853 3f00 ldrex r3, [r3] 8005faa: 613b str r3, [r7, #16] return(result); 8005fac: 693b ldr r3, [r7, #16] 8005fae: f023 0301 bic.w r3, r3, #1 8005fb2: 66bb str r3, [r7, #104] ; 0x68 8005fb4: 68fb ldr r3, [r7, #12] 8005fb6: 681b ldr r3, [r3, #0] 8005fb8: 3308 adds r3, #8 8005fba: 6eba ldr r2, [r7, #104] ; 0x68 8005fbc: 623a str r2, [r7, #32] 8005fbe: 61fb str r3, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005fc0: 69f9 ldr r1, [r7, #28] 8005fc2: 6a3a ldr r2, [r7, #32] 8005fc4: e841 2300 strex r3, r2, [r1] 8005fc8: 61bb str r3, [r7, #24] return(result); 8005fca: 69bb ldr r3, [r7, #24] 8005fcc: 2b00 cmp r3, #0 8005fce: d1e5 bne.n 8005f9c huart->gState = HAL_UART_STATE_READY; 8005fd0: 68fb ldr r3, [r7, #12] 8005fd2: 2220 movs r2, #32 8005fd4: f8c3 2084 str.w r2, [r3, #132] ; 0x84 huart->RxState = HAL_UART_STATE_READY; 8005fd8: 68fb ldr r3, [r7, #12] 8005fda: 2220 movs r2, #32 8005fdc: f8c3 2088 str.w r2, [r3, #136] ; 0x88 huart->ErrorCode = HAL_UART_ERROR_RTO; 8005fe0: 68fb ldr r3, [r7, #12] 8005fe2: 2220 movs r2, #32 8005fe4: f8c3 208c str.w r2, [r3, #140] ; 0x8c /* Process Unlocked */ __HAL_UNLOCK(huart); 8005fe8: 68fb ldr r3, [r7, #12] 8005fea: 2200 movs r2, #0 8005fec: f883 2080 strb.w r2, [r3, #128] ; 0x80 return HAL_TIMEOUT; 8005ff0: 2303 movs r3, #3 8005ff2: e010 b.n 8006016 while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8005ff4: 68fb ldr r3, [r7, #12] 8005ff6: 681b ldr r3, [r3, #0] 8005ff8: 69da ldr r2, [r3, #28] 8005ffa: 68bb ldr r3, [r7, #8] 8005ffc: 4013 ands r3, r2 8005ffe: 68ba ldr r2, [r7, #8] 8006000: 429a cmp r2, r3 8006002: bf0c ite eq 8006004: 2301 moveq r3, #1 8006006: 2300 movne r3, #0 8006008: b2db uxtb r3, r3 800600a: 461a mov r2, r3 800600c: 79fb ldrb r3, [r7, #7] 800600e: 429a cmp r2, r3 8006010: f43f af46 beq.w 8005ea0 } } } } return HAL_OK; 8006014: 2300 movs r3, #0 } 8006016: 4618 mov r0, r3 8006018: 3770 adds r7, #112 ; 0x70 800601a: 46bd mov sp, r7 800601c: bd80 pop {r7, pc} ... 08006020 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8006020: b480 push {r7} 8006022: b0a3 sub sp, #140 ; 0x8c 8006024: af00 add r7, sp, #0 8006026: 60f8 str r0, [r7, #12] 8006028: 60b9 str r1, [r7, #8] 800602a: 4613 mov r3, r2 800602c: 80fb strh r3, [r7, #6] huart->pRxBuffPtr = pData; 800602e: 68fb ldr r3, [r7, #12] 8006030: 68ba ldr r2, [r7, #8] 8006032: 659a str r2, [r3, #88] ; 0x58 huart->RxXferSize = Size; 8006034: 68fb ldr r3, [r7, #12] 8006036: 88fa ldrh r2, [r7, #6] 8006038: f8a3 205c strh.w r2, [r3, #92] ; 0x5c huart->RxXferCount = Size; 800603c: 68fb ldr r3, [r7, #12] 800603e: 88fa ldrh r2, [r7, #6] 8006040: f8a3 205e strh.w r2, [r3, #94] ; 0x5e huart->RxISR = NULL; 8006044: 68fb ldr r3, [r7, #12] 8006046: 2200 movs r2, #0 8006048: 671a str r2, [r3, #112] ; 0x70 /* Computation of UART mask to apply to RDR register */ UART_MASK_COMPUTATION(huart); 800604a: 68fb ldr r3, [r7, #12] 800604c: 689b ldr r3, [r3, #8] 800604e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8006052: d10e bne.n 8006072 8006054: 68fb ldr r3, [r7, #12] 8006056: 691b ldr r3, [r3, #16] 8006058: 2b00 cmp r3, #0 800605a: d105 bne.n 8006068 800605c: 68fb ldr r3, [r7, #12] 800605e: f240 12ff movw r2, #511 ; 0x1ff 8006062: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 8006066: e02d b.n 80060c4 8006068: 68fb ldr r3, [r7, #12] 800606a: 22ff movs r2, #255 ; 0xff 800606c: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 8006070: e028 b.n 80060c4 8006072: 68fb ldr r3, [r7, #12] 8006074: 689b ldr r3, [r3, #8] 8006076: 2b00 cmp r3, #0 8006078: d10d bne.n 8006096 800607a: 68fb ldr r3, [r7, #12] 800607c: 691b ldr r3, [r3, #16] 800607e: 2b00 cmp r3, #0 8006080: d104 bne.n 800608c 8006082: 68fb ldr r3, [r7, #12] 8006084: 22ff movs r2, #255 ; 0xff 8006086: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 800608a: e01b b.n 80060c4 800608c: 68fb ldr r3, [r7, #12] 800608e: 227f movs r2, #127 ; 0x7f 8006090: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 8006094: e016 b.n 80060c4 8006096: 68fb ldr r3, [r7, #12] 8006098: 689b ldr r3, [r3, #8] 800609a: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 800609e: d10d bne.n 80060bc 80060a0: 68fb ldr r3, [r7, #12] 80060a2: 691b ldr r3, [r3, #16] 80060a4: 2b00 cmp r3, #0 80060a6: d104 bne.n 80060b2 80060a8: 68fb ldr r3, [r7, #12] 80060aa: 227f movs r2, #127 ; 0x7f 80060ac: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 80060b0: e008 b.n 80060c4 80060b2: 68fb ldr r3, [r7, #12] 80060b4: 223f movs r2, #63 ; 0x3f 80060b6: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 80060ba: e003 b.n 80060c4 80060bc: 68fb ldr r3, [r7, #12] 80060be: 2200 movs r2, #0 80060c0: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 huart->ErrorCode = HAL_UART_ERROR_NONE; 80060c4: 68fb ldr r3, [r7, #12] 80060c6: 2200 movs r2, #0 80060c8: f8c3 208c str.w r2, [r3, #140] ; 0x8c huart->RxState = HAL_UART_STATE_BUSY_RX; 80060cc: 68fb ldr r3, [r7, #12] 80060ce: 2222 movs r2, #34 ; 0x22 80060d0: f8c3 2088 str.w r2, [r3, #136] ; 0x88 /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 80060d4: 68fb ldr r3, [r7, #12] 80060d6: 681b ldr r3, [r3, #0] 80060d8: 3308 adds r3, #8 80060da: 667b str r3, [r7, #100] ; 0x64 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80060dc: 6e7b ldr r3, [r7, #100] ; 0x64 80060de: e853 3f00 ldrex r3, [r3] 80060e2: 663b str r3, [r7, #96] ; 0x60 return(result); 80060e4: 6e3b ldr r3, [r7, #96] ; 0x60 80060e6: f043 0301 orr.w r3, r3, #1 80060ea: f8c7 3084 str.w r3, [r7, #132] ; 0x84 80060ee: 68fb ldr r3, [r7, #12] 80060f0: 681b ldr r3, [r3, #0] 80060f2: 3308 adds r3, #8 80060f4: f8d7 2084 ldr.w r2, [r7, #132] ; 0x84 80060f8: 673a str r2, [r7, #112] ; 0x70 80060fa: 66fb str r3, [r7, #108] ; 0x6c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80060fc: 6ef9 ldr r1, [r7, #108] ; 0x6c 80060fe: 6f3a ldr r2, [r7, #112] ; 0x70 8006100: e841 2300 strex r3, r2, [r1] 8006104: 66bb str r3, [r7, #104] ; 0x68 return(result); 8006106: 6ebb ldr r3, [r7, #104] ; 0x68 8006108: 2b00 cmp r3, #0 800610a: d1e3 bne.n 80060d4 /* Configure Rx interrupt processing */ if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) 800610c: 68fb ldr r3, [r7, #12] 800610e: 6e5b ldr r3, [r3, #100] ; 0x64 8006110: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8006114: d153 bne.n 80061be 8006116: 68fb ldr r3, [r7, #12] 8006118: f8b3 3068 ldrh.w r3, [r3, #104] ; 0x68 800611c: 88fa ldrh r2, [r7, #6] 800611e: 429a cmp r2, r3 8006120: d34d bcc.n 80061be { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8006122: 68fb ldr r3, [r7, #12] 8006124: 689b ldr r3, [r3, #8] 8006126: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 800612a: d107 bne.n 800613c 800612c: 68fb ldr r3, [r7, #12] 800612e: 691b ldr r3, [r3, #16] 8006130: 2b00 cmp r3, #0 8006132: d103 bne.n 800613c { huart->RxISR = UART_RxISR_16BIT_FIFOEN; 8006134: 68fb ldr r3, [r7, #12] 8006136: 4a4b ldr r2, [pc, #300] ; (8006264 ) 8006138: 671a str r2, [r3, #112] ; 0x70 800613a: e002 b.n 8006142 } else { huart->RxISR = UART_RxISR_8BIT_FIFOEN; 800613c: 68fb ldr r3, [r7, #12] 800613e: 4a4a ldr r2, [pc, #296] ; (8006268 ) 8006140: 671a str r2, [r3, #112] ; 0x70 } __HAL_UNLOCK(huart); 8006142: 68fb ldr r3, [r7, #12] 8006144: 2200 movs r2, #0 8006146: f883 2080 strb.w r2, [r3, #128] ; 0x80 /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) 800614a: 68fb ldr r3, [r7, #12] 800614c: 691b ldr r3, [r3, #16] 800614e: 2b00 cmp r3, #0 8006150: d01a beq.n 8006188 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8006152: 68fb ldr r3, [r7, #12] 8006154: 681b ldr r3, [r3, #0] 8006156: 653b str r3, [r7, #80] ; 0x50 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006158: 6d3b ldr r3, [r7, #80] ; 0x50 800615a: e853 3f00 ldrex r3, [r3] 800615e: 64fb str r3, [r7, #76] ; 0x4c return(result); 8006160: 6cfb ldr r3, [r7, #76] ; 0x4c 8006162: f443 7380 orr.w r3, r3, #256 ; 0x100 8006166: f8c7 3080 str.w r3, [r7, #128] ; 0x80 800616a: 68fb ldr r3, [r7, #12] 800616c: 681b ldr r3, [r3, #0] 800616e: 461a mov r2, r3 8006170: f8d7 3080 ldr.w r3, [r7, #128] ; 0x80 8006174: 65fb str r3, [r7, #92] ; 0x5c 8006176: 65ba str r2, [r7, #88] ; 0x58 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006178: 6db9 ldr r1, [r7, #88] ; 0x58 800617a: 6dfa ldr r2, [r7, #92] ; 0x5c 800617c: e841 2300 strex r3, r2, [r1] 8006180: 657b str r3, [r7, #84] ; 0x54 return(result); 8006182: 6d7b ldr r3, [r7, #84] ; 0x54 8006184: 2b00 cmp r3, #0 8006186: d1e4 bne.n 8006152 } ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 8006188: 68fb ldr r3, [r7, #12] 800618a: 681b ldr r3, [r3, #0] 800618c: 3308 adds r3, #8 800618e: 63fb str r3, [r7, #60] ; 0x3c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006190: 6bfb ldr r3, [r7, #60] ; 0x3c 8006192: e853 3f00 ldrex r3, [r3] 8006196: 63bb str r3, [r7, #56] ; 0x38 return(result); 8006198: 6bbb ldr r3, [r7, #56] ; 0x38 800619a: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 800619e: 67fb str r3, [r7, #124] ; 0x7c 80061a0: 68fb ldr r3, [r7, #12] 80061a2: 681b ldr r3, [r3, #0] 80061a4: 3308 adds r3, #8 80061a6: 6ffa ldr r2, [r7, #124] ; 0x7c 80061a8: 64ba str r2, [r7, #72] ; 0x48 80061aa: 647b str r3, [r7, #68] ; 0x44 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80061ac: 6c79 ldr r1, [r7, #68] ; 0x44 80061ae: 6cba ldr r2, [r7, #72] ; 0x48 80061b0: e841 2300 strex r3, r2, [r1] 80061b4: 643b str r3, [r7, #64] ; 0x40 return(result); 80061b6: 6c3b ldr r3, [r7, #64] ; 0x40 80061b8: 2b00 cmp r3, #0 80061ba: d1e5 bne.n 8006188 80061bc: e04a b.n 8006254 } else { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 80061be: 68fb ldr r3, [r7, #12] 80061c0: 689b ldr r3, [r3, #8] 80061c2: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 80061c6: d107 bne.n 80061d8 80061c8: 68fb ldr r3, [r7, #12] 80061ca: 691b ldr r3, [r3, #16] 80061cc: 2b00 cmp r3, #0 80061ce: d103 bne.n 80061d8 { huart->RxISR = UART_RxISR_16BIT; 80061d0: 68fb ldr r3, [r7, #12] 80061d2: 4a26 ldr r2, [pc, #152] ; (800626c ) 80061d4: 671a str r2, [r3, #112] ; 0x70 80061d6: e002 b.n 80061de } else { huart->RxISR = UART_RxISR_8BIT; 80061d8: 68fb ldr r3, [r7, #12] 80061da: 4a25 ldr r2, [pc, #148] ; (8006270 ) 80061dc: 671a str r2, [r3, #112] ; 0x70 } __HAL_UNLOCK(huart); 80061de: 68fb ldr r3, [r7, #12] 80061e0: 2200 movs r2, #0 80061e2: f883 2080 strb.w r2, [r3, #128] ; 0x80 /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) 80061e6: 68fb ldr r3, [r7, #12] 80061e8: 691b ldr r3, [r3, #16] 80061ea: 2b00 cmp r3, #0 80061ec: d019 beq.n 8006222 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); 80061ee: 68fb ldr r3, [r7, #12] 80061f0: 681b ldr r3, [r3, #0] 80061f2: 62bb str r3, [r7, #40] ; 0x28 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80061f4: 6abb ldr r3, [r7, #40] ; 0x28 80061f6: e853 3f00 ldrex r3, [r3] 80061fa: 627b str r3, [r7, #36] ; 0x24 return(result); 80061fc: 6a7b ldr r3, [r7, #36] ; 0x24 80061fe: f443 7390 orr.w r3, r3, #288 ; 0x120 8006202: 677b str r3, [r7, #116] ; 0x74 8006204: 68fb ldr r3, [r7, #12] 8006206: 681b ldr r3, [r3, #0] 8006208: 461a mov r2, r3 800620a: 6f7b ldr r3, [r7, #116] ; 0x74 800620c: 637b str r3, [r7, #52] ; 0x34 800620e: 633a str r2, [r7, #48] ; 0x30 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006210: 6b39 ldr r1, [r7, #48] ; 0x30 8006212: 6b7a ldr r2, [r7, #52] ; 0x34 8006214: e841 2300 strex r3, r2, [r1] 8006218: 62fb str r3, [r7, #44] ; 0x2c return(result); 800621a: 6afb ldr r3, [r7, #44] ; 0x2c 800621c: 2b00 cmp r3, #0 800621e: d1e6 bne.n 80061ee 8006220: e018 b.n 8006254 } else { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8006222: 68fb ldr r3, [r7, #12] 8006224: 681b ldr r3, [r3, #0] 8006226: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006228: 697b ldr r3, [r7, #20] 800622a: e853 3f00 ldrex r3, [r3] 800622e: 613b str r3, [r7, #16] return(result); 8006230: 693b ldr r3, [r7, #16] 8006232: f043 0320 orr.w r3, r3, #32 8006236: 67bb str r3, [r7, #120] ; 0x78 8006238: 68fb ldr r3, [r7, #12] 800623a: 681b ldr r3, [r3, #0] 800623c: 461a mov r2, r3 800623e: 6fbb ldr r3, [r7, #120] ; 0x78 8006240: 623b str r3, [r7, #32] 8006242: 61fa str r2, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006244: 69f9 ldr r1, [r7, #28] 8006246: 6a3a ldr r2, [r7, #32] 8006248: e841 2300 strex r3, r2, [r1] 800624c: 61bb str r3, [r7, #24] return(result); 800624e: 69bb ldr r3, [r7, #24] 8006250: 2b00 cmp r3, #0 8006252: d1e6 bne.n 8006222 } } return HAL_OK; 8006254: 2300 movs r3, #0 } 8006256: 4618 mov r0, r3 8006258: 378c adds r7, #140 ; 0x8c 800625a: 46bd mov sp, r7 800625c: f85d 7b04 ldr.w r7, [sp], #4 8006260: 4770 bx lr 8006262: bf00 nop 8006264: 08006cc1 .word 0x08006cc1 8006268: 080069c9 .word 0x080069c9 800626c: 08006867 .word 0x08006867 8006270: 08006707 .word 0x08006707 08006274 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8006274: b480 push {r7} 8006276: b095 sub sp, #84 ; 0x54 8006278: af00 add r7, sp, #0 800627a: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 800627c: 687b ldr r3, [r7, #4] 800627e: 681b ldr r3, [r3, #0] 8006280: 637b str r3, [r7, #52] ; 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006282: 6b7b ldr r3, [r7, #52] ; 0x34 8006284: e853 3f00 ldrex r3, [r3] 8006288: 633b str r3, [r7, #48] ; 0x30 return(result); 800628a: 6b3b ldr r3, [r7, #48] ; 0x30 800628c: f423 7390 bic.w r3, r3, #288 ; 0x120 8006290: 64fb str r3, [r7, #76] ; 0x4c 8006292: 687b ldr r3, [r7, #4] 8006294: 681b ldr r3, [r3, #0] 8006296: 461a mov r2, r3 8006298: 6cfb ldr r3, [r7, #76] ; 0x4c 800629a: 643b str r3, [r7, #64] ; 0x40 800629c: 63fa str r2, [r7, #60] ; 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800629e: 6bf9 ldr r1, [r7, #60] ; 0x3c 80062a0: 6c3a ldr r2, [r7, #64] ; 0x40 80062a2: e841 2300 strex r3, r2, [r1] 80062a6: 63bb str r3, [r7, #56] ; 0x38 return(result); 80062a8: 6bbb ldr r3, [r7, #56] ; 0x38 80062aa: 2b00 cmp r3, #0 80062ac: d1e6 bne.n 800627c ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 80062ae: 687b ldr r3, [r7, #4] 80062b0: 681b ldr r3, [r3, #0] 80062b2: 3308 adds r3, #8 80062b4: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80062b6: 6a3b ldr r3, [r7, #32] 80062b8: e853 3f00 ldrex r3, [r3] 80062bc: 61fb str r3, [r7, #28] return(result); 80062be: 69fa ldr r2, [r7, #28] 80062c0: 4b1e ldr r3, [pc, #120] ; (800633c ) 80062c2: 4013 ands r3, r2 80062c4: 64bb str r3, [r7, #72] ; 0x48 80062c6: 687b ldr r3, [r7, #4] 80062c8: 681b ldr r3, [r3, #0] 80062ca: 3308 adds r3, #8 80062cc: 6cba ldr r2, [r7, #72] ; 0x48 80062ce: 62fa str r2, [r7, #44] ; 0x2c 80062d0: 62bb str r3, [r7, #40] ; 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80062d2: 6ab9 ldr r1, [r7, #40] ; 0x28 80062d4: 6afa ldr r2, [r7, #44] ; 0x2c 80062d6: e841 2300 strex r3, r2, [r1] 80062da: 627b str r3, [r7, #36] ; 0x24 return(result); 80062dc: 6a7b ldr r3, [r7, #36] ; 0x24 80062de: 2b00 cmp r3, #0 80062e0: d1e5 bne.n 80062ae /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80062e2: 687b ldr r3, [r7, #4] 80062e4: 6edb ldr r3, [r3, #108] ; 0x6c 80062e6: 2b01 cmp r3, #1 80062e8: d118 bne.n 800631c { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80062ea: 687b ldr r3, [r7, #4] 80062ec: 681b ldr r3, [r3, #0] 80062ee: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80062f0: 68fb ldr r3, [r7, #12] 80062f2: e853 3f00 ldrex r3, [r3] 80062f6: 60bb str r3, [r7, #8] return(result); 80062f8: 68bb ldr r3, [r7, #8] 80062fa: f023 0310 bic.w r3, r3, #16 80062fe: 647b str r3, [r7, #68] ; 0x44 8006300: 687b ldr r3, [r7, #4] 8006302: 681b ldr r3, [r3, #0] 8006304: 461a mov r2, r3 8006306: 6c7b ldr r3, [r7, #68] ; 0x44 8006308: 61bb str r3, [r7, #24] 800630a: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800630c: 6979 ldr r1, [r7, #20] 800630e: 69ba ldr r2, [r7, #24] 8006310: e841 2300 strex r3, r2, [r1] 8006314: 613b str r3, [r7, #16] return(result); 8006316: 693b ldr r3, [r7, #16] 8006318: 2b00 cmp r3, #0 800631a: d1e6 bne.n 80062ea } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800631c: 687b ldr r3, [r7, #4] 800631e: 2220 movs r2, #32 8006320: f8c3 2088 str.w r2, [r3, #136] ; 0x88 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8006324: 687b ldr r3, [r7, #4] 8006326: 2200 movs r2, #0 8006328: 66da str r2, [r3, #108] ; 0x6c /* Reset RxIsr function pointer */ huart->RxISR = NULL; 800632a: 687b ldr r3, [r7, #4] 800632c: 2200 movs r2, #0 800632e: 671a str r2, [r3, #112] ; 0x70 } 8006330: bf00 nop 8006332: 3754 adds r7, #84 ; 0x54 8006334: 46bd mov sp, r7 8006336: f85d 7b04 ldr.w r7, [sp], #4 800633a: 4770 bx lr 800633c: effffffe .word 0xeffffffe 08006340 : * (To be called at end of DMA Abort procedure following error occurrence). * @param hdma DMA handle. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 8006340: b580 push {r7, lr} 8006342: b084 sub sp, #16 8006344: af00 add r7, sp, #0 8006346: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); 8006348: 687b ldr r3, [r7, #4] 800634a: 6b9b ldr r3, [r3, #56] ; 0x38 800634c: 60fb str r3, [r7, #12] huart->RxXferCount = 0U; 800634e: 68fb ldr r3, [r7, #12] 8006350: 2200 movs r2, #0 8006352: f8a3 205e strh.w r2, [r3, #94] ; 0x5e huart->TxXferCount = 0U; 8006356: 68fb ldr r3, [r7, #12] 8006358: 2200 movs r2, #0 800635a: f8a3 2056 strh.w r2, [r3, #86] ; 0x56 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 800635e: 68f8 ldr r0, [r7, #12] 8006360: f7fe fe34 bl 8004fcc #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8006364: bf00 nop 8006366: 3710 adds r7, #16 8006368: 46bd mov sp, r7 800636a: bd80 pop {r7, pc} 0800636c : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) { 800636c: b480 push {r7} 800636e: b08f sub sp, #60 ; 0x3c 8006370: af00 add r7, sp, #0 8006372: 6078 str r0, [r7, #4] /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8006374: 687b ldr r3, [r7, #4] 8006376: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 800637a: 2b21 cmp r3, #33 ; 0x21 800637c: d14c bne.n 8006418 { if (huart->TxXferCount == 0U) 800637e: 687b ldr r3, [r7, #4] 8006380: f8b3 3056 ldrh.w r3, [r3, #86] ; 0x56 8006384: b29b uxth r3, r3 8006386: 2b00 cmp r3, #0 8006388: d132 bne.n 80063f0 { /* Disable the UART Transmit Data Register Empty Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 800638a: 687b ldr r3, [r7, #4] 800638c: 681b ldr r3, [r3, #0] 800638e: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006390: 6a3b ldr r3, [r7, #32] 8006392: e853 3f00 ldrex r3, [r3] 8006396: 61fb str r3, [r7, #28] return(result); 8006398: 69fb ldr r3, [r7, #28] 800639a: f023 0380 bic.w r3, r3, #128 ; 0x80 800639e: 637b str r3, [r7, #52] ; 0x34 80063a0: 687b ldr r3, [r7, #4] 80063a2: 681b ldr r3, [r3, #0] 80063a4: 461a mov r2, r3 80063a6: 6b7b ldr r3, [r7, #52] ; 0x34 80063a8: 62fb str r3, [r7, #44] ; 0x2c 80063aa: 62ba str r2, [r7, #40] ; 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80063ac: 6ab9 ldr r1, [r7, #40] ; 0x28 80063ae: 6afa ldr r2, [r7, #44] ; 0x2c 80063b0: e841 2300 strex r3, r2, [r1] 80063b4: 627b str r3, [r7, #36] ; 0x24 return(result); 80063b6: 6a7b ldr r3, [r7, #36] ; 0x24 80063b8: 2b00 cmp r3, #0 80063ba: d1e6 bne.n 800638a /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 80063bc: 687b ldr r3, [r7, #4] 80063be: 681b ldr r3, [r3, #0] 80063c0: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80063c2: 68fb ldr r3, [r7, #12] 80063c4: e853 3f00 ldrex r3, [r3] 80063c8: 60bb str r3, [r7, #8] return(result); 80063ca: 68bb ldr r3, [r7, #8] 80063cc: f043 0340 orr.w r3, r3, #64 ; 0x40 80063d0: 633b str r3, [r7, #48] ; 0x30 80063d2: 687b ldr r3, [r7, #4] 80063d4: 681b ldr r3, [r3, #0] 80063d6: 461a mov r2, r3 80063d8: 6b3b ldr r3, [r7, #48] ; 0x30 80063da: 61bb str r3, [r7, #24] 80063dc: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80063de: 6979 ldr r1, [r7, #20] 80063e0: 69ba ldr r2, [r7, #24] 80063e2: e841 2300 strex r3, r2, [r1] 80063e6: 613b str r3, [r7, #16] return(result); 80063e8: 693b ldr r3, [r7, #16] 80063ea: 2b00 cmp r3, #0 80063ec: d1e6 bne.n 80063bc huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); huart->pTxBuffPtr++; huart->TxXferCount--; } } } 80063ee: e013 b.n 8006418 huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); 80063f0: 687b ldr r3, [r7, #4] 80063f2: 6d1b ldr r3, [r3, #80] ; 0x50 80063f4: 781a ldrb r2, [r3, #0] 80063f6: 687b ldr r3, [r7, #4] 80063f8: 681b ldr r3, [r3, #0] 80063fa: 629a str r2, [r3, #40] ; 0x28 huart->pTxBuffPtr++; 80063fc: 687b ldr r3, [r7, #4] 80063fe: 6d1b ldr r3, [r3, #80] ; 0x50 8006400: 1c5a adds r2, r3, #1 8006402: 687b ldr r3, [r7, #4] 8006404: 651a str r2, [r3, #80] ; 0x50 huart->TxXferCount--; 8006406: 687b ldr r3, [r7, #4] 8006408: f8b3 3056 ldrh.w r3, [r3, #86] ; 0x56 800640c: b29b uxth r3, r3 800640e: 3b01 subs r3, #1 8006410: b29a uxth r2, r3 8006412: 687b ldr r3, [r7, #4] 8006414: f8a3 2056 strh.w r2, [r3, #86] ; 0x56 } 8006418: bf00 nop 800641a: 373c adds r7, #60 ; 0x3c 800641c: 46bd mov sp, r7 800641e: f85d 7b04 ldr.w r7, [sp], #4 8006422: 4770 bx lr 08006424 : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) { 8006424: b480 push {r7} 8006426: b091 sub sp, #68 ; 0x44 8006428: af00 add r7, sp, #0 800642a: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 800642c: 687b ldr r3, [r7, #4] 800642e: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 8006432: 2b21 cmp r3, #33 ; 0x21 8006434: d151 bne.n 80064da { if (huart->TxXferCount == 0U) 8006436: 687b ldr r3, [r7, #4] 8006438: f8b3 3056 ldrh.w r3, [r3, #86] ; 0x56 800643c: b29b uxth r3, r3 800643e: 2b00 cmp r3, #0 8006440: d132 bne.n 80064a8 { /* Disable the UART Transmit Data Register Empty Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 8006442: 687b ldr r3, [r7, #4] 8006444: 681b ldr r3, [r3, #0] 8006446: 627b str r3, [r7, #36] ; 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006448: 6a7b ldr r3, [r7, #36] ; 0x24 800644a: e853 3f00 ldrex r3, [r3] 800644e: 623b str r3, [r7, #32] return(result); 8006450: 6a3b ldr r3, [r7, #32] 8006452: f023 0380 bic.w r3, r3, #128 ; 0x80 8006456: 63bb str r3, [r7, #56] ; 0x38 8006458: 687b ldr r3, [r7, #4] 800645a: 681b ldr r3, [r3, #0] 800645c: 461a mov r2, r3 800645e: 6bbb ldr r3, [r7, #56] ; 0x38 8006460: 633b str r3, [r7, #48] ; 0x30 8006462: 62fa str r2, [r7, #44] ; 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006464: 6af9 ldr r1, [r7, #44] ; 0x2c 8006466: 6b3a ldr r2, [r7, #48] ; 0x30 8006468: e841 2300 strex r3, r2, [r1] 800646c: 62bb str r3, [r7, #40] ; 0x28 return(result); 800646e: 6abb ldr r3, [r7, #40] ; 0x28 8006470: 2b00 cmp r3, #0 8006472: d1e6 bne.n 8006442 /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8006474: 687b ldr r3, [r7, #4] 8006476: 681b ldr r3, [r3, #0] 8006478: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800647a: 693b ldr r3, [r7, #16] 800647c: e853 3f00 ldrex r3, [r3] 8006480: 60fb str r3, [r7, #12] return(result); 8006482: 68fb ldr r3, [r7, #12] 8006484: f043 0340 orr.w r3, r3, #64 ; 0x40 8006488: 637b str r3, [r7, #52] ; 0x34 800648a: 687b ldr r3, [r7, #4] 800648c: 681b ldr r3, [r3, #0] 800648e: 461a mov r2, r3 8006490: 6b7b ldr r3, [r7, #52] ; 0x34 8006492: 61fb str r3, [r7, #28] 8006494: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006496: 69b9 ldr r1, [r7, #24] 8006498: 69fa ldr r2, [r7, #28] 800649a: e841 2300 strex r3, r2, [r1] 800649e: 617b str r3, [r7, #20] return(result); 80064a0: 697b ldr r3, [r7, #20] 80064a2: 2b00 cmp r3, #0 80064a4: d1e6 bne.n 8006474 huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); huart->pTxBuffPtr += 2U; huart->TxXferCount--; } } } 80064a6: e018 b.n 80064da tmp = (const uint16_t *) huart->pTxBuffPtr; 80064a8: 687b ldr r3, [r7, #4] 80064aa: 6d1b ldr r3, [r3, #80] ; 0x50 80064ac: 63fb str r3, [r7, #60] ; 0x3c huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); 80064ae: 6bfb ldr r3, [r7, #60] ; 0x3c 80064b0: 881b ldrh r3, [r3, #0] 80064b2: 461a mov r2, r3 80064b4: 687b ldr r3, [r7, #4] 80064b6: 681b ldr r3, [r3, #0] 80064b8: f3c2 0208 ubfx r2, r2, #0, #9 80064bc: 629a str r2, [r3, #40] ; 0x28 huart->pTxBuffPtr += 2U; 80064be: 687b ldr r3, [r7, #4] 80064c0: 6d1b ldr r3, [r3, #80] ; 0x50 80064c2: 1c9a adds r2, r3, #2 80064c4: 687b ldr r3, [r7, #4] 80064c6: 651a str r2, [r3, #80] ; 0x50 huart->TxXferCount--; 80064c8: 687b ldr r3, [r7, #4] 80064ca: f8b3 3056 ldrh.w r3, [r3, #86] ; 0x56 80064ce: b29b uxth r3, r3 80064d0: 3b01 subs r3, #1 80064d2: b29a uxth r2, r3 80064d4: 687b ldr r3, [r7, #4] 80064d6: f8a3 2056 strh.w r2, [r3, #86] ; 0x56 } 80064da: bf00 nop 80064dc: 3744 adds r7, #68 ; 0x44 80064de: 46bd mov sp, r7 80064e0: f85d 7b04 ldr.w r7, [sp], #4 80064e4: 4770 bx lr 080064e6 : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { 80064e6: b480 push {r7} 80064e8: b091 sub sp, #68 ; 0x44 80064ea: af00 add r7, sp, #0 80064ec: 6078 str r0, [r7, #4] uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 80064ee: 687b ldr r3, [r7, #4] 80064f0: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 80064f4: 2b21 cmp r3, #33 ; 0x21 80064f6: d160 bne.n 80065ba { for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 80064f8: 687b ldr r3, [r7, #4] 80064fa: f8b3 306a ldrh.w r3, [r3, #106] ; 0x6a 80064fe: 87fb strh r3, [r7, #62] ; 0x3e 8006500: e057 b.n 80065b2 { if (huart->TxXferCount == 0U) 8006502: 687b ldr r3, [r7, #4] 8006504: f8b3 3056 ldrh.w r3, [r3, #86] ; 0x56 8006508: b29b uxth r3, r3 800650a: 2b00 cmp r3, #0 800650c: d133 bne.n 8006576 { /* Disable the TX FIFO threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 800650e: 687b ldr r3, [r7, #4] 8006510: 681b ldr r3, [r3, #0] 8006512: 3308 adds r3, #8 8006514: 627b str r3, [r7, #36] ; 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006516: 6a7b ldr r3, [r7, #36] ; 0x24 8006518: e853 3f00 ldrex r3, [r3] 800651c: 623b str r3, [r7, #32] return(result); 800651e: 6a3b ldr r3, [r7, #32] 8006520: f423 0300 bic.w r3, r3, #8388608 ; 0x800000 8006524: 63bb str r3, [r7, #56] ; 0x38 8006526: 687b ldr r3, [r7, #4] 8006528: 681b ldr r3, [r3, #0] 800652a: 3308 adds r3, #8 800652c: 6bba ldr r2, [r7, #56] ; 0x38 800652e: 633a str r2, [r7, #48] ; 0x30 8006530: 62fb str r3, [r7, #44] ; 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006532: 6af9 ldr r1, [r7, #44] ; 0x2c 8006534: 6b3a ldr r2, [r7, #48] ; 0x30 8006536: e841 2300 strex r3, r2, [r1] 800653a: 62bb str r3, [r7, #40] ; 0x28 return(result); 800653c: 6abb ldr r3, [r7, #40] ; 0x28 800653e: 2b00 cmp r3, #0 8006540: d1e5 bne.n 800650e /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8006542: 687b ldr r3, [r7, #4] 8006544: 681b ldr r3, [r3, #0] 8006546: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006548: 693b ldr r3, [r7, #16] 800654a: e853 3f00 ldrex r3, [r3] 800654e: 60fb str r3, [r7, #12] return(result); 8006550: 68fb ldr r3, [r7, #12] 8006552: f043 0340 orr.w r3, r3, #64 ; 0x40 8006556: 637b str r3, [r7, #52] ; 0x34 8006558: 687b ldr r3, [r7, #4] 800655a: 681b ldr r3, [r3, #0] 800655c: 461a mov r2, r3 800655e: 6b7b ldr r3, [r7, #52] ; 0x34 8006560: 61fb str r3, [r7, #28] 8006562: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006564: 69b9 ldr r1, [r7, #24] 8006566: 69fa ldr r2, [r7, #28] 8006568: e841 2300 strex r3, r2, [r1] 800656c: 617b str r3, [r7, #20] return(result); 800656e: 697b ldr r3, [r7, #20] 8006570: 2b00 cmp r3, #0 8006572: d1e6 bne.n 8006542 break; /* force exit loop */ 8006574: e021 b.n 80065ba } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) 8006576: 687b ldr r3, [r7, #4] 8006578: 681b ldr r3, [r3, #0] 800657a: 69db ldr r3, [r3, #28] 800657c: f003 0380 and.w r3, r3, #128 ; 0x80 8006580: 2b00 cmp r3, #0 8006582: d013 beq.n 80065ac { huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); 8006584: 687b ldr r3, [r7, #4] 8006586: 6d1b ldr r3, [r3, #80] ; 0x50 8006588: 781a ldrb r2, [r3, #0] 800658a: 687b ldr r3, [r7, #4] 800658c: 681b ldr r3, [r3, #0] 800658e: 629a str r2, [r3, #40] ; 0x28 huart->pTxBuffPtr++; 8006590: 687b ldr r3, [r7, #4] 8006592: 6d1b ldr r3, [r3, #80] ; 0x50 8006594: 1c5a adds r2, r3, #1 8006596: 687b ldr r3, [r7, #4] 8006598: 651a str r2, [r3, #80] ; 0x50 huart->TxXferCount--; 800659a: 687b ldr r3, [r7, #4] 800659c: f8b3 3056 ldrh.w r3, [r3, #86] ; 0x56 80065a0: b29b uxth r3, r3 80065a2: 3b01 subs r3, #1 80065a4: b29a uxth r2, r3 80065a6: 687b ldr r3, [r7, #4] 80065a8: f8a3 2056 strh.w r2, [r3, #86] ; 0x56 for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 80065ac: 8ffb ldrh r3, [r7, #62] ; 0x3e 80065ae: 3b01 subs r3, #1 80065b0: 87fb strh r3, [r7, #62] ; 0x3e 80065b2: 8ffb ldrh r3, [r7, #62] ; 0x3e 80065b4: 2b00 cmp r3, #0 80065b6: d1a4 bne.n 8006502 { /* Nothing to do */ } } } } 80065b8: e7ff b.n 80065ba 80065ba: bf00 nop 80065bc: 3744 adds r7, #68 ; 0x44 80065be: 46bd mov sp, r7 80065c0: f85d 7b04 ldr.w r7, [sp], #4 80065c4: 4770 bx lr 080065c6 : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { 80065c6: b480 push {r7} 80065c8: b091 sub sp, #68 ; 0x44 80065ca: af00 add r7, sp, #0 80065cc: 6078 str r0, [r7, #4] const uint16_t *tmp; uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 80065ce: 687b ldr r3, [r7, #4] 80065d0: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 80065d4: 2b21 cmp r3, #33 ; 0x21 80065d6: d165 bne.n 80066a4 { for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 80065d8: 687b ldr r3, [r7, #4] 80065da: f8b3 306a ldrh.w r3, [r3, #106] ; 0x6a 80065de: 87fb strh r3, [r7, #62] ; 0x3e 80065e0: e05c b.n 800669c { if (huart->TxXferCount == 0U) 80065e2: 687b ldr r3, [r7, #4] 80065e4: f8b3 3056 ldrh.w r3, [r3, #86] ; 0x56 80065e8: b29b uxth r3, r3 80065ea: 2b00 cmp r3, #0 80065ec: d133 bne.n 8006656 { /* Disable the TX FIFO threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 80065ee: 687b ldr r3, [r7, #4] 80065f0: 681b ldr r3, [r3, #0] 80065f2: 3308 adds r3, #8 80065f4: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80065f6: 6a3b ldr r3, [r7, #32] 80065f8: e853 3f00 ldrex r3, [r3] 80065fc: 61fb str r3, [r7, #28] return(result); 80065fe: 69fb ldr r3, [r7, #28] 8006600: f423 0300 bic.w r3, r3, #8388608 ; 0x800000 8006604: 637b str r3, [r7, #52] ; 0x34 8006606: 687b ldr r3, [r7, #4] 8006608: 681b ldr r3, [r3, #0] 800660a: 3308 adds r3, #8 800660c: 6b7a ldr r2, [r7, #52] ; 0x34 800660e: 62fa str r2, [r7, #44] ; 0x2c 8006610: 62bb str r3, [r7, #40] ; 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006612: 6ab9 ldr r1, [r7, #40] ; 0x28 8006614: 6afa ldr r2, [r7, #44] ; 0x2c 8006616: e841 2300 strex r3, r2, [r1] 800661a: 627b str r3, [r7, #36] ; 0x24 return(result); 800661c: 6a7b ldr r3, [r7, #36] ; 0x24 800661e: 2b00 cmp r3, #0 8006620: d1e5 bne.n 80065ee /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8006622: 687b ldr r3, [r7, #4] 8006624: 681b ldr r3, [r3, #0] 8006626: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006628: 68fb ldr r3, [r7, #12] 800662a: e853 3f00 ldrex r3, [r3] 800662e: 60bb str r3, [r7, #8] return(result); 8006630: 68bb ldr r3, [r7, #8] 8006632: f043 0340 orr.w r3, r3, #64 ; 0x40 8006636: 633b str r3, [r7, #48] ; 0x30 8006638: 687b ldr r3, [r7, #4] 800663a: 681b ldr r3, [r3, #0] 800663c: 461a mov r2, r3 800663e: 6b3b ldr r3, [r7, #48] ; 0x30 8006640: 61bb str r3, [r7, #24] 8006642: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006644: 6979 ldr r1, [r7, #20] 8006646: 69ba ldr r2, [r7, #24] 8006648: e841 2300 strex r3, r2, [r1] 800664c: 613b str r3, [r7, #16] return(result); 800664e: 693b ldr r3, [r7, #16] 8006650: 2b00 cmp r3, #0 8006652: d1e6 bne.n 8006622 break; /* force exit loop */ 8006654: e026 b.n 80066a4 } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) 8006656: 687b ldr r3, [r7, #4] 8006658: 681b ldr r3, [r3, #0] 800665a: 69db ldr r3, [r3, #28] 800665c: f003 0380 and.w r3, r3, #128 ; 0x80 8006660: 2b00 cmp r3, #0 8006662: d018 beq.n 8006696 { tmp = (const uint16_t *) huart->pTxBuffPtr; 8006664: 687b ldr r3, [r7, #4] 8006666: 6d1b ldr r3, [r3, #80] ; 0x50 8006668: 63bb str r3, [r7, #56] ; 0x38 huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); 800666a: 6bbb ldr r3, [r7, #56] ; 0x38 800666c: 881b ldrh r3, [r3, #0] 800666e: 461a mov r2, r3 8006670: 687b ldr r3, [r7, #4] 8006672: 681b ldr r3, [r3, #0] 8006674: f3c2 0208 ubfx r2, r2, #0, #9 8006678: 629a str r2, [r3, #40] ; 0x28 huart->pTxBuffPtr += 2U; 800667a: 687b ldr r3, [r7, #4] 800667c: 6d1b ldr r3, [r3, #80] ; 0x50 800667e: 1c9a adds r2, r3, #2 8006680: 687b ldr r3, [r7, #4] 8006682: 651a str r2, [r3, #80] ; 0x50 huart->TxXferCount--; 8006684: 687b ldr r3, [r7, #4] 8006686: f8b3 3056 ldrh.w r3, [r3, #86] ; 0x56 800668a: b29b uxth r3, r3 800668c: 3b01 subs r3, #1 800668e: b29a uxth r2, r3 8006690: 687b ldr r3, [r7, #4] 8006692: f8a3 2056 strh.w r2, [r3, #86] ; 0x56 for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 8006696: 8ffb ldrh r3, [r7, #62] ; 0x3e 8006698: 3b01 subs r3, #1 800669a: 87fb strh r3, [r7, #62] ; 0x3e 800669c: 8ffb ldrh r3, [r7, #62] ; 0x3e 800669e: 2b00 cmp r3, #0 80066a0: d19f bne.n 80065e2 { /* Nothing to do */ } } } } 80066a2: e7ff b.n 80066a4 80066a4: bf00 nop 80066a6: 3744 adds r7, #68 ; 0x44 80066a8: 46bd mov sp, r7 80066aa: f85d 7b04 ldr.w r7, [sp], #4 80066ae: 4770 bx lr 080066b0 : * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 80066b0: b580 push {r7, lr} 80066b2: b088 sub sp, #32 80066b4: af00 add r7, sp, #0 80066b6: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); 80066b8: 687b ldr r3, [r7, #4] 80066ba: 681b ldr r3, [r3, #0] 80066bc: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80066be: 68fb ldr r3, [r7, #12] 80066c0: e853 3f00 ldrex r3, [r3] 80066c4: 60bb str r3, [r7, #8] return(result); 80066c6: 68bb ldr r3, [r7, #8] 80066c8: f023 0340 bic.w r3, r3, #64 ; 0x40 80066cc: 61fb str r3, [r7, #28] 80066ce: 687b ldr r3, [r7, #4] 80066d0: 681b ldr r3, [r3, #0] 80066d2: 461a mov r2, r3 80066d4: 69fb ldr r3, [r7, #28] 80066d6: 61bb str r3, [r7, #24] 80066d8: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80066da: 6979 ldr r1, [r7, #20] 80066dc: 69ba ldr r2, [r7, #24] 80066de: e841 2300 strex r3, r2, [r1] 80066e2: 613b str r3, [r7, #16] return(result); 80066e4: 693b ldr r3, [r7, #16] 80066e6: 2b00 cmp r3, #0 80066e8: d1e6 bne.n 80066b8 /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 80066ea: 687b ldr r3, [r7, #4] 80066ec: 2220 movs r2, #32 80066ee: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Cleat TxISR function pointer */ huart->TxISR = NULL; 80066f2: 687b ldr r3, [r7, #4] 80066f4: 2200 movs r2, #0 80066f6: 675a str r2, [r3, #116] ; 0x74 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 80066f8: 6878 ldr r0, [r7, #4] 80066fa: f7f9 ff73 bl 80005e4 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 80066fe: bf00 nop 8006700: 3720 adds r7, #32 8006702: 46bd mov sp, r7 8006704: bd80 pop {r7, pc} 08006706 : * @brief RX interrupt handler for 7 or 8 bits data word length . * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) { 8006706: b580 push {r7, lr} 8006708: b096 sub sp, #88 ; 0x58 800670a: af00 add r7, sp, #0 800670c: 6078 str r0, [r7, #4] uint16_t uhMask = huart->Mask; 800670e: 687b ldr r3, [r7, #4] 8006710: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 8006714: f8a7 3056 strh.w r3, [r7, #86] ; 0x56 uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8006718: 687b ldr r3, [r7, #4] 800671a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 800671e: 2b22 cmp r3, #34 ; 0x22 8006720: f040 8095 bne.w 800684e { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8006724: 687b ldr r3, [r7, #4] 8006726: 681b ldr r3, [r3, #0] 8006728: 6a5b ldr r3, [r3, #36] ; 0x24 800672a: f8a7 3054 strh.w r3, [r7, #84] ; 0x54 *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 800672e: f8b7 3054 ldrh.w r3, [r7, #84] ; 0x54 8006732: b2d9 uxtb r1, r3 8006734: f8b7 3056 ldrh.w r3, [r7, #86] ; 0x56 8006738: b2da uxtb r2, r3 800673a: 687b ldr r3, [r7, #4] 800673c: 6d9b ldr r3, [r3, #88] ; 0x58 800673e: 400a ands r2, r1 8006740: b2d2 uxtb r2, r2 8006742: 701a strb r2, [r3, #0] huart->pRxBuffPtr++; 8006744: 687b ldr r3, [r7, #4] 8006746: 6d9b ldr r3, [r3, #88] ; 0x58 8006748: 1c5a adds r2, r3, #1 800674a: 687b ldr r3, [r7, #4] 800674c: 659a str r2, [r3, #88] ; 0x58 huart->RxXferCount--; 800674e: 687b ldr r3, [r7, #4] 8006750: f8b3 305e ldrh.w r3, [r3, #94] ; 0x5e 8006754: b29b uxth r3, r3 8006756: 3b01 subs r3, #1 8006758: b29a uxth r2, r3 800675a: 687b ldr r3, [r7, #4] 800675c: f8a3 205e strh.w r2, [r3, #94] ; 0x5e if (huart->RxXferCount == 0U) 8006760: 687b ldr r3, [r7, #4] 8006762: f8b3 305e ldrh.w r3, [r3, #94] ; 0x5e 8006766: b29b uxth r3, r3 8006768: 2b00 cmp r3, #0 800676a: d178 bne.n 800685e { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 800676c: 687b ldr r3, [r7, #4] 800676e: 681b ldr r3, [r3, #0] 8006770: 63bb str r3, [r7, #56] ; 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006772: 6bbb ldr r3, [r7, #56] ; 0x38 8006774: e853 3f00 ldrex r3, [r3] 8006778: 637b str r3, [r7, #52] ; 0x34 return(result); 800677a: 6b7b ldr r3, [r7, #52] ; 0x34 800677c: f423 7390 bic.w r3, r3, #288 ; 0x120 8006780: 653b str r3, [r7, #80] ; 0x50 8006782: 687b ldr r3, [r7, #4] 8006784: 681b ldr r3, [r3, #0] 8006786: 461a mov r2, r3 8006788: 6d3b ldr r3, [r7, #80] ; 0x50 800678a: 647b str r3, [r7, #68] ; 0x44 800678c: 643a str r2, [r7, #64] ; 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800678e: 6c39 ldr r1, [r7, #64] ; 0x40 8006790: 6c7a ldr r2, [r7, #68] ; 0x44 8006792: e841 2300 strex r3, r2, [r1] 8006796: 63fb str r3, [r7, #60] ; 0x3c return(result); 8006798: 6bfb ldr r3, [r7, #60] ; 0x3c 800679a: 2b00 cmp r3, #0 800679c: d1e6 bne.n 800676c /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 800679e: 687b ldr r3, [r7, #4] 80067a0: 681b ldr r3, [r3, #0] 80067a2: 3308 adds r3, #8 80067a4: 627b str r3, [r7, #36] ; 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80067a6: 6a7b ldr r3, [r7, #36] ; 0x24 80067a8: e853 3f00 ldrex r3, [r3] 80067ac: 623b str r3, [r7, #32] return(result); 80067ae: 6a3b ldr r3, [r7, #32] 80067b0: f023 0301 bic.w r3, r3, #1 80067b4: 64fb str r3, [r7, #76] ; 0x4c 80067b6: 687b ldr r3, [r7, #4] 80067b8: 681b ldr r3, [r3, #0] 80067ba: 3308 adds r3, #8 80067bc: 6cfa ldr r2, [r7, #76] ; 0x4c 80067be: 633a str r2, [r7, #48] ; 0x30 80067c0: 62fb str r3, [r7, #44] ; 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80067c2: 6af9 ldr r1, [r7, #44] ; 0x2c 80067c4: 6b3a ldr r2, [r7, #48] ; 0x30 80067c6: e841 2300 strex r3, r2, [r1] 80067ca: 62bb str r3, [r7, #40] ; 0x28 return(result); 80067cc: 6abb ldr r3, [r7, #40] ; 0x28 80067ce: 2b00 cmp r3, #0 80067d0: d1e5 bne.n 800679e /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80067d2: 687b ldr r3, [r7, #4] 80067d4: 2220 movs r2, #32 80067d6: f8c3 2088 str.w r2, [r3, #136] ; 0x88 /* Clear RxISR function pointer */ huart->RxISR = NULL; 80067da: 687b ldr r3, [r7, #4] 80067dc: 2200 movs r2, #0 80067de: 671a str r2, [r3, #112] ; 0x70 /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80067e0: 687b ldr r3, [r7, #4] 80067e2: 6edb ldr r3, [r3, #108] ; 0x6c 80067e4: 2b01 cmp r3, #1 80067e6: d12e bne.n 8006846 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80067e8: 687b ldr r3, [r7, #4] 80067ea: 2200 movs r2, #0 80067ec: 66da str r2, [r3, #108] ; 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80067ee: 687b ldr r3, [r7, #4] 80067f0: 681b ldr r3, [r3, #0] 80067f2: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80067f4: 693b ldr r3, [r7, #16] 80067f6: e853 3f00 ldrex r3, [r3] 80067fa: 60fb str r3, [r7, #12] return(result); 80067fc: 68fb ldr r3, [r7, #12] 80067fe: f023 0310 bic.w r3, r3, #16 8006802: 64bb str r3, [r7, #72] ; 0x48 8006804: 687b ldr r3, [r7, #4] 8006806: 681b ldr r3, [r3, #0] 8006808: 461a mov r2, r3 800680a: 6cbb ldr r3, [r7, #72] ; 0x48 800680c: 61fb str r3, [r7, #28] 800680e: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006810: 69b9 ldr r1, [r7, #24] 8006812: 69fa ldr r2, [r7, #28] 8006814: e841 2300 strex r3, r2, [r1] 8006818: 617b str r3, [r7, #20] return(result); 800681a: 697b ldr r3, [r7, #20] 800681c: 2b00 cmp r3, #0 800681e: d1e6 bne.n 80067ee if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8006820: 687b ldr r3, [r7, #4] 8006822: 681b ldr r3, [r3, #0] 8006824: 69db ldr r3, [r3, #28] 8006826: f003 0310 and.w r3, r3, #16 800682a: 2b10 cmp r3, #16 800682c: d103 bne.n 8006836 { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 800682e: 687b ldr r3, [r7, #4] 8006830: 681b ldr r3, [r3, #0] 8006832: 2210 movs r2, #16 8006834: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8006836: 687b ldr r3, [r7, #4] 8006838: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c 800683c: 4619 mov r1, r3 800683e: 6878 ldr r0, [r7, #4] 8006840: f7fe fbce bl 8004fe0 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 8006844: e00b b.n 800685e HAL_UART_RxCpltCallback(huart); 8006846: 6878 ldr r0, [r7, #4] 8006848: f7f9 fedc bl 8000604 } 800684c: e007 b.n 800685e __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 800684e: 687b ldr r3, [r7, #4] 8006850: 681b ldr r3, [r3, #0] 8006852: 699a ldr r2, [r3, #24] 8006854: 687b ldr r3, [r7, #4] 8006856: 681b ldr r3, [r3, #0] 8006858: f042 0208 orr.w r2, r2, #8 800685c: 619a str r2, [r3, #24] } 800685e: bf00 nop 8006860: 3758 adds r7, #88 ; 0x58 8006862: 46bd mov sp, r7 8006864: bd80 pop {r7, pc} 08006866 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) { 8006866: b580 push {r7, lr} 8006868: b096 sub sp, #88 ; 0x58 800686a: af00 add r7, sp, #0 800686c: 6078 str r0, [r7, #4] uint16_t *tmp; uint16_t uhMask = huart->Mask; 800686e: 687b ldr r3, [r7, #4] 8006870: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 8006874: f8a7 3056 strh.w r3, [r7, #86] ; 0x56 uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8006878: 687b ldr r3, [r7, #4] 800687a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 800687e: 2b22 cmp r3, #34 ; 0x22 8006880: f040 8095 bne.w 80069ae { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8006884: 687b ldr r3, [r7, #4] 8006886: 681b ldr r3, [r3, #0] 8006888: 6a5b ldr r3, [r3, #36] ; 0x24 800688a: f8a7 3054 strh.w r3, [r7, #84] ; 0x54 tmp = (uint16_t *) huart->pRxBuffPtr ; 800688e: 687b ldr r3, [r7, #4] 8006890: 6d9b ldr r3, [r3, #88] ; 0x58 8006892: 653b str r3, [r7, #80] ; 0x50 *tmp = (uint16_t)(uhdata & uhMask); 8006894: f8b7 2054 ldrh.w r2, [r7, #84] ; 0x54 8006898: f8b7 3056 ldrh.w r3, [r7, #86] ; 0x56 800689c: 4013 ands r3, r2 800689e: b29a uxth r2, r3 80068a0: 6d3b ldr r3, [r7, #80] ; 0x50 80068a2: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 80068a4: 687b ldr r3, [r7, #4] 80068a6: 6d9b ldr r3, [r3, #88] ; 0x58 80068a8: 1c9a adds r2, r3, #2 80068aa: 687b ldr r3, [r7, #4] 80068ac: 659a str r2, [r3, #88] ; 0x58 huart->RxXferCount--; 80068ae: 687b ldr r3, [r7, #4] 80068b0: f8b3 305e ldrh.w r3, [r3, #94] ; 0x5e 80068b4: b29b uxth r3, r3 80068b6: 3b01 subs r3, #1 80068b8: b29a uxth r2, r3 80068ba: 687b ldr r3, [r7, #4] 80068bc: f8a3 205e strh.w r2, [r3, #94] ; 0x5e if (huart->RxXferCount == 0U) 80068c0: 687b ldr r3, [r7, #4] 80068c2: f8b3 305e ldrh.w r3, [r3, #94] ; 0x5e 80068c6: b29b uxth r3, r3 80068c8: 2b00 cmp r3, #0 80068ca: d178 bne.n 80069be { /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 80068cc: 687b ldr r3, [r7, #4] 80068ce: 681b ldr r3, [r3, #0] 80068d0: 637b str r3, [r7, #52] ; 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80068d2: 6b7b ldr r3, [r7, #52] ; 0x34 80068d4: e853 3f00 ldrex r3, [r3] 80068d8: 633b str r3, [r7, #48] ; 0x30 return(result); 80068da: 6b3b ldr r3, [r7, #48] ; 0x30 80068dc: f423 7390 bic.w r3, r3, #288 ; 0x120 80068e0: 64fb str r3, [r7, #76] ; 0x4c 80068e2: 687b ldr r3, [r7, #4] 80068e4: 681b ldr r3, [r3, #0] 80068e6: 461a mov r2, r3 80068e8: 6cfb ldr r3, [r7, #76] ; 0x4c 80068ea: 643b str r3, [r7, #64] ; 0x40 80068ec: 63fa str r2, [r7, #60] ; 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80068ee: 6bf9 ldr r1, [r7, #60] ; 0x3c 80068f0: 6c3a ldr r2, [r7, #64] ; 0x40 80068f2: e841 2300 strex r3, r2, [r1] 80068f6: 63bb str r3, [r7, #56] ; 0x38 return(result); 80068f8: 6bbb ldr r3, [r7, #56] ; 0x38 80068fa: 2b00 cmp r3, #0 80068fc: d1e6 bne.n 80068cc /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80068fe: 687b ldr r3, [r7, #4] 8006900: 681b ldr r3, [r3, #0] 8006902: 3308 adds r3, #8 8006904: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006906: 6a3b ldr r3, [r7, #32] 8006908: e853 3f00 ldrex r3, [r3] 800690c: 61fb str r3, [r7, #28] return(result); 800690e: 69fb ldr r3, [r7, #28] 8006910: f023 0301 bic.w r3, r3, #1 8006914: 64bb str r3, [r7, #72] ; 0x48 8006916: 687b ldr r3, [r7, #4] 8006918: 681b ldr r3, [r3, #0] 800691a: 3308 adds r3, #8 800691c: 6cba ldr r2, [r7, #72] ; 0x48 800691e: 62fa str r2, [r7, #44] ; 0x2c 8006920: 62bb str r3, [r7, #40] ; 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006922: 6ab9 ldr r1, [r7, #40] ; 0x28 8006924: 6afa ldr r2, [r7, #44] ; 0x2c 8006926: e841 2300 strex r3, r2, [r1] 800692a: 627b str r3, [r7, #36] ; 0x24 return(result); 800692c: 6a7b ldr r3, [r7, #36] ; 0x24 800692e: 2b00 cmp r3, #0 8006930: d1e5 bne.n 80068fe /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8006932: 687b ldr r3, [r7, #4] 8006934: 2220 movs r2, #32 8006936: f8c3 2088 str.w r2, [r3, #136] ; 0x88 /* Clear RxISR function pointer */ huart->RxISR = NULL; 800693a: 687b ldr r3, [r7, #4] 800693c: 2200 movs r2, #0 800693e: 671a str r2, [r3, #112] ; 0x70 /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006940: 687b ldr r3, [r7, #4] 8006942: 6edb ldr r3, [r3, #108] ; 0x6c 8006944: 2b01 cmp r3, #1 8006946: d12e bne.n 80069a6 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8006948: 687b ldr r3, [r7, #4] 800694a: 2200 movs r2, #0 800694c: 66da str r2, [r3, #108] ; 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800694e: 687b ldr r3, [r7, #4] 8006950: 681b ldr r3, [r3, #0] 8006952: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006954: 68fb ldr r3, [r7, #12] 8006956: e853 3f00 ldrex r3, [r3] 800695a: 60bb str r3, [r7, #8] return(result); 800695c: 68bb ldr r3, [r7, #8] 800695e: f023 0310 bic.w r3, r3, #16 8006962: 647b str r3, [r7, #68] ; 0x44 8006964: 687b ldr r3, [r7, #4] 8006966: 681b ldr r3, [r3, #0] 8006968: 461a mov r2, r3 800696a: 6c7b ldr r3, [r7, #68] ; 0x44 800696c: 61bb str r3, [r7, #24] 800696e: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006970: 6979 ldr r1, [r7, #20] 8006972: 69ba ldr r2, [r7, #24] 8006974: e841 2300 strex r3, r2, [r1] 8006978: 613b str r3, [r7, #16] return(result); 800697a: 693b ldr r3, [r7, #16] 800697c: 2b00 cmp r3, #0 800697e: d1e6 bne.n 800694e if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8006980: 687b ldr r3, [r7, #4] 8006982: 681b ldr r3, [r3, #0] 8006984: 69db ldr r3, [r3, #28] 8006986: f003 0310 and.w r3, r3, #16 800698a: 2b10 cmp r3, #16 800698c: d103 bne.n 8006996 { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 800698e: 687b ldr r3, [r7, #4] 8006990: 681b ldr r3, [r3, #0] 8006992: 2210 movs r2, #16 8006994: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8006996: 687b ldr r3, [r7, #4] 8006998: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c 800699c: 4619 mov r1, r3 800699e: 6878 ldr r0, [r7, #4] 80069a0: f7fe fb1e bl 8004fe0 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 80069a4: e00b b.n 80069be HAL_UART_RxCpltCallback(huart); 80069a6: 6878 ldr r0, [r7, #4] 80069a8: f7f9 fe2c bl 8000604 } 80069ac: e007 b.n 80069be __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 80069ae: 687b ldr r3, [r7, #4] 80069b0: 681b ldr r3, [r3, #0] 80069b2: 699a ldr r2, [r3, #24] 80069b4: 687b ldr r3, [r7, #4] 80069b6: 681b ldr r3, [r3, #0] 80069b8: f042 0208 orr.w r2, r2, #8 80069bc: 619a str r2, [r3, #24] } 80069be: bf00 nop 80069c0: 3758 adds r7, #88 ; 0x58 80069c2: 46bd mov sp, r7 80069c4: bd80 pop {r7, pc} ... 080069c8 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { 80069c8: b580 push {r7, lr} 80069ca: b0a6 sub sp, #152 ; 0x98 80069cc: af00 add r7, sp, #0 80069ce: 6078 str r0, [r7, #4] uint16_t uhMask = huart->Mask; 80069d0: 687b ldr r3, [r7, #4] 80069d2: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 80069d6: f8a7 3092 strh.w r3, [r7, #146] ; 0x92 uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); 80069da: 687b ldr r3, [r7, #4] 80069dc: 681b ldr r3, [r3, #0] 80069de: 69db ldr r3, [r3, #28] 80069e0: f8c7 3094 str.w r3, [r7, #148] ; 0x94 uint32_t cr1its = READ_REG(huart->Instance->CR1); 80069e4: 687b ldr r3, [r7, #4] 80069e6: 681b ldr r3, [r3, #0] 80069e8: 681b ldr r3, [r3, #0] 80069ea: f8c7 308c str.w r3, [r7, #140] ; 0x8c uint32_t cr3its = READ_REG(huart->Instance->CR3); 80069ee: 687b ldr r3, [r7, #4] 80069f0: 681b ldr r3, [r3, #0] 80069f2: 689b ldr r3, [r3, #8] 80069f4: f8c7 3088 str.w r3, [r7, #136] ; 0x88 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 80069f8: 687b ldr r3, [r7, #4] 80069fa: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 80069fe: 2b22 cmp r3, #34 ; 0x22 8006a00: f040 814d bne.w 8006c9e { nb_rx_data = huart->NbRxDataToProcess; 8006a04: 687b ldr r3, [r7, #4] 8006a06: f8b3 3068 ldrh.w r3, [r3, #104] ; 0x68 8006a0a: f8a7 3086 strh.w r3, [r7, #134] ; 0x86 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8006a0e: e0f4 b.n 8006bfa { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8006a10: 687b ldr r3, [r7, #4] 8006a12: 681b ldr r3, [r3, #0] 8006a14: 6a5b ldr r3, [r3, #36] ; 0x24 8006a16: f8a7 3084 strh.w r3, [r7, #132] ; 0x84 *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 8006a1a: f8b7 3084 ldrh.w r3, [r7, #132] ; 0x84 8006a1e: b2d9 uxtb r1, r3 8006a20: f8b7 3092 ldrh.w r3, [r7, #146] ; 0x92 8006a24: b2da uxtb r2, r3 8006a26: 687b ldr r3, [r7, #4] 8006a28: 6d9b ldr r3, [r3, #88] ; 0x58 8006a2a: 400a ands r2, r1 8006a2c: b2d2 uxtb r2, r2 8006a2e: 701a strb r2, [r3, #0] huart->pRxBuffPtr++; 8006a30: 687b ldr r3, [r7, #4] 8006a32: 6d9b ldr r3, [r3, #88] ; 0x58 8006a34: 1c5a adds r2, r3, #1 8006a36: 687b ldr r3, [r7, #4] 8006a38: 659a str r2, [r3, #88] ; 0x58 huart->RxXferCount--; 8006a3a: 687b ldr r3, [r7, #4] 8006a3c: f8b3 305e ldrh.w r3, [r3, #94] ; 0x5e 8006a40: b29b uxth r3, r3 8006a42: 3b01 subs r3, #1 8006a44: b29a uxth r2, r3 8006a46: 687b ldr r3, [r7, #4] 8006a48: f8a3 205e strh.w r2, [r3, #94] ; 0x5e isrflags = READ_REG(huart->Instance->ISR); 8006a4c: 687b ldr r3, [r7, #4] 8006a4e: 681b ldr r3, [r3, #0] 8006a50: 69db ldr r3, [r3, #28] 8006a52: f8c7 3094 str.w r3, [r7, #148] ; 0x94 /* If some non blocking errors occurred */ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) 8006a56: f8d7 3094 ldr.w r3, [r7, #148] ; 0x94 8006a5a: f003 0307 and.w r3, r3, #7 8006a5e: 2b00 cmp r3, #0 8006a60: d053 beq.n 8006b0a { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 8006a62: f8d7 3094 ldr.w r3, [r7, #148] ; 0x94 8006a66: f003 0301 and.w r3, r3, #1 8006a6a: 2b00 cmp r3, #0 8006a6c: d011 beq.n 8006a92 8006a6e: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c 8006a72: f403 7380 and.w r3, r3, #256 ; 0x100 8006a76: 2b00 cmp r3, #0 8006a78: d00b beq.n 8006a92 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 8006a7a: 687b ldr r3, [r7, #4] 8006a7c: 681b ldr r3, [r3, #0] 8006a7e: 2201 movs r2, #1 8006a80: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 8006a82: 687b ldr r3, [r7, #4] 8006a84: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 8006a88: f043 0201 orr.w r2, r3, #1 8006a8c: 687b ldr r3, [r7, #4] 8006a8e: f8c3 208c str.w r2, [r3, #140] ; 0x8c } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8006a92: f8d7 3094 ldr.w r3, [r7, #148] ; 0x94 8006a96: f003 0302 and.w r3, r3, #2 8006a9a: 2b00 cmp r3, #0 8006a9c: d011 beq.n 8006ac2 8006a9e: f8d7 3088 ldr.w r3, [r7, #136] ; 0x88 8006aa2: f003 0301 and.w r3, r3, #1 8006aa6: 2b00 cmp r3, #0 8006aa8: d00b beq.n 8006ac2 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 8006aaa: 687b ldr r3, [r7, #4] 8006aac: 681b ldr r3, [r3, #0] 8006aae: 2202 movs r2, #2 8006ab0: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 8006ab2: 687b ldr r3, [r7, #4] 8006ab4: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 8006ab8: f043 0204 orr.w r2, r3, #4 8006abc: 687b ldr r3, [r7, #4] 8006abe: f8c3 208c str.w r2, [r3, #140] ; 0x8c } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8006ac2: f8d7 3094 ldr.w r3, [r7, #148] ; 0x94 8006ac6: f003 0304 and.w r3, r3, #4 8006aca: 2b00 cmp r3, #0 8006acc: d011 beq.n 8006af2 8006ace: f8d7 3088 ldr.w r3, [r7, #136] ; 0x88 8006ad2: f003 0301 and.w r3, r3, #1 8006ad6: 2b00 cmp r3, #0 8006ad8: d00b beq.n 8006af2 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 8006ada: 687b ldr r3, [r7, #4] 8006adc: 681b ldr r3, [r3, #0] 8006ade: 2204 movs r2, #4 8006ae0: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 8006ae2: 687b ldr r3, [r7, #4] 8006ae4: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 8006ae8: f043 0202 orr.w r2, r3, #2 8006aec: 687b ldr r3, [r7, #4] 8006aee: f8c3 208c str.w r2, [r3, #140] ; 0x8c } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8006af2: 687b ldr r3, [r7, #4] 8006af4: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 8006af8: 2b00 cmp r3, #0 8006afa: d006 beq.n 8006b0a #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8006afc: 6878 ldr r0, [r7, #4] 8006afe: f7fe fa65 bl 8004fcc #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8006b02: 687b ldr r3, [r7, #4] 8006b04: 2200 movs r2, #0 8006b06: f8c3 208c str.w r2, [r3, #140] ; 0x8c } } if (huart->RxXferCount == 0U) 8006b0a: 687b ldr r3, [r7, #4] 8006b0c: f8b3 305e ldrh.w r3, [r3, #94] ; 0x5e 8006b10: b29b uxth r3, r3 8006b12: 2b00 cmp r3, #0 8006b14: d171 bne.n 8006bfa { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8006b16: 687b ldr r3, [r7, #4] 8006b18: 681b ldr r3, [r3, #0] 8006b1a: 65fb str r3, [r7, #92] ; 0x5c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006b1c: 6dfb ldr r3, [r7, #92] ; 0x5c 8006b1e: e853 3f00 ldrex r3, [r3] 8006b22: 65bb str r3, [r7, #88] ; 0x58 return(result); 8006b24: 6dbb ldr r3, [r7, #88] ; 0x58 8006b26: f423 7380 bic.w r3, r3, #256 ; 0x100 8006b2a: f8c7 3080 str.w r3, [r7, #128] ; 0x80 8006b2e: 687b ldr r3, [r7, #4] 8006b30: 681b ldr r3, [r3, #0] 8006b32: 461a mov r2, r3 8006b34: f8d7 3080 ldr.w r3, [r7, #128] ; 0x80 8006b38: 66bb str r3, [r7, #104] ; 0x68 8006b3a: 667a str r2, [r7, #100] ; 0x64 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006b3c: 6e79 ldr r1, [r7, #100] ; 0x64 8006b3e: 6eba ldr r2, [r7, #104] ; 0x68 8006b40: e841 2300 strex r3, r2, [r1] 8006b44: 663b str r3, [r7, #96] ; 0x60 return(result); 8006b46: 6e3b ldr r3, [r7, #96] ; 0x60 8006b48: 2b00 cmp r3, #0 8006b4a: d1e4 bne.n 8006b16 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8006b4c: 687b ldr r3, [r7, #4] 8006b4e: 681b ldr r3, [r3, #0] 8006b50: 3308 adds r3, #8 8006b52: 64bb str r3, [r7, #72] ; 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006b54: 6cbb ldr r3, [r7, #72] ; 0x48 8006b56: e853 3f00 ldrex r3, [r3] 8006b5a: 647b str r3, [r7, #68] ; 0x44 return(result); 8006b5c: 6c7a ldr r2, [r7, #68] ; 0x44 8006b5e: 4b56 ldr r3, [pc, #344] ; (8006cb8 ) 8006b60: 4013 ands r3, r2 8006b62: 67fb str r3, [r7, #124] ; 0x7c 8006b64: 687b ldr r3, [r7, #4] 8006b66: 681b ldr r3, [r3, #0] 8006b68: 3308 adds r3, #8 8006b6a: 6ffa ldr r2, [r7, #124] ; 0x7c 8006b6c: 657a str r2, [r7, #84] ; 0x54 8006b6e: 653b str r3, [r7, #80] ; 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006b70: 6d39 ldr r1, [r7, #80] ; 0x50 8006b72: 6d7a ldr r2, [r7, #84] ; 0x54 8006b74: e841 2300 strex r3, r2, [r1] 8006b78: 64fb str r3, [r7, #76] ; 0x4c return(result); 8006b7a: 6cfb ldr r3, [r7, #76] ; 0x4c 8006b7c: 2b00 cmp r3, #0 8006b7e: d1e5 bne.n 8006b4c /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8006b80: 687b ldr r3, [r7, #4] 8006b82: 2220 movs r2, #32 8006b84: f8c3 2088 str.w r2, [r3, #136] ; 0x88 /* Clear RxISR function pointer */ huart->RxISR = NULL; 8006b88: 687b ldr r3, [r7, #4] 8006b8a: 2200 movs r2, #0 8006b8c: 671a str r2, [r3, #112] ; 0x70 /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006b8e: 687b ldr r3, [r7, #4] 8006b90: 6edb ldr r3, [r3, #108] ; 0x6c 8006b92: 2b01 cmp r3, #1 8006b94: d12e bne.n 8006bf4 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8006b96: 687b ldr r3, [r7, #4] 8006b98: 2200 movs r2, #0 8006b9a: 66da str r2, [r3, #108] ; 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8006b9c: 687b ldr r3, [r7, #4] 8006b9e: 681b ldr r3, [r3, #0] 8006ba0: 637b str r3, [r7, #52] ; 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006ba2: 6b7b ldr r3, [r7, #52] ; 0x34 8006ba4: e853 3f00 ldrex r3, [r3] 8006ba8: 633b str r3, [r7, #48] ; 0x30 return(result); 8006baa: 6b3b ldr r3, [r7, #48] ; 0x30 8006bac: f023 0310 bic.w r3, r3, #16 8006bb0: 67bb str r3, [r7, #120] ; 0x78 8006bb2: 687b ldr r3, [r7, #4] 8006bb4: 681b ldr r3, [r3, #0] 8006bb6: 461a mov r2, r3 8006bb8: 6fbb ldr r3, [r7, #120] ; 0x78 8006bba: 643b str r3, [r7, #64] ; 0x40 8006bbc: 63fa str r2, [r7, #60] ; 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006bbe: 6bf9 ldr r1, [r7, #60] ; 0x3c 8006bc0: 6c3a ldr r2, [r7, #64] ; 0x40 8006bc2: e841 2300 strex r3, r2, [r1] 8006bc6: 63bb str r3, [r7, #56] ; 0x38 return(result); 8006bc8: 6bbb ldr r3, [r7, #56] ; 0x38 8006bca: 2b00 cmp r3, #0 8006bcc: d1e6 bne.n 8006b9c if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8006bce: 687b ldr r3, [r7, #4] 8006bd0: 681b ldr r3, [r3, #0] 8006bd2: 69db ldr r3, [r3, #28] 8006bd4: f003 0310 and.w r3, r3, #16 8006bd8: 2b10 cmp r3, #16 8006bda: d103 bne.n 8006be4 { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8006bdc: 687b ldr r3, [r7, #4] 8006bde: 681b ldr r3, [r3, #0] 8006be0: 2210 movs r2, #16 8006be2: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8006be4: 687b ldr r3, [r7, #4] 8006be6: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c 8006bea: 4619 mov r1, r3 8006bec: 6878 ldr r0, [r7, #4] 8006bee: f7fe f9f7 bl 8004fe0 8006bf2: e002 b.n 8006bfa #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8006bf4: 6878 ldr r0, [r7, #4] 8006bf6: f7f9 fd05 bl 8000604 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8006bfa: f8b7 3086 ldrh.w r3, [r7, #134] ; 0x86 8006bfe: 2b00 cmp r3, #0 8006c00: d006 beq.n 8006c10 8006c02: f8d7 3094 ldr.w r3, [r7, #148] ; 0x94 8006c06: f003 0320 and.w r3, r3, #32 8006c0a: 2b00 cmp r3, #0 8006c0c: f47f af00 bne.w 8006a10 /* When remaining number of bytes to receive is less than the RX FIFO threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ rxdatacount = huart->RxXferCount; 8006c10: 687b ldr r3, [r7, #4] 8006c12: f8b3 305e ldrh.w r3, [r3, #94] ; 0x5e 8006c16: f8a7 3076 strh.w r3, [r7, #118] ; 0x76 if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 8006c1a: f8b7 3076 ldrh.w r3, [r7, #118] ; 0x76 8006c1e: 2b00 cmp r3, #0 8006c20: d045 beq.n 8006cae 8006c22: 687b ldr r3, [r7, #4] 8006c24: f8b3 3068 ldrh.w r3, [r3, #104] ; 0x68 8006c28: f8b7 2076 ldrh.w r2, [r7, #118] ; 0x76 8006c2c: 429a cmp r2, r3 8006c2e: d23e bcs.n 8006cae { /* Disable the UART RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 8006c30: 687b ldr r3, [r7, #4] 8006c32: 681b ldr r3, [r3, #0] 8006c34: 3308 adds r3, #8 8006c36: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006c38: 6a3b ldr r3, [r7, #32] 8006c3a: e853 3f00 ldrex r3, [r3] 8006c3e: 61fb str r3, [r7, #28] return(result); 8006c40: 69fb ldr r3, [r7, #28] 8006c42: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8006c46: 673b str r3, [r7, #112] ; 0x70 8006c48: 687b ldr r3, [r7, #4] 8006c4a: 681b ldr r3, [r3, #0] 8006c4c: 3308 adds r3, #8 8006c4e: 6f3a ldr r2, [r7, #112] ; 0x70 8006c50: 62fa str r2, [r7, #44] ; 0x2c 8006c52: 62bb str r3, [r7, #40] ; 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006c54: 6ab9 ldr r1, [r7, #40] ; 0x28 8006c56: 6afa ldr r2, [r7, #44] ; 0x2c 8006c58: e841 2300 strex r3, r2, [r1] 8006c5c: 627b str r3, [r7, #36] ; 0x24 return(result); 8006c5e: 6a7b ldr r3, [r7, #36] ; 0x24 8006c60: 2b00 cmp r3, #0 8006c62: d1e5 bne.n 8006c30 /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_8BIT; 8006c64: 687b ldr r3, [r7, #4] 8006c66: 4a15 ldr r2, [pc, #84] ; (8006cbc ) 8006c68: 671a str r2, [r3, #112] ; 0x70 /* Enable the UART Data Register Not Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8006c6a: 687b ldr r3, [r7, #4] 8006c6c: 681b ldr r3, [r3, #0] 8006c6e: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006c70: 68fb ldr r3, [r7, #12] 8006c72: e853 3f00 ldrex r3, [r3] 8006c76: 60bb str r3, [r7, #8] return(result); 8006c78: 68bb ldr r3, [r7, #8] 8006c7a: f043 0320 orr.w r3, r3, #32 8006c7e: 66fb str r3, [r7, #108] ; 0x6c 8006c80: 687b ldr r3, [r7, #4] 8006c82: 681b ldr r3, [r3, #0] 8006c84: 461a mov r2, r3 8006c86: 6efb ldr r3, [r7, #108] ; 0x6c 8006c88: 61bb str r3, [r7, #24] 8006c8a: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006c8c: 6979 ldr r1, [r7, #20] 8006c8e: 69ba ldr r2, [r7, #24] 8006c90: e841 2300 strex r3, r2, [r1] 8006c94: 613b str r3, [r7, #16] return(result); 8006c96: 693b ldr r3, [r7, #16] 8006c98: 2b00 cmp r3, #0 8006c9a: d1e6 bne.n 8006c6a else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 8006c9c: e007 b.n 8006cae __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 8006c9e: 687b ldr r3, [r7, #4] 8006ca0: 681b ldr r3, [r3, #0] 8006ca2: 699a ldr r2, [r3, #24] 8006ca4: 687b ldr r3, [r7, #4] 8006ca6: 681b ldr r3, [r3, #0] 8006ca8: f042 0208 orr.w r2, r2, #8 8006cac: 619a str r2, [r3, #24] } 8006cae: bf00 nop 8006cb0: 3798 adds r7, #152 ; 0x98 8006cb2: 46bd mov sp, r7 8006cb4: bd80 pop {r7, pc} 8006cb6: bf00 nop 8006cb8: effffffe .word 0xeffffffe 8006cbc: 08006707 .word 0x08006707 08006cc0 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { 8006cc0: b580 push {r7, lr} 8006cc2: b0a8 sub sp, #160 ; 0xa0 8006cc4: af00 add r7, sp, #0 8006cc6: 6078 str r0, [r7, #4] uint16_t *tmp; uint16_t uhMask = huart->Mask; 8006cc8: 687b ldr r3, [r7, #4] 8006cca: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 8006cce: f8a7 309a strh.w r3, [r7, #154] ; 0x9a uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); 8006cd2: 687b ldr r3, [r7, #4] 8006cd4: 681b ldr r3, [r3, #0] 8006cd6: 69db ldr r3, [r3, #28] 8006cd8: f8c7 309c str.w r3, [r7, #156] ; 0x9c uint32_t cr1its = READ_REG(huart->Instance->CR1); 8006cdc: 687b ldr r3, [r7, #4] 8006cde: 681b ldr r3, [r3, #0] 8006ce0: 681b ldr r3, [r3, #0] 8006ce2: f8c7 3094 str.w r3, [r7, #148] ; 0x94 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8006ce6: 687b ldr r3, [r7, #4] 8006ce8: 681b ldr r3, [r3, #0] 8006cea: 689b ldr r3, [r3, #8] 8006cec: f8c7 3090 str.w r3, [r7, #144] ; 0x90 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8006cf0: 687b ldr r3, [r7, #4] 8006cf2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8006cf6: 2b22 cmp r3, #34 ; 0x22 8006cf8: f040 8151 bne.w 8006f9e { nb_rx_data = huart->NbRxDataToProcess; 8006cfc: 687b ldr r3, [r7, #4] 8006cfe: f8b3 3068 ldrh.w r3, [r3, #104] ; 0x68 8006d02: f8a7 308e strh.w r3, [r7, #142] ; 0x8e while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8006d06: e0f8 b.n 8006efa { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8006d08: 687b ldr r3, [r7, #4] 8006d0a: 681b ldr r3, [r3, #0] 8006d0c: 6a5b ldr r3, [r3, #36] ; 0x24 8006d0e: f8a7 308c strh.w r3, [r7, #140] ; 0x8c tmp = (uint16_t *) huart->pRxBuffPtr ; 8006d12: 687b ldr r3, [r7, #4] 8006d14: 6d9b ldr r3, [r3, #88] ; 0x58 8006d16: f8c7 3088 str.w r3, [r7, #136] ; 0x88 *tmp = (uint16_t)(uhdata & uhMask); 8006d1a: f8b7 208c ldrh.w r2, [r7, #140] ; 0x8c 8006d1e: f8b7 309a ldrh.w r3, [r7, #154] ; 0x9a 8006d22: 4013 ands r3, r2 8006d24: b29a uxth r2, r3 8006d26: f8d7 3088 ldr.w r3, [r7, #136] ; 0x88 8006d2a: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8006d2c: 687b ldr r3, [r7, #4] 8006d2e: 6d9b ldr r3, [r3, #88] ; 0x58 8006d30: 1c9a adds r2, r3, #2 8006d32: 687b ldr r3, [r7, #4] 8006d34: 659a str r2, [r3, #88] ; 0x58 huart->RxXferCount--; 8006d36: 687b ldr r3, [r7, #4] 8006d38: f8b3 305e ldrh.w r3, [r3, #94] ; 0x5e 8006d3c: b29b uxth r3, r3 8006d3e: 3b01 subs r3, #1 8006d40: b29a uxth r2, r3 8006d42: 687b ldr r3, [r7, #4] 8006d44: f8a3 205e strh.w r2, [r3, #94] ; 0x5e isrflags = READ_REG(huart->Instance->ISR); 8006d48: 687b ldr r3, [r7, #4] 8006d4a: 681b ldr r3, [r3, #0] 8006d4c: 69db ldr r3, [r3, #28] 8006d4e: f8c7 309c str.w r3, [r7, #156] ; 0x9c /* If some non blocking errors occurred */ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) 8006d52: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c 8006d56: f003 0307 and.w r3, r3, #7 8006d5a: 2b00 cmp r3, #0 8006d5c: d053 beq.n 8006e06 { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 8006d5e: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c 8006d62: f003 0301 and.w r3, r3, #1 8006d66: 2b00 cmp r3, #0 8006d68: d011 beq.n 8006d8e 8006d6a: f8d7 3094 ldr.w r3, [r7, #148] ; 0x94 8006d6e: f403 7380 and.w r3, r3, #256 ; 0x100 8006d72: 2b00 cmp r3, #0 8006d74: d00b beq.n 8006d8e { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 8006d76: 687b ldr r3, [r7, #4] 8006d78: 681b ldr r3, [r3, #0] 8006d7a: 2201 movs r2, #1 8006d7c: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 8006d7e: 687b ldr r3, [r7, #4] 8006d80: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 8006d84: f043 0201 orr.w r2, r3, #1 8006d88: 687b ldr r3, [r7, #4] 8006d8a: f8c3 208c str.w r2, [r3, #140] ; 0x8c } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8006d8e: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c 8006d92: f003 0302 and.w r3, r3, #2 8006d96: 2b00 cmp r3, #0 8006d98: d011 beq.n 8006dbe 8006d9a: f8d7 3090 ldr.w r3, [r7, #144] ; 0x90 8006d9e: f003 0301 and.w r3, r3, #1 8006da2: 2b00 cmp r3, #0 8006da4: d00b beq.n 8006dbe { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 8006da6: 687b ldr r3, [r7, #4] 8006da8: 681b ldr r3, [r3, #0] 8006daa: 2202 movs r2, #2 8006dac: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 8006dae: 687b ldr r3, [r7, #4] 8006db0: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 8006db4: f043 0204 orr.w r2, r3, #4 8006db8: 687b ldr r3, [r7, #4] 8006dba: f8c3 208c str.w r2, [r3, #140] ; 0x8c } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8006dbe: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c 8006dc2: f003 0304 and.w r3, r3, #4 8006dc6: 2b00 cmp r3, #0 8006dc8: d011 beq.n 8006dee 8006dca: f8d7 3090 ldr.w r3, [r7, #144] ; 0x90 8006dce: f003 0301 and.w r3, r3, #1 8006dd2: 2b00 cmp r3, #0 8006dd4: d00b beq.n 8006dee { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 8006dd6: 687b ldr r3, [r7, #4] 8006dd8: 681b ldr r3, [r3, #0] 8006dda: 2204 movs r2, #4 8006ddc: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 8006dde: 687b ldr r3, [r7, #4] 8006de0: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 8006de4: f043 0202 orr.w r2, r3, #2 8006de8: 687b ldr r3, [r7, #4] 8006dea: f8c3 208c str.w r2, [r3, #140] ; 0x8c } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8006dee: 687b ldr r3, [r7, #4] 8006df0: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 8006df4: 2b00 cmp r3, #0 8006df6: d006 beq.n 8006e06 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8006df8: 6878 ldr r0, [r7, #4] 8006dfa: f7fe f8e7 bl 8004fcc #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8006dfe: 687b ldr r3, [r7, #4] 8006e00: 2200 movs r2, #0 8006e02: f8c3 208c str.w r2, [r3, #140] ; 0x8c } } if (huart->RxXferCount == 0U) 8006e06: 687b ldr r3, [r7, #4] 8006e08: f8b3 305e ldrh.w r3, [r3, #94] ; 0x5e 8006e0c: b29b uxth r3, r3 8006e0e: 2b00 cmp r3, #0 8006e10: d173 bne.n 8006efa { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8006e12: 687b ldr r3, [r7, #4] 8006e14: 681b ldr r3, [r3, #0] 8006e16: 663b str r3, [r7, #96] ; 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006e18: 6e3b ldr r3, [r7, #96] ; 0x60 8006e1a: e853 3f00 ldrex r3, [r3] 8006e1e: 65fb str r3, [r7, #92] ; 0x5c return(result); 8006e20: 6dfb ldr r3, [r7, #92] ; 0x5c 8006e22: f423 7380 bic.w r3, r3, #256 ; 0x100 8006e26: f8c7 3084 str.w r3, [r7, #132] ; 0x84 8006e2a: 687b ldr r3, [r7, #4] 8006e2c: 681b ldr r3, [r3, #0] 8006e2e: 461a mov r2, r3 8006e30: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84 8006e34: 66fb str r3, [r7, #108] ; 0x6c 8006e36: 66ba str r2, [r7, #104] ; 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006e38: 6eb9 ldr r1, [r7, #104] ; 0x68 8006e3a: 6efa ldr r2, [r7, #108] ; 0x6c 8006e3c: e841 2300 strex r3, r2, [r1] 8006e40: 667b str r3, [r7, #100] ; 0x64 return(result); 8006e42: 6e7b ldr r3, [r7, #100] ; 0x64 8006e44: 2b00 cmp r3, #0 8006e46: d1e4 bne.n 8006e12 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8006e48: 687b ldr r3, [r7, #4] 8006e4a: 681b ldr r3, [r3, #0] 8006e4c: 3308 adds r3, #8 8006e4e: 64fb str r3, [r7, #76] ; 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006e50: 6cfb ldr r3, [r7, #76] ; 0x4c 8006e52: e853 3f00 ldrex r3, [r3] 8006e56: 64bb str r3, [r7, #72] ; 0x48 return(result); 8006e58: 6cba ldr r2, [r7, #72] ; 0x48 8006e5a: 4b57 ldr r3, [pc, #348] ; (8006fb8 ) 8006e5c: 4013 ands r3, r2 8006e5e: f8c7 3080 str.w r3, [r7, #128] ; 0x80 8006e62: 687b ldr r3, [r7, #4] 8006e64: 681b ldr r3, [r3, #0] 8006e66: 3308 adds r3, #8 8006e68: f8d7 2080 ldr.w r2, [r7, #128] ; 0x80 8006e6c: 65ba str r2, [r7, #88] ; 0x58 8006e6e: 657b str r3, [r7, #84] ; 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006e70: 6d79 ldr r1, [r7, #84] ; 0x54 8006e72: 6dba ldr r2, [r7, #88] ; 0x58 8006e74: e841 2300 strex r3, r2, [r1] 8006e78: 653b str r3, [r7, #80] ; 0x50 return(result); 8006e7a: 6d3b ldr r3, [r7, #80] ; 0x50 8006e7c: 2b00 cmp r3, #0 8006e7e: d1e3 bne.n 8006e48 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8006e80: 687b ldr r3, [r7, #4] 8006e82: 2220 movs r2, #32 8006e84: f8c3 2088 str.w r2, [r3, #136] ; 0x88 /* Clear RxISR function pointer */ huart->RxISR = NULL; 8006e88: 687b ldr r3, [r7, #4] 8006e8a: 2200 movs r2, #0 8006e8c: 671a str r2, [r3, #112] ; 0x70 /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006e8e: 687b ldr r3, [r7, #4] 8006e90: 6edb ldr r3, [r3, #108] ; 0x6c 8006e92: 2b01 cmp r3, #1 8006e94: d12e bne.n 8006ef4 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8006e96: 687b ldr r3, [r7, #4] 8006e98: 2200 movs r2, #0 8006e9a: 66da str r2, [r3, #108] ; 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8006e9c: 687b ldr r3, [r7, #4] 8006e9e: 681b ldr r3, [r3, #0] 8006ea0: 63bb str r3, [r7, #56] ; 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006ea2: 6bbb ldr r3, [r7, #56] ; 0x38 8006ea4: e853 3f00 ldrex r3, [r3] 8006ea8: 637b str r3, [r7, #52] ; 0x34 return(result); 8006eaa: 6b7b ldr r3, [r7, #52] ; 0x34 8006eac: f023 0310 bic.w r3, r3, #16 8006eb0: 67fb str r3, [r7, #124] ; 0x7c 8006eb2: 687b ldr r3, [r7, #4] 8006eb4: 681b ldr r3, [r3, #0] 8006eb6: 461a mov r2, r3 8006eb8: 6ffb ldr r3, [r7, #124] ; 0x7c 8006eba: 647b str r3, [r7, #68] ; 0x44 8006ebc: 643a str r2, [r7, #64] ; 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006ebe: 6c39 ldr r1, [r7, #64] ; 0x40 8006ec0: 6c7a ldr r2, [r7, #68] ; 0x44 8006ec2: e841 2300 strex r3, r2, [r1] 8006ec6: 63fb str r3, [r7, #60] ; 0x3c return(result); 8006ec8: 6bfb ldr r3, [r7, #60] ; 0x3c 8006eca: 2b00 cmp r3, #0 8006ecc: d1e6 bne.n 8006e9c if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8006ece: 687b ldr r3, [r7, #4] 8006ed0: 681b ldr r3, [r3, #0] 8006ed2: 69db ldr r3, [r3, #28] 8006ed4: f003 0310 and.w r3, r3, #16 8006ed8: 2b10 cmp r3, #16 8006eda: d103 bne.n 8006ee4 { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8006edc: 687b ldr r3, [r7, #4] 8006ede: 681b ldr r3, [r3, #0] 8006ee0: 2210 movs r2, #16 8006ee2: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8006ee4: 687b ldr r3, [r7, #4] 8006ee6: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c 8006eea: 4619 mov r1, r3 8006eec: 6878 ldr r0, [r7, #4] 8006eee: f7fe f877 bl 8004fe0 8006ef2: e002 b.n 8006efa #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8006ef4: 6878 ldr r0, [r7, #4] 8006ef6: f7f9 fb85 bl 8000604 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8006efa: f8b7 308e ldrh.w r3, [r7, #142] ; 0x8e 8006efe: 2b00 cmp r3, #0 8006f00: d006 beq.n 8006f10 8006f02: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c 8006f06: f003 0320 and.w r3, r3, #32 8006f0a: 2b00 cmp r3, #0 8006f0c: f47f aefc bne.w 8006d08 /* When remaining number of bytes to receive is less than the RX FIFO threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ rxdatacount = huart->RxXferCount; 8006f10: 687b ldr r3, [r7, #4] 8006f12: f8b3 305e ldrh.w r3, [r3, #94] ; 0x5e 8006f16: f8a7 307a strh.w r3, [r7, #122] ; 0x7a if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 8006f1a: f8b7 307a ldrh.w r3, [r7, #122] ; 0x7a 8006f1e: 2b00 cmp r3, #0 8006f20: d045 beq.n 8006fae 8006f22: 687b ldr r3, [r7, #4] 8006f24: f8b3 3068 ldrh.w r3, [r3, #104] ; 0x68 8006f28: f8b7 207a ldrh.w r2, [r7, #122] ; 0x7a 8006f2c: 429a cmp r2, r3 8006f2e: d23e bcs.n 8006fae { /* Disable the UART RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 8006f30: 687b ldr r3, [r7, #4] 8006f32: 681b ldr r3, [r3, #0] 8006f34: 3308 adds r3, #8 8006f36: 627b str r3, [r7, #36] ; 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006f38: 6a7b ldr r3, [r7, #36] ; 0x24 8006f3a: e853 3f00 ldrex r3, [r3] 8006f3e: 623b str r3, [r7, #32] return(result); 8006f40: 6a3b ldr r3, [r7, #32] 8006f42: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8006f46: 677b str r3, [r7, #116] ; 0x74 8006f48: 687b ldr r3, [r7, #4] 8006f4a: 681b ldr r3, [r3, #0] 8006f4c: 3308 adds r3, #8 8006f4e: 6f7a ldr r2, [r7, #116] ; 0x74 8006f50: 633a str r2, [r7, #48] ; 0x30 8006f52: 62fb str r3, [r7, #44] ; 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006f54: 6af9 ldr r1, [r7, #44] ; 0x2c 8006f56: 6b3a ldr r2, [r7, #48] ; 0x30 8006f58: e841 2300 strex r3, r2, [r1] 8006f5c: 62bb str r3, [r7, #40] ; 0x28 return(result); 8006f5e: 6abb ldr r3, [r7, #40] ; 0x28 8006f60: 2b00 cmp r3, #0 8006f62: d1e5 bne.n 8006f30 /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_16BIT; 8006f64: 687b ldr r3, [r7, #4] 8006f66: 4a15 ldr r2, [pc, #84] ; (8006fbc ) 8006f68: 671a str r2, [r3, #112] ; 0x70 /* Enable the UART Data Register Not Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8006f6a: 687b ldr r3, [r7, #4] 8006f6c: 681b ldr r3, [r3, #0] 8006f6e: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006f70: 693b ldr r3, [r7, #16] 8006f72: e853 3f00 ldrex r3, [r3] 8006f76: 60fb str r3, [r7, #12] return(result); 8006f78: 68fb ldr r3, [r7, #12] 8006f7a: f043 0320 orr.w r3, r3, #32 8006f7e: 673b str r3, [r7, #112] ; 0x70 8006f80: 687b ldr r3, [r7, #4] 8006f82: 681b ldr r3, [r3, #0] 8006f84: 461a mov r2, r3 8006f86: 6f3b ldr r3, [r7, #112] ; 0x70 8006f88: 61fb str r3, [r7, #28] 8006f8a: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006f8c: 69b9 ldr r1, [r7, #24] 8006f8e: 69fa ldr r2, [r7, #28] 8006f90: e841 2300 strex r3, r2, [r1] 8006f94: 617b str r3, [r7, #20] return(result); 8006f96: 697b ldr r3, [r7, #20] 8006f98: 2b00 cmp r3, #0 8006f9a: d1e6 bne.n 8006f6a else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 8006f9c: e007 b.n 8006fae __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 8006f9e: 687b ldr r3, [r7, #4] 8006fa0: 681b ldr r3, [r3, #0] 8006fa2: 699a ldr r2, [r3, #24] 8006fa4: 687b ldr r3, [r7, #4] 8006fa6: 681b ldr r3, [r3, #0] 8006fa8: f042 0208 orr.w r2, r2, #8 8006fac: 619a str r2, [r3, #24] } 8006fae: bf00 nop 8006fb0: 37a0 adds r7, #160 ; 0xa0 8006fb2: 46bd mov sp, r7 8006fb4: bd80 pop {r7, pc} 8006fb6: bf00 nop 8006fb8: effffffe .word 0xeffffffe 8006fbc: 08006867 .word 0x08006867 08006fc0 : * @brief UART wakeup from Stop mode callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) { 8006fc0: b480 push {r7} 8006fc2: b083 sub sp, #12 8006fc4: af00 add r7, sp, #0 8006fc6: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_WakeupCallback can be implemented in the user file. */ } 8006fc8: bf00 nop 8006fca: 370c adds r7, #12 8006fcc: 46bd mov sp, r7 8006fce: f85d 7b04 ldr.w r7, [sp], #4 8006fd2: 4770 bx lr 08006fd4 : * @brief UART RX Fifo full callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) { 8006fd4: b480 push {r7} 8006fd6: b083 sub sp, #12 8006fd8: af00 add r7, sp, #0 8006fda: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. */ } 8006fdc: bf00 nop 8006fde: 370c adds r7, #12 8006fe0: 46bd mov sp, r7 8006fe2: f85d 7b04 ldr.w r7, [sp], #4 8006fe6: 4770 bx lr 08006fe8 : * @brief UART TX Fifo empty callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) { 8006fe8: b480 push {r7} 8006fea: b083 sub sp, #12 8006fec: af00 add r7, sp, #0 8006fee: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. */ } 8006ff0: bf00 nop 8006ff2: 370c adds r7, #12 8006ff4: 46bd mov sp, r7 8006ff6: f85d 7b04 ldr.w r7, [sp], #4 8006ffa: 4770 bx lr 08006ffc : * @brief Enable the FIFO mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) { 8006ffc: b580 push {r7, lr} 8006ffe: b084 sub sp, #16 8007000: af00 add r7, sp, #0 8007002: 6078 str r0, [r7, #4] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); 8007004: 687b ldr r3, [r7, #4] 8007006: f893 3080 ldrb.w r3, [r3, #128] ; 0x80 800700a: 2b01 cmp r3, #1 800700c: d101 bne.n 8007012 800700e: 2302 movs r3, #2 8007010: e02b b.n 800706a 8007012: 687b ldr r3, [r7, #4] 8007014: 2201 movs r2, #1 8007016: f883 2080 strb.w r2, [r3, #128] ; 0x80 huart->gState = HAL_UART_STATE_BUSY; 800701a: 687b ldr r3, [r7, #4] 800701c: 2224 movs r2, #36 ; 0x24 800701e: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8007022: 687b ldr r3, [r7, #4] 8007024: 681b ldr r3, [r3, #0] 8007026: 681b ldr r3, [r3, #0] 8007028: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 800702a: 687b ldr r3, [r7, #4] 800702c: 681b ldr r3, [r3, #0] 800702e: 681a ldr r2, [r3, #0] 8007030: 687b ldr r3, [r7, #4] 8007032: 681b ldr r3, [r3, #0] 8007034: f022 0201 bic.w r2, r2, #1 8007038: 601a str r2, [r3, #0] /* Enable FIFO mode */ SET_BIT(tmpcr1, USART_CR1_FIFOEN); 800703a: 68fb ldr r3, [r7, #12] 800703c: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000 8007040: 60fb str r3, [r7, #12] huart->FifoMode = UART_FIFOMODE_ENABLE; 8007042: 687b ldr r3, [r7, #4] 8007044: f04f 5200 mov.w r2, #536870912 ; 0x20000000 8007048: 665a str r2, [r3, #100] ; 0x64 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 800704a: 687b ldr r3, [r7, #4] 800704c: 681b ldr r3, [r3, #0] 800704e: 68fa ldr r2, [r7, #12] 8007050: 601a str r2, [r3, #0] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 8007052: 6878 ldr r0, [r7, #4] 8007054: f000 f88a bl 800716c huart->gState = HAL_UART_STATE_READY; 8007058: 687b ldr r3, [r7, #4] 800705a: 2220 movs r2, #32 800705c: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Process Unlocked */ __HAL_UNLOCK(huart); 8007060: 687b ldr r3, [r7, #4] 8007062: 2200 movs r2, #0 8007064: f883 2080 strb.w r2, [r3, #128] ; 0x80 return HAL_OK; 8007068: 2300 movs r3, #0 } 800706a: 4618 mov r0, r3 800706c: 3710 adds r7, #16 800706e: 46bd mov sp, r7 8007070: bd80 pop {r7, pc} 08007072 : * @arg @ref UART_TXFIFO_THRESHOLD_7_8 * @arg @ref UART_TXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 8007072: b580 push {r7, lr} 8007074: b084 sub sp, #16 8007076: af00 add r7, sp, #0 8007078: 6078 str r0, [r7, #4] 800707a: 6039 str r1, [r7, #0] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 800707c: 687b ldr r3, [r7, #4] 800707e: f893 3080 ldrb.w r3, [r3, #128] ; 0x80 8007082: 2b01 cmp r3, #1 8007084: d101 bne.n 800708a 8007086: 2302 movs r3, #2 8007088: e02d b.n 80070e6 800708a: 687b ldr r3, [r7, #4] 800708c: 2201 movs r2, #1 800708e: f883 2080 strb.w r2, [r3, #128] ; 0x80 huart->gState = HAL_UART_STATE_BUSY; 8007092: 687b ldr r3, [r7, #4] 8007094: 2224 movs r2, #36 ; 0x24 8007096: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 800709a: 687b ldr r3, [r7, #4] 800709c: 681b ldr r3, [r3, #0] 800709e: 681b ldr r3, [r3, #0] 80070a0: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 80070a2: 687b ldr r3, [r7, #4] 80070a4: 681b ldr r3, [r3, #0] 80070a6: 681a ldr r2, [r3, #0] 80070a8: 687b ldr r3, [r7, #4] 80070aa: 681b ldr r3, [r3, #0] 80070ac: f022 0201 bic.w r2, r2, #1 80070b0: 601a str r2, [r3, #0] /* Update TX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); 80070b2: 687b ldr r3, [r7, #4] 80070b4: 681b ldr r3, [r3, #0] 80070b6: 689b ldr r3, [r3, #8] 80070b8: f023 4160 bic.w r1, r3, #3758096384 ; 0xe0000000 80070bc: 687b ldr r3, [r7, #4] 80070be: 681b ldr r3, [r3, #0] 80070c0: 683a ldr r2, [r7, #0] 80070c2: 430a orrs r2, r1 80070c4: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 80070c6: 6878 ldr r0, [r7, #4] 80070c8: f000 f850 bl 800716c /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 80070cc: 687b ldr r3, [r7, #4] 80070ce: 681b ldr r3, [r3, #0] 80070d0: 68fa ldr r2, [r7, #12] 80070d2: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 80070d4: 687b ldr r3, [r7, #4] 80070d6: 2220 movs r2, #32 80070d8: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Process Unlocked */ __HAL_UNLOCK(huart); 80070dc: 687b ldr r3, [r7, #4] 80070de: 2200 movs r2, #0 80070e0: f883 2080 strb.w r2, [r3, #128] ; 0x80 return HAL_OK; 80070e4: 2300 movs r3, #0 } 80070e6: 4618 mov r0, r3 80070e8: 3710 adds r7, #16 80070ea: 46bd mov sp, r7 80070ec: bd80 pop {r7, pc} 080070ee : * @arg @ref UART_RXFIFO_THRESHOLD_7_8 * @arg @ref UART_RXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 80070ee: b580 push {r7, lr} 80070f0: b084 sub sp, #16 80070f2: af00 add r7, sp, #0 80070f4: 6078 str r0, [r7, #4] 80070f6: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 80070f8: 687b ldr r3, [r7, #4] 80070fa: f893 3080 ldrb.w r3, [r3, #128] ; 0x80 80070fe: 2b01 cmp r3, #1 8007100: d101 bne.n 8007106 8007102: 2302 movs r3, #2 8007104: e02d b.n 8007162 8007106: 687b ldr r3, [r7, #4] 8007108: 2201 movs r2, #1 800710a: f883 2080 strb.w r2, [r3, #128] ; 0x80 huart->gState = HAL_UART_STATE_BUSY; 800710e: 687b ldr r3, [r7, #4] 8007110: 2224 movs r2, #36 ; 0x24 8007112: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8007116: 687b ldr r3, [r7, #4] 8007118: 681b ldr r3, [r3, #0] 800711a: 681b ldr r3, [r3, #0] 800711c: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 800711e: 687b ldr r3, [r7, #4] 8007120: 681b ldr r3, [r3, #0] 8007122: 681a ldr r2, [r3, #0] 8007124: 687b ldr r3, [r7, #4] 8007126: 681b ldr r3, [r3, #0] 8007128: f022 0201 bic.w r2, r2, #1 800712c: 601a str r2, [r3, #0] /* Update RX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); 800712e: 687b ldr r3, [r7, #4] 8007130: 681b ldr r3, [r3, #0] 8007132: 689b ldr r3, [r3, #8] 8007134: f023 6160 bic.w r1, r3, #234881024 ; 0xe000000 8007138: 687b ldr r3, [r7, #4] 800713a: 681b ldr r3, [r3, #0] 800713c: 683a ldr r2, [r7, #0] 800713e: 430a orrs r2, r1 8007140: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 8007142: 6878 ldr r0, [r7, #4] 8007144: f000 f812 bl 800716c /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8007148: 687b ldr r3, [r7, #4] 800714a: 681b ldr r3, [r3, #0] 800714c: 68fa ldr r2, [r7, #12] 800714e: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8007150: 687b ldr r3, [r7, #4] 8007152: 2220 movs r2, #32 8007154: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Process Unlocked */ __HAL_UNLOCK(huart); 8007158: 687b ldr r3, [r7, #4] 800715a: 2200 movs r2, #0 800715c: f883 2080 strb.w r2, [r3, #128] ; 0x80 return HAL_OK; 8007160: 2300 movs r3, #0 } 8007162: 4618 mov r0, r3 8007164: 3710 adds r7, #16 8007166: 46bd mov sp, r7 8007168: bd80 pop {r7, pc} ... 0800716c : * the UART configuration registers. * @param huart UART handle. * @retval None */ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) { 800716c: b480 push {r7} 800716e: b085 sub sp, #20 8007170: af00 add r7, sp, #0 8007172: 6078 str r0, [r7, #4] uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) 8007174: 687b ldr r3, [r7, #4] 8007176: 6e5b ldr r3, [r3, #100] ; 0x64 8007178: 2b00 cmp r3, #0 800717a: d108 bne.n 800718e { huart->NbTxDataToProcess = 1U; 800717c: 687b ldr r3, [r7, #4] 800717e: 2201 movs r2, #1 8007180: f8a3 206a strh.w r2, [r3, #106] ; 0x6a huart->NbRxDataToProcess = 1U; 8007184: 687b ldr r3, [r7, #4] 8007186: 2201 movs r2, #1 8007188: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } 800718c: e031 b.n 80071f2 rx_fifo_depth = RX_FIFO_DEPTH; 800718e: 2310 movs r3, #16 8007190: 73fb strb r3, [r7, #15] tx_fifo_depth = TX_FIFO_DEPTH; 8007192: 2310 movs r3, #16 8007194: 73bb strb r3, [r7, #14] rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); 8007196: 687b ldr r3, [r7, #4] 8007198: 681b ldr r3, [r3, #0] 800719a: 689b ldr r3, [r3, #8] 800719c: 0e5b lsrs r3, r3, #25 800719e: b2db uxtb r3, r3 80071a0: f003 0307 and.w r3, r3, #7 80071a4: 737b strb r3, [r7, #13] tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); 80071a6: 687b ldr r3, [r7, #4] 80071a8: 681b ldr r3, [r3, #0] 80071aa: 689b ldr r3, [r3, #8] 80071ac: 0f5b lsrs r3, r3, #29 80071ae: b2db uxtb r3, r3 80071b0: f003 0307 and.w r3, r3, #7 80071b4: 733b strb r3, [r7, #12] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 80071b6: 7bbb ldrb r3, [r7, #14] 80071b8: 7b3a ldrb r2, [r7, #12] 80071ba: 4911 ldr r1, [pc, #68] ; (8007200 ) 80071bc: 5c8a ldrb r2, [r1, r2] 80071be: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[tx_fifo_threshold]; 80071c2: 7b3a ldrb r2, [r7, #12] 80071c4: 490f ldr r1, [pc, #60] ; (8007204 ) 80071c6: 5c8a ldrb r2, [r1, r2] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 80071c8: fb93 f3f2 sdiv r3, r3, r2 80071cc: b29a uxth r2, r3 80071ce: 687b ldr r3, [r7, #4] 80071d0: f8a3 206a strh.w r2, [r3, #106] ; 0x6a huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 80071d4: 7bfb ldrb r3, [r7, #15] 80071d6: 7b7a ldrb r2, [r7, #13] 80071d8: 4909 ldr r1, [pc, #36] ; (8007200 ) 80071da: 5c8a ldrb r2, [r1, r2] 80071dc: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[rx_fifo_threshold]; 80071e0: 7b7a ldrb r2, [r7, #13] 80071e2: 4908 ldr r1, [pc, #32] ; (8007204 ) 80071e4: 5c8a ldrb r2, [r1, r2] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 80071e6: fb93 f3f2 sdiv r3, r3, r2 80071ea: b29a uxth r2, r3 80071ec: 687b ldr r3, [r7, #4] 80071ee: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 } 80071f2: bf00 nop 80071f4: 3714 adds r7, #20 80071f6: 46bd mov sp, r7 80071f8: f85d 7b04 ldr.w r7, [sp], #4 80071fc: 4770 bx lr 80071fe: bf00 nop 8007200: 080072a0 .word 0x080072a0 8007204: 080072a8 .word 0x080072a8 08007208 <__libc_init_array>: 8007208: b570 push {r4, r5, r6, lr} 800720a: 4d0d ldr r5, [pc, #52] ; (8007240 <__libc_init_array+0x38>) 800720c: 4c0d ldr r4, [pc, #52] ; (8007244 <__libc_init_array+0x3c>) 800720e: 1b64 subs r4, r4, r5 8007210: 10a4 asrs r4, r4, #2 8007212: 2600 movs r6, #0 8007214: 42a6 cmp r6, r4 8007216: d109 bne.n 800722c <__libc_init_array+0x24> 8007218: 4d0b ldr r5, [pc, #44] ; (8007248 <__libc_init_array+0x40>) 800721a: 4c0c ldr r4, [pc, #48] ; (800724c <__libc_init_array+0x44>) 800721c: f000 f820 bl 8007260 <_init> 8007220: 1b64 subs r4, r4, r5 8007222: 10a4 asrs r4, r4, #2 8007224: 2600 movs r6, #0 8007226: 42a6 cmp r6, r4 8007228: d105 bne.n 8007236 <__libc_init_array+0x2e> 800722a: bd70 pop {r4, r5, r6, pc} 800722c: f855 3b04 ldr.w r3, [r5], #4 8007230: 4798 blx r3 8007232: 3601 adds r6, #1 8007234: e7ee b.n 8007214 <__libc_init_array+0xc> 8007236: f855 3b04 ldr.w r3, [r5], #4 800723a: 4798 blx r3 800723c: 3601 adds r6, #1 800723e: e7f2 b.n 8007226 <__libc_init_array+0x1e> 8007240: 080072b8 .word 0x080072b8 8007244: 080072b8 .word 0x080072b8 8007248: 080072b8 .word 0x080072b8 800724c: 080072bc .word 0x080072bc 08007250 : 8007250: 4402 add r2, r0 8007252: 4603 mov r3, r0 8007254: 4293 cmp r3, r2 8007256: d100 bne.n 800725a 8007258: 4770 bx lr 800725a: f803 1b01 strb.w r1, [r3], #1 800725e: e7f9 b.n 8007254 08007260 <_init>: 8007260: b5f8 push {r3, r4, r5, r6, r7, lr} 8007262: bf00 nop 8007264: bcf8 pop {r3, r4, r5, r6, r7} 8007266: bc08 pop {r3} 8007268: 469e mov lr, r3 800726a: 4770 bx lr 0800726c <_fini>: 800726c: b5f8 push {r3, r4, r5, r6, r7, lr} 800726e: bf00 nop 8007270: bcf8 pop {r3, r4, r5, r6, r7} 8007272: bc08 pop {r3} 8007274: 469e mov lr, r3 8007276: 4770 bx lr