H7L3ABaseProject.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000002ac 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000e3a0 080002ac 080002ac 000102ac 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000064 0800e64c 0800e64c 0001e64c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM 00000008 0800e6b0 0800e6b0 0001e6b0 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 4 .init_array 00000004 0800e6b8 0800e6b8 0001e6b8 2**2 CONTENTS, ALLOC, LOAD, DATA 5 .fini_array 00000004 0800e6bc 0800e6bc 0001e6bc 2**2 CONTENTS, ALLOC, LOAD, DATA 6 .data 00000010 20000000 0800e6c0 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .bss 00000f44 20000010 0800e6d0 00020010 2**2 ALLOC 8 ._user_heap_stack 00000604 20000f54 0800e6d0 00020f54 2**0 ALLOC 9 .ARM.attributes 0000002e 00000000 00000000 00020010 2**0 CONTENTS, READONLY 10 .debug_info 00037347 00000000 00000000 0002003e 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 11 .debug_abbrev 000055ac 00000000 00000000 00057385 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 12 .debug_aranges 00001b00 00000000 00000000 0005c938 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_ranges 00001948 00000000 00000000 0005e438 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_macro 00035c1f 00000000 00000000 0005fd80 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_line 00027b96 00000000 00000000 0009599f 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_str 00151c89 00000000 00000000 000bd535 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .comment 00000053 00000000 00000000 0020f1be 2**0 CONTENTS, READONLY 18 .debug_frame 000071c8 00000000 00000000 0020f214 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080002ac <__do_global_dtors_aux>: 80002ac: b510 push {r4, lr} 80002ae: 4c05 ldr r4, [pc, #20] ; (80002c4 <__do_global_dtors_aux+0x18>) 80002b0: 7823 ldrb r3, [r4, #0] 80002b2: b933 cbnz r3, 80002c2 <__do_global_dtors_aux+0x16> 80002b4: 4b04 ldr r3, [pc, #16] ; (80002c8 <__do_global_dtors_aux+0x1c>) 80002b6: b113 cbz r3, 80002be <__do_global_dtors_aux+0x12> 80002b8: 4804 ldr r0, [pc, #16] ; (80002cc <__do_global_dtors_aux+0x20>) 80002ba: f3af 8000 nop.w 80002be: 2301 movs r3, #1 80002c0: 7023 strb r3, [r4, #0] 80002c2: bd10 pop {r4, pc} 80002c4: 20000010 .word 0x20000010 80002c8: 00000000 .word 0x00000000 80002cc: 0800e634 .word 0x0800e634 080002d0 : 80002d0: b508 push {r3, lr} 80002d2: 4b03 ldr r3, [pc, #12] ; (80002e0 ) 80002d4: b11b cbz r3, 80002de 80002d6: 4903 ldr r1, [pc, #12] ; (80002e4 ) 80002d8: 4803 ldr r0, [pc, #12] ; (80002e8 ) 80002da: f3af 8000 nop.w 80002de: bd08 pop {r3, pc} 80002e0: 00000000 .word 0x00000000 80002e4: 20000014 .word 0x20000014 80002e8: 0800e634 .word 0x0800e634 080002ec <__aeabi_uldivmod>: 80002ec: b953 cbnz r3, 8000304 <__aeabi_uldivmod+0x18> 80002ee: b94a cbnz r2, 8000304 <__aeabi_uldivmod+0x18> 80002f0: 2900 cmp r1, #0 80002f2: bf08 it eq 80002f4: 2800 cmpeq r0, #0 80002f6: bf1c itt ne 80002f8: f04f 31ff movne.w r1, #4294967295 80002fc: f04f 30ff movne.w r0, #4294967295 8000300: f000 b96e b.w 80005e0 <__aeabi_idiv0> 8000304: f1ad 0c08 sub.w ip, sp, #8 8000308: e96d ce04 strd ip, lr, [sp, #-16]! 800030c: f000 f806 bl 800031c <__udivmoddi4> 8000310: f8dd e004 ldr.w lr, [sp, #4] 8000314: e9dd 2302 ldrd r2, r3, [sp, #8] 8000318: b004 add sp, #16 800031a: 4770 bx lr 0800031c <__udivmoddi4>: 800031c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8000320: 9d08 ldr r5, [sp, #32] 8000322: 4604 mov r4, r0 8000324: 468c mov ip, r1 8000326: 2b00 cmp r3, #0 8000328: f040 8083 bne.w 8000432 <__udivmoddi4+0x116> 800032c: 428a cmp r2, r1 800032e: 4617 mov r7, r2 8000330: d947 bls.n 80003c2 <__udivmoddi4+0xa6> 8000332: fab2 f282 clz r2, r2 8000336: b142 cbz r2, 800034a <__udivmoddi4+0x2e> 8000338: f1c2 0020 rsb r0, r2, #32 800033c: fa24 f000 lsr.w r0, r4, r0 8000340: 4091 lsls r1, r2 8000342: 4097 lsls r7, r2 8000344: ea40 0c01 orr.w ip, r0, r1 8000348: 4094 lsls r4, r2 800034a: ea4f 4817 mov.w r8, r7, lsr #16 800034e: 0c23 lsrs r3, r4, #16 8000350: fbbc f6f8 udiv r6, ip, r8 8000354: fa1f fe87 uxth.w lr, r7 8000358: fb08 c116 mls r1, r8, r6, ip 800035c: ea43 4301 orr.w r3, r3, r1, lsl #16 8000360: fb06 f10e mul.w r1, r6, lr 8000364: 4299 cmp r1, r3 8000366: d909 bls.n 800037c <__udivmoddi4+0x60> 8000368: 18fb adds r3, r7, r3 800036a: f106 30ff add.w r0, r6, #4294967295 800036e: f080 8119 bcs.w 80005a4 <__udivmoddi4+0x288> 8000372: 4299 cmp r1, r3 8000374: f240 8116 bls.w 80005a4 <__udivmoddi4+0x288> 8000378: 3e02 subs r6, #2 800037a: 443b add r3, r7 800037c: 1a5b subs r3, r3, r1 800037e: b2a4 uxth r4, r4 8000380: fbb3 f0f8 udiv r0, r3, r8 8000384: fb08 3310 mls r3, r8, r0, r3 8000388: ea44 4403 orr.w r4, r4, r3, lsl #16 800038c: fb00 fe0e mul.w lr, r0, lr 8000390: 45a6 cmp lr, r4 8000392: d909 bls.n 80003a8 <__udivmoddi4+0x8c> 8000394: 193c adds r4, r7, r4 8000396: f100 33ff add.w r3, r0, #4294967295 800039a: f080 8105 bcs.w 80005a8 <__udivmoddi4+0x28c> 800039e: 45a6 cmp lr, r4 80003a0: f240 8102 bls.w 80005a8 <__udivmoddi4+0x28c> 80003a4: 3802 subs r0, #2 80003a6: 443c add r4, r7 80003a8: ea40 4006 orr.w r0, r0, r6, lsl #16 80003ac: eba4 040e sub.w r4, r4, lr 80003b0: 2600 movs r6, #0 80003b2: b11d cbz r5, 80003bc <__udivmoddi4+0xa0> 80003b4: 40d4 lsrs r4, r2 80003b6: 2300 movs r3, #0 80003b8: e9c5 4300 strd r4, r3, [r5] 80003bc: 4631 mov r1, r6 80003be: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80003c2: b902 cbnz r2, 80003c6 <__udivmoddi4+0xaa> 80003c4: deff udf #255 ; 0xff 80003c6: fab2 f282 clz r2, r2 80003ca: 2a00 cmp r2, #0 80003cc: d150 bne.n 8000470 <__udivmoddi4+0x154> 80003ce: 1bcb subs r3, r1, r7 80003d0: ea4f 4e17 mov.w lr, r7, lsr #16 80003d4: fa1f f887 uxth.w r8, r7 80003d8: 2601 movs r6, #1 80003da: fbb3 fcfe udiv ip, r3, lr 80003de: 0c21 lsrs r1, r4, #16 80003e0: fb0e 331c mls r3, lr, ip, r3 80003e4: ea41 4103 orr.w r1, r1, r3, lsl #16 80003e8: fb08 f30c mul.w r3, r8, ip 80003ec: 428b cmp r3, r1 80003ee: d907 bls.n 8000400 <__udivmoddi4+0xe4> 80003f0: 1879 adds r1, r7, r1 80003f2: f10c 30ff add.w r0, ip, #4294967295 80003f6: d202 bcs.n 80003fe <__udivmoddi4+0xe2> 80003f8: 428b cmp r3, r1 80003fa: f200 80e9 bhi.w 80005d0 <__udivmoddi4+0x2b4> 80003fe: 4684 mov ip, r0 8000400: 1ac9 subs r1, r1, r3 8000402: b2a3 uxth r3, r4 8000404: fbb1 f0fe udiv r0, r1, lr 8000408: fb0e 1110 mls r1, lr, r0, r1 800040c: ea43 4401 orr.w r4, r3, r1, lsl #16 8000410: fb08 f800 mul.w r8, r8, r0 8000414: 45a0 cmp r8, r4 8000416: d907 bls.n 8000428 <__udivmoddi4+0x10c> 8000418: 193c adds r4, r7, r4 800041a: f100 33ff add.w r3, r0, #4294967295 800041e: d202 bcs.n 8000426 <__udivmoddi4+0x10a> 8000420: 45a0 cmp r8, r4 8000422: f200 80d9 bhi.w 80005d8 <__udivmoddi4+0x2bc> 8000426: 4618 mov r0, r3 8000428: eba4 0408 sub.w r4, r4, r8 800042c: ea40 400c orr.w r0, r0, ip, lsl #16 8000430: e7bf b.n 80003b2 <__udivmoddi4+0x96> 8000432: 428b cmp r3, r1 8000434: d909 bls.n 800044a <__udivmoddi4+0x12e> 8000436: 2d00 cmp r5, #0 8000438: f000 80b1 beq.w 800059e <__udivmoddi4+0x282> 800043c: 2600 movs r6, #0 800043e: e9c5 0100 strd r0, r1, [r5] 8000442: 4630 mov r0, r6 8000444: 4631 mov r1, r6 8000446: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800044a: fab3 f683 clz r6, r3 800044e: 2e00 cmp r6, #0 8000450: d14a bne.n 80004e8 <__udivmoddi4+0x1cc> 8000452: 428b cmp r3, r1 8000454: d302 bcc.n 800045c <__udivmoddi4+0x140> 8000456: 4282 cmp r2, r0 8000458: f200 80b8 bhi.w 80005cc <__udivmoddi4+0x2b0> 800045c: 1a84 subs r4, r0, r2 800045e: eb61 0103 sbc.w r1, r1, r3 8000462: 2001 movs r0, #1 8000464: 468c mov ip, r1 8000466: 2d00 cmp r5, #0 8000468: d0a8 beq.n 80003bc <__udivmoddi4+0xa0> 800046a: e9c5 4c00 strd r4, ip, [r5] 800046e: e7a5 b.n 80003bc <__udivmoddi4+0xa0> 8000470: f1c2 0320 rsb r3, r2, #32 8000474: fa20 f603 lsr.w r6, r0, r3 8000478: 4097 lsls r7, r2 800047a: fa01 f002 lsl.w r0, r1, r2 800047e: ea4f 4e17 mov.w lr, r7, lsr #16 8000482: 40d9 lsrs r1, r3 8000484: 4330 orrs r0, r6 8000486: 0c03 lsrs r3, r0, #16 8000488: fbb1 f6fe udiv r6, r1, lr 800048c: fa1f f887 uxth.w r8, r7 8000490: fb0e 1116 mls r1, lr, r6, r1 8000494: ea43 4301 orr.w r3, r3, r1, lsl #16 8000498: fb06 f108 mul.w r1, r6, r8 800049c: 4299 cmp r1, r3 800049e: fa04 f402 lsl.w r4, r4, r2 80004a2: d909 bls.n 80004b8 <__udivmoddi4+0x19c> 80004a4: 18fb adds r3, r7, r3 80004a6: f106 3cff add.w ip, r6, #4294967295 80004aa: f080 808d bcs.w 80005c8 <__udivmoddi4+0x2ac> 80004ae: 4299 cmp r1, r3 80004b0: f240 808a bls.w 80005c8 <__udivmoddi4+0x2ac> 80004b4: 3e02 subs r6, #2 80004b6: 443b add r3, r7 80004b8: 1a5b subs r3, r3, r1 80004ba: b281 uxth r1, r0 80004bc: fbb3 f0fe udiv r0, r3, lr 80004c0: fb0e 3310 mls r3, lr, r0, r3 80004c4: ea41 4103 orr.w r1, r1, r3, lsl #16 80004c8: fb00 f308 mul.w r3, r0, r8 80004cc: 428b cmp r3, r1 80004ce: d907 bls.n 80004e0 <__udivmoddi4+0x1c4> 80004d0: 1879 adds r1, r7, r1 80004d2: f100 3cff add.w ip, r0, #4294967295 80004d6: d273 bcs.n 80005c0 <__udivmoddi4+0x2a4> 80004d8: 428b cmp r3, r1 80004da: d971 bls.n 80005c0 <__udivmoddi4+0x2a4> 80004dc: 3802 subs r0, #2 80004de: 4439 add r1, r7 80004e0: 1acb subs r3, r1, r3 80004e2: ea40 4606 orr.w r6, r0, r6, lsl #16 80004e6: e778 b.n 80003da <__udivmoddi4+0xbe> 80004e8: f1c6 0c20 rsb ip, r6, #32 80004ec: fa03 f406 lsl.w r4, r3, r6 80004f0: fa22 f30c lsr.w r3, r2, ip 80004f4: 431c orrs r4, r3 80004f6: fa20 f70c lsr.w r7, r0, ip 80004fa: fa01 f306 lsl.w r3, r1, r6 80004fe: ea4f 4e14 mov.w lr, r4, lsr #16 8000502: fa21 f10c lsr.w r1, r1, ip 8000506: 431f orrs r7, r3 8000508: 0c3b lsrs r3, r7, #16 800050a: fbb1 f9fe udiv r9, r1, lr 800050e: fa1f f884 uxth.w r8, r4 8000512: fb0e 1119 mls r1, lr, r9, r1 8000516: ea43 4101 orr.w r1, r3, r1, lsl #16 800051a: fb09 fa08 mul.w sl, r9, r8 800051e: 458a cmp sl, r1 8000520: fa02 f206 lsl.w r2, r2, r6 8000524: fa00 f306 lsl.w r3, r0, r6 8000528: d908 bls.n 800053c <__udivmoddi4+0x220> 800052a: 1861 adds r1, r4, r1 800052c: f109 30ff add.w r0, r9, #4294967295 8000530: d248 bcs.n 80005c4 <__udivmoddi4+0x2a8> 8000532: 458a cmp sl, r1 8000534: d946 bls.n 80005c4 <__udivmoddi4+0x2a8> 8000536: f1a9 0902 sub.w r9, r9, #2 800053a: 4421 add r1, r4 800053c: eba1 010a sub.w r1, r1, sl 8000540: b2bf uxth r7, r7 8000542: fbb1 f0fe udiv r0, r1, lr 8000546: fb0e 1110 mls r1, lr, r0, r1 800054a: ea47 4701 orr.w r7, r7, r1, lsl #16 800054e: fb00 f808 mul.w r8, r0, r8 8000552: 45b8 cmp r8, r7 8000554: d907 bls.n 8000566 <__udivmoddi4+0x24a> 8000556: 19e7 adds r7, r4, r7 8000558: f100 31ff add.w r1, r0, #4294967295 800055c: d22e bcs.n 80005bc <__udivmoddi4+0x2a0> 800055e: 45b8 cmp r8, r7 8000560: d92c bls.n 80005bc <__udivmoddi4+0x2a0> 8000562: 3802 subs r0, #2 8000564: 4427 add r7, r4 8000566: ea40 4009 orr.w r0, r0, r9, lsl #16 800056a: eba7 0708 sub.w r7, r7, r8 800056e: fba0 8902 umull r8, r9, r0, r2 8000572: 454f cmp r7, r9 8000574: 46c6 mov lr, r8 8000576: 4649 mov r1, r9 8000578: d31a bcc.n 80005b0 <__udivmoddi4+0x294> 800057a: d017 beq.n 80005ac <__udivmoddi4+0x290> 800057c: b15d cbz r5, 8000596 <__udivmoddi4+0x27a> 800057e: ebb3 020e subs.w r2, r3, lr 8000582: eb67 0701 sbc.w r7, r7, r1 8000586: fa07 fc0c lsl.w ip, r7, ip 800058a: 40f2 lsrs r2, r6 800058c: ea4c 0202 orr.w r2, ip, r2 8000590: 40f7 lsrs r7, r6 8000592: e9c5 2700 strd r2, r7, [r5] 8000596: 2600 movs r6, #0 8000598: 4631 mov r1, r6 800059a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800059e: 462e mov r6, r5 80005a0: 4628 mov r0, r5 80005a2: e70b b.n 80003bc <__udivmoddi4+0xa0> 80005a4: 4606 mov r6, r0 80005a6: e6e9 b.n 800037c <__udivmoddi4+0x60> 80005a8: 4618 mov r0, r3 80005aa: e6fd b.n 80003a8 <__udivmoddi4+0x8c> 80005ac: 4543 cmp r3, r8 80005ae: d2e5 bcs.n 800057c <__udivmoddi4+0x260> 80005b0: ebb8 0e02 subs.w lr, r8, r2 80005b4: eb69 0104 sbc.w r1, r9, r4 80005b8: 3801 subs r0, #1 80005ba: e7df b.n 800057c <__udivmoddi4+0x260> 80005bc: 4608 mov r0, r1 80005be: e7d2 b.n 8000566 <__udivmoddi4+0x24a> 80005c0: 4660 mov r0, ip 80005c2: e78d b.n 80004e0 <__udivmoddi4+0x1c4> 80005c4: 4681 mov r9, r0 80005c6: e7b9 b.n 800053c <__udivmoddi4+0x220> 80005c8: 4666 mov r6, ip 80005ca: e775 b.n 80004b8 <__udivmoddi4+0x19c> 80005cc: 4630 mov r0, r6 80005ce: e74a b.n 8000466 <__udivmoddi4+0x14a> 80005d0: f1ac 0c02 sub.w ip, ip, #2 80005d4: 4439 add r1, r7 80005d6: e713 b.n 8000400 <__udivmoddi4+0xe4> 80005d8: 3802 subs r0, #2 80005da: 443c add r4, r7 80005dc: e724 b.n 8000428 <__udivmoddi4+0x10c> 80005de: bf00 nop 080005e0 <__aeabi_idiv0>: 80005e0: 4770 bx lr 80005e2: bf00 nop 080005e4
: /** * @brief The application entry point. * @retval int */ int main(void) { 80005e4: b580 push {r7, lr} 80005e6: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 80005e8: f002 fd78 bl 80030dc /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 80005ec: f000 f83a bl 8000664 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 80005f0: f000 ffac bl 800154c MX_DMA_Init(); 80005f4: f000 ff82 bl 80014fc MX_USART1_UART_Init(); 80005f8: f000 fba8 bl 8000d4c MX_USART2_UART_Init(); 80005fc: f000 fbf2 bl 8000de4 MX_I2C2_Init(); 8000600: f000 f8a2 bl 8000748 MX_I2C3_Init(); 8000604: f000 f8e0 bl 80007c8 MX_I2C4_Init(); 8000608: f000 f91e bl 8000848 MX_IWDG1_Init(); 800060c: f000 f95c bl 80008c8 MX_LPTIM1_Init(); 8000610: f000 f978 bl 8000904 MX_LPTIM3_Init(); 8000614: f000 f9a2 bl 800095c MX_LPUART1_UART_Init(); 8000618: f000 f9ca bl 80009b0 MX_UART4_Init(); 800061c: f000 fa16 bl 8000a4c MX_UART7_Init(); 8000620: f000 faac bl 8000b7c MX_UART8_Init(); 8000624: f000 faf6 bl 8000c14 MX_UART9_Init(); 8000628: f000 fb42 bl 8000cb0 MX_USART6_Init(); 800062c: f000 fc74 bl 8000f18 MX_USART10_Init(); 8000630: f000 fcbe bl 8000fb0 MX_OCTOSPI1_Init(); 8000634: f000 fd08 bl 8001048 MX_OCTOSPI2_Init(); 8000638: f000 fd8a bl 8001150 MX_RTC_Init(); 800063c: f000 fe0e bl 800125c MX_SPI2_Init(); 8000640: f000 fe88 bl 8001354 MX_WWDG1_Init(); 8000644: f000 ff3a bl 80014bc MX_FATFS_Init(); 8000648: f00d fdce bl 800e1e8 MX_SDMMC1_SD_Init(); 800064c: f000 fe64 bl 8001318 MX_SPI4_Init(); 8000650: f000 fed6 bl 8001400 MX_UART5_Init(); 8000654: f000 fa46 bl 8000ae4 MX_USART3_UART_Init(); 8000658: f000 fc10 bl 8000e7c MX_USB_OTG_HS_USB_Init(); 800065c: f000 ff26 bl 80014ac /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 8000660: e7fe b.n 8000660 ... 08000664 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000664: b580 push {r7, lr} 8000666: b09c sub sp, #112 ; 0x70 8000668: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800066a: f107 0324 add.w r3, r7, #36 ; 0x24 800066e: 224c movs r2, #76 ; 0x4c 8000670: 2100 movs r1, #0 8000672: 4618 mov r0, r3 8000674: f00d ffd6 bl 800e624 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000678: 1d3b adds r3, r7, #4 800067a: 2220 movs r2, #32 800067c: 2100 movs r1, #0 800067e: 4618 mov r0, r3 8000680: f00d ffd0 bl 800e624 /** Supply configuration update enable */ HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY); 8000684: 2004 movs r0, #4 8000686: f005 ff39 bl 80064fc /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); 800068a: 2300 movs r3, #0 800068c: 603b str r3, [r7, #0] 800068e: 4b2d ldr r3, [pc, #180] ; (8000744 ) 8000690: 699b ldr r3, [r3, #24] 8000692: 4a2c ldr r2, [pc, #176] ; (8000744 ) 8000694: f423 4340 bic.w r3, r3, #49152 ; 0xc000 8000698: 6193 str r3, [r2, #24] 800069a: 4b2a ldr r3, [pc, #168] ; (8000744 ) 800069c: 699b ldr r3, [r3, #24] 800069e: f403 4340 and.w r3, r3, #49152 ; 0xc000 80006a2: 603b str r3, [r7, #0] 80006a4: 683b ldr r3, [r7, #0] while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} 80006a6: bf00 nop 80006a8: 4b26 ldr r3, [pc, #152] ; (8000744 ) 80006aa: 699b ldr r3, [r3, #24] 80006ac: f403 5300 and.w r3, r3, #8192 ; 0x2000 80006b0: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 80006b4: d1f8 bne.n 80006a8 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSI 80006b6: 232a movs r3, #42 ; 0x2a 80006b8: 627b str r3, [r7, #36] ; 0x24 |RCC_OSCILLATORTYPE_LSI; RCC_OscInitStruct.HSIState = RCC_HSI_DIV1; 80006ba: 2301 movs r3, #1 80006bc: 633b str r3, [r7, #48] ; 0x30 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 80006be: 2340 movs r3, #64 ; 0x40 80006c0: 637b str r3, [r7, #52] ; 0x34 RCC_OscInitStruct.LSIState = RCC_LSI_ON; 80006c2: 2301 movs r3, #1 80006c4: 63bb str r3, [r7, #56] ; 0x38 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; 80006c6: 2301 movs r3, #1 80006c8: 63fb str r3, [r7, #60] ; 0x3c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 80006ca: 2302 movs r3, #2 80006cc: 64bb str r3, [r7, #72] ; 0x48 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; 80006ce: 2300 movs r3, #0 80006d0: 64fb str r3, [r7, #76] ; 0x4c RCC_OscInitStruct.PLL.PLLM = 32; 80006d2: 2320 movs r3, #32 80006d4: 653b str r3, [r7, #80] ; 0x50 RCC_OscInitStruct.PLL.PLLN = 129; 80006d6: 2381 movs r3, #129 ; 0x81 80006d8: 657b str r3, [r7, #84] ; 0x54 RCC_OscInitStruct.PLL.PLLP = 2; 80006da: 2302 movs r3, #2 80006dc: 65bb str r3, [r7, #88] ; 0x58 RCC_OscInitStruct.PLL.PLLQ = 2; 80006de: 2302 movs r3, #2 80006e0: 65fb str r3, [r7, #92] ; 0x5c RCC_OscInitStruct.PLL.PLLR = 2; 80006e2: 2302 movs r3, #2 80006e4: 663b str r3, [r7, #96] ; 0x60 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1; 80006e6: 2304 movs r3, #4 80006e8: 667b str r3, [r7, #100] ; 0x64 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; 80006ea: 2300 movs r3, #0 80006ec: 66bb str r3, [r7, #104] ; 0x68 RCC_OscInitStruct.PLL.PLLFRACN = 0; 80006ee: 2300 movs r3, #0 80006f0: 66fb str r3, [r7, #108] ; 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 80006f2: f107 0324 add.w r3, r7, #36 ; 0x24 80006f6: 4618 mov r0, r3 80006f8: f005 ff5a bl 80065b0 80006fc: 4603 mov r3, r0 80006fe: 2b00 cmp r3, #0 8000700: d001 beq.n 8000706 { Error_Handler(); 8000702: f001 f90d bl 8001920 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000706: 233f movs r3, #63 ; 0x3f 8000708: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; 800070a: 2300 movs r3, #0 800070c: 60bb str r3, [r7, #8] RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 800070e: 2300 movs r3, #0 8000710: 60fb str r3, [r7, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1; 8000712: 2300 movs r3, #0 8000714: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; 8000716: 2340 movs r3, #64 ; 0x40 8000718: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; 800071a: 2340 movs r3, #64 ; 0x40 800071c: 61bb str r3, [r7, #24] RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; 800071e: f44f 6380 mov.w r3, #1024 ; 0x400 8000722: 61fb str r3, [r7, #28] RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; 8000724: 2340 movs r3, #64 ; 0x40 8000726: 623b str r3, [r7, #32] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 8000728: 1d3b adds r3, r7, #4 800072a: 2102 movs r1, #2 800072c: 4618 mov r0, r3 800072e: f006 fb43 bl 8006db8 8000732: 4603 mov r3, r0 8000734: 2b00 cmp r3, #0 8000736: d001 beq.n 800073c { Error_Handler(); 8000738: f001 f8f2 bl 8001920 } } 800073c: bf00 nop 800073e: 3770 adds r7, #112 ; 0x70 8000740: 46bd mov sp, r7 8000742: bd80 pop {r7, pc} 8000744: 58024800 .word 0x58024800 08000748 : * @brief I2C2 Initialization Function * @param None * @retval None */ static void MX_I2C2_Init(void) { 8000748: b580 push {r7, lr} 800074a: af00 add r7, sp, #0 /* USER CODE END I2C2_Init 0 */ /* USER CODE BEGIN I2C2_Init 1 */ /* USER CODE END I2C2_Init 1 */ hi2c2.Instance = I2C2; 800074c: 4b1b ldr r3, [pc, #108] ; (80007bc ) 800074e: 4a1c ldr r2, [pc, #112] ; (80007c0 ) 8000750: 601a str r2, [r3, #0] hi2c2.Init.Timing = 0x00707CBB; 8000752: 4b1a ldr r3, [pc, #104] ; (80007bc ) 8000754: 4a1b ldr r2, [pc, #108] ; (80007c4 ) 8000756: 605a str r2, [r3, #4] hi2c2.Init.OwnAddress1 = 0; 8000758: 4b18 ldr r3, [pc, #96] ; (80007bc ) 800075a: 2200 movs r2, #0 800075c: 609a str r2, [r3, #8] hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 800075e: 4b17 ldr r3, [pc, #92] ; (80007bc ) 8000760: 2201 movs r2, #1 8000762: 60da str r2, [r3, #12] hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 8000764: 4b15 ldr r3, [pc, #84] ; (80007bc ) 8000766: 2200 movs r2, #0 8000768: 611a str r2, [r3, #16] hi2c2.Init.OwnAddress2 = 0; 800076a: 4b14 ldr r3, [pc, #80] ; (80007bc ) 800076c: 2200 movs r2, #0 800076e: 615a str r2, [r3, #20] hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK; 8000770: 4b12 ldr r3, [pc, #72] ; (80007bc ) 8000772: 2200 movs r2, #0 8000774: 619a str r2, [r3, #24] hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 8000776: 4b11 ldr r3, [pc, #68] ; (80007bc ) 8000778: 2200 movs r2, #0 800077a: 61da str r2, [r3, #28] hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 800077c: 4b0f ldr r3, [pc, #60] ; (80007bc ) 800077e: 2200 movs r2, #0 8000780: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c2) != HAL_OK) 8000782: 480e ldr r0, [pc, #56] ; (80007bc ) 8000784: f004 fd80 bl 8005288 8000788: 4603 mov r3, r0 800078a: 2b00 cmp r3, #0 800078c: d001 beq.n 8000792 { Error_Handler(); 800078e: f001 f8c7 bl 8001920 } /** Configure Analogue filter */ if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK) 8000792: 2100 movs r1, #0 8000794: 4809 ldr r0, [pc, #36] ; (80007bc ) 8000796: f004 fe07 bl 80053a8 800079a: 4603 mov r3, r0 800079c: 2b00 cmp r3, #0 800079e: d001 beq.n 80007a4 { Error_Handler(); 80007a0: f001 f8be bl 8001920 } /** Configure Digital filter */ if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK) 80007a4: 2100 movs r1, #0 80007a6: 4805 ldr r0, [pc, #20] ; (80007bc ) 80007a8: f004 fe49 bl 800543e 80007ac: 4603 mov r3, r0 80007ae: 2b00 cmp r3, #0 80007b0: d001 beq.n 80007b6 { Error_Handler(); 80007b2: f001 f8b5 bl 8001920 } /* USER CODE BEGIN I2C2_Init 2 */ /* USER CODE END I2C2_Init 2 */ } 80007b6: bf00 nop 80007b8: bd80 pop {r7, pc} 80007ba: bf00 nop 80007bc: 20000454 .word 0x20000454 80007c0: 40005800 .word 0x40005800 80007c4: 00707cbb .word 0x00707cbb 080007c8 : * @brief I2C3 Initialization Function * @param None * @retval None */ static void MX_I2C3_Init(void) { 80007c8: b580 push {r7, lr} 80007ca: af00 add r7, sp, #0 /* USER CODE END I2C3_Init 0 */ /* USER CODE BEGIN I2C3_Init 1 */ /* USER CODE END I2C3_Init 1 */ hi2c3.Instance = I2C3; 80007cc: 4b1b ldr r3, [pc, #108] ; (800083c ) 80007ce: 4a1c ldr r2, [pc, #112] ; (8000840 ) 80007d0: 601a str r2, [r3, #0] hi2c3.Init.Timing = 0x00707CBB; 80007d2: 4b1a ldr r3, [pc, #104] ; (800083c ) 80007d4: 4a1b ldr r2, [pc, #108] ; (8000844 ) 80007d6: 605a str r2, [r3, #4] hi2c3.Init.OwnAddress1 = 0; 80007d8: 4b18 ldr r3, [pc, #96] ; (800083c ) 80007da: 2200 movs r2, #0 80007dc: 609a str r2, [r3, #8] hi2c3.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 80007de: 4b17 ldr r3, [pc, #92] ; (800083c ) 80007e0: 2201 movs r2, #1 80007e2: 60da str r2, [r3, #12] hi2c3.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 80007e4: 4b15 ldr r3, [pc, #84] ; (800083c ) 80007e6: 2200 movs r2, #0 80007e8: 611a str r2, [r3, #16] hi2c3.Init.OwnAddress2 = 0; 80007ea: 4b14 ldr r3, [pc, #80] ; (800083c ) 80007ec: 2200 movs r2, #0 80007ee: 615a str r2, [r3, #20] hi2c3.Init.OwnAddress2Masks = I2C_OA2_NOMASK; 80007f0: 4b12 ldr r3, [pc, #72] ; (800083c ) 80007f2: 2200 movs r2, #0 80007f4: 619a str r2, [r3, #24] hi2c3.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 80007f6: 4b11 ldr r3, [pc, #68] ; (800083c ) 80007f8: 2200 movs r2, #0 80007fa: 61da str r2, [r3, #28] hi2c3.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 80007fc: 4b0f ldr r3, [pc, #60] ; (800083c ) 80007fe: 2200 movs r2, #0 8000800: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c3) != HAL_OK) 8000802: 480e ldr r0, [pc, #56] ; (800083c ) 8000804: f004 fd40 bl 8005288 8000808: 4603 mov r3, r0 800080a: 2b00 cmp r3, #0 800080c: d001 beq.n 8000812 { Error_Handler(); 800080e: f001 f887 bl 8001920 } /** Configure Analogue filter */ if (HAL_I2CEx_ConfigAnalogFilter(&hi2c3, I2C_ANALOGFILTER_ENABLE) != HAL_OK) 8000812: 2100 movs r1, #0 8000814: 4809 ldr r0, [pc, #36] ; (800083c ) 8000816: f004 fdc7 bl 80053a8 800081a: 4603 mov r3, r0 800081c: 2b00 cmp r3, #0 800081e: d001 beq.n 8000824 { Error_Handler(); 8000820: f001 f87e bl 8001920 } /** Configure Digital filter */ if (HAL_I2CEx_ConfigDigitalFilter(&hi2c3, 0) != HAL_OK) 8000824: 2100 movs r1, #0 8000826: 4805 ldr r0, [pc, #20] ; (800083c ) 8000828: f004 fe09 bl 800543e 800082c: 4603 mov r3, r0 800082e: 2b00 cmp r3, #0 8000830: d001 beq.n 8000836 { Error_Handler(); 8000832: f001 f875 bl 8001920 } /* USER CODE BEGIN I2C3_Init 2 */ /* USER CODE END I2C3_Init 2 */ } 8000836: bf00 nop 8000838: bd80 pop {r7, pc} 800083a: bf00 nop 800083c: 20000114 .word 0x20000114 8000840: 40005c00 .word 0x40005c00 8000844: 00707cbb .word 0x00707cbb 08000848 : * @brief I2C4 Initialization Function * @param None * @retval None */ static void MX_I2C4_Init(void) { 8000848: b580 push {r7, lr} 800084a: af00 add r7, sp, #0 /* USER CODE END I2C4_Init 0 */ /* USER CODE BEGIN I2C4_Init 1 */ /* USER CODE END I2C4_Init 1 */ hi2c4.Instance = I2C4; 800084c: 4b1b ldr r3, [pc, #108] ; (80008bc ) 800084e: 4a1c ldr r2, [pc, #112] ; (80008c0 ) 8000850: 601a str r2, [r3, #0] hi2c4.Init.Timing = 0x00707CBB; 8000852: 4b1a ldr r3, [pc, #104] ; (80008bc ) 8000854: 4a1b ldr r2, [pc, #108] ; (80008c4 ) 8000856: 605a str r2, [r3, #4] hi2c4.Init.OwnAddress1 = 0; 8000858: 4b18 ldr r3, [pc, #96] ; (80008bc ) 800085a: 2200 movs r2, #0 800085c: 609a str r2, [r3, #8] hi2c4.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 800085e: 4b17 ldr r3, [pc, #92] ; (80008bc ) 8000860: 2201 movs r2, #1 8000862: 60da str r2, [r3, #12] hi2c4.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 8000864: 4b15 ldr r3, [pc, #84] ; (80008bc ) 8000866: 2200 movs r2, #0 8000868: 611a str r2, [r3, #16] hi2c4.Init.OwnAddress2 = 0; 800086a: 4b14 ldr r3, [pc, #80] ; (80008bc ) 800086c: 2200 movs r2, #0 800086e: 615a str r2, [r3, #20] hi2c4.Init.OwnAddress2Masks = I2C_OA2_NOMASK; 8000870: 4b12 ldr r3, [pc, #72] ; (80008bc ) 8000872: 2200 movs r2, #0 8000874: 619a str r2, [r3, #24] hi2c4.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 8000876: 4b11 ldr r3, [pc, #68] ; (80008bc ) 8000878: 2200 movs r2, #0 800087a: 61da str r2, [r3, #28] hi2c4.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 800087c: 4b0f ldr r3, [pc, #60] ; (80008bc ) 800087e: 2200 movs r2, #0 8000880: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c4) != HAL_OK) 8000882: 480e ldr r0, [pc, #56] ; (80008bc ) 8000884: f004 fd00 bl 8005288 8000888: 4603 mov r3, r0 800088a: 2b00 cmp r3, #0 800088c: d001 beq.n 8000892 { Error_Handler(); 800088e: f001 f847 bl 8001920 } /** Configure Analogue filter */ if (HAL_I2CEx_ConfigAnalogFilter(&hi2c4, I2C_ANALOGFILTER_ENABLE) != HAL_OK) 8000892: 2100 movs r1, #0 8000894: 4809 ldr r0, [pc, #36] ; (80008bc ) 8000896: f004 fd87 bl 80053a8 800089a: 4603 mov r3, r0 800089c: 2b00 cmp r3, #0 800089e: d001 beq.n 80008a4 { Error_Handler(); 80008a0: f001 f83e bl 8001920 } /** Configure Digital filter */ if (HAL_I2CEx_ConfigDigitalFilter(&hi2c4, 0) != HAL_OK) 80008a4: 2100 movs r1, #0 80008a6: 4805 ldr r0, [pc, #20] ; (80008bc ) 80008a8: f004 fdc9 bl 800543e 80008ac: 4603 mov r3, r0 80008ae: 2b00 cmp r3, #0 80008b0: d001 beq.n 80008b6 { Error_Handler(); 80008b2: f001 f835 bl 8001920 } /* USER CODE BEGIN I2C4_Init 2 */ /* USER CODE END I2C4_Init 2 */ } 80008b6: bf00 nop 80008b8: bd80 pop {r7, pc} 80008ba: bf00 nop 80008bc: 20000160 .word 0x20000160 80008c0: 58001c00 .word 0x58001c00 80008c4: 00707cbb .word 0x00707cbb 080008c8 : * @brief IWDG1 Initialization Function * @param None * @retval None */ static void MX_IWDG1_Init(void) { 80008c8: b580 push {r7, lr} 80008ca: af00 add r7, sp, #0 /* USER CODE END IWDG1_Init 0 */ /* USER CODE BEGIN IWDG1_Init 1 */ /* USER CODE END IWDG1_Init 1 */ hiwdg1.Instance = IWDG1; 80008cc: 4b0b ldr r3, [pc, #44] ; (80008fc ) 80008ce: 4a0c ldr r2, [pc, #48] ; (8000900 ) 80008d0: 601a str r2, [r3, #0] hiwdg1.Init.Prescaler = IWDG_PRESCALER_4; 80008d2: 4b0a ldr r3, [pc, #40] ; (80008fc ) 80008d4: 2200 movs r2, #0 80008d6: 605a str r2, [r3, #4] hiwdg1.Init.Window = 4095; 80008d8: 4b08 ldr r3, [pc, #32] ; (80008fc ) 80008da: f640 72ff movw r2, #4095 ; 0xfff 80008de: 60da str r2, [r3, #12] hiwdg1.Init.Reload = 4095; 80008e0: 4b06 ldr r3, [pc, #24] ; (80008fc ) 80008e2: f640 72ff movw r2, #4095 ; 0xfff 80008e6: 609a str r2, [r3, #8] if (HAL_IWDG_Init(&hiwdg1) != HAL_OK) 80008e8: 4804 ldr r0, [pc, #16] ; (80008fc ) 80008ea: f004 fdf4 bl 80054d6 80008ee: 4603 mov r3, r0 80008f0: 2b00 cmp r3, #0 80008f2: d001 beq.n 80008f8 { Error_Handler(); 80008f4: f001 f814 bl 8001920 } /* USER CODE BEGIN IWDG1_Init 2 */ /* USER CODE END IWDG1_Init 2 */ } 80008f8: bf00 nop 80008fa: bd80 pop {r7, pc} 80008fc: 200001ac .word 0x200001ac 8000900: 58004800 .word 0x58004800 08000904 : * @brief LPTIM1 Initialization Function * @param None * @retval None */ static void MX_LPTIM1_Init(void) { 8000904: b580 push {r7, lr} 8000906: af00 add r7, sp, #0 /* USER CODE END LPTIM1_Init 0 */ /* USER CODE BEGIN LPTIM1_Init 1 */ /* USER CODE END LPTIM1_Init 1 */ hlptim1.Instance = LPTIM1; 8000908: 4b12 ldr r3, [pc, #72] ; (8000954 ) 800090a: 4a13 ldr r2, [pc, #76] ; (8000958 ) 800090c: 601a str r2, [r3, #0] hlptim1.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC; 800090e: 4b11 ldr r3, [pc, #68] ; (8000954 ) 8000910: 2200 movs r2, #0 8000912: 605a str r2, [r3, #4] hlptim1.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV1; 8000914: 4b0f ldr r3, [pc, #60] ; (8000954 ) 8000916: 2200 movs r2, #0 8000918: 609a str r2, [r3, #8] hlptim1.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE; 800091a: 4b0e ldr r3, [pc, #56] ; (8000954 ) 800091c: f64f 72ff movw r2, #65535 ; 0xffff 8000920: 615a str r2, [r3, #20] hlptim1.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH; 8000922: 4b0c ldr r3, [pc, #48] ; (8000954 ) 8000924: 2200 movs r2, #0 8000926: 621a str r2, [r3, #32] hlptim1.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE; 8000928: 4b0a ldr r3, [pc, #40] ; (8000954 ) 800092a: 2200 movs r2, #0 800092c: 625a str r2, [r3, #36] ; 0x24 hlptim1.Init.CounterSource = LPTIM_COUNTERSOURCE_INTERNAL; 800092e: 4b09 ldr r3, [pc, #36] ; (8000954 ) 8000930: 2200 movs r2, #0 8000932: 629a str r2, [r3, #40] ; 0x28 hlptim1.Init.Input1Source = LPTIM_INPUT1SOURCE_GPIO; 8000934: 4b07 ldr r3, [pc, #28] ; (8000954 ) 8000936: 2200 movs r2, #0 8000938: 62da str r2, [r3, #44] ; 0x2c hlptim1.Init.Input2Source = LPTIM_INPUT2SOURCE_GPIO; 800093a: 4b06 ldr r3, [pc, #24] ; (8000954 ) 800093c: 2200 movs r2, #0 800093e: 631a str r2, [r3, #48] ; 0x30 if (HAL_LPTIM_Init(&hlptim1) != HAL_OK) 8000940: 4804 ldr r0, [pc, #16] ; (8000954 ) 8000942: f004 fe17 bl 8005574 8000946: 4603 mov r3, r0 8000948: 2b00 cmp r3, #0 800094a: d001 beq.n 8000950 { Error_Handler(); 800094c: f000 ffe8 bl 8001920 } /* USER CODE BEGIN LPTIM1_Init 2 */ /* USER CODE END LPTIM1_Init 2 */ } 8000950: bf00 nop 8000952: bd80 pop {r7, pc} 8000954: 2000077c .word 0x2000077c 8000958: 40002400 .word 0x40002400 0800095c : * @brief LPTIM3 Initialization Function * @param None * @retval None */ static void MX_LPTIM3_Init(void) { 800095c: b580 push {r7, lr} 800095e: af00 add r7, sp, #0 /* USER CODE END LPTIM3_Init 0 */ /* USER CODE BEGIN LPTIM3_Init 1 */ /* USER CODE END LPTIM3_Init 1 */ hlptim3.Instance = LPTIM3; 8000960: 4b11 ldr r3, [pc, #68] ; (80009a8 ) 8000962: 4a12 ldr r2, [pc, #72] ; (80009ac ) 8000964: 601a str r2, [r3, #0] hlptim3.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC; 8000966: 4b10 ldr r3, [pc, #64] ; (80009a8 ) 8000968: 2200 movs r2, #0 800096a: 605a str r2, [r3, #4] hlptim3.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV1; 800096c: 4b0e ldr r3, [pc, #56] ; (80009a8 ) 800096e: 2200 movs r2, #0 8000970: 609a str r2, [r3, #8] hlptim3.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE; 8000972: 4b0d ldr r3, [pc, #52] ; (80009a8 ) 8000974: f64f 72ff movw r2, #65535 ; 0xffff 8000978: 615a str r2, [r3, #20] hlptim3.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH; 800097a: 4b0b ldr r3, [pc, #44] ; (80009a8 ) 800097c: 2200 movs r2, #0 800097e: 621a str r2, [r3, #32] hlptim3.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE; 8000980: 4b09 ldr r3, [pc, #36] ; (80009a8 ) 8000982: 2200 movs r2, #0 8000984: 625a str r2, [r3, #36] ; 0x24 hlptim3.Init.CounterSource = LPTIM_COUNTERSOURCE_INTERNAL; 8000986: 4b08 ldr r3, [pc, #32] ; (80009a8 ) 8000988: 2200 movs r2, #0 800098a: 629a str r2, [r3, #40] ; 0x28 hlptim3.Init.Input1Source = LPTIM_INPUT1SOURCE_GPIO; 800098c: 4b06 ldr r3, [pc, #24] ; (80009a8 ) 800098e: 2200 movs r2, #0 8000990: 62da str r2, [r3, #44] ; 0x2c if (HAL_LPTIM_Init(&hlptim3) != HAL_OK) 8000992: 4805 ldr r0, [pc, #20] ; (80009a8 ) 8000994: f004 fdee bl 8005574 8000998: 4603 mov r3, r0 800099a: 2b00 cmp r3, #0 800099c: d001 beq.n 80009a2 { Error_Handler(); 800099e: f000 ffbf bl 8001920 } /* USER CODE BEGIN LPTIM3_Init 2 */ /* USER CODE END LPTIM3_Init 2 */ } 80009a2: bf00 nop 80009a4: bd80 pop {r7, pc} 80009a6: bf00 nop 80009a8: 2000051c .word 0x2000051c 80009ac: 58002800 .word 0x58002800 080009b0 : * @brief LPUART1 Initialization Function * @param None * @retval None */ static void MX_LPUART1_UART_Init(void) { 80009b0: b580 push {r7, lr} 80009b2: af00 add r7, sp, #0 /* USER CODE END LPUART1_Init 0 */ /* USER CODE BEGIN LPUART1_Init 1 */ /* USER CODE END LPUART1_Init 1 */ hlpuart1.Instance = LPUART1; 80009b4: 4b22 ldr r3, [pc, #136] ; (8000a40 ) 80009b6: 4a23 ldr r2, [pc, #140] ; (8000a44 ) 80009b8: 601a str r2, [r3, #0] hlpuart1.Init.BaudRate = 209700; 80009ba: 4b21 ldr r3, [pc, #132] ; (8000a40 ) 80009bc: 4a22 ldr r2, [pc, #136] ; (8000a48 ) 80009be: 605a str r2, [r3, #4] hlpuart1.Init.WordLength = UART_WORDLENGTH_8B; 80009c0: 4b1f ldr r3, [pc, #124] ; (8000a40 ) 80009c2: 2200 movs r2, #0 80009c4: 609a str r2, [r3, #8] hlpuart1.Init.StopBits = UART_STOPBITS_1; 80009c6: 4b1e ldr r3, [pc, #120] ; (8000a40 ) 80009c8: 2200 movs r2, #0 80009ca: 60da str r2, [r3, #12] hlpuart1.Init.Parity = UART_PARITY_NONE; 80009cc: 4b1c ldr r3, [pc, #112] ; (8000a40 ) 80009ce: 2200 movs r2, #0 80009d0: 611a str r2, [r3, #16] hlpuart1.Init.Mode = UART_MODE_TX_RX; 80009d2: 4b1b ldr r3, [pc, #108] ; (8000a40 ) 80009d4: 220c movs r2, #12 80009d6: 615a str r2, [r3, #20] hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80009d8: 4b19 ldr r3, [pc, #100] ; (8000a40 ) 80009da: 2200 movs r2, #0 80009dc: 619a str r2, [r3, #24] hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 80009de: 4b18 ldr r3, [pc, #96] ; (8000a40 ) 80009e0: 2200 movs r2, #0 80009e2: 621a str r2, [r3, #32] hlpuart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; 80009e4: 4b16 ldr r3, [pc, #88] ; (8000a40 ) 80009e6: 2200 movs r2, #0 80009e8: 625a str r2, [r3, #36] ; 0x24 hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 80009ea: 4b15 ldr r3, [pc, #84] ; (8000a40 ) 80009ec: 2200 movs r2, #0 80009ee: 629a str r2, [r3, #40] ; 0x28 hlpuart1.FifoMode = UART_FIFOMODE_DISABLE; 80009f0: 4b13 ldr r3, [pc, #76] ; (8000a40 ) 80009f2: 2200 movs r2, #0 80009f4: 665a str r2, [r3, #100] ; 0x64 if (HAL_UART_Init(&hlpuart1) != HAL_OK) 80009f6: 4812 ldr r0, [pc, #72] ; (8000a40 ) 80009f8: f00a fd3d bl 800b476 80009fc: 4603 mov r3, r0 80009fe: 2b00 cmp r3, #0 8000a00: d001 beq.n 8000a06 { Error_Handler(); 8000a02: f000 ff8d bl 8001920 } if (HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8000a06: 2100 movs r1, #0 8000a08: 480d ldr r0, [pc, #52] ; (8000a40 ) 8000a0a: f00b fdd1 bl 800c5b0 8000a0e: 4603 mov r3, r0 8000a10: 2b00 cmp r3, #0 8000a12: d001 beq.n 8000a18 { Error_Handler(); 8000a14: f000 ff84 bl 8001920 } if (HAL_UARTEx_SetRxFifoThreshold(&hlpuart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 8000a18: 2100 movs r1, #0 8000a1a: 4809 ldr r0, [pc, #36] ; (8000a40 ) 8000a1c: f00b fe06 bl 800c62c 8000a20: 4603 mov r3, r0 8000a22: 2b00 cmp r3, #0 8000a24: d001 beq.n 8000a2a { Error_Handler(); 8000a26: f000 ff7b bl 8001920 } if (HAL_UARTEx_DisableFifoMode(&hlpuart1) != HAL_OK) 8000a2a: 4805 ldr r0, [pc, #20] ; (8000a40 ) 8000a2c: f00b fd87 bl 800c53e 8000a30: 4603 mov r3, r0 8000a32: 2b00 cmp r3, #0 8000a34: d001 beq.n 8000a3a { Error_Handler(); 8000a36: f000 ff73 bl 8001920 } /* USER CODE BEGIN LPUART1_Init 2 */ /* USER CODE END LPUART1_Init 2 */ } 8000a3a: bf00 nop 8000a3c: bd80 pop {r7, pc} 8000a3e: bf00 nop 8000a40: 20000554 .word 0x20000554 8000a44: 58000c00 .word 0x58000c00 8000a48: 00033324 .word 0x00033324 08000a4c : * @brief UART4 Initialization Function * @param None * @retval None */ static void MX_UART4_Init(void) { 8000a4c: b580 push {r7, lr} 8000a4e: af00 add r7, sp, #0 /* USER CODE END UART4_Init 0 */ /* USER CODE BEGIN UART4_Init 1 */ /* USER CODE END UART4_Init 1 */ huart4.Instance = UART4; 8000a50: 4b22 ldr r3, [pc, #136] ; (8000adc ) 8000a52: 4a23 ldr r2, [pc, #140] ; (8000ae0 ) 8000a54: 601a str r2, [r3, #0] huart4.Init.BaudRate = 115200; 8000a56: 4b21 ldr r3, [pc, #132] ; (8000adc ) 8000a58: f44f 32e1 mov.w r2, #115200 ; 0x1c200 8000a5c: 605a str r2, [r3, #4] huart4.Init.WordLength = UART_WORDLENGTH_8B; 8000a5e: 4b1f ldr r3, [pc, #124] ; (8000adc ) 8000a60: 2200 movs r2, #0 8000a62: 609a str r2, [r3, #8] huart4.Init.StopBits = UART_STOPBITS_1; 8000a64: 4b1d ldr r3, [pc, #116] ; (8000adc ) 8000a66: 2200 movs r2, #0 8000a68: 60da str r2, [r3, #12] huart4.Init.Parity = UART_PARITY_NONE; 8000a6a: 4b1c ldr r3, [pc, #112] ; (8000adc ) 8000a6c: 2200 movs r2, #0 8000a6e: 611a str r2, [r3, #16] huart4.Init.Mode = UART_MODE_TX_RX; 8000a70: 4b1a ldr r3, [pc, #104] ; (8000adc ) 8000a72: 220c movs r2, #12 8000a74: 615a str r2, [r3, #20] huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8000a76: 4b19 ldr r3, [pc, #100] ; (8000adc ) 8000a78: 2200 movs r2, #0 8000a7a: 619a str r2, [r3, #24] huart4.Init.OverSampling = UART_OVERSAMPLING_16; 8000a7c: 4b17 ldr r3, [pc, #92] ; (8000adc ) 8000a7e: 2200 movs r2, #0 8000a80: 61da str r2, [r3, #28] huart4.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 8000a82: 4b16 ldr r3, [pc, #88] ; (8000adc ) 8000a84: 2200 movs r2, #0 8000a86: 621a str r2, [r3, #32] huart4.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8000a88: 4b14 ldr r3, [pc, #80] ; (8000adc ) 8000a8a: 2200 movs r2, #0 8000a8c: 625a str r2, [r3, #36] ; 0x24 huart4.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 8000a8e: 4b13 ldr r3, [pc, #76] ; (8000adc ) 8000a90: 2200 movs r2, #0 8000a92: 629a str r2, [r3, #40] ; 0x28 if (HAL_UART_Init(&huart4) != HAL_OK) 8000a94: 4811 ldr r0, [pc, #68] ; (8000adc ) 8000a96: f00a fcee bl 800b476 8000a9a: 4603 mov r3, r0 8000a9c: 2b00 cmp r3, #0 8000a9e: d001 beq.n 8000aa4 { Error_Handler(); 8000aa0: f000 ff3e bl 8001920 } if (HAL_UARTEx_SetTxFifoThreshold(&huart4, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8000aa4: 2100 movs r1, #0 8000aa6: 480d ldr r0, [pc, #52] ; (8000adc ) 8000aa8: f00b fd82 bl 800c5b0 8000aac: 4603 mov r3, r0 8000aae: 2b00 cmp r3, #0 8000ab0: d001 beq.n 8000ab6 { Error_Handler(); 8000ab2: f000 ff35 bl 8001920 } if (HAL_UARTEx_SetRxFifoThreshold(&huart4, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 8000ab6: 2100 movs r1, #0 8000ab8: 4808 ldr r0, [pc, #32] ; (8000adc ) 8000aba: f00b fdb7 bl 800c62c 8000abe: 4603 mov r3, r0 8000ac0: 2b00 cmp r3, #0 8000ac2: d001 beq.n 8000ac8 { Error_Handler(); 8000ac4: f000 ff2c bl 8001920 } if (HAL_UARTEx_DisableFifoMode(&huart4) != HAL_OK) 8000ac8: 4804 ldr r0, [pc, #16] ; (8000adc ) 8000aca: f00b fd38 bl 800c53e 8000ace: 4603 mov r3, r0 8000ad0: 2b00 cmp r3, #0 8000ad2: d001 beq.n 8000ad8 { Error_Handler(); 8000ad4: f000 ff24 bl 8001920 } /* USER CODE BEGIN UART4_Init 2 */ /* USER CODE END UART4_Init 2 */ } 8000ad8: bf00 nop 8000ada: bd80 pop {r7, pc} 8000adc: 200008f4 .word 0x200008f4 8000ae0: 40004c00 .word 0x40004c00 08000ae4 : * @brief UART5 Initialization Function * @param None * @retval None */ static void MX_UART5_Init(void) { 8000ae4: b580 push {r7, lr} 8000ae6: af00 add r7, sp, #0 /* USER CODE END UART5_Init 0 */ /* USER CODE BEGIN UART5_Init 1 */ /* USER CODE END UART5_Init 1 */ huart5.Instance = UART5; 8000ae8: 4b22 ldr r3, [pc, #136] ; (8000b74 ) 8000aea: 4a23 ldr r2, [pc, #140] ; (8000b78 ) 8000aec: 601a str r2, [r3, #0] huart5.Init.BaudRate = 115200; 8000aee: 4b21 ldr r3, [pc, #132] ; (8000b74 ) 8000af0: f44f 32e1 mov.w r2, #115200 ; 0x1c200 8000af4: 605a str r2, [r3, #4] huart5.Init.WordLength = UART_WORDLENGTH_8B; 8000af6: 4b1f ldr r3, [pc, #124] ; (8000b74 ) 8000af8: 2200 movs r2, #0 8000afa: 609a str r2, [r3, #8] huart5.Init.StopBits = UART_STOPBITS_1; 8000afc: 4b1d ldr r3, [pc, #116] ; (8000b74 ) 8000afe: 2200 movs r2, #0 8000b00: 60da str r2, [r3, #12] huart5.Init.Parity = UART_PARITY_NONE; 8000b02: 4b1c ldr r3, [pc, #112] ; (8000b74 ) 8000b04: 2200 movs r2, #0 8000b06: 611a str r2, [r3, #16] huart5.Init.Mode = UART_MODE_TX_RX; 8000b08: 4b1a ldr r3, [pc, #104] ; (8000b74 ) 8000b0a: 220c movs r2, #12 8000b0c: 615a str r2, [r3, #20] huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8000b0e: 4b19 ldr r3, [pc, #100] ; (8000b74 ) 8000b10: 2200 movs r2, #0 8000b12: 619a str r2, [r3, #24] huart5.Init.OverSampling = UART_OVERSAMPLING_16; 8000b14: 4b17 ldr r3, [pc, #92] ; (8000b74 ) 8000b16: 2200 movs r2, #0 8000b18: 61da str r2, [r3, #28] huart5.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 8000b1a: 4b16 ldr r3, [pc, #88] ; (8000b74 ) 8000b1c: 2200 movs r2, #0 8000b1e: 621a str r2, [r3, #32] huart5.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8000b20: 4b14 ldr r3, [pc, #80] ; (8000b74 ) 8000b22: 2200 movs r2, #0 8000b24: 625a str r2, [r3, #36] ; 0x24 huart5.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 8000b26: 4b13 ldr r3, [pc, #76] ; (8000b74 ) 8000b28: 2200 movs r2, #0 8000b2a: 629a str r2, [r3, #40] ; 0x28 if (HAL_UART_Init(&huart5) != HAL_OK) 8000b2c: 4811 ldr r0, [pc, #68] ; (8000b74 ) 8000b2e: f00a fca2 bl 800b476 8000b32: 4603 mov r3, r0 8000b34: 2b00 cmp r3, #0 8000b36: d001 beq.n 8000b3c { Error_Handler(); 8000b38: f000 fef2 bl 8001920 } if (HAL_UARTEx_SetTxFifoThreshold(&huart5, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8000b3c: 2100 movs r1, #0 8000b3e: 480d ldr r0, [pc, #52] ; (8000b74 ) 8000b40: f00b fd36 bl 800c5b0 8000b44: 4603 mov r3, r0 8000b46: 2b00 cmp r3, #0 8000b48: d001 beq.n 8000b4e { Error_Handler(); 8000b4a: f000 fee9 bl 8001920 } if (HAL_UARTEx_SetRxFifoThreshold(&huart5, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 8000b4e: 2100 movs r1, #0 8000b50: 4808 ldr r0, [pc, #32] ; (8000b74 ) 8000b52: f00b fd6b bl 800c62c 8000b56: 4603 mov r3, r0 8000b58: 2b00 cmp r3, #0 8000b5a: d001 beq.n 8000b60 { Error_Handler(); 8000b5c: f000 fee0 bl 8001920 } if (HAL_UARTEx_DisableFifoMode(&huart5) != HAL_OK) 8000b60: 4804 ldr r0, [pc, #16] ; (8000b74 ) 8000b62: f00b fcec bl 800c53e 8000b66: 4603 mov r3, r0 8000b68: 2b00 cmp r3, #0 8000b6a: d001 beq.n 8000b70 { Error_Handler(); 8000b6c: f000 fed8 bl 8001920 } /* USER CODE BEGIN UART5_Init 2 */ /* USER CODE END UART5_Init 2 */ } 8000b70: bf00 nop 8000b72: bd80 pop {r7, pc} 8000b74: 200005e4 .word 0x200005e4 8000b78: 40005000 .word 0x40005000 08000b7c : * @brief UART7 Initialization Function * @param None * @retval None */ static void MX_UART7_Init(void) { 8000b7c: b580 push {r7, lr} 8000b7e: af00 add r7, sp, #0 /* USER CODE END UART7_Init 0 */ /* USER CODE BEGIN UART7_Init 1 */ /* USER CODE END UART7_Init 1 */ huart7.Instance = UART7; 8000b80: 4b22 ldr r3, [pc, #136] ; (8000c0c ) 8000b82: 4a23 ldr r2, [pc, #140] ; (8000c10 ) 8000b84: 601a str r2, [r3, #0] huart7.Init.BaudRate = 115200; 8000b86: 4b21 ldr r3, [pc, #132] ; (8000c0c ) 8000b88: f44f 32e1 mov.w r2, #115200 ; 0x1c200 8000b8c: 605a str r2, [r3, #4] huart7.Init.WordLength = UART_WORDLENGTH_8B; 8000b8e: 4b1f ldr r3, [pc, #124] ; (8000c0c ) 8000b90: 2200 movs r2, #0 8000b92: 609a str r2, [r3, #8] huart7.Init.StopBits = UART_STOPBITS_1; 8000b94: 4b1d ldr r3, [pc, #116] ; (8000c0c ) 8000b96: 2200 movs r2, #0 8000b98: 60da str r2, [r3, #12] huart7.Init.Parity = UART_PARITY_NONE; 8000b9a: 4b1c ldr r3, [pc, #112] ; (8000c0c ) 8000b9c: 2200 movs r2, #0 8000b9e: 611a str r2, [r3, #16] huart7.Init.Mode = UART_MODE_TX_RX; 8000ba0: 4b1a ldr r3, [pc, #104] ; (8000c0c ) 8000ba2: 220c movs r2, #12 8000ba4: 615a str r2, [r3, #20] huart7.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8000ba6: 4b19 ldr r3, [pc, #100] ; (8000c0c ) 8000ba8: 2200 movs r2, #0 8000baa: 619a str r2, [r3, #24] huart7.Init.OverSampling = UART_OVERSAMPLING_16; 8000bac: 4b17 ldr r3, [pc, #92] ; (8000c0c ) 8000bae: 2200 movs r2, #0 8000bb0: 61da str r2, [r3, #28] huart7.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 8000bb2: 4b16 ldr r3, [pc, #88] ; (8000c0c ) 8000bb4: 2200 movs r2, #0 8000bb6: 621a str r2, [r3, #32] huart7.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8000bb8: 4b14 ldr r3, [pc, #80] ; (8000c0c ) 8000bba: 2200 movs r2, #0 8000bbc: 625a str r2, [r3, #36] ; 0x24 huart7.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 8000bbe: 4b13 ldr r3, [pc, #76] ; (8000c0c ) 8000bc0: 2200 movs r2, #0 8000bc2: 629a str r2, [r3, #40] ; 0x28 if (HAL_UART_Init(&huart7) != HAL_OK) 8000bc4: 4811 ldr r0, [pc, #68] ; (8000c0c ) 8000bc6: f00a fc56 bl 800b476 8000bca: 4603 mov r3, r0 8000bcc: 2b00 cmp r3, #0 8000bce: d001 beq.n 8000bd4 { Error_Handler(); 8000bd0: f000 fea6 bl 8001920 } if (HAL_UARTEx_SetTxFifoThreshold(&huart7, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8000bd4: 2100 movs r1, #0 8000bd6: 480d ldr r0, [pc, #52] ; (8000c0c ) 8000bd8: f00b fcea bl 800c5b0 8000bdc: 4603 mov r3, r0 8000bde: 2b00 cmp r3, #0 8000be0: d001 beq.n 8000be6 { Error_Handler(); 8000be2: f000 fe9d bl 8001920 } if (HAL_UARTEx_SetRxFifoThreshold(&huart7, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 8000be6: 2100 movs r1, #0 8000be8: 4808 ldr r0, [pc, #32] ; (8000c0c ) 8000bea: f00b fd1f bl 800c62c 8000bee: 4603 mov r3, r0 8000bf0: 2b00 cmp r3, #0 8000bf2: d001 beq.n 8000bf8 { Error_Handler(); 8000bf4: f000 fe94 bl 8001920 } if (HAL_UARTEx_DisableFifoMode(&huart7) != HAL_OK) 8000bf8: 4804 ldr r0, [pc, #16] ; (8000c0c ) 8000bfa: f00b fca0 bl 800c53e 8000bfe: 4603 mov r3, r0 8000c00: 2b00 cmp r3, #0 8000c02: d001 beq.n 8000c08 { Error_Handler(); 8000c04: f000 fe8c bl 8001920 } /* USER CODE BEGIN UART7_Init 2 */ /* USER CODE END UART7_Init 2 */ } 8000c08: bf00 nop 8000c0a: bd80 pop {r7, pc} 8000c0c: 200002d4 .word 0x200002d4 8000c10: 40007800 .word 0x40007800 08000c14 : * @brief UART8 Initialization Function * @param None * @retval None */ static void MX_UART8_Init(void) { 8000c14: b580 push {r7, lr} 8000c16: af00 add r7, sp, #0 /* USER CODE END UART8_Init 0 */ /* USER CODE BEGIN UART8_Init 1 */ /* USER CODE END UART8_Init 1 */ huart8.Instance = UART8; 8000c18: 4b23 ldr r3, [pc, #140] ; (8000ca8 ) 8000c1a: 4a24 ldr r2, [pc, #144] ; (8000cac ) 8000c1c: 601a str r2, [r3, #0] huart8.Init.BaudRate = 115200; 8000c1e: 4b22 ldr r3, [pc, #136] ; (8000ca8 ) 8000c20: f44f 32e1 mov.w r2, #115200 ; 0x1c200 8000c24: 605a str r2, [r3, #4] huart8.Init.WordLength = UART_WORDLENGTH_8B; 8000c26: 4b20 ldr r3, [pc, #128] ; (8000ca8 ) 8000c28: 2200 movs r2, #0 8000c2a: 609a str r2, [r3, #8] huart8.Init.StopBits = UART_STOPBITS_1; 8000c2c: 4b1e ldr r3, [pc, #120] ; (8000ca8 ) 8000c2e: 2200 movs r2, #0 8000c30: 60da str r2, [r3, #12] huart8.Init.Parity = UART_PARITY_NONE; 8000c32: 4b1d ldr r3, [pc, #116] ; (8000ca8 ) 8000c34: 2200 movs r2, #0 8000c36: 611a str r2, [r3, #16] huart8.Init.Mode = UART_MODE_TX_RX; 8000c38: 4b1b ldr r3, [pc, #108] ; (8000ca8 ) 8000c3a: 220c movs r2, #12 8000c3c: 615a str r2, [r3, #20] huart8.Init.HwFlowCtl = UART_HWCONTROL_RTS_CTS; 8000c3e: 4b1a ldr r3, [pc, #104] ; (8000ca8 ) 8000c40: f44f 7240 mov.w r2, #768 ; 0x300 8000c44: 619a str r2, [r3, #24] huart8.Init.OverSampling = UART_OVERSAMPLING_16; 8000c46: 4b18 ldr r3, [pc, #96] ; (8000ca8 ) 8000c48: 2200 movs r2, #0 8000c4a: 61da str r2, [r3, #28] huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 8000c4c: 4b16 ldr r3, [pc, #88] ; (8000ca8 ) 8000c4e: 2200 movs r2, #0 8000c50: 621a str r2, [r3, #32] huart8.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8000c52: 4b15 ldr r3, [pc, #84] ; (8000ca8 ) 8000c54: 2200 movs r2, #0 8000c56: 625a str r2, [r3, #36] ; 0x24 huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 8000c58: 4b13 ldr r3, [pc, #76] ; (8000ca8 ) 8000c5a: 2200 movs r2, #0 8000c5c: 629a str r2, [r3, #40] ; 0x28 if (HAL_UART_Init(&huart8) != HAL_OK) 8000c5e: 4812 ldr r0, [pc, #72] ; (8000ca8 ) 8000c60: f00a fc09 bl 800b476 8000c64: 4603 mov r3, r0 8000c66: 2b00 cmp r3, #0 8000c68: d001 beq.n 8000c6e { Error_Handler(); 8000c6a: f000 fe59 bl 8001920 } if (HAL_UARTEx_SetTxFifoThreshold(&huart8, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8000c6e: 2100 movs r1, #0 8000c70: 480d ldr r0, [pc, #52] ; (8000ca8 ) 8000c72: f00b fc9d bl 800c5b0 8000c76: 4603 mov r3, r0 8000c78: 2b00 cmp r3, #0 8000c7a: d001 beq.n 8000c80 { Error_Handler(); 8000c7c: f000 fe50 bl 8001920 } if (HAL_UARTEx_SetRxFifoThreshold(&huart8, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 8000c80: 2100 movs r1, #0 8000c82: 4809 ldr r0, [pc, #36] ; (8000ca8 ) 8000c84: f00b fcd2 bl 800c62c 8000c88: 4603 mov r3, r0 8000c8a: 2b00 cmp r3, #0 8000c8c: d001 beq.n 8000c92 { Error_Handler(); 8000c8e: f000 fe47 bl 8001920 } if (HAL_UARTEx_DisableFifoMode(&huart8) != HAL_OK) 8000c92: 4805 ldr r0, [pc, #20] ; (8000ca8 ) 8000c94: f00b fc53 bl 800c53e 8000c98: 4603 mov r3, r0 8000c9a: 2b00 cmp r3, #0 8000c9c: d001 beq.n 8000ca2 { Error_Handler(); 8000c9e: f000 fe3f bl 8001920 } /* USER CODE BEGIN UART8_Init 2 */ /* USER CODE END UART8_Init 2 */ } 8000ca2: bf00 nop 8000ca4: bd80 pop {r7, pc} 8000ca6: bf00 nop 8000ca8: 20000864 .word 0x20000864 8000cac: 40007c00 .word 0x40007c00 08000cb0 : * @brief UART9 Initialization Function * @param None * @retval None */ static void MX_UART9_Init(void) { 8000cb0: b580 push {r7, lr} 8000cb2: af00 add r7, sp, #0 /* USER CODE END UART9_Init 0 */ /* USER CODE BEGIN UART9_Init 1 */ /* USER CODE END UART9_Init 1 */ huart9.Instance = UART9; 8000cb4: 4b23 ldr r3, [pc, #140] ; (8000d44 ) 8000cb6: 4a24 ldr r2, [pc, #144] ; (8000d48 ) 8000cb8: 601a str r2, [r3, #0] huart9.Init.BaudRate = 115200; 8000cba: 4b22 ldr r3, [pc, #136] ; (8000d44 ) 8000cbc: f44f 32e1 mov.w r2, #115200 ; 0x1c200 8000cc0: 605a str r2, [r3, #4] huart9.Init.WordLength = UART_WORDLENGTH_8B; 8000cc2: 4b20 ldr r3, [pc, #128] ; (8000d44 ) 8000cc4: 2200 movs r2, #0 8000cc6: 609a str r2, [r3, #8] huart9.Init.StopBits = UART_STOPBITS_1; 8000cc8: 4b1e ldr r3, [pc, #120] ; (8000d44 ) 8000cca: 2200 movs r2, #0 8000ccc: 60da str r2, [r3, #12] huart9.Init.Parity = UART_PARITY_NONE; 8000cce: 4b1d ldr r3, [pc, #116] ; (8000d44 ) 8000cd0: 2200 movs r2, #0 8000cd2: 611a str r2, [r3, #16] huart9.Init.Mode = UART_MODE_TX_RX; 8000cd4: 4b1b ldr r3, [pc, #108] ; (8000d44 ) 8000cd6: 220c movs r2, #12 8000cd8: 615a str r2, [r3, #20] huart9.Init.HwFlowCtl = UART_HWCONTROL_RTS_CTS; 8000cda: 4b1a ldr r3, [pc, #104] ; (8000d44 ) 8000cdc: f44f 7240 mov.w r2, #768 ; 0x300 8000ce0: 619a str r2, [r3, #24] huart9.Init.OverSampling = UART_OVERSAMPLING_16; 8000ce2: 4b18 ldr r3, [pc, #96] ; (8000d44 ) 8000ce4: 2200 movs r2, #0 8000ce6: 61da str r2, [r3, #28] huart9.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 8000ce8: 4b16 ldr r3, [pc, #88] ; (8000d44 ) 8000cea: 2200 movs r2, #0 8000cec: 621a str r2, [r3, #32] huart9.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8000cee: 4b15 ldr r3, [pc, #84] ; (8000d44 ) 8000cf0: 2200 movs r2, #0 8000cf2: 625a str r2, [r3, #36] ; 0x24 huart9.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 8000cf4: 4b13 ldr r3, [pc, #76] ; (8000d44 ) 8000cf6: 2200 movs r2, #0 8000cf8: 629a str r2, [r3, #40] ; 0x28 if (HAL_UART_Init(&huart9) != HAL_OK) 8000cfa: 4812 ldr r0, [pc, #72] ; (8000d44 ) 8000cfc: f00a fbbb bl 800b476 8000d00: 4603 mov r3, r0 8000d02: 2b00 cmp r3, #0 8000d04: d001 beq.n 8000d0a { Error_Handler(); 8000d06: f000 fe0b bl 8001920 } if (HAL_UARTEx_SetTxFifoThreshold(&huart9, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8000d0a: 2100 movs r1, #0 8000d0c: 480d ldr r0, [pc, #52] ; (8000d44 ) 8000d0e: f00b fc4f bl 800c5b0 8000d12: 4603 mov r3, r0 8000d14: 2b00 cmp r3, #0 8000d16: d001 beq.n 8000d1c { Error_Handler(); 8000d18: f000 fe02 bl 8001920 } if (HAL_UARTEx_SetRxFifoThreshold(&huart9, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 8000d1c: 2100 movs r1, #0 8000d1e: 4809 ldr r0, [pc, #36] ; (8000d44 ) 8000d20: f00b fc84 bl 800c62c 8000d24: 4603 mov r3, r0 8000d26: 2b00 cmp r3, #0 8000d28: d001 beq.n 8000d2e { Error_Handler(); 8000d2a: f000 fdf9 bl 8001920 } if (HAL_UARTEx_DisableFifoMode(&huart9) != HAL_OK) 8000d2e: 4805 ldr r0, [pc, #20] ; (8000d44 ) 8000d30: f00b fc05 bl 800c53e 8000d34: 4603 mov r3, r0 8000d36: 2b00 cmp r3, #0 8000d38: d001 beq.n 8000d3e { Error_Handler(); 8000d3a: f000 fdf1 bl 8001920 } /* USER CODE BEGIN UART9_Init 2 */ /* USER CODE END UART9_Init 2 */ } 8000d3e: bf00 nop 8000d40: bd80 pop {r7, pc} 8000d42: bf00 nop 8000d44: 200001bc .word 0x200001bc 8000d48: 40011800 .word 0x40011800 08000d4c : * @brief USART1 Initialization Function * @param None * @retval None */ static void MX_USART1_UART_Init(void) { 8000d4c: b580 push {r7, lr} 8000d4e: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 8000d50: 4b22 ldr r3, [pc, #136] ; (8000ddc ) 8000d52: 4a23 ldr r2, [pc, #140] ; (8000de0 ) 8000d54: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 8000d56: 4b21 ldr r3, [pc, #132] ; (8000ddc ) 8000d58: f44f 32e1 mov.w r2, #115200 ; 0x1c200 8000d5c: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 8000d5e: 4b1f ldr r3, [pc, #124] ; (8000ddc ) 8000d60: 2200 movs r2, #0 8000d62: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 8000d64: 4b1d ldr r3, [pc, #116] ; (8000ddc ) 8000d66: 2200 movs r2, #0 8000d68: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 8000d6a: 4b1c ldr r3, [pc, #112] ; (8000ddc ) 8000d6c: 2200 movs r2, #0 8000d6e: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 8000d70: 4b1a ldr r3, [pc, #104] ; (8000ddc ) 8000d72: 220c movs r2, #12 8000d74: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8000d76: 4b19 ldr r3, [pc, #100] ; (8000ddc ) 8000d78: 2200 movs r2, #0 8000d7a: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 8000d7c: 4b17 ldr r3, [pc, #92] ; (8000ddc ) 8000d7e: 2200 movs r2, #0 8000d80: 61da str r2, [r3, #28] huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 8000d82: 4b16 ldr r3, [pc, #88] ; (8000ddc ) 8000d84: 2200 movs r2, #0 8000d86: 621a str r2, [r3, #32] huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8000d88: 4b14 ldr r3, [pc, #80] ; (8000ddc ) 8000d8a: 2200 movs r2, #0 8000d8c: 625a str r2, [r3, #36] ; 0x24 huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 8000d8e: 4b13 ldr r3, [pc, #76] ; (8000ddc ) 8000d90: 2200 movs r2, #0 8000d92: 629a str r2, [r3, #40] ; 0x28 if (HAL_UART_Init(&huart1) != HAL_OK) 8000d94: 4811 ldr r0, [pc, #68] ; (8000ddc ) 8000d96: f00a fb6e bl 800b476 8000d9a: 4603 mov r3, r0 8000d9c: 2b00 cmp r3, #0 8000d9e: d001 beq.n 8000da4 { Error_Handler(); 8000da0: f000 fdbe bl 8001920 } if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8000da4: 2100 movs r1, #0 8000da6: 480d ldr r0, [pc, #52] ; (8000ddc ) 8000da8: f00b fc02 bl 800c5b0 8000dac: 4603 mov r3, r0 8000dae: 2b00 cmp r3, #0 8000db0: d001 beq.n 8000db6 { Error_Handler(); 8000db2: f000 fdb5 bl 8001920 } if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 8000db6: 2100 movs r1, #0 8000db8: 4808 ldr r0, [pc, #32] ; (8000ddc ) 8000dba: f00b fc37 bl 800c62c 8000dbe: 4603 mov r3, r0 8000dc0: 2b00 cmp r3, #0 8000dc2: d001 beq.n 8000dc8 { Error_Handler(); 8000dc4: f000 fdac bl 8001920 } if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK) 8000dc8: 4804 ldr r0, [pc, #16] ; (8000ddc ) 8000dca: f00b fbb8 bl 800c53e 8000dce: 4603 mov r3, r0 8000dd0: 2b00 cmp r3, #0 8000dd2: d001 beq.n 8000dd8 { Error_Handler(); 8000dd4: f000 fda4 bl 8001920 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 8000dd8: bf00 nop 8000dda: bd80 pop {r7, pc} 8000ddc: 200006ec .word 0x200006ec 8000de0: 40011000 .word 0x40011000 08000de4 : * @brief USART2 Initialization Function * @param None * @retval None */ static void MX_USART2_UART_Init(void) { 8000de4: b580 push {r7, lr} 8000de6: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 8000de8: 4b22 ldr r3, [pc, #136] ; (8000e74 ) 8000dea: 4a23 ldr r2, [pc, #140] ; (8000e78 ) 8000dec: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 8000dee: 4b21 ldr r3, [pc, #132] ; (8000e74 ) 8000df0: f44f 32e1 mov.w r2, #115200 ; 0x1c200 8000df4: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 8000df6: 4b1f ldr r3, [pc, #124] ; (8000e74 ) 8000df8: 2200 movs r2, #0 8000dfa: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 8000dfc: 4b1d ldr r3, [pc, #116] ; (8000e74 ) 8000dfe: 2200 movs r2, #0 8000e00: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 8000e02: 4b1c ldr r3, [pc, #112] ; (8000e74 ) 8000e04: 2200 movs r2, #0 8000e06: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 8000e08: 4b1a ldr r3, [pc, #104] ; (8000e74 ) 8000e0a: 220c movs r2, #12 8000e0c: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8000e0e: 4b19 ldr r3, [pc, #100] ; (8000e74 ) 8000e10: 2200 movs r2, #0 8000e12: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 8000e14: 4b17 ldr r3, [pc, #92] ; (8000e74 ) 8000e16: 2200 movs r2, #0 8000e18: 61da str r2, [r3, #28] huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 8000e1a: 4b16 ldr r3, [pc, #88] ; (8000e74 ) 8000e1c: 2200 movs r2, #0 8000e1e: 621a str r2, [r3, #32] huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8000e20: 4b14 ldr r3, [pc, #80] ; (8000e74 ) 8000e22: 2200 movs r2, #0 8000e24: 625a str r2, [r3, #36] ; 0x24 huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 8000e26: 4b13 ldr r3, [pc, #76] ; (8000e74 ) 8000e28: 2200 movs r2, #0 8000e2a: 629a str r2, [r3, #40] ; 0x28 if (HAL_UART_Init(&huart2) != HAL_OK) 8000e2c: 4811 ldr r0, [pc, #68] ; (8000e74 ) 8000e2e: f00a fb22 bl 800b476 8000e32: 4603 mov r3, r0 8000e34: 2b00 cmp r3, #0 8000e36: d001 beq.n 8000e3c { Error_Handler(); 8000e38: f000 fd72 bl 8001920 } if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8000e3c: 2100 movs r1, #0 8000e3e: 480d ldr r0, [pc, #52] ; (8000e74 ) 8000e40: f00b fbb6 bl 800c5b0 8000e44: 4603 mov r3, r0 8000e46: 2b00 cmp r3, #0 8000e48: d001 beq.n 8000e4e { Error_Handler(); 8000e4a: f000 fd69 bl 8001920 } if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 8000e4e: 2100 movs r1, #0 8000e50: 4808 ldr r0, [pc, #32] ; (8000e74 ) 8000e52: f00b fbeb bl 800c62c 8000e56: 4603 mov r3, r0 8000e58: 2b00 cmp r3, #0 8000e5a: d001 beq.n 8000e60 { Error_Handler(); 8000e5c: f000 fd60 bl 8001920 } if (HAL_UARTEx_DisableFifoMode(&huart2) != HAL_OK) 8000e60: 4804 ldr r0, [pc, #16] ; (8000e74 ) 8000e62: f00b fb6c bl 800c53e 8000e66: 4603 mov r3, r0 8000e68: 2b00 cmp r3, #0 8000e6a: d001 beq.n 8000e70 { Error_Handler(); 8000e6c: f000 fd58 bl 8001920 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 8000e70: bf00 nop 8000e72: bd80 pop {r7, pc} 8000e74: 20000984 .word 0x20000984 8000e78: 40004400 .word 0x40004400 08000e7c : * @brief USART3 Initialization Function * @param None * @retval None */ static void MX_USART3_UART_Init(void) { 8000e7c: b580 push {r7, lr} 8000e7e: af00 add r7, sp, #0 /* USER CODE END USART3_Init 0 */ /* USER CODE BEGIN USART3_Init 1 */ /* USER CODE END USART3_Init 1 */ huart3.Instance = USART3; 8000e80: 4b23 ldr r3, [pc, #140] ; (8000f10 ) 8000e82: 4a24 ldr r2, [pc, #144] ; (8000f14 ) 8000e84: 601a str r2, [r3, #0] huart3.Init.BaudRate = 115200; 8000e86: 4b22 ldr r3, [pc, #136] ; (8000f10 ) 8000e88: f44f 32e1 mov.w r2, #115200 ; 0x1c200 8000e8c: 605a str r2, [r3, #4] huart3.Init.WordLength = UART_WORDLENGTH_8B; 8000e8e: 4b20 ldr r3, [pc, #128] ; (8000f10 ) 8000e90: 2200 movs r2, #0 8000e92: 609a str r2, [r3, #8] huart3.Init.StopBits = UART_STOPBITS_1; 8000e94: 4b1e ldr r3, [pc, #120] ; (8000f10 ) 8000e96: 2200 movs r2, #0 8000e98: 60da str r2, [r3, #12] huart3.Init.Parity = UART_PARITY_NONE; 8000e9a: 4b1d ldr r3, [pc, #116] ; (8000f10 ) 8000e9c: 2200 movs r2, #0 8000e9e: 611a str r2, [r3, #16] huart3.Init.Mode = UART_MODE_TX_RX; 8000ea0: 4b1b ldr r3, [pc, #108] ; (8000f10 ) 8000ea2: 220c movs r2, #12 8000ea4: 615a str r2, [r3, #20] huart3.Init.HwFlowCtl = UART_HWCONTROL_RTS_CTS; 8000ea6: 4b1a ldr r3, [pc, #104] ; (8000f10 ) 8000ea8: f44f 7240 mov.w r2, #768 ; 0x300 8000eac: 619a str r2, [r3, #24] huart3.Init.OverSampling = UART_OVERSAMPLING_16; 8000eae: 4b18 ldr r3, [pc, #96] ; (8000f10 ) 8000eb0: 2200 movs r2, #0 8000eb2: 61da str r2, [r3, #28] huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 8000eb4: 4b16 ldr r3, [pc, #88] ; (8000f10 ) 8000eb6: 2200 movs r2, #0 8000eb8: 621a str r2, [r3, #32] huart3.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8000eba: 4b15 ldr r3, [pc, #84] ; (8000f10 ) 8000ebc: 2200 movs r2, #0 8000ebe: 625a str r2, [r3, #36] ; 0x24 huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 8000ec0: 4b13 ldr r3, [pc, #76] ; (8000f10 ) 8000ec2: 2200 movs r2, #0 8000ec4: 629a str r2, [r3, #40] ; 0x28 if (HAL_UART_Init(&huart3) != HAL_OK) 8000ec6: 4812 ldr r0, [pc, #72] ; (8000f10 ) 8000ec8: f00a fad5 bl 800b476 8000ecc: 4603 mov r3, r0 8000ece: 2b00 cmp r3, #0 8000ed0: d001 beq.n 8000ed6 { Error_Handler(); 8000ed2: f000 fd25 bl 8001920 } if (HAL_UARTEx_SetTxFifoThreshold(&huart3, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8000ed6: 2100 movs r1, #0 8000ed8: 480d ldr r0, [pc, #52] ; (8000f10 ) 8000eda: f00b fb69 bl 800c5b0 8000ede: 4603 mov r3, r0 8000ee0: 2b00 cmp r3, #0 8000ee2: d001 beq.n 8000ee8 { Error_Handler(); 8000ee4: f000 fd1c bl 8001920 } if (HAL_UARTEx_SetRxFifoThreshold(&huart3, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 8000ee8: 2100 movs r1, #0 8000eea: 4809 ldr r0, [pc, #36] ; (8000f10 ) 8000eec: f00b fb9e bl 800c62c 8000ef0: 4603 mov r3, r0 8000ef2: 2b00 cmp r3, #0 8000ef4: d001 beq.n 8000efa { Error_Handler(); 8000ef6: f000 fd13 bl 8001920 } if (HAL_UARTEx_DisableFifoMode(&huart3) != HAL_OK) 8000efa: 4805 ldr r0, [pc, #20] ; (8000f10 ) 8000efc: f00b fb1f bl 800c53e 8000f00: 4603 mov r3, r0 8000f02: 2b00 cmp r3, #0 8000f04: d001 beq.n 8000f0a { Error_Handler(); 8000f06: f000 fd0b bl 8001920 } /* USER CODE BEGIN USART3_Init 2 */ /* USER CODE END USART3_Init 2 */ } 8000f0a: bf00 nop 8000f0c: bd80 pop {r7, pc} 8000f0e: bf00 nop 8000f10: 20000364 .word 0x20000364 8000f14: 40004800 .word 0x40004800 08000f18 : * @brief USART6 Initialization Function * @param None * @retval None */ static void MX_USART6_Init(void) { 8000f18: b580 push {r7, lr} 8000f1a: af00 add r7, sp, #0 /* USER CODE END USART6_Init 0 */ /* USER CODE BEGIN USART6_Init 1 */ /* USER CODE END USART6_Init 1 */ husart6.Instance = USART6; 8000f1c: 4b22 ldr r3, [pc, #136] ; (8000fa8 ) 8000f1e: 4a23 ldr r2, [pc, #140] ; (8000fac ) 8000f20: 601a str r2, [r3, #0] husart6.Init.BaudRate = 115200; 8000f22: 4b21 ldr r3, [pc, #132] ; (8000fa8 ) 8000f24: f44f 32e1 mov.w r2, #115200 ; 0x1c200 8000f28: 605a str r2, [r3, #4] husart6.Init.WordLength = USART_WORDLENGTH_8B; 8000f2a: 4b1f ldr r3, [pc, #124] ; (8000fa8 ) 8000f2c: 2200 movs r2, #0 8000f2e: 609a str r2, [r3, #8] husart6.Init.StopBits = USART_STOPBITS_1; 8000f30: 4b1d ldr r3, [pc, #116] ; (8000fa8 ) 8000f32: 2200 movs r2, #0 8000f34: 60da str r2, [r3, #12] husart6.Init.Parity = USART_PARITY_NONE; 8000f36: 4b1c ldr r3, [pc, #112] ; (8000fa8 ) 8000f38: 2200 movs r2, #0 8000f3a: 611a str r2, [r3, #16] husart6.Init.Mode = USART_MODE_TX_RX; 8000f3c: 4b1a ldr r3, [pc, #104] ; (8000fa8 ) 8000f3e: 220c movs r2, #12 8000f40: 615a str r2, [r3, #20] husart6.Init.CLKPolarity = USART_POLARITY_LOW; 8000f42: 4b19 ldr r3, [pc, #100] ; (8000fa8 ) 8000f44: 2200 movs r2, #0 8000f46: 619a str r2, [r3, #24] husart6.Init.CLKPhase = USART_PHASE_1EDGE; 8000f48: 4b17 ldr r3, [pc, #92] ; (8000fa8 ) 8000f4a: 2200 movs r2, #0 8000f4c: 61da str r2, [r3, #28] husart6.Init.CLKLastBit = USART_LASTBIT_DISABLE; 8000f4e: 4b16 ldr r3, [pc, #88] ; (8000fa8 ) 8000f50: 2200 movs r2, #0 8000f52: 621a str r2, [r3, #32] husart6.Init.ClockPrescaler = USART_PRESCALER_DIV1; 8000f54: 4b14 ldr r3, [pc, #80] ; (8000fa8 ) 8000f56: 2200 movs r2, #0 8000f58: 625a str r2, [r3, #36] ; 0x24 husart6.SlaveMode = USART_SLAVEMODE_DISABLE; 8000f5a: 4b13 ldr r3, [pc, #76] ; (8000fa8 ) 8000f5c: 2200 movs r2, #0 8000f5e: 641a str r2, [r3, #64] ; 0x40 if (HAL_USART_Init(&husart6) != HAL_OK) 8000f60: 4811 ldr r0, [pc, #68] ; (8000fa8 ) 8000f62: f00b fbef bl 800c744 8000f66: 4603 mov r3, r0 8000f68: 2b00 cmp r3, #0 8000f6a: d001 beq.n 8000f70 { Error_Handler(); 8000f6c: f000 fcd8 bl 8001920 } if (HAL_USARTEx_SetTxFifoThreshold(&husart6, USART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8000f70: 2100 movs r1, #0 8000f72: 480d ldr r0, [pc, #52] ; (8000fa8 ) 8000f74: f00c fa84 bl 800d480 8000f78: 4603 mov r3, r0 8000f7a: 2b00 cmp r3, #0 8000f7c: d001 beq.n 8000f82 { Error_Handler(); 8000f7e: f000 fccf bl 8001920 } if (HAL_USARTEx_SetRxFifoThreshold(&husart6, USART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 8000f82: 2100 movs r1, #0 8000f84: 4808 ldr r0, [pc, #32] ; (8000fa8 ) 8000f86: f00c fab9 bl 800d4fc 8000f8a: 4603 mov r3, r0 8000f8c: 2b00 cmp r3, #0 8000f8e: d001 beq.n 8000f94 { Error_Handler(); 8000f90: f000 fcc6 bl 8001920 } if (HAL_USARTEx_DisableFifoMode(&husart6) != HAL_OK) 8000f94: 4804 ldr r0, [pc, #16] ; (8000fa8 ) 8000f96: f00c fa3a bl 800d40e 8000f9a: 4603 mov r3, r0 8000f9c: 2b00 cmp r3, #0 8000f9e: d001 beq.n 8000fa4 { Error_Handler(); 8000fa0: f000 fcbe bl 8001920 } /* USER CODE BEGIN USART6_Init 2 */ /* USER CODE END USART6_Init 2 */ } 8000fa4: bf00 nop 8000fa6: bd80 pop {r7, pc} 8000fa8: 2000003c .word 0x2000003c 8000fac: 40011400 .word 0x40011400 08000fb0 : * @brief USART10 Initialization Function * @param None * @retval None */ static void MX_USART10_Init(void) { 8000fb0: b580 push {r7, lr} 8000fb2: af00 add r7, sp, #0 /* USER CODE END USART10_Init 0 */ /* USER CODE BEGIN USART10_Init 1 */ /* USER CODE END USART10_Init 1 */ husart10.Instance = USART10; 8000fb4: 4b22 ldr r3, [pc, #136] ; (8001040 ) 8000fb6: 4a23 ldr r2, [pc, #140] ; (8001044 ) 8000fb8: 601a str r2, [r3, #0] husart10.Init.BaudRate = 115200; 8000fba: 4b21 ldr r3, [pc, #132] ; (8001040 ) 8000fbc: f44f 32e1 mov.w r2, #115200 ; 0x1c200 8000fc0: 605a str r2, [r3, #4] husart10.Init.WordLength = USART_WORDLENGTH_8B; 8000fc2: 4b1f ldr r3, [pc, #124] ; (8001040 ) 8000fc4: 2200 movs r2, #0 8000fc6: 609a str r2, [r3, #8] husart10.Init.StopBits = USART_STOPBITS_1; 8000fc8: 4b1d ldr r3, [pc, #116] ; (8001040 ) 8000fca: 2200 movs r2, #0 8000fcc: 60da str r2, [r3, #12] husart10.Init.Parity = USART_PARITY_NONE; 8000fce: 4b1c ldr r3, [pc, #112] ; (8001040 ) 8000fd0: 2200 movs r2, #0 8000fd2: 611a str r2, [r3, #16] husart10.Init.Mode = USART_MODE_TX_RX; 8000fd4: 4b1a ldr r3, [pc, #104] ; (8001040 ) 8000fd6: 220c movs r2, #12 8000fd8: 615a str r2, [r3, #20] husart10.Init.CLKPolarity = USART_POLARITY_LOW; 8000fda: 4b19 ldr r3, [pc, #100] ; (8001040 ) 8000fdc: 2200 movs r2, #0 8000fde: 619a str r2, [r3, #24] husart10.Init.CLKPhase = USART_PHASE_1EDGE; 8000fe0: 4b17 ldr r3, [pc, #92] ; (8001040 ) 8000fe2: 2200 movs r2, #0 8000fe4: 61da str r2, [r3, #28] husart10.Init.CLKLastBit = USART_LASTBIT_DISABLE; 8000fe6: 4b16 ldr r3, [pc, #88] ; (8001040 ) 8000fe8: 2200 movs r2, #0 8000fea: 621a str r2, [r3, #32] husart10.Init.ClockPrescaler = USART_PRESCALER_DIV1; 8000fec: 4b14 ldr r3, [pc, #80] ; (8001040 ) 8000fee: 2200 movs r2, #0 8000ff0: 625a str r2, [r3, #36] ; 0x24 husart10.SlaveMode = USART_SLAVEMODE_DISABLE; 8000ff2: 4b13 ldr r3, [pc, #76] ; (8001040 ) 8000ff4: 2200 movs r2, #0 8000ff6: 641a str r2, [r3, #64] ; 0x40 if (HAL_USART_Init(&husart10) != HAL_OK) 8000ff8: 4811 ldr r0, [pc, #68] ; (8001040 ) 8000ffa: f00b fba3 bl 800c744 8000ffe: 4603 mov r3, r0 8001000: 2b00 cmp r3, #0 8001002: d001 beq.n 8001008 { Error_Handler(); 8001004: f000 fc8c bl 8001920 } if (HAL_USARTEx_SetTxFifoThreshold(&husart10, USART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8001008: 2100 movs r1, #0 800100a: 480d ldr r0, [pc, #52] ; (8001040 ) 800100c: f00c fa38 bl 800d480 8001010: 4603 mov r3, r0 8001012: 2b00 cmp r3, #0 8001014: d001 beq.n 800101a { Error_Handler(); 8001016: f000 fc83 bl 8001920 } if (HAL_USARTEx_SetRxFifoThreshold(&husart10, USART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 800101a: 2100 movs r1, #0 800101c: 4808 ldr r0, [pc, #32] ; (8001040 ) 800101e: f00c fa6d bl 800d4fc 8001022: 4603 mov r3, r0 8001024: 2b00 cmp r3, #0 8001026: d001 beq.n 800102c { Error_Handler(); 8001028: f000 fc7a bl 8001920 } if (HAL_USARTEx_DisableFifoMode(&husart10) != HAL_OK) 800102c: 4804 ldr r0, [pc, #16] ; (8001040 ) 800102e: f00c f9ee bl 800d40e 8001032: 4603 mov r3, r0 8001034: 2b00 cmp r3, #0 8001036: d001 beq.n 800103c { Error_Handler(); 8001038: f000 fc72 bl 8001920 } /* USER CODE BEGIN USART10_Init 2 */ /* USER CODE END USART10_Init 2 */ } 800103c: bf00 nop 800103e: bd80 pop {r7, pc} 8001040: 20000a28 .word 0x20000a28 8001044: 40011c00 .word 0x40011c00 08001048 : * @brief OCTOSPI1 Initialization Function * @param None * @retval None */ static void MX_OCTOSPI1_Init(void) { 8001048: b580 push {r7, lr} 800104a: b08a sub sp, #40 ; 0x28 800104c: af00 add r7, sp, #0 /* USER CODE BEGIN OCTOSPI1_Init 0 */ /* USER CODE END OCTOSPI1_Init 0 */ OSPIM_CfgTypeDef sOspiManagerCfg = {0}; 800104e: f107 0310 add.w r3, r7, #16 8001052: 2200 movs r2, #0 8001054: 601a str r2, [r3, #0] 8001056: 605a str r2, [r3, #4] 8001058: 609a str r2, [r3, #8] 800105a: 60da str r2, [r3, #12] 800105c: 611a str r2, [r3, #16] 800105e: 615a str r2, [r3, #20] OSPI_HyperbusCfgTypeDef sHyperBusCfg = {0}; 8001060: 463b mov r3, r7 8001062: 2200 movs r2, #0 8001064: 601a str r2, [r3, #0] 8001066: 605a str r2, [r3, #4] 8001068: 609a str r2, [r3, #8] 800106a: 60da str r2, [r3, #12] /* USER CODE BEGIN OCTOSPI1_Init 1 */ /* USER CODE END OCTOSPI1_Init 1 */ /* OCTOSPI1 parameter configuration*/ hospi1.Instance = OCTOSPI1; 800106c: 4b35 ldr r3, [pc, #212] ; (8001144 ) 800106e: 4a36 ldr r2, [pc, #216] ; (8001148 ) 8001070: 601a str r2, [r3, #0] hospi1.Init.FifoThreshold = 1; 8001072: 4b34 ldr r3, [pc, #208] ; (8001144 ) 8001074: 2201 movs r2, #1 8001076: 605a str r2, [r3, #4] hospi1.Init.DualQuad = HAL_OSPI_DUALQUAD_DISABLE; 8001078: 4b32 ldr r3, [pc, #200] ; (8001144 ) 800107a: 2200 movs r2, #0 800107c: 609a str r2, [r3, #8] hospi1.Init.MemoryType = HAL_OSPI_MEMTYPE_HYPERBUS; 800107e: 4b31 ldr r3, [pc, #196] ; (8001144 ) 8001080: f04f 6280 mov.w r2, #67108864 ; 0x4000000 8001084: 60da str r2, [r3, #12] hospi1.Init.DeviceSize = 32; 8001086: 4b2f ldr r3, [pc, #188] ; (8001144 ) 8001088: 2220 movs r2, #32 800108a: 611a str r2, [r3, #16] hospi1.Init.ChipSelectHighTime = 1; 800108c: 4b2d ldr r3, [pc, #180] ; (8001144 ) 800108e: 2201 movs r2, #1 8001090: 615a str r2, [r3, #20] hospi1.Init.FreeRunningClock = HAL_OSPI_FREERUNCLK_DISABLE; 8001092: 4b2c ldr r3, [pc, #176] ; (8001144 ) 8001094: 2200 movs r2, #0 8001096: 619a str r2, [r3, #24] hospi1.Init.ClockMode = HAL_OSPI_CLOCK_MODE_0; 8001098: 4b2a ldr r3, [pc, #168] ; (8001144 ) 800109a: 2200 movs r2, #0 800109c: 61da str r2, [r3, #28] hospi1.Init.WrapSize = HAL_OSPI_WRAP_NOT_SUPPORTED; 800109e: 4b29 ldr r3, [pc, #164] ; (8001144 ) 80010a0: 2200 movs r2, #0 80010a2: 621a str r2, [r3, #32] hospi1.Init.ClockPrescaler = 1; 80010a4: 4b27 ldr r3, [pc, #156] ; (8001144 ) 80010a6: 2201 movs r2, #1 80010a8: 625a str r2, [r3, #36] ; 0x24 hospi1.Init.SampleShifting = HAL_OSPI_SAMPLE_SHIFTING_NONE; 80010aa: 4b26 ldr r3, [pc, #152] ; (8001144 ) 80010ac: 2200 movs r2, #0 80010ae: 629a str r2, [r3, #40] ; 0x28 hospi1.Init.DelayHoldQuarterCycle = HAL_OSPI_DHQC_DISABLE; 80010b0: 4b24 ldr r3, [pc, #144] ; (8001144 ) 80010b2: 2200 movs r2, #0 80010b4: 62da str r2, [r3, #44] ; 0x2c hospi1.Init.ChipSelectBoundary = 0; 80010b6: 4b23 ldr r3, [pc, #140] ; (8001144 ) 80010b8: 2200 movs r2, #0 80010ba: 631a str r2, [r3, #48] ; 0x30 hospi1.Init.ClkChipSelectHighTime = 0; 80010bc: 4b21 ldr r3, [pc, #132] ; (8001144 ) 80010be: 2200 movs r2, #0 80010c0: 635a str r2, [r3, #52] ; 0x34 hospi1.Init.DelayBlockBypass = HAL_OSPI_DELAY_BLOCK_BYPASSED; 80010c2: 4b20 ldr r3, [pc, #128] ; (8001144 ) 80010c4: 2208 movs r2, #8 80010c6: 639a str r2, [r3, #56] ; 0x38 hospi1.Init.MaxTran = 0; 80010c8: 4b1e ldr r3, [pc, #120] ; (8001144 ) 80010ca: 2200 movs r2, #0 80010cc: 63da str r2, [r3, #60] ; 0x3c hospi1.Init.Refresh = 0; 80010ce: 4b1d ldr r3, [pc, #116] ; (8001144 ) 80010d0: 2200 movs r2, #0 80010d2: 641a str r2, [r3, #64] ; 0x40 if (HAL_OSPI_Init(&hospi1) != HAL_OK) 80010d4: 481b ldr r0, [pc, #108] ; (8001144 ) 80010d6: f004 fafd bl 80056d4 80010da: 4603 mov r3, r0 80010dc: 2b00 cmp r3, #0 80010de: d001 beq.n 80010e4 { Error_Handler(); 80010e0: f000 fc1e bl 8001920 } sOspiManagerCfg.ClkPort = 1; 80010e4: 2301 movs r3, #1 80010e6: 613b str r3, [r7, #16] sOspiManagerCfg.DQSPort = 1; 80010e8: 2301 movs r3, #1 80010ea: 617b str r3, [r7, #20] sOspiManagerCfg.NCSPort = 1; 80010ec: 2301 movs r3, #1 80010ee: 61bb str r3, [r7, #24] sOspiManagerCfg.IOLowPort = HAL_OSPIM_IOPORT_1_LOW; 80010f0: f04f 1301 mov.w r3, #65537 ; 0x10001 80010f4: 61fb str r3, [r7, #28] sOspiManagerCfg.IOHighPort = HAL_OSPIM_IOPORT_1_HIGH; 80010f6: 4b15 ldr r3, [pc, #84] ; (800114c ) 80010f8: 623b str r3, [r7, #32] if (HAL_OSPIM_Config(&hospi1, &sOspiManagerCfg, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) 80010fa: f107 0310 add.w r3, r7, #16 80010fe: f241 3288 movw r2, #5000 ; 0x1388 8001102: 4619 mov r1, r3 8001104: 480f ldr r0, [pc, #60] ; (8001144 ) 8001106: f004 fbf1 bl 80058ec 800110a: 4603 mov r3, r0 800110c: 2b00 cmp r3, #0 800110e: d001 beq.n 8001114 { Error_Handler(); 8001110: f000 fc06 bl 8001920 } sHyperBusCfg.RWRecoveryTime = 0; 8001114: 2300 movs r3, #0 8001116: 603b str r3, [r7, #0] sHyperBusCfg.AccessTime = 0; 8001118: 2300 movs r3, #0 800111a: 607b str r3, [r7, #4] sHyperBusCfg.WriteZeroLatency = HAL_OSPI_NO_LATENCY_ON_WRITE; 800111c: 2302 movs r3, #2 800111e: 60bb str r3, [r7, #8] sHyperBusCfg.LatencyMode = HAL_OSPI_VARIABLE_LATENCY; 8001120: 2300 movs r3, #0 8001122: 60fb str r3, [r7, #12] if (HAL_OSPI_HyperbusCfg(&hospi1, &sHyperBusCfg, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) 8001124: 463b mov r3, r7 8001126: f241 3288 movw r2, #5000 ; 0x1388 800112a: 4619 mov r1, r3 800112c: 4805 ldr r0, [pc, #20] ; (8001144 ) 800112e: f004 fb8f bl 8005850 8001132: 4603 mov r3, r0 8001134: 2b00 cmp r3, #0 8001136: d001 beq.n 800113c { Error_Handler(); 8001138: f000 fbf2 bl 8001920 } /* USER CODE BEGIN OCTOSPI1_Init 2 */ /* USER CODE END OCTOSPI1_Init 2 */ } 800113c: bf00 nop 800113e: 3728 adds r7, #40 ; 0x28 8001140: 46bd mov sp, r7 8001142: bd80 pop {r7, pc} 8001144: 200003f4 .word 0x200003f4 8001148: 52005000 .word 0x52005000 800114c: 01000001 .word 0x01000001 08001150 : * @brief OCTOSPI2 Initialization Function * @param None * @retval None */ static void MX_OCTOSPI2_Init(void) { 8001150: b580 push {r7, lr} 8001152: b08a sub sp, #40 ; 0x28 8001154: af00 add r7, sp, #0 /* USER CODE BEGIN OCTOSPI2_Init 0 */ /* USER CODE END OCTOSPI2_Init 0 */ OSPIM_CfgTypeDef sOspiManagerCfg = {0}; 8001156: f107 0310 add.w r3, r7, #16 800115a: 2200 movs r2, #0 800115c: 601a str r2, [r3, #0] 800115e: 605a str r2, [r3, #4] 8001160: 609a str r2, [r3, #8] 8001162: 60da str r2, [r3, #12] 8001164: 611a str r2, [r3, #16] 8001166: 615a str r2, [r3, #20] OSPI_HyperbusCfgTypeDef sHyperBusCfg = {0}; 8001168: 463b mov r3, r7 800116a: 2200 movs r2, #0 800116c: 601a str r2, [r3, #0] 800116e: 605a str r2, [r3, #4] 8001170: 609a str r2, [r3, #8] 8001172: 60da str r2, [r3, #12] /* USER CODE BEGIN OCTOSPI2_Init 1 */ /* USER CODE END OCTOSPI2_Init 1 */ /* OCTOSPI2 parameter configuration*/ hospi2.Instance = OCTOSPI2; 8001174: 4b35 ldr r3, [pc, #212] ; (800124c ) 8001176: 4a36 ldr r2, [pc, #216] ; (8001250 ) 8001178: 601a str r2, [r3, #0] hospi2.Init.FifoThreshold = 1; 800117a: 4b34 ldr r3, [pc, #208] ; (800124c ) 800117c: 2201 movs r2, #1 800117e: 605a str r2, [r3, #4] hospi2.Init.DualQuad = HAL_OSPI_DUALQUAD_DISABLE; 8001180: 4b32 ldr r3, [pc, #200] ; (800124c ) 8001182: 2200 movs r2, #0 8001184: 609a str r2, [r3, #8] hospi2.Init.MemoryType = HAL_OSPI_MEMTYPE_HYPERBUS; 8001186: 4b31 ldr r3, [pc, #196] ; (800124c ) 8001188: f04f 6280 mov.w r2, #67108864 ; 0x4000000 800118c: 60da str r2, [r3, #12] hospi2.Init.DeviceSize = 32; 800118e: 4b2f ldr r3, [pc, #188] ; (800124c ) 8001190: 2220 movs r2, #32 8001192: 611a str r2, [r3, #16] hospi2.Init.ChipSelectHighTime = 1; 8001194: 4b2d ldr r3, [pc, #180] ; (800124c ) 8001196: 2201 movs r2, #1 8001198: 615a str r2, [r3, #20] hospi2.Init.FreeRunningClock = HAL_OSPI_FREERUNCLK_DISABLE; 800119a: 4b2c ldr r3, [pc, #176] ; (800124c ) 800119c: 2200 movs r2, #0 800119e: 619a str r2, [r3, #24] hospi2.Init.ClockMode = HAL_OSPI_CLOCK_MODE_0; 80011a0: 4b2a ldr r3, [pc, #168] ; (800124c ) 80011a2: 2200 movs r2, #0 80011a4: 61da str r2, [r3, #28] hospi2.Init.WrapSize = HAL_OSPI_WRAP_NOT_SUPPORTED; 80011a6: 4b29 ldr r3, [pc, #164] ; (800124c ) 80011a8: 2200 movs r2, #0 80011aa: 621a str r2, [r3, #32] hospi2.Init.ClockPrescaler = 1; 80011ac: 4b27 ldr r3, [pc, #156] ; (800124c ) 80011ae: 2201 movs r2, #1 80011b0: 625a str r2, [r3, #36] ; 0x24 hospi2.Init.SampleShifting = HAL_OSPI_SAMPLE_SHIFTING_NONE; 80011b2: 4b26 ldr r3, [pc, #152] ; (800124c ) 80011b4: 2200 movs r2, #0 80011b6: 629a str r2, [r3, #40] ; 0x28 hospi2.Init.DelayHoldQuarterCycle = HAL_OSPI_DHQC_DISABLE; 80011b8: 4b24 ldr r3, [pc, #144] ; (800124c ) 80011ba: 2200 movs r2, #0 80011bc: 62da str r2, [r3, #44] ; 0x2c hospi2.Init.ChipSelectBoundary = 0; 80011be: 4b23 ldr r3, [pc, #140] ; (800124c ) 80011c0: 2200 movs r2, #0 80011c2: 631a str r2, [r3, #48] ; 0x30 hospi2.Init.ClkChipSelectHighTime = 0; 80011c4: 4b21 ldr r3, [pc, #132] ; (800124c ) 80011c6: 2200 movs r2, #0 80011c8: 635a str r2, [r3, #52] ; 0x34 hospi2.Init.DelayBlockBypass = HAL_OSPI_DELAY_BLOCK_BYPASSED; 80011ca: 4b20 ldr r3, [pc, #128] ; (800124c ) 80011cc: 2208 movs r2, #8 80011ce: 639a str r2, [r3, #56] ; 0x38 hospi2.Init.MaxTran = 0; 80011d0: 4b1e ldr r3, [pc, #120] ; (800124c ) 80011d2: 2200 movs r2, #0 80011d4: 63da str r2, [r3, #60] ; 0x3c hospi2.Init.Refresh = 0; 80011d6: 4b1d ldr r3, [pc, #116] ; (800124c ) 80011d8: 2200 movs r2, #0 80011da: 641a str r2, [r3, #64] ; 0x40 if (HAL_OSPI_Init(&hospi2) != HAL_OK) 80011dc: 481b ldr r0, [pc, #108] ; (800124c ) 80011de: f004 fa79 bl 80056d4 80011e2: 4603 mov r3, r0 80011e4: 2b00 cmp r3, #0 80011e6: d001 beq.n 80011ec { Error_Handler(); 80011e8: f000 fb9a bl 8001920 } sOspiManagerCfg.ClkPort = 2; 80011ec: 2302 movs r3, #2 80011ee: 613b str r3, [r7, #16] sOspiManagerCfg.DQSPort = 2; 80011f0: 2302 movs r3, #2 80011f2: 617b str r3, [r7, #20] sOspiManagerCfg.NCSPort = 2; 80011f4: 2302 movs r3, #2 80011f6: 61bb str r3, [r7, #24] sOspiManagerCfg.IOLowPort = HAL_OSPIM_IOPORT_2_LOW; 80011f8: 4b16 ldr r3, [pc, #88] ; (8001254 ) 80011fa: 61fb str r3, [r7, #28] sOspiManagerCfg.IOHighPort = HAL_OSPIM_IOPORT_2_HIGH; 80011fc: 4b16 ldr r3, [pc, #88] ; (8001258 ) 80011fe: 623b str r3, [r7, #32] if (HAL_OSPIM_Config(&hospi2, &sOspiManagerCfg, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) 8001200: f107 0310 add.w r3, r7, #16 8001204: f241 3288 movw r2, #5000 ; 0x1388 8001208: 4619 mov r1, r3 800120a: 4810 ldr r0, [pc, #64] ; (800124c ) 800120c: f004 fb6e bl 80058ec 8001210: 4603 mov r3, r0 8001212: 2b00 cmp r3, #0 8001214: d001 beq.n 800121a { Error_Handler(); 8001216: f000 fb83 bl 8001920 } sHyperBusCfg.RWRecoveryTime = 0; 800121a: 2300 movs r3, #0 800121c: 603b str r3, [r7, #0] sHyperBusCfg.AccessTime = 0; 800121e: 2300 movs r3, #0 8001220: 607b str r3, [r7, #4] sHyperBusCfg.WriteZeroLatency = HAL_OSPI_NO_LATENCY_ON_WRITE; 8001222: 2302 movs r3, #2 8001224: 60bb str r3, [r7, #8] sHyperBusCfg.LatencyMode = HAL_OSPI_VARIABLE_LATENCY; 8001226: 2300 movs r3, #0 8001228: 60fb str r3, [r7, #12] if (HAL_OSPI_HyperbusCfg(&hospi2, &sHyperBusCfg, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) 800122a: 463b mov r3, r7 800122c: f241 3288 movw r2, #5000 ; 0x1388 8001230: 4619 mov r1, r3 8001232: 4806 ldr r0, [pc, #24] ; (800124c ) 8001234: f004 fb0c bl 8005850 8001238: 4603 mov r3, r0 800123a: 2b00 cmp r3, #0 800123c: d001 beq.n 8001242 { Error_Handler(); 800123e: f000 fb6f bl 8001920 } /* USER CODE BEGIN OCTOSPI2_Init 2 */ /* USER CODE END OCTOSPI2_Init 2 */ } 8001242: bf00 nop 8001244: 3728 adds r7, #40 ; 0x28 8001246: 46bd mov sp, r7 8001248: bd80 pop {r7, pc} 800124a: bf00 nop 800124c: 20000a88 .word 0x20000a88 8001250: 5200a000 .word 0x5200a000 8001254: 00010002 .word 0x00010002 8001258: 01000002 .word 0x01000002 0800125c : * @brief RTC Initialization Function * @param None * @retval None */ static void MX_RTC_Init(void) { 800125c: b580 push {r7, lr} 800125e: b086 sub sp, #24 8001260: af00 add r7, sp, #0 /* USER CODE BEGIN RTC_Init 0 */ /* USER CODE END RTC_Init 0 */ RTC_TimeTypeDef sTime = {0}; 8001262: 1d3b adds r3, r7, #4 8001264: 2200 movs r2, #0 8001266: 601a str r2, [r3, #0] 8001268: 605a str r2, [r3, #4] 800126a: 609a str r2, [r3, #8] 800126c: 60da str r2, [r3, #12] 800126e: 611a str r2, [r3, #16] RTC_DateTypeDef sDate = {0}; 8001270: 2300 movs r3, #0 8001272: 603b str r3, [r7, #0] /* USER CODE BEGIN RTC_Init 1 */ /* USER CODE END RTC_Init 1 */ /** Initialize RTC Only */ hrtc.Instance = RTC; 8001274: 4b26 ldr r3, [pc, #152] ; (8001310 ) 8001276: 4a27 ldr r2, [pc, #156] ; (8001314 ) 8001278: 601a str r2, [r3, #0] hrtc.Init.HourFormat = RTC_HOURFORMAT_24; 800127a: 4b25 ldr r3, [pc, #148] ; (8001310 ) 800127c: 2200 movs r2, #0 800127e: 605a str r2, [r3, #4] hrtc.Init.AsynchPrediv = 127; 8001280: 4b23 ldr r3, [pc, #140] ; (8001310 ) 8001282: 227f movs r2, #127 ; 0x7f 8001284: 609a str r2, [r3, #8] hrtc.Init.SynchPrediv = 255; 8001286: 4b22 ldr r3, [pc, #136] ; (8001310 ) 8001288: 22ff movs r2, #255 ; 0xff 800128a: 60da str r2, [r3, #12] hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; 800128c: 4b20 ldr r3, [pc, #128] ; (8001310 ) 800128e: 2200 movs r2, #0 8001290: 611a str r2, [r3, #16] hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; 8001292: 4b1f ldr r3, [pc, #124] ; (8001310 ) 8001294: 2200 movs r2, #0 8001296: 619a str r2, [r3, #24] hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; 8001298: 4b1d ldr r3, [pc, #116] ; (8001310 ) 800129a: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 800129e: 61da str r2, [r3, #28] hrtc.Init.OutPutRemap = RTC_OUTPUT_REMAP_NONE; 80012a0: 4b1b ldr r3, [pc, #108] ; (8001310 ) 80012a2: 2200 movs r2, #0 80012a4: 615a str r2, [r3, #20] if (HAL_RTC_Init(&hrtc) != HAL_OK) 80012a6: 481a ldr r0, [pc, #104] ; (8001310 ) 80012a8: f008 f9bc bl 8009624 80012ac: 4603 mov r3, r0 80012ae: 2b00 cmp r3, #0 80012b0: d001 beq.n 80012b6 { Error_Handler(); 80012b2: f000 fb35 bl 8001920 /* USER CODE END Check_RTC_BKUP */ /** Initialize RTC and set the Time and Date */ sTime.Hours = 0x0; 80012b6: 2300 movs r3, #0 80012b8: 713b strb r3, [r7, #4] sTime.Minutes = 0x0; 80012ba: 2300 movs r3, #0 80012bc: 717b strb r3, [r7, #5] sTime.Seconds = 0x0; 80012be: 2300 movs r3, #0 80012c0: 71bb strb r3, [r7, #6] sTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; 80012c2: 2300 movs r3, #0 80012c4: 613b str r3, [r7, #16] sTime.StoreOperation = RTC_STOREOPERATION_RESET; 80012c6: 2300 movs r3, #0 80012c8: 617b str r3, [r7, #20] if (HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BCD) != HAL_OK) 80012ca: 1d3b adds r3, r7, #4 80012cc: 2201 movs r2, #1 80012ce: 4619 mov r1, r3 80012d0: 480f ldr r0, [pc, #60] ; (8001310 ) 80012d2: f008 fa23 bl 800971c 80012d6: 4603 mov r3, r0 80012d8: 2b00 cmp r3, #0 80012da: d001 beq.n 80012e0 { Error_Handler(); 80012dc: f000 fb20 bl 8001920 } sDate.WeekDay = RTC_WEEKDAY_MONDAY; 80012e0: 2301 movs r3, #1 80012e2: 703b strb r3, [r7, #0] sDate.Month = RTC_MONTH_JANUARY; 80012e4: 2301 movs r3, #1 80012e6: 707b strb r3, [r7, #1] sDate.Date = 0x1; 80012e8: 2301 movs r3, #1 80012ea: 70bb strb r3, [r7, #2] sDate.Year = 0x0; 80012ec: 2300 movs r3, #0 80012ee: 70fb strb r3, [r7, #3] if (HAL_RTC_SetDate(&hrtc, &sDate, RTC_FORMAT_BCD) != HAL_OK) 80012f0: 463b mov r3, r7 80012f2: 2201 movs r2, #1 80012f4: 4619 mov r1, r3 80012f6: 4806 ldr r0, [pc, #24] ; (8001310 ) 80012f8: f008 faae bl 8009858 80012fc: 4603 mov r3, r0 80012fe: 2b00 cmp r3, #0 8001300: d001 beq.n 8001306 { Error_Handler(); 8001302: f000 fb0d bl 8001920 } /* USER CODE BEGIN RTC_Init 2 */ /* USER CODE END RTC_Init 2 */ } 8001306: bf00 nop 8001308: 3718 adds r7, #24 800130a: 46bd mov sp, r7 800130c: bd80 pop {r7, pc} 800130e: bf00 nop 8001310: 2000083c .word 0x2000083c 8001314: 58004000 .word 0x58004000 08001318 : * @brief SDMMC1 Initialization Function * @param None * @retval None */ static void MX_SDMMC1_SD_Init(void) { 8001318: b480 push {r7} 800131a: af00 add r7, sp, #0 /* USER CODE END SDMMC1_Init 0 */ /* USER CODE BEGIN SDMMC1_Init 1 */ /* USER CODE END SDMMC1_Init 1 */ hsd1.Instance = SDMMC1; 800131c: 4b0b ldr r3, [pc, #44] ; (800134c ) 800131e: 4a0c ldr r2, [pc, #48] ; (8001350 ) 8001320: 601a str r2, [r3, #0] hsd1.Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; 8001322: 4b0a ldr r3, [pc, #40] ; (800134c ) 8001324: 2200 movs r2, #0 8001326: 605a str r2, [r3, #4] hsd1.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; 8001328: 4b08 ldr r3, [pc, #32] ; (800134c ) 800132a: 2200 movs r2, #0 800132c: 609a str r2, [r3, #8] hsd1.Init.BusWide = SDMMC_BUS_WIDE_4B; 800132e: 4b07 ldr r3, [pc, #28] ; (800134c ) 8001330: f44f 4280 mov.w r2, #16384 ; 0x4000 8001334: 60da str r2, [r3, #12] hsd1.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; 8001336: 4b05 ldr r3, [pc, #20] ; (800134c ) 8001338: 2200 movs r2, #0 800133a: 611a str r2, [r3, #16] hsd1.Init.ClockDiv = 0; 800133c: 4b03 ldr r3, [pc, #12] ; (800134c ) 800133e: 2200 movs r2, #0 8001340: 615a str r2, [r3, #20] /* USER CODE BEGIN SDMMC1_Init 2 */ /* USER CODE END SDMMC1_Init 2 */ } 8001342: bf00 nop 8001344: 46bd mov sp, r7 8001346: f85d 7b04 ldr.w r7, [sp], #4 800134a: 4770 bx lr 800134c: 200004a0 .word 0x200004a0 8001350: 52007000 .word 0x52007000 08001354 : * @brief SPI2 Initialization Function * @param None * @retval None */ static void MX_SPI2_Init(void) { 8001354: b580 push {r7, lr} 8001356: af00 add r7, sp, #0 /* USER CODE BEGIN SPI2_Init 1 */ /* USER CODE END SPI2_Init 1 */ /* SPI2 parameter configuration*/ hspi2.Instance = SPI2; 8001358: 4b27 ldr r3, [pc, #156] ; (80013f8 ) 800135a: 4a28 ldr r2, [pc, #160] ; (80013fc ) 800135c: 601a str r2, [r3, #0] hspi2.Init.Mode = SPI_MODE_MASTER; 800135e: 4b26 ldr r3, [pc, #152] ; (80013f8 ) 8001360: f44f 0280 mov.w r2, #4194304 ; 0x400000 8001364: 605a str r2, [r3, #4] hspi2.Init.Direction = SPI_DIRECTION_2LINES; 8001366: 4b24 ldr r3, [pc, #144] ; (80013f8 ) 8001368: 2200 movs r2, #0 800136a: 609a str r2, [r3, #8] hspi2.Init.DataSize = SPI_DATASIZE_4BIT; 800136c: 4b22 ldr r3, [pc, #136] ; (80013f8 ) 800136e: 2203 movs r2, #3 8001370: 60da str r2, [r3, #12] hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; 8001372: 4b21 ldr r3, [pc, #132] ; (80013f8 ) 8001374: 2200 movs r2, #0 8001376: 611a str r2, [r3, #16] hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; 8001378: 4b1f ldr r3, [pc, #124] ; (80013f8 ) 800137a: 2200 movs r2, #0 800137c: 615a str r2, [r3, #20] hspi2.Init.NSS = SPI_NSS_SOFT; 800137e: 4b1e ldr r3, [pc, #120] ; (80013f8 ) 8001380: f04f 6280 mov.w r2, #67108864 ; 0x4000000 8001384: 619a str r2, [r3, #24] hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 8001386: 4b1c ldr r3, [pc, #112] ; (80013f8 ) 8001388: 2200 movs r2, #0 800138a: 61da str r2, [r3, #28] hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; 800138c: 4b1a ldr r3, [pc, #104] ; (80013f8 ) 800138e: 2200 movs r2, #0 8001390: 621a str r2, [r3, #32] hspi2.Init.TIMode = SPI_TIMODE_DISABLE; 8001392: 4b19 ldr r3, [pc, #100] ; (80013f8 ) 8001394: 2200 movs r2, #0 8001396: 625a str r2, [r3, #36] ; 0x24 hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 8001398: 4b17 ldr r3, [pc, #92] ; (80013f8 ) 800139a: 2200 movs r2, #0 800139c: 629a str r2, [r3, #40] ; 0x28 hspi2.Init.CRCPolynomial = 0x0; 800139e: 4b16 ldr r3, [pc, #88] ; (80013f8 ) 80013a0: 2200 movs r2, #0 80013a2: 62da str r2, [r3, #44] ; 0x2c hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; 80013a4: 4b14 ldr r3, [pc, #80] ; (80013f8 ) 80013a6: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 80013aa: 635a str r2, [r3, #52] ; 0x34 hspi2.Init.NSSPolarity = SPI_NSS_POLARITY_LOW; 80013ac: 4b12 ldr r3, [pc, #72] ; (80013f8 ) 80013ae: 2200 movs r2, #0 80013b0: 639a str r2, [r3, #56] ; 0x38 hspi2.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA; 80013b2: 4b11 ldr r3, [pc, #68] ; (80013f8 ) 80013b4: 2200 movs r2, #0 80013b6: 63da str r2, [r3, #60] ; 0x3c hspi2.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN; 80013b8: 4b0f ldr r3, [pc, #60] ; (80013f8 ) 80013ba: 2200 movs r2, #0 80013bc: 641a str r2, [r3, #64] ; 0x40 hspi2.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN; 80013be: 4b0e ldr r3, [pc, #56] ; (80013f8 ) 80013c0: 2200 movs r2, #0 80013c2: 645a str r2, [r3, #68] ; 0x44 hspi2.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE; 80013c4: 4b0c ldr r3, [pc, #48] ; (80013f8 ) 80013c6: 2200 movs r2, #0 80013c8: 649a str r2, [r3, #72] ; 0x48 hspi2.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE; 80013ca: 4b0b ldr r3, [pc, #44] ; (80013f8 ) 80013cc: 2200 movs r2, #0 80013ce: 64da str r2, [r3, #76] ; 0x4c hspi2.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE; 80013d0: 4b09 ldr r3, [pc, #36] ; (80013f8 ) 80013d2: 2200 movs r2, #0 80013d4: 651a str r2, [r3, #80] ; 0x50 hspi2.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE; 80013d6: 4b08 ldr r3, [pc, #32] ; (80013f8 ) 80013d8: 2200 movs r2, #0 80013da: 655a str r2, [r3, #84] ; 0x54 hspi2.Init.IOSwap = SPI_IO_SWAP_DISABLE; 80013dc: 4b06 ldr r3, [pc, #24] ; (80013f8 ) 80013de: 2200 movs r2, #0 80013e0: 659a str r2, [r3, #88] ; 0x58 if (HAL_SPI_Init(&hspi2) != HAL_OK) 80013e2: 4805 ldr r0, [pc, #20] ; (80013f8 ) 80013e4: f009 ff26 bl 800b234 80013e8: 4603 mov r3, r0 80013ea: 2b00 cmp r3, #0 80013ec: d001 beq.n 80013f2 { Error_Handler(); 80013ee: f000 fa97 bl 8001920 } /* USER CODE BEGIN SPI2_Init 2 */ /* USER CODE END SPI2_Init 2 */ } 80013f2: bf00 nop 80013f4: bd80 pop {r7, pc} 80013f6: bf00 nop 80013f8: 2000024c .word 0x2000024c 80013fc: 40003800 .word 0x40003800 08001400 : * @brief SPI4 Initialization Function * @param None * @retval None */ static void MX_SPI4_Init(void) { 8001400: b580 push {r7, lr} 8001402: af00 add r7, sp, #0 /* USER CODE BEGIN SPI4_Init 1 */ /* USER CODE END SPI4_Init 1 */ /* SPI4 parameter configuration*/ hspi4.Instance = SPI4; 8001404: 4b27 ldr r3, [pc, #156] ; (80014a4 ) 8001406: 4a28 ldr r2, [pc, #160] ; (80014a8 ) 8001408: 601a str r2, [r3, #0] hspi4.Init.Mode = SPI_MODE_MASTER; 800140a: 4b26 ldr r3, [pc, #152] ; (80014a4 ) 800140c: f44f 0280 mov.w r2, #4194304 ; 0x400000 8001410: 605a str r2, [r3, #4] hspi4.Init.Direction = SPI_DIRECTION_2LINES; 8001412: 4b24 ldr r3, [pc, #144] ; (80014a4 ) 8001414: 2200 movs r2, #0 8001416: 609a str r2, [r3, #8] hspi4.Init.DataSize = SPI_DATASIZE_4BIT; 8001418: 4b22 ldr r3, [pc, #136] ; (80014a4 ) 800141a: 2203 movs r2, #3 800141c: 60da str r2, [r3, #12] hspi4.Init.CLKPolarity = SPI_POLARITY_LOW; 800141e: 4b21 ldr r3, [pc, #132] ; (80014a4 ) 8001420: 2200 movs r2, #0 8001422: 611a str r2, [r3, #16] hspi4.Init.CLKPhase = SPI_PHASE_1EDGE; 8001424: 4b1f ldr r3, [pc, #124] ; (80014a4 ) 8001426: 2200 movs r2, #0 8001428: 615a str r2, [r3, #20] hspi4.Init.NSS = SPI_NSS_SOFT; 800142a: 4b1e ldr r3, [pc, #120] ; (80014a4 ) 800142c: f04f 6280 mov.w r2, #67108864 ; 0x4000000 8001430: 619a str r2, [r3, #24] hspi4.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 8001432: 4b1c ldr r3, [pc, #112] ; (80014a4 ) 8001434: 2200 movs r2, #0 8001436: 61da str r2, [r3, #28] hspi4.Init.FirstBit = SPI_FIRSTBIT_MSB; 8001438: 4b1a ldr r3, [pc, #104] ; (80014a4 ) 800143a: 2200 movs r2, #0 800143c: 621a str r2, [r3, #32] hspi4.Init.TIMode = SPI_TIMODE_DISABLE; 800143e: 4b19 ldr r3, [pc, #100] ; (80014a4 ) 8001440: 2200 movs r2, #0 8001442: 625a str r2, [r3, #36] ; 0x24 hspi4.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 8001444: 4b17 ldr r3, [pc, #92] ; (80014a4 ) 8001446: 2200 movs r2, #0 8001448: 629a str r2, [r3, #40] ; 0x28 hspi4.Init.CRCPolynomial = 0x0; 800144a: 4b16 ldr r3, [pc, #88] ; (80014a4 ) 800144c: 2200 movs r2, #0 800144e: 62da str r2, [r3, #44] ; 0x2c hspi4.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; 8001450: 4b14 ldr r3, [pc, #80] ; (80014a4 ) 8001452: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 8001456: 635a str r2, [r3, #52] ; 0x34 hspi4.Init.NSSPolarity = SPI_NSS_POLARITY_LOW; 8001458: 4b12 ldr r3, [pc, #72] ; (80014a4 ) 800145a: 2200 movs r2, #0 800145c: 639a str r2, [r3, #56] ; 0x38 hspi4.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA; 800145e: 4b11 ldr r3, [pc, #68] ; (80014a4 ) 8001460: 2200 movs r2, #0 8001462: 63da str r2, [r3, #60] ; 0x3c hspi4.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN; 8001464: 4b0f ldr r3, [pc, #60] ; (80014a4 ) 8001466: 2200 movs r2, #0 8001468: 641a str r2, [r3, #64] ; 0x40 hspi4.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN; 800146a: 4b0e ldr r3, [pc, #56] ; (80014a4 ) 800146c: 2200 movs r2, #0 800146e: 645a str r2, [r3, #68] ; 0x44 hspi4.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE; 8001470: 4b0c ldr r3, [pc, #48] ; (80014a4 ) 8001472: 2200 movs r2, #0 8001474: 649a str r2, [r3, #72] ; 0x48 hspi4.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE; 8001476: 4b0b ldr r3, [pc, #44] ; (80014a4 ) 8001478: 2200 movs r2, #0 800147a: 64da str r2, [r3, #76] ; 0x4c hspi4.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE; 800147c: 4b09 ldr r3, [pc, #36] ; (80014a4 ) 800147e: 2200 movs r2, #0 8001480: 651a str r2, [r3, #80] ; 0x50 hspi4.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE; 8001482: 4b08 ldr r3, [pc, #32] ; (80014a4 ) 8001484: 2200 movs r2, #0 8001486: 655a str r2, [r3, #84] ; 0x54 hspi4.Init.IOSwap = SPI_IO_SWAP_DISABLE; 8001488: 4b06 ldr r3, [pc, #24] ; (80014a4 ) 800148a: 2200 movs r2, #0 800148c: 659a str r2, [r3, #88] ; 0x58 if (HAL_SPI_Init(&hspi4) != HAL_OK) 800148e: 4805 ldr r0, [pc, #20] ; (80014a4 ) 8001490: f009 fed0 bl 800b234 8001494: 4603 mov r3, r0 8001496: 2b00 cmp r3, #0 8001498: d001 beq.n 800149e { Error_Handler(); 800149a: f000 fa41 bl 8001920 } /* USER CODE BEGIN SPI4_Init 2 */ /* USER CODE END SPI4_Init 2 */ } 800149e: bf00 nop 80014a0: bd80 pop {r7, pc} 80014a2: bf00 nop 80014a4: 200007b4 .word 0x200007b4 80014a8: 40013400 .word 0x40013400 080014ac : * @brief USB_OTG_HS Initialization Function * @param None * @retval None */ static void MX_USB_OTG_HS_USB_Init(void) { 80014ac: b480 push {r7} 80014ae: af00 add r7, sp, #0 /* USER CODE END USB_OTG_HS_Init 1 */ /* USER CODE BEGIN USB_OTG_HS_Init 2 */ /* USER CODE END USB_OTG_HS_Init 2 */ } 80014b0: bf00 nop 80014b2: 46bd mov sp, r7 80014b4: f85d 7b04 ldr.w r7, [sp], #4 80014b8: 4770 bx lr ... 080014bc : * @brief WWDG1 Initialization Function * @param None * @retval None */ static void MX_WWDG1_Init(void) { 80014bc: b580 push {r7, lr} 80014be: af00 add r7, sp, #0 /* USER CODE END WWDG1_Init 0 */ /* USER CODE BEGIN WWDG1_Init 1 */ /* USER CODE END WWDG1_Init 1 */ hwwdg1.Instance = WWDG1; 80014c0: 4b0c ldr r3, [pc, #48] ; (80014f4 ) 80014c2: 4a0d ldr r2, [pc, #52] ; (80014f8 ) 80014c4: 601a str r2, [r3, #0] hwwdg1.Init.Prescaler = WWDG_PRESCALER_1; 80014c6: 4b0b ldr r3, [pc, #44] ; (80014f4 ) 80014c8: 2200 movs r2, #0 80014ca: 605a str r2, [r3, #4] hwwdg1.Init.Window = 64; 80014cc: 4b09 ldr r3, [pc, #36] ; (80014f4 ) 80014ce: 2240 movs r2, #64 ; 0x40 80014d0: 609a str r2, [r3, #8] hwwdg1.Init.Counter = 64; 80014d2: 4b08 ldr r3, [pc, #32] ; (80014f4 ) 80014d4: 2240 movs r2, #64 ; 0x40 80014d6: 60da str r2, [r3, #12] hwwdg1.Init.EWIMode = WWDG_EWI_DISABLE; 80014d8: 4b06 ldr r3, [pc, #24] ; (80014f4 ) 80014da: 2200 movs r2, #0 80014dc: 611a str r2, [r3, #16] if (HAL_WWDG_Init(&hwwdg1) != HAL_OK) 80014de: 4805 ldr r0, [pc, #20] ; (80014f4 ) 80014e0: f00c f894 bl 800d60c 80014e4: 4603 mov r3, r0 80014e6: 2b00 cmp r3, #0 80014e8: d001 beq.n 80014ee { Error_Handler(); 80014ea: f000 fa19 bl 8001920 } /* USER CODE BEGIN WWDG1_Init 2 */ /* USER CODE END WWDG1_Init 2 */ } 80014ee: bf00 nop 80014f0: bd80 pop {r7, pc} 80014f2: bf00 nop 80014f4: 20000a14 .word 0x20000a14 80014f8: 50003000 .word 0x50003000 080014fc : /** * Enable DMA controller clock */ static void MX_DMA_Init(void) { 80014fc: b580 push {r7, lr} 80014fe: b082 sub sp, #8 8001500: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 8001502: 4b11 ldr r3, [pc, #68] ; (8001548 ) 8001504: f8d3 3138 ldr.w r3, [r3, #312] ; 0x138 8001508: 4a0f ldr r2, [pc, #60] ; (8001548 ) 800150a: f043 0301 orr.w r3, r3, #1 800150e: f8c2 3138 str.w r3, [r2, #312] ; 0x138 8001512: 4b0d ldr r3, [pc, #52] ; (8001548 ) 8001514: f8d3 3138 ldr.w r3, [r3, #312] ; 0x138 8001518: f003 0301 and.w r3, r3, #1 800151c: 607b str r3, [r7, #4] 800151e: 687b ldr r3, [r7, #4] /* DMA interrupt init */ /* DMA1_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 0, 0); 8001520: 2200 movs r2, #0 8001522: 2100 movs r1, #0 8001524: 200d movs r0, #13 8001526: f001 ff6a bl 80033fe HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); 800152a: 200d movs r0, #13 800152c: f001 ff81 bl 8003432 /* DMA1_Stream3_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream3_IRQn, 0, 0); 8001530: 2200 movs r2, #0 8001532: 2100 movs r1, #0 8001534: 200e movs r0, #14 8001536: f001 ff62 bl 80033fe HAL_NVIC_EnableIRQ(DMA1_Stream3_IRQn); 800153a: 200e movs r0, #14 800153c: f001 ff79 bl 8003432 } 8001540: bf00 nop 8001542: 3708 adds r7, #8 8001544: 46bd mov sp, r7 8001546: bd80 pop {r7, pc} 8001548: 58024400 .word 0x58024400 0800154c : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 800154c: b580 push {r7, lr} 800154e: b090 sub sp, #64 ; 0x40 8001550: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001552: f107 032c add.w r3, r7, #44 ; 0x2c 8001556: 2200 movs r2, #0 8001558: 601a str r2, [r3, #0] 800155a: 605a str r2, [r3, #4] 800155c: 609a str r2, [r3, #8] 800155e: 60da str r2, [r3, #12] 8001560: 611a str r2, [r3, #16] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOB_CLK_ENABLE(); 8001562: 4bc0 ldr r3, [pc, #768] ; (8001864 ) 8001564: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001568: 4abe ldr r2, [pc, #760] ; (8001864 ) 800156a: f043 0302 orr.w r3, r3, #2 800156e: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8001572: 4bbc ldr r3, [pc, #752] ; (8001864 ) 8001574: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001578: f003 0302 and.w r3, r3, #2 800157c: 62bb str r3, [r7, #40] ; 0x28 800157e: 6abb ldr r3, [r7, #40] ; 0x28 __HAL_RCC_GPIOG_CLK_ENABLE(); 8001580: 4bb8 ldr r3, [pc, #736] ; (8001864 ) 8001582: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001586: 4ab7 ldr r2, [pc, #732] ; (8001864 ) 8001588: f043 0340 orr.w r3, r3, #64 ; 0x40 800158c: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8001590: 4bb4 ldr r3, [pc, #720] ; (8001864 ) 8001592: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001596: f003 0340 and.w r3, r3, #64 ; 0x40 800159a: 627b str r3, [r7, #36] ; 0x24 800159c: 6a7b ldr r3, [r7, #36] ; 0x24 __HAL_RCC_GPIOK_CLK_ENABLE(); 800159e: 4bb1 ldr r3, [pc, #708] ; (8001864 ) 80015a0: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80015a4: 4aaf ldr r2, [pc, #700] ; (8001864 ) 80015a6: f443 6380 orr.w r3, r3, #1024 ; 0x400 80015aa: f8c2 3140 str.w r3, [r2, #320] ; 0x140 80015ae: 4bad ldr r3, [pc, #692] ; (8001864 ) 80015b0: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80015b4: f403 6380 and.w r3, r3, #1024 ; 0x400 80015b8: 623b str r3, [r7, #32] 80015ba: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOD_CLK_ENABLE(); 80015bc: 4ba9 ldr r3, [pc, #676] ; (8001864 ) 80015be: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80015c2: 4aa8 ldr r2, [pc, #672] ; (8001864 ) 80015c4: f043 0308 orr.w r3, r3, #8 80015c8: f8c2 3140 str.w r3, [r2, #320] ; 0x140 80015cc: 4ba5 ldr r3, [pc, #660] ; (8001864 ) 80015ce: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80015d2: f003 0308 and.w r3, r3, #8 80015d6: 61fb str r3, [r7, #28] 80015d8: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOC_CLK_ENABLE(); 80015da: 4ba2 ldr r3, [pc, #648] ; (8001864 ) 80015dc: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80015e0: 4aa0 ldr r2, [pc, #640] ; (8001864 ) 80015e2: f043 0304 orr.w r3, r3, #4 80015e6: f8c2 3140 str.w r3, [r2, #320] ; 0x140 80015ea: 4b9e ldr r3, [pc, #632] ; (8001864 ) 80015ec: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80015f0: f003 0304 and.w r3, r3, #4 80015f4: 61bb str r3, [r7, #24] 80015f6: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOI_CLK_ENABLE(); 80015f8: 4b9a ldr r3, [pc, #616] ; (8001864 ) 80015fa: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80015fe: 4a99 ldr r2, [pc, #612] ; (8001864 ) 8001600: f443 7380 orr.w r3, r3, #256 ; 0x100 8001604: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8001608: 4b96 ldr r3, [pc, #600] ; (8001864 ) 800160a: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 800160e: f403 7380 and.w r3, r3, #256 ; 0x100 8001612: 617b str r3, [r7, #20] 8001614: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOE_CLK_ENABLE(); 8001616: 4b93 ldr r3, [pc, #588] ; (8001864 ) 8001618: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 800161c: 4a91 ldr r2, [pc, #580] ; (8001864 ) 800161e: f043 0310 orr.w r3, r3, #16 8001622: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8001626: 4b8f ldr r3, [pc, #572] ; (8001864 ) 8001628: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 800162c: f003 0310 and.w r3, r3, #16 8001630: 613b str r3, [r7, #16] 8001632: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001634: 4b8b ldr r3, [pc, #556] ; (8001864 ) 8001636: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 800163a: 4a8a ldr r2, [pc, #552] ; (8001864 ) 800163c: f043 0301 orr.w r3, r3, #1 8001640: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8001644: 4b87 ldr r3, [pc, #540] ; (8001864 ) 8001646: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 800164a: f003 0301 and.w r3, r3, #1 800164e: 60fb str r3, [r7, #12] 8001650: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOH_CLK_ENABLE(); 8001652: 4b84 ldr r3, [pc, #528] ; (8001864 ) 8001654: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001658: 4a82 ldr r2, [pc, #520] ; (8001864 ) 800165a: f043 0380 orr.w r3, r3, #128 ; 0x80 800165e: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8001662: 4b80 ldr r3, [pc, #512] ; (8001864 ) 8001664: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001668: f003 0380 and.w r3, r3, #128 ; 0x80 800166c: 60bb str r3, [r7, #8] 800166e: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOJ_CLK_ENABLE(); 8001670: 4b7c ldr r3, [pc, #496] ; (8001864 ) 8001672: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001676: 4a7b ldr r2, [pc, #492] ; (8001864 ) 8001678: f443 7300 orr.w r3, r3, #512 ; 0x200 800167c: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8001680: 4b78 ldr r3, [pc, #480] ; (8001864 ) 8001682: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001686: f403 7300 and.w r3, r3, #512 ; 0x200 800168a: 607b str r3, [r7, #4] 800168c: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOF_CLK_ENABLE(); 800168e: 4b75 ldr r3, [pc, #468] ; (8001864 ) 8001690: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001694: 4a73 ldr r2, [pc, #460] ; (8001864 ) 8001696: f043 0320 orr.w r3, r3, #32 800169a: f8c2 3140 str.w r3, [r2, #320] ; 0x140 800169e: 4b71 ldr r3, [pc, #452] ; (8001864 ) 80016a0: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80016a4: f003 0320 and.w r3, r3, #32 80016a8: 603b str r3, [r7, #0] 80016aa: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOE, CTD_DR_Pin|CTD_PWR_Pin|UART4_PWR_Pin, GPIO_PIN_RESET); 80016ac: 2200 movs r2, #0 80016ae: 2123 movs r1, #35 ; 0x23 80016b0: 486d ldr r0, [pc, #436] ; (8001868 ) 80016b2: f003 fdcf bl 8005254 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOI, USART6_PWR_Pin|CTD_MODE_Pin|UART7_PWR_Pin, GPIO_PIN_RESET); 80016b6: 2200 movs r2, #0 80016b8: f242 0181 movw r1, #8321 ; 0x2081 80016bc: 486b ldr r0, [pc, #428] ; (800186c ) 80016be: f003 fdc9 bl 8005254 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOK, LPUART1_PWR_Pin|UART8_PWR_Pin, GPIO_PIN_RESET); 80016c2: 2200 movs r2, #0 80016c4: 2181 movs r1, #129 ; 0x81 80016c6: 486a ldr r0, [pc, #424] ; (8001870 ) 80016c8: f003 fdc4 bl 8005254 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(USART2_PWR_GPIO_Port, USART2_PWR_Pin, GPIO_PIN_RESET); 80016cc: 2200 movs r2, #0 80016ce: f44f 5100 mov.w r1, #8192 ; 0x2000 80016d2: 4868 ldr r0, [pc, #416] ; (8001874 ) 80016d4: f003 fdbe bl 8005254 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(USART1_PWRA8_GPIO_Port, USART1_PWRA8_Pin, GPIO_PIN_RESET); 80016d8: 2200 movs r2, #0 80016da: f44f 7180 mov.w r1, #256 ; 0x100 80016de: 4866 ldr r0, [pc, #408] ; (8001878 ) 80016e0: f003 fdb8 bl 8005254 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOH, UART5_PWR_Pin|UART9_PWR_Pin, GPIO_PIN_RESET); 80016e4: 2200 movs r2, #0 80016e6: f44f 6188 mov.w r1, #1088 ; 0x440 80016ea: 4864 ldr r0, [pc, #400] ; (800187c ) 80016ec: f003 fdb2 bl 8005254 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(USART3_PWR_GPIO_Port, USART3_PWR_Pin, GPIO_PIN_RESET); 80016f0: 2200 movs r2, #0 80016f2: f44f 4180 mov.w r1, #16384 ; 0x4000 80016f6: 4862 ldr r0, [pc, #392] ; (8001880 ) 80016f8: f003 fdac bl 8005254 /*Configure GPIO pin : PD7 */ GPIO_InitStruct.Pin = GPIO_PIN_7; 80016fc: 2380 movs r3, #128 ; 0x80 80016fe: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001700: 2302 movs r3, #2 8001702: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001704: 2300 movs r3, #0 8001706: 637b str r3, [r7, #52] ; 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001708: 2303 movs r3, #3 800170a: 63bb str r3, [r7, #56] ; 0x38 GPIO_InitStruct.Alternate = GPIO_AF11_SDMMC2; 800170c: 230b movs r3, #11 800170e: 63fb str r3, [r7, #60] ; 0x3c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8001710: f107 032c add.w r3, r7, #44 ; 0x2c 8001714: 4619 mov r1, r3 8001716: 485b ldr r0, [pc, #364] ; (8001884 ) 8001718: f003 fbd4 bl 8004ec4 /*Configure GPIO pins : CTD_DR_Pin CTD_PWR_Pin UART4_PWR_Pin */ GPIO_InitStruct.Pin = CTD_DR_Pin|CTD_PWR_Pin|UART4_PWR_Pin; 800171c: 2323 movs r3, #35 ; 0x23 800171e: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001720: 2301 movs r3, #1 8001722: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001724: 2300 movs r3, #0 8001726: 637b str r3, [r7, #52] ; 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001728: 2300 movs r3, #0 800172a: 63bb str r3, [r7, #56] ; 0x38 HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 800172c: f107 032c add.w r3, r7, #44 ; 0x2c 8001730: 4619 mov r1, r3 8001732: 484d ldr r0, [pc, #308] ; (8001868 ) 8001734: f003 fbc6 bl 8004ec4 /*Configure GPIO pins : UART4_FLT_Pin USART1_PWR_Pin */ GPIO_InitStruct.Pin = UART4_FLT_Pin|USART1_PWR_Pin; 8001738: 2342 movs r3, #66 ; 0x42 800173a: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800173c: 2300 movs r3, #0 800173e: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001740: 2300 movs r3, #0 8001742: 637b str r3, [r7, #52] ; 0x34 HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); 8001744: f107 032c add.w r3, r7, #44 ; 0x2c 8001748: 4619 mov r1, r3 800174a: 4848 ldr r0, [pc, #288] ; (800186c ) 800174c: f003 fbba bl 8004ec4 /*Configure GPIO pins : USART6_PWR_Pin CTD_MODE_Pin UART7_PWR_Pin */ GPIO_InitStruct.Pin = USART6_PWR_Pin|CTD_MODE_Pin|UART7_PWR_Pin; 8001750: f242 0381 movw r3, #8321 ; 0x2081 8001754: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001756: 2301 movs r3, #1 8001758: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 800175a: 2300 movs r3, #0 800175c: 637b str r3, [r7, #52] ; 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800175e: 2300 movs r3, #0 8001760: 63bb str r3, [r7, #56] ; 0x38 HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); 8001762: f107 032c add.w r3, r7, #44 ; 0x2c 8001766: 4619 mov r1, r3 8001768: 4840 ldr r0, [pc, #256] ; (800186c ) 800176a: f003 fbab bl 8004ec4 /*Configure GPIO pins : PA12 PA11 */ GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_11; 800176e: f44f 53c0 mov.w r3, #6144 ; 0x1800 8001772: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001774: 2302 movs r3, #2 8001776: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001778: 2300 movs r3, #0 800177a: 637b str r3, [r7, #52] ; 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800177c: 2300 movs r3, #0 800177e: 63bb str r3, [r7, #56] ; 0x38 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001780: f107 032c add.w r3, r7, #44 ; 0x2c 8001784: 4619 mov r1, r3 8001786: 483c ldr r0, [pc, #240] ; (8001878 ) 8001788: f003 fb9c bl 8004ec4 /*Configure GPIO pins : LPUART1_PWR_Pin UART8_PWR_Pin */ GPIO_InitStruct.Pin = LPUART1_PWR_Pin|UART8_PWR_Pin; 800178c: 2381 movs r3, #129 ; 0x81 800178e: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001790: 2301 movs r3, #1 8001792: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001794: 2300 movs r3, #0 8001796: 637b str r3, [r7, #52] ; 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001798: 2300 movs r3, #0 800179a: 63bb str r3, [r7, #56] ; 0x38 HAL_GPIO_Init(GPIOK, &GPIO_InitStruct); 800179c: f107 032c add.w r3, r7, #44 ; 0x2c 80017a0: 4619 mov r1, r3 80017a2: 4833 ldr r0, [pc, #204] ; (8001870 ) 80017a4: f003 fb8e bl 8004ec4 /*Configure GPIO pin : USART2_PWR_Pin */ GPIO_InitStruct.Pin = USART2_PWR_Pin; 80017a8: f44f 5300 mov.w r3, #8192 ; 0x2000 80017ac: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80017ae: 2301 movs r3, #1 80017b0: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 80017b2: 2300 movs r3, #0 80017b4: 637b str r3, [r7, #52] ; 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80017b6: 2300 movs r3, #0 80017b8: 63bb str r3, [r7, #56] ; 0x38 HAL_GPIO_Init(USART2_PWR_GPIO_Port, &GPIO_InitStruct); 80017ba: f107 032c add.w r3, r7, #44 ; 0x2c 80017be: 4619 mov r1, r3 80017c0: 482c ldr r0, [pc, #176] ; (8001874 ) 80017c2: f003 fb7f bl 8004ec4 /*Configure GPIO pins : USART6_FLT_Pin UART5_FLT_Pin */ GPIO_InitStruct.Pin = USART6_FLT_Pin|UART5_FLT_Pin; 80017c6: f44f 5340 mov.w r3, #12288 ; 0x3000 80017ca: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80017cc: 2300 movs r3, #0 80017ce: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 80017d0: 2300 movs r3, #0 80017d2: 637b str r3, [r7, #52] ; 0x34 HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); 80017d4: f107 032c add.w r3, r7, #44 ; 0x2c 80017d8: 4619 mov r1, r3 80017da: 4828 ldr r0, [pc, #160] ; (800187c ) 80017dc: f003 fb72 bl 8004ec4 /*Configure GPIO pins : USART10_FLT_Pin UART9_FLT_Pin */ GPIO_InitStruct.Pin = USART10_FLT_Pin|UART9_FLT_Pin; 80017e0: 23c0 movs r3, #192 ; 0xc0 80017e2: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80017e4: 2300 movs r3, #0 80017e6: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 80017e8: 2300 movs r3, #0 80017ea: 637b str r3, [r7, #52] ; 0x34 HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 80017ec: f107 032c add.w r3, r7, #44 ; 0x2c 80017f0: 4619 mov r1, r3 80017f2: 481d ldr r0, [pc, #116] ; (8001868 ) 80017f4: f003 fb66 bl 8004ec4 /*Configure GPIO pin : LPUART1_FLT_Pin */ GPIO_InitStruct.Pin = LPUART1_FLT_Pin; 80017f8: 2320 movs r3, #32 80017fa: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80017fc: 2300 movs r3, #0 80017fe: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001800: 2300 movs r3, #0 8001802: 637b str r3, [r7, #52] ; 0x34 HAL_GPIO_Init(LPUART1_FLT_GPIO_Port, &GPIO_InitStruct); 8001804: f107 032c add.w r3, r7, #44 ; 0x2c 8001808: 4619 mov r1, r3 800180a: 481d ldr r0, [pc, #116] ; (8001880 ) 800180c: f003 fb5a bl 8004ec4 /*Configure GPIO pins : USART2_FLT_Pin UART8_FLT_Pin */ GPIO_InitStruct.Pin = USART2_FLT_Pin|UART8_FLT_Pin; 8001810: f44f 53c0 mov.w r3, #6144 ; 0x1800 8001814: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8001816: 2300 movs r3, #0 8001818: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 800181a: 2300 movs r3, #0 800181c: 637b str r3, [r7, #52] ; 0x34 HAL_GPIO_Init(GPIOJ, &GPIO_InitStruct); 800181e: f107 032c add.w r3, r7, #44 ; 0x2c 8001822: 4619 mov r1, r3 8001824: 4813 ldr r0, [pc, #76] ; (8001874 ) 8001826: f003 fb4d bl 8004ec4 /*Configure GPIO pin : PA10 */ GPIO_InitStruct.Pin = GPIO_PIN_10; 800182a: f44f 6380 mov.w r3, #1024 ; 0x400 800182e: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001830: 2302 movs r3, #2 8001832: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001834: 2300 movs r3, #0 8001836: 637b str r3, [r7, #52] ; 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001838: 2300 movs r3, #0 800183a: 63bb str r3, [r7, #56] ; 0x38 GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_HS; 800183c: 230a movs r3, #10 800183e: 63fb str r3, [r7, #60] ; 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001840: f107 032c add.w r3, r7, #44 ; 0x2c 8001844: 4619 mov r1, r3 8001846: 480c ldr r0, [pc, #48] ; (8001878 ) 8001848: f003 fb3c bl 8004ec4 /*Configure GPIO pins : USART10_FLTC13_Pin UART7_FLT_Pin uSD_Detec_Pin */ GPIO_InitStruct.Pin = USART10_FLTC13_Pin|UART7_FLT_Pin|uSD_Detec_Pin; 800184c: f242 0314 movw r3, #8212 ; 0x2014 8001850: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8001852: 2300 movs r3, #0 8001854: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001856: 2300 movs r3, #0 8001858: 637b str r3, [r7, #52] ; 0x34 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800185a: f107 032c add.w r3, r7, #44 ; 0x2c 800185e: 4619 mov r1, r3 8001860: e012 b.n 8001888 8001862: bf00 nop 8001864: 58024400 .word 0x58024400 8001868: 58021000 .word 0x58021000 800186c: 58022000 .word 0x58022000 8001870: 58022800 .word 0x58022800 8001874: 58022400 .word 0x58022400 8001878: 58020000 .word 0x58020000 800187c: 58021c00 .word 0x58021c00 8001880: 58020400 .word 0x58020400 8001884: 58020c00 .word 0x58020c00 8001888: 4820 ldr r0, [pc, #128] ; (800190c ) 800188a: f003 fb1b bl 8004ec4 /*Configure GPIO pin : USART1_PWRA8_Pin */ GPIO_InitStruct.Pin = USART1_PWRA8_Pin; 800188e: f44f 7380 mov.w r3, #256 ; 0x100 8001892: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001894: 2301 movs r3, #1 8001896: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001898: 2300 movs r3, #0 800189a: 637b str r3, [r7, #52] ; 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800189c: 2300 movs r3, #0 800189e: 63bb str r3, [r7, #56] ; 0x38 HAL_GPIO_Init(USART1_PWRA8_GPIO_Port, &GPIO_InitStruct); 80018a0: f107 032c add.w r3, r7, #44 ; 0x2c 80018a4: 4619 mov r1, r3 80018a6: 481a ldr r0, [pc, #104] ; (8001910 ) 80018a8: f003 fb0c bl 8004ec4 /*Configure GPIO pin : USART3_FLT_Pin */ GPIO_InitStruct.Pin = USART3_FLT_Pin; 80018ac: f44f 6380 mov.w r3, #1024 ; 0x400 80018b0: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80018b2: 2300 movs r3, #0 80018b4: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 80018b6: 2300 movs r3, #0 80018b8: 637b str r3, [r7, #52] ; 0x34 HAL_GPIO_Init(USART3_FLT_GPIO_Port, &GPIO_InitStruct); 80018ba: f107 032c add.w r3, r7, #44 ; 0x2c 80018be: 4619 mov r1, r3 80018c0: 4814 ldr r0, [pc, #80] ; (8001914 ) 80018c2: f003 faff bl 8004ec4 /*Configure GPIO pins : UART5_PWR_Pin UART9_PWR_Pin */ GPIO_InitStruct.Pin = UART5_PWR_Pin|UART9_PWR_Pin; 80018c6: f44f 6388 mov.w r3, #1088 ; 0x440 80018ca: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80018cc: 2301 movs r3, #1 80018ce: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 80018d0: 2300 movs r3, #0 80018d2: 637b str r3, [r7, #52] ; 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80018d4: 2300 movs r3, #0 80018d6: 63bb str r3, [r7, #56] ; 0x38 HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); 80018d8: f107 032c add.w r3, r7, #44 ; 0x2c 80018dc: 4619 mov r1, r3 80018de: 480e ldr r0, [pc, #56] ; (8001918 ) 80018e0: f003 faf0 bl 8004ec4 /*Configure GPIO pin : USART3_PWR_Pin */ GPIO_InitStruct.Pin = USART3_PWR_Pin; 80018e4: f44f 4380 mov.w r3, #16384 ; 0x4000 80018e8: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80018ea: 2301 movs r3, #1 80018ec: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Pull = GPIO_NOPULL; 80018ee: 2300 movs r3, #0 80018f0: 637b str r3, [r7, #52] ; 0x34 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80018f2: 2300 movs r3, #0 80018f4: 63bb str r3, [r7, #56] ; 0x38 HAL_GPIO_Init(USART3_PWR_GPIO_Port, &GPIO_InitStruct); 80018f6: f107 032c add.w r3, r7, #44 ; 0x2c 80018fa: 4619 mov r1, r3 80018fc: 4807 ldr r0, [pc, #28] ; (800191c ) 80018fe: f003 fae1 bl 8004ec4 } 8001902: bf00 nop 8001904: 3740 adds r7, #64 ; 0x40 8001906: 46bd mov sp, r7 8001908: bd80 pop {r7, pc} 800190a: bf00 nop 800190c: 58020800 .word 0x58020800 8001910: 58020000 .word 0x58020000 8001914: 58020c00 .word 0x58020c00 8001918: 58021c00 .word 0x58021c00 800191c: 58020400 .word 0x58020400 08001920 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8001920: b480 push {r7} 8001922: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8001924: b672 cpsid i } 8001926: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8001928: e7fe b.n 8001928 ... 0800192c : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 800192c: b480 push {r7} 800192e: b083 sub sp, #12 8001930: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8001932: 4b0a ldr r3, [pc, #40] ; (800195c ) 8001934: f8d3 3154 ldr.w r3, [r3, #340] ; 0x154 8001938: 4a08 ldr r2, [pc, #32] ; (800195c ) 800193a: f043 0302 orr.w r3, r3, #2 800193e: f8c2 3154 str.w r3, [r2, #340] ; 0x154 8001942: 4b06 ldr r3, [pc, #24] ; (800195c ) 8001944: f8d3 3154 ldr.w r3, [r3, #340] ; 0x154 8001948: f003 0302 and.w r3, r3, #2 800194c: 607b str r3, [r7, #4] 800194e: 687b ldr r3, [r7, #4] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8001950: bf00 nop 8001952: 370c adds r7, #12 8001954: 46bd mov sp, r7 8001956: f85d 7b04 ldr.w r7, [sp], #4 800195a: 4770 bx lr 800195c: 58024400 .word 0x58024400 08001960 : * This function configures the hardware resources used in this example * @param hi2c: I2C handle pointer * @retval None */ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) { 8001960: b580 push {r7, lr} 8001962: b0bc sub sp, #240 ; 0xf0 8001964: af00 add r7, sp, #0 8001966: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001968: f107 03dc add.w r3, r7, #220 ; 0xdc 800196c: 2200 movs r2, #0 800196e: 601a str r2, [r3, #0] 8001970: 605a str r2, [r3, #4] 8001972: 609a str r2, [r3, #8] 8001974: 60da str r2, [r3, #12] 8001976: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8001978: f107 0324 add.w r3, r7, #36 ; 0x24 800197c: 22b8 movs r2, #184 ; 0xb8 800197e: 2100 movs r1, #0 8001980: 4618 mov r0, r3 8001982: f00c fe4f bl 800e624 if(hi2c->Instance==I2C2) 8001986: 687b ldr r3, [r7, #4] 8001988: 681b ldr r3, [r3, #0] 800198a: 4a80 ldr r2, [pc, #512] ; (8001b8c ) 800198c: 4293 cmp r3, r2 800198e: d142 bne.n 8001a16 /* USER CODE BEGIN I2C2_MspInit 0 */ /* USER CODE END I2C2_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C2; 8001990: 2308 movs r3, #8 8001992: 627b str r3, [r7, #36] ; 0x24 PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1; 8001994: 2300 movs r3, #0 8001996: f8c7 30ac str.w r3, [r7, #172] ; 0xac if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 800199a: f107 0324 add.w r3, r7, #36 ; 0x24 800199e: 4618 mov r0, r3 80019a0: f005 fd96 bl 80074d0 80019a4: 4603 mov r3, r0 80019a6: 2b00 cmp r3, #0 80019a8: d001 beq.n 80019ae { Error_Handler(); 80019aa: f7ff ffb9 bl 8001920 } __HAL_RCC_GPIOF_CLK_ENABLE(); 80019ae: 4b78 ldr r3, [pc, #480] ; (8001b90 ) 80019b0: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80019b4: 4a76 ldr r2, [pc, #472] ; (8001b90 ) 80019b6: f043 0320 orr.w r3, r3, #32 80019ba: f8c2 3140 str.w r3, [r2, #320] ; 0x140 80019be: 4b74 ldr r3, [pc, #464] ; (8001b90 ) 80019c0: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80019c4: f003 0320 and.w r3, r3, #32 80019c8: 623b str r3, [r7, #32] 80019ca: 6a3b ldr r3, [r7, #32] /**I2C2 GPIO Configuration PF1 ------> I2C2_SCL PF0 ------> I2C2_SDA */ GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_0; 80019cc: 2303 movs r3, #3 80019ce: f8c7 30dc str.w r3, [r7, #220] ; 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 80019d2: 2312 movs r3, #18 80019d4: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 GPIO_InitStruct.Pull = GPIO_PULLUP; 80019d8: 2301 movs r3, #1 80019da: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80019de: 2300 movs r3, #0 80019e0: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8 GPIO_InitStruct.Alternate = GPIO_AF4_I2C2; 80019e4: 2304 movs r3, #4 80019e6: f8c7 30ec str.w r3, [r7, #236] ; 0xec HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 80019ea: f107 03dc add.w r3, r7, #220 ; 0xdc 80019ee: 4619 mov r1, r3 80019f0: 4868 ldr r0, [pc, #416] ; (8001b94 ) 80019f2: f003 fa67 bl 8004ec4 /* Peripheral clock enable */ __HAL_RCC_I2C2_CLK_ENABLE(); 80019f6: 4b66 ldr r3, [pc, #408] ; (8001b90 ) 80019f8: f8d3 3148 ldr.w r3, [r3, #328] ; 0x148 80019fc: 4a64 ldr r2, [pc, #400] ; (8001b90 ) 80019fe: f443 0380 orr.w r3, r3, #4194304 ; 0x400000 8001a02: f8c2 3148 str.w r3, [r2, #328] ; 0x148 8001a06: 4b62 ldr r3, [pc, #392] ; (8001b90 ) 8001a08: f8d3 3148 ldr.w r3, [r3, #328] ; 0x148 8001a0c: f403 0380 and.w r3, r3, #4194304 ; 0x400000 8001a10: 61fb str r3, [r7, #28] 8001a12: 69fb ldr r3, [r7, #28] /* USER CODE BEGIN I2C4_MspInit 1 */ /* USER CODE END I2C4_MspInit 1 */ } } 8001a14: e0b5 b.n 8001b82 else if(hi2c->Instance==I2C3) 8001a16: 687b ldr r3, [r7, #4] 8001a18: 681b ldr r3, [r3, #0] 8001a1a: 4a5f ldr r2, [pc, #380] ; (8001b98 ) 8001a1c: 4293 cmp r3, r2 8001a1e: d143 bne.n 8001aa8 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C3; 8001a20: 2308 movs r3, #8 8001a22: 627b str r3, [r7, #36] ; 0x24 PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1; 8001a24: 2300 movs r3, #0 8001a26: f8c7 30ac str.w r3, [r7, #172] ; 0xac if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8001a2a: f107 0324 add.w r3, r7, #36 ; 0x24 8001a2e: 4618 mov r0, r3 8001a30: f005 fd4e bl 80074d0 8001a34: 4603 mov r3, r0 8001a36: 2b00 cmp r3, #0 8001a38: d001 beq.n 8001a3e Error_Handler(); 8001a3a: f7ff ff71 bl 8001920 __HAL_RCC_GPIOH_CLK_ENABLE(); 8001a3e: 4b54 ldr r3, [pc, #336] ; (8001b90 ) 8001a40: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001a44: 4a52 ldr r2, [pc, #328] ; (8001b90 ) 8001a46: f043 0380 orr.w r3, r3, #128 ; 0x80 8001a4a: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8001a4e: 4b50 ldr r3, [pc, #320] ; (8001b90 ) 8001a50: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001a54: f003 0380 and.w r3, r3, #128 ; 0x80 8001a58: 61bb str r3, [r7, #24] 8001a5a: 69bb ldr r3, [r7, #24] GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_7; 8001a5c: f44f 73c0 mov.w r3, #384 ; 0x180 8001a60: f8c7 30dc str.w r3, [r7, #220] ; 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 8001a64: 2312 movs r3, #18 8001a66: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 GPIO_InitStruct.Pull = GPIO_PULLUP; 8001a6a: 2301 movs r3, #1 8001a6c: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001a70: 2300 movs r3, #0 8001a72: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8 GPIO_InitStruct.Alternate = GPIO_AF4_I2C3; 8001a76: 2304 movs r3, #4 8001a78: f8c7 30ec str.w r3, [r7, #236] ; 0xec HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); 8001a7c: f107 03dc add.w r3, r7, #220 ; 0xdc 8001a80: 4619 mov r1, r3 8001a82: 4846 ldr r0, [pc, #280] ; (8001b9c ) 8001a84: f003 fa1e bl 8004ec4 __HAL_RCC_I2C3_CLK_ENABLE(); 8001a88: 4b41 ldr r3, [pc, #260] ; (8001b90 ) 8001a8a: f8d3 3148 ldr.w r3, [r3, #328] ; 0x148 8001a8e: 4a40 ldr r2, [pc, #256] ; (8001b90 ) 8001a90: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 8001a94: f8c2 3148 str.w r3, [r2, #328] ; 0x148 8001a98: 4b3d ldr r3, [pc, #244] ; (8001b90 ) 8001a9a: f8d3 3148 ldr.w r3, [r3, #328] ; 0x148 8001a9e: f403 0300 and.w r3, r3, #8388608 ; 0x800000 8001aa2: 617b str r3, [r7, #20] 8001aa4: 697b ldr r3, [r7, #20] } 8001aa6: e06c b.n 8001b82 else if(hi2c->Instance==I2C4) 8001aa8: 687b ldr r3, [r7, #4] 8001aaa: 681b ldr r3, [r3, #0] 8001aac: 4a3c ldr r2, [pc, #240] ; (8001ba0 ) 8001aae: 4293 cmp r3, r2 8001ab0: d167 bne.n 8001b82 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C4; 8001ab2: 2310 movs r3, #16 8001ab4: 627b str r3, [r7, #36] ; 0x24 PeriphClkInitStruct.I2c4ClockSelection = RCC_I2C4CLKSOURCE_D3PCLK1; 8001ab6: 2300 movs r3, #0 8001ab8: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8001abc: f107 0324 add.w r3, r7, #36 ; 0x24 8001ac0: 4618 mov r0, r3 8001ac2: f005 fd05 bl 80074d0 8001ac6: 4603 mov r3, r0 8001ac8: 2b00 cmp r3, #0 8001aca: d001 beq.n 8001ad0 Error_Handler(); 8001acc: f7ff ff28 bl 8001920 __HAL_RCC_GPIOB_CLK_ENABLE(); 8001ad0: 4b2f ldr r3, [pc, #188] ; (8001b90 ) 8001ad2: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001ad6: 4a2e ldr r2, [pc, #184] ; (8001b90 ) 8001ad8: f043 0302 orr.w r3, r3, #2 8001adc: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8001ae0: 4b2b ldr r3, [pc, #172] ; (8001b90 ) 8001ae2: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001ae6: f003 0302 and.w r3, r3, #2 8001aea: 613b str r3, [r7, #16] 8001aec: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOF_CLK_ENABLE(); 8001aee: 4b28 ldr r3, [pc, #160] ; (8001b90 ) 8001af0: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001af4: 4a26 ldr r2, [pc, #152] ; (8001b90 ) 8001af6: f043 0320 orr.w r3, r3, #32 8001afa: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8001afe: 4b24 ldr r3, [pc, #144] ; (8001b90 ) 8001b00: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001b04: f003 0320 and.w r3, r3, #32 8001b08: 60fb str r3, [r7, #12] 8001b0a: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_8; 8001b0c: f44f 7380 mov.w r3, #256 ; 0x100 8001b10: f8c7 30dc str.w r3, [r7, #220] ; 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 8001b14: 2312 movs r3, #18 8001b16: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001b1a: 2300 movs r3, #0 8001b1c: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001b20: 2300 movs r3, #0 8001b22: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8 GPIO_InitStruct.Alternate = GPIO_AF6_I2C4; 8001b26: 2306 movs r3, #6 8001b28: f8c7 30ec str.w r3, [r7, #236] ; 0xec HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001b2c: f107 03dc add.w r3, r7, #220 ; 0xdc 8001b30: 4619 mov r1, r3 8001b32: 481c ldr r0, [pc, #112] ; (8001ba4 ) 8001b34: f003 f9c6 bl 8004ec4 GPIO_InitStruct.Pin = GPIO_PIN_15; 8001b38: f44f 4300 mov.w r3, #32768 ; 0x8000 8001b3c: f8c7 30dc str.w r3, [r7, #220] ; 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 8001b40: 2312 movs r3, #18 8001b42: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001b46: 2300 movs r3, #0 8001b48: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001b4c: 2300 movs r3, #0 8001b4e: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8 GPIO_InitStruct.Alternate = GPIO_AF4_I2C4; 8001b52: 2304 movs r3, #4 8001b54: f8c7 30ec str.w r3, [r7, #236] ; 0xec HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 8001b58: f107 03dc add.w r3, r7, #220 ; 0xdc 8001b5c: 4619 mov r1, r3 8001b5e: 480d ldr r0, [pc, #52] ; (8001b94 ) 8001b60: f003 f9b0 bl 8004ec4 __HAL_RCC_I2C4_CLK_ENABLE(); 8001b64: 4b0a ldr r3, [pc, #40] ; (8001b90 ) 8001b66: f8d3 3154 ldr.w r3, [r3, #340] ; 0x154 8001b6a: 4a09 ldr r2, [pc, #36] ; (8001b90 ) 8001b6c: f043 0380 orr.w r3, r3, #128 ; 0x80 8001b70: f8c2 3154 str.w r3, [r2, #340] ; 0x154 8001b74: 4b06 ldr r3, [pc, #24] ; (8001b90 ) 8001b76: f8d3 3154 ldr.w r3, [r3, #340] ; 0x154 8001b7a: f003 0380 and.w r3, r3, #128 ; 0x80 8001b7e: 60bb str r3, [r7, #8] 8001b80: 68bb ldr r3, [r7, #8] } 8001b82: bf00 nop 8001b84: 37f0 adds r7, #240 ; 0xf0 8001b86: 46bd mov sp, r7 8001b88: bd80 pop {r7, pc} 8001b8a: bf00 nop 8001b8c: 40005800 .word 0x40005800 8001b90: 58024400 .word 0x58024400 8001b94: 58021400 .word 0x58021400 8001b98: 40005c00 .word 0x40005c00 8001b9c: 58021c00 .word 0x58021c00 8001ba0: 58001c00 .word 0x58001c00 8001ba4: 58020400 .word 0x58020400 08001ba8 : * This function configures the hardware resources used in this example * @param hlptim: LPTIM handle pointer * @retval None */ void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef* hlptim) { 8001ba8: b580 push {r7, lr} 8001baa: b0b2 sub sp, #200 ; 0xc8 8001bac: af00 add r7, sp, #0 8001bae: 6078 str r0, [r7, #4] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8001bb0: f107 0310 add.w r3, r7, #16 8001bb4: 22b8 movs r2, #184 ; 0xb8 8001bb6: 2100 movs r1, #0 8001bb8: 4618 mov r0, r3 8001bba: f00c fd33 bl 800e624 if(hlptim->Instance==LPTIM1) 8001bbe: 687b ldr r3, [r7, #4] 8001bc0: 681b ldr r3, [r3, #0] 8001bc2: 4a24 ldr r2, [pc, #144] ; (8001c54 ) 8001bc4: 4293 cmp r3, r2 8001bc6: d11e bne.n 8001c06 /* USER CODE BEGIN LPTIM1_MspInit 0 */ /* USER CODE END LPTIM1_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPTIM1; 8001bc8: 2320 movs r3, #32 8001bca: 613b str r3, [r7, #16] PeriphClkInitStruct.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_D2PCLK1; 8001bcc: 2300 movs r3, #0 8001bce: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8001bd2: f107 0310 add.w r3, r7, #16 8001bd6: 4618 mov r0, r3 8001bd8: f005 fc7a bl 80074d0 8001bdc: 4603 mov r3, r0 8001bde: 2b00 cmp r3, #0 8001be0: d001 beq.n 8001be6 { Error_Handler(); 8001be2: f7ff fe9d bl 8001920 } /* Peripheral clock enable */ __HAL_RCC_LPTIM1_CLK_ENABLE(); 8001be6: 4b1c ldr r3, [pc, #112] ; (8001c58 ) 8001be8: f8d3 3148 ldr.w r3, [r3, #328] ; 0x148 8001bec: 4a1a ldr r2, [pc, #104] ; (8001c58 ) 8001bee: f443 7300 orr.w r3, r3, #512 ; 0x200 8001bf2: f8c2 3148 str.w r3, [r2, #328] ; 0x148 8001bf6: 4b18 ldr r3, [pc, #96] ; (8001c58 ) 8001bf8: f8d3 3148 ldr.w r3, [r3, #328] ; 0x148 8001bfc: f403 7300 and.w r3, r3, #512 ; 0x200 8001c00: 60fb str r3, [r7, #12] 8001c02: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN LPTIM3_MspInit 1 */ /* USER CODE END LPTIM3_MspInit 1 */ } } 8001c04: e022 b.n 8001c4c else if(hlptim->Instance==LPTIM3) 8001c06: 687b ldr r3, [r7, #4] 8001c08: 681b ldr r3, [r3, #0] 8001c0a: 4a14 ldr r2, [pc, #80] ; (8001c5c ) 8001c0c: 4293 cmp r3, r2 8001c0e: d11d bne.n 8001c4c PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPTIM3; 8001c10: 2380 movs r3, #128 ; 0x80 8001c12: 613b str r3, [r7, #16] PeriphClkInitStruct.Lptim345ClockSelection = RCC_LPTIM3CLKSOURCE_D3PCLK1; 8001c14: 2300 movs r3, #0 8001c16: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8001c1a: f107 0310 add.w r3, r7, #16 8001c1e: 4618 mov r0, r3 8001c20: f005 fc56 bl 80074d0 8001c24: 4603 mov r3, r0 8001c26: 2b00 cmp r3, #0 8001c28: d001 beq.n 8001c2e Error_Handler(); 8001c2a: f7ff fe79 bl 8001920 __HAL_RCC_LPTIM3_CLK_ENABLE(); 8001c2e: 4b0a ldr r3, [pc, #40] ; (8001c58 ) 8001c30: f8d3 3154 ldr.w r3, [r3, #340] ; 0x154 8001c34: 4a08 ldr r2, [pc, #32] ; (8001c58 ) 8001c36: f443 6380 orr.w r3, r3, #1024 ; 0x400 8001c3a: f8c2 3154 str.w r3, [r2, #340] ; 0x154 8001c3e: 4b06 ldr r3, [pc, #24] ; (8001c58 ) 8001c40: f8d3 3154 ldr.w r3, [r3, #340] ; 0x154 8001c44: f403 6380 and.w r3, r3, #1024 ; 0x400 8001c48: 60bb str r3, [r7, #8] 8001c4a: 68bb ldr r3, [r7, #8] } 8001c4c: bf00 nop 8001c4e: 37c8 adds r7, #200 ; 0xc8 8001c50: 46bd mov sp, r7 8001c52: bd80 pop {r7, pc} 8001c54: 40002400 .word 0x40002400 8001c58: 58024400 .word 0x58024400 8001c5c: 58002800 .word 0x58002800 08001c60 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 8001c60: b580 push {r7, lr} 8001c62: b0cc sub sp, #304 ; 0x130 8001c64: af00 add r7, sp, #0 8001c66: 1d3b adds r3, r7, #4 8001c68: 6018 str r0, [r3, #0] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001c6a: f507 738e add.w r3, r7, #284 ; 0x11c 8001c6e: 2200 movs r2, #0 8001c70: 601a str r2, [r3, #0] 8001c72: 605a str r2, [r3, #4] 8001c74: 609a str r2, [r3, #8] 8001c76: 60da str r2, [r3, #12] 8001c78: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8001c7a: f107 0364 add.w r3, r7, #100 ; 0x64 8001c7e: 22b8 movs r2, #184 ; 0xb8 8001c80: 2100 movs r1, #0 8001c82: 4618 mov r0, r3 8001c84: f00c fcce bl 800e624 if(huart->Instance==LPUART1) 8001c88: 1d3b adds r3, r7, #4 8001c8a: 681b ldr r3, [r3, #0] 8001c8c: 681b ldr r3, [r3, #0] 8001c8e: 4aa4 ldr r2, [pc, #656] ; (8001f20 ) 8001c90: 4293 cmp r3, r2 8001c92: d142 bne.n 8001d1a /* USER CODE BEGIN LPUART1_MspInit 0 */ /* USER CODE END LPUART1_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; 8001c94: 2304 movs r3, #4 8001c96: 667b str r3, [r7, #100] ; 0x64 PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_D3PCLK1; 8001c98: 2300 movs r3, #0 8001c9a: f8c7 30fc str.w r3, [r7, #252] ; 0xfc if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8001c9e: f107 0364 add.w r3, r7, #100 ; 0x64 8001ca2: 4618 mov r0, r3 8001ca4: f005 fc14 bl 80074d0 8001ca8: 4603 mov r3, r0 8001caa: 2b00 cmp r3, #0 8001cac: d001 beq.n 8001cb2 { Error_Handler(); 8001cae: f7ff fe37 bl 8001920 } /* Peripheral clock enable */ __HAL_RCC_LPUART1_CLK_ENABLE(); 8001cb2: 4b9c ldr r3, [pc, #624] ; (8001f24 ) 8001cb4: f8d3 3154 ldr.w r3, [r3, #340] ; 0x154 8001cb8: 4a9a ldr r2, [pc, #616] ; (8001f24 ) 8001cba: f043 0308 orr.w r3, r3, #8 8001cbe: f8c2 3154 str.w r3, [r2, #340] ; 0x154 8001cc2: 4b98 ldr r3, [pc, #608] ; (8001f24 ) 8001cc4: f8d3 3154 ldr.w r3, [r3, #340] ; 0x154 8001cc8: f003 0308 and.w r3, r3, #8 8001ccc: 663b str r3, [r7, #96] ; 0x60 8001cce: 6e3b ldr r3, [r7, #96] ; 0x60 __HAL_RCC_GPIOB_CLK_ENABLE(); 8001cd0: 4b94 ldr r3, [pc, #592] ; (8001f24 ) 8001cd2: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001cd6: 4a93 ldr r2, [pc, #588] ; (8001f24 ) 8001cd8: f043 0302 orr.w r3, r3, #2 8001cdc: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8001ce0: 4b90 ldr r3, [pc, #576] ; (8001f24 ) 8001ce2: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001ce6: f003 0302 and.w r3, r3, #2 8001cea: 65fb str r3, [r7, #92] ; 0x5c 8001cec: 6dfb ldr r3, [r7, #92] ; 0x5c /**LPUART1 GPIO Configuration PB6 ------> LPUART1_TX PB7 ------> LPUART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; 8001cee: 23c0 movs r3, #192 ; 0xc0 8001cf0: f8c7 311c str.w r3, [r7, #284] ; 0x11c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001cf4: 2302 movs r3, #2 8001cf6: f8c7 3120 str.w r3, [r7, #288] ; 0x120 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001cfa: 2300 movs r3, #0 8001cfc: f8c7 3124 str.w r3, [r7, #292] ; 0x124 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001d00: 2300 movs r3, #0 8001d02: f8c7 3128 str.w r3, [r7, #296] ; 0x128 GPIO_InitStruct.Alternate = GPIO_AF8_LPUART; 8001d06: 2308 movs r3, #8 8001d08: f8c7 312c str.w r3, [r7, #300] ; 0x12c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001d0c: f507 738e add.w r3, r7, #284 ; 0x11c 8001d10: 4619 mov r1, r3 8001d12: 4885 ldr r0, [pc, #532] ; (8001f28 ) 8001d14: f003 f8d6 bl 8004ec4 /* USER CODE BEGIN USART3_MspInit 1 */ /* USER CODE END USART3_MspInit 1 */ } } 8001d18: e3b3 b.n 8002482 else if(huart->Instance==UART4) 8001d1a: 1d3b adds r3, r7, #4 8001d1c: 681b ldr r3, [r3, #0] 8001d1e: 681b ldr r3, [r3, #0] 8001d20: 4a82 ldr r2, [pc, #520] ; (8001f2c ) 8001d22: 4293 cmp r3, r2 8001d24: d168 bne.n 8001df8 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART4; 8001d26: 2302 movs r3, #2 8001d28: 667b str r3, [r7, #100] ; 0x64 PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; 8001d2a: 2300 movs r3, #0 8001d2c: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8001d30: f107 0364 add.w r3, r7, #100 ; 0x64 8001d34: 4618 mov r0, r3 8001d36: f005 fbcb bl 80074d0 8001d3a: 4603 mov r3, r0 8001d3c: 2b00 cmp r3, #0 8001d3e: d001 beq.n 8001d44 Error_Handler(); 8001d40: f7ff fdee bl 8001920 __HAL_RCC_UART4_CLK_ENABLE(); 8001d44: 4b77 ldr r3, [pc, #476] ; (8001f24 ) 8001d46: f8d3 3148 ldr.w r3, [r3, #328] ; 0x148 8001d4a: 4a76 ldr r2, [pc, #472] ; (8001f24 ) 8001d4c: f443 2300 orr.w r3, r3, #524288 ; 0x80000 8001d50: f8c2 3148 str.w r3, [r2, #328] ; 0x148 8001d54: 4b73 ldr r3, [pc, #460] ; (8001f24 ) 8001d56: f8d3 3148 ldr.w r3, [r3, #328] ; 0x148 8001d5a: f403 2300 and.w r3, r3, #524288 ; 0x80000 8001d5e: 65bb str r3, [r7, #88] ; 0x58 8001d60: 6dbb ldr r3, [r7, #88] ; 0x58 __HAL_RCC_GPIOB_CLK_ENABLE(); 8001d62: 4b70 ldr r3, [pc, #448] ; (8001f24 ) 8001d64: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001d68: 4a6e ldr r2, [pc, #440] ; (8001f24 ) 8001d6a: f043 0302 orr.w r3, r3, #2 8001d6e: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8001d72: 4b6c ldr r3, [pc, #432] ; (8001f24 ) 8001d74: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001d78: f003 0302 and.w r3, r3, #2 8001d7c: 657b str r3, [r7, #84] ; 0x54 8001d7e: 6d7b ldr r3, [r7, #84] ; 0x54 __HAL_RCC_GPIOH_CLK_ENABLE(); 8001d80: 4b68 ldr r3, [pc, #416] ; (8001f24 ) 8001d82: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001d86: 4a67 ldr r2, [pc, #412] ; (8001f24 ) 8001d88: f043 0380 orr.w r3, r3, #128 ; 0x80 8001d8c: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8001d90: 4b64 ldr r3, [pc, #400] ; (8001f24 ) 8001d92: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001d96: f003 0380 and.w r3, r3, #128 ; 0x80 8001d9a: 653b str r3, [r7, #80] ; 0x50 8001d9c: 6d3b ldr r3, [r7, #80] ; 0x50 GPIO_InitStruct.Pin = GPIO_PIN_9; 8001d9e: f44f 7300 mov.w r3, #512 ; 0x200 8001da2: f8c7 311c str.w r3, [r7, #284] ; 0x11c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001da6: 2302 movs r3, #2 8001da8: f8c7 3120 str.w r3, [r7, #288] ; 0x120 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001dac: 2300 movs r3, #0 8001dae: f8c7 3124 str.w r3, [r7, #292] ; 0x124 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001db2: 2300 movs r3, #0 8001db4: f8c7 3128 str.w r3, [r7, #296] ; 0x128 GPIO_InitStruct.Alternate = GPIO_AF8_UART4; 8001db8: 2308 movs r3, #8 8001dba: f8c7 312c str.w r3, [r7, #300] ; 0x12c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001dbe: f507 738e add.w r3, r7, #284 ; 0x11c 8001dc2: 4619 mov r1, r3 8001dc4: 4858 ldr r0, [pc, #352] ; (8001f28 ) 8001dc6: f003 f87d bl 8004ec4 GPIO_InitStruct.Pin = GPIO_PIN_14; 8001dca: f44f 4380 mov.w r3, #16384 ; 0x4000 8001dce: f8c7 311c str.w r3, [r7, #284] ; 0x11c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001dd2: 2302 movs r3, #2 8001dd4: f8c7 3120 str.w r3, [r7, #288] ; 0x120 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001dd8: 2300 movs r3, #0 8001dda: f8c7 3124 str.w r3, [r7, #292] ; 0x124 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001dde: 2300 movs r3, #0 8001de0: f8c7 3128 str.w r3, [r7, #296] ; 0x128 GPIO_InitStruct.Alternate = GPIO_AF8_UART4; 8001de4: 2308 movs r3, #8 8001de6: f8c7 312c str.w r3, [r7, #300] ; 0x12c HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); 8001dea: f507 738e add.w r3, r7, #284 ; 0x11c 8001dee: 4619 mov r1, r3 8001df0: 484f ldr r0, [pc, #316] ; (8001f30 ) 8001df2: f003 f867 bl 8004ec4 } 8001df6: e344 b.n 8002482 else if(huart->Instance==UART5) 8001df8: 1d3b adds r3, r7, #4 8001dfa: 681b ldr r3, [r3, #0] 8001dfc: 681b ldr r3, [r3, #0] 8001dfe: 4a4d ldr r2, [pc, #308] ; (8001f34 ) 8001e00: 4293 cmp r3, r2 8001e02: d143 bne.n 8001e8c PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART5; 8001e04: 2302 movs r3, #2 8001e06: 667b str r3, [r7, #100] ; 0x64 PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; 8001e08: 2300 movs r3, #0 8001e0a: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8001e0e: f107 0364 add.w r3, r7, #100 ; 0x64 8001e12: 4618 mov r0, r3 8001e14: f005 fb5c bl 80074d0 8001e18: 4603 mov r3, r0 8001e1a: 2b00 cmp r3, #0 8001e1c: d001 beq.n 8001e22 Error_Handler(); 8001e1e: f7ff fd7f bl 8001920 __HAL_RCC_UART5_CLK_ENABLE(); 8001e22: 4b40 ldr r3, [pc, #256] ; (8001f24 ) 8001e24: f8d3 3148 ldr.w r3, [r3, #328] ; 0x148 8001e28: 4a3e ldr r2, [pc, #248] ; (8001f24 ) 8001e2a: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 8001e2e: f8c2 3148 str.w r3, [r2, #328] ; 0x148 8001e32: 4b3c ldr r3, [pc, #240] ; (8001f24 ) 8001e34: f8d3 3148 ldr.w r3, [r3, #328] ; 0x148 8001e38: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8001e3c: 64fb str r3, [r7, #76] ; 0x4c 8001e3e: 6cfb ldr r3, [r7, #76] ; 0x4c __HAL_RCC_GPIOB_CLK_ENABLE(); 8001e40: 4b38 ldr r3, [pc, #224] ; (8001f24 ) 8001e42: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001e46: 4a37 ldr r2, [pc, #220] ; (8001f24 ) 8001e48: f043 0302 orr.w r3, r3, #2 8001e4c: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8001e50: 4b34 ldr r3, [pc, #208] ; (8001f24 ) 8001e52: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001e56: f003 0302 and.w r3, r3, #2 8001e5a: 64bb str r3, [r7, #72] ; 0x48 8001e5c: 6cbb ldr r3, [r7, #72] ; 0x48 GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_12; 8001e5e: f44f 5340 mov.w r3, #12288 ; 0x3000 8001e62: f8c7 311c str.w r3, [r7, #284] ; 0x11c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001e66: 2302 movs r3, #2 8001e68: f8c7 3120 str.w r3, [r7, #288] ; 0x120 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001e6c: 2300 movs r3, #0 8001e6e: f8c7 3124 str.w r3, [r7, #292] ; 0x124 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001e72: 2300 movs r3, #0 8001e74: f8c7 3128 str.w r3, [r7, #296] ; 0x128 GPIO_InitStruct.Alternate = GPIO_AF14_UART5; 8001e78: 230e movs r3, #14 8001e7a: f8c7 312c str.w r3, [r7, #300] ; 0x12c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001e7e: f507 738e add.w r3, r7, #284 ; 0x11c 8001e82: 4619 mov r1, r3 8001e84: 4828 ldr r0, [pc, #160] ; (8001f28 ) 8001e86: f003 f81d bl 8004ec4 } 8001e8a: e2fa b.n 8002482 else if(huart->Instance==UART7) 8001e8c: 1d3b adds r3, r7, #4 8001e8e: 681b ldr r3, [r3, #0] 8001e90: 681b ldr r3, [r3, #0] 8001e92: 4a29 ldr r2, [pc, #164] ; (8001f38 ) 8001e94: 4293 cmp r3, r2 8001e96: d153 bne.n 8001f40 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART7; 8001e98: 2302 movs r3, #2 8001e9a: 667b str r3, [r7, #100] ; 0x64 PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; 8001e9c: 2300 movs r3, #0 8001e9e: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8001ea2: f107 0364 add.w r3, r7, #100 ; 0x64 8001ea6: 4618 mov r0, r3 8001ea8: f005 fb12 bl 80074d0 8001eac: 4603 mov r3, r0 8001eae: 2b00 cmp r3, #0 8001eb0: d001 beq.n 8001eb6 Error_Handler(); 8001eb2: f7ff fd35 bl 8001920 __HAL_RCC_UART7_CLK_ENABLE(); 8001eb6: 4b1b ldr r3, [pc, #108] ; (8001f24 ) 8001eb8: f8d3 3148 ldr.w r3, [r3, #328] ; 0x148 8001ebc: 4a19 ldr r2, [pc, #100] ; (8001f24 ) 8001ebe: f043 4380 orr.w r3, r3, #1073741824 ; 0x40000000 8001ec2: f8c2 3148 str.w r3, [r2, #328] ; 0x148 8001ec6: 4b17 ldr r3, [pc, #92] ; (8001f24 ) 8001ec8: f8d3 3148 ldr.w r3, [r3, #328] ; 0x148 8001ecc: f003 4380 and.w r3, r3, #1073741824 ; 0x40000000 8001ed0: 647b str r3, [r7, #68] ; 0x44 8001ed2: 6c7b ldr r3, [r7, #68] ; 0x44 __HAL_RCC_GPIOF_CLK_ENABLE(); 8001ed4: 4b13 ldr r3, [pc, #76] ; (8001f24 ) 8001ed6: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001eda: 4a12 ldr r2, [pc, #72] ; (8001f24 ) 8001edc: f043 0320 orr.w r3, r3, #32 8001ee0: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8001ee4: 4b0f ldr r3, [pc, #60] ; (8001f24 ) 8001ee6: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001eea: f003 0320 and.w r3, r3, #32 8001eee: 643b str r3, [r7, #64] ; 0x40 8001ef0: 6c3b ldr r3, [r7, #64] ; 0x40 GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; 8001ef2: 23c0 movs r3, #192 ; 0xc0 8001ef4: f8c7 311c str.w r3, [r7, #284] ; 0x11c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001ef8: 2302 movs r3, #2 8001efa: f8c7 3120 str.w r3, [r7, #288] ; 0x120 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001efe: 2300 movs r3, #0 8001f00: f8c7 3124 str.w r3, [r7, #292] ; 0x124 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001f04: 2300 movs r3, #0 8001f06: f8c7 3128 str.w r3, [r7, #296] ; 0x128 GPIO_InitStruct.Alternate = GPIO_AF7_UART7; 8001f0a: 2307 movs r3, #7 8001f0c: f8c7 312c str.w r3, [r7, #300] ; 0x12c HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 8001f10: f507 738e add.w r3, r7, #284 ; 0x11c 8001f14: 4619 mov r1, r3 8001f16: 4809 ldr r0, [pc, #36] ; (8001f3c ) 8001f18: f002 ffd4 bl 8004ec4 } 8001f1c: e2b1 b.n 8002482 8001f1e: bf00 nop 8001f20: 58000c00 .word 0x58000c00 8001f24: 58024400 .word 0x58024400 8001f28: 58020400 .word 0x58020400 8001f2c: 40004c00 .word 0x40004c00 8001f30: 58021c00 .word 0x58021c00 8001f34: 40005000 .word 0x40005000 8001f38: 40007800 .word 0x40007800 8001f3c: 58021400 .word 0x58021400 else if(huart->Instance==UART8) 8001f40: 1d3b adds r3, r7, #4 8001f42: 681b ldr r3, [r3, #0] 8001f44: 681b ldr r3, [r3, #0] 8001f46: 4ac5 ldr r2, [pc, #788] ; (800225c ) 8001f48: 4293 cmp r3, r2 8001f4a: d168 bne.n 800201e PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART8; 8001f4c: 2302 movs r3, #2 8001f4e: 667b str r3, [r7, #100] ; 0x64 PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; 8001f50: 2300 movs r3, #0 8001f52: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8001f56: f107 0364 add.w r3, r7, #100 ; 0x64 8001f5a: 4618 mov r0, r3 8001f5c: f005 fab8 bl 80074d0 8001f60: 4603 mov r3, r0 8001f62: 2b00 cmp r3, #0 8001f64: d001 beq.n 8001f6a Error_Handler(); 8001f66: f7ff fcdb bl 8001920 __HAL_RCC_UART8_CLK_ENABLE(); 8001f6a: 4bbd ldr r3, [pc, #756] ; (8002260 ) 8001f6c: f8d3 3148 ldr.w r3, [r3, #328] ; 0x148 8001f70: 4abb ldr r2, [pc, #748] ; (8002260 ) 8001f72: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 8001f76: f8c2 3148 str.w r3, [r2, #328] ; 0x148 8001f7a: 4bb9 ldr r3, [pc, #740] ; (8002260 ) 8001f7c: f8d3 3148 ldr.w r3, [r3, #328] ; 0x148 8001f80: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 8001f84: 63fb str r3, [r7, #60] ; 0x3c 8001f86: 6bfb ldr r3, [r7, #60] ; 0x3c __HAL_RCC_GPIOJ_CLK_ENABLE(); 8001f88: 4bb5 ldr r3, [pc, #724] ; (8002260 ) 8001f8a: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001f8e: 4ab4 ldr r2, [pc, #720] ; (8002260 ) 8001f90: f443 7300 orr.w r3, r3, #512 ; 0x200 8001f94: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8001f98: 4bb1 ldr r3, [pc, #708] ; (8002260 ) 8001f9a: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001f9e: f403 7300 and.w r3, r3, #512 ; 0x200 8001fa2: 63bb str r3, [r7, #56] ; 0x38 8001fa4: 6bbb ldr r3, [r7, #56] ; 0x38 __HAL_RCC_GPIOD_CLK_ENABLE(); 8001fa6: 4bae ldr r3, [pc, #696] ; (8002260 ) 8001fa8: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001fac: 4aac ldr r2, [pc, #688] ; (8002260 ) 8001fae: f043 0308 orr.w r3, r3, #8 8001fb2: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8001fb6: 4baa ldr r3, [pc, #680] ; (8002260 ) 8001fb8: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8001fbc: f003 0308 and.w r3, r3, #8 8001fc0: 637b str r3, [r7, #52] ; 0x34 8001fc2: 6b7b ldr r3, [r7, #52] ; 0x34 GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_8; 8001fc4: f44f 7340 mov.w r3, #768 ; 0x300 8001fc8: f8c7 311c str.w r3, [r7, #284] ; 0x11c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001fcc: 2302 movs r3, #2 8001fce: f8c7 3120 str.w r3, [r7, #288] ; 0x120 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001fd2: 2300 movs r3, #0 8001fd4: f8c7 3124 str.w r3, [r7, #292] ; 0x124 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001fd8: 2300 movs r3, #0 8001fda: f8c7 3128 str.w r3, [r7, #296] ; 0x128 GPIO_InitStruct.Alternate = GPIO_AF8_UART8; 8001fde: 2308 movs r3, #8 8001fe0: f8c7 312c str.w r3, [r7, #300] ; 0x12c HAL_GPIO_Init(GPIOJ, &GPIO_InitStruct); 8001fe4: f507 738e add.w r3, r7, #284 ; 0x11c 8001fe8: 4619 mov r1, r3 8001fea: 489e ldr r0, [pc, #632] ; (8002264 ) 8001fec: f002 ff6a bl 8004ec4 GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; 8001ff0: f44f 4340 mov.w r3, #49152 ; 0xc000 8001ff4: f8c7 311c str.w r3, [r7, #284] ; 0x11c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001ff8: 2302 movs r3, #2 8001ffa: f8c7 3120 str.w r3, [r7, #288] ; 0x120 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001ffe: 2300 movs r3, #0 8002000: f8c7 3124 str.w r3, [r7, #292] ; 0x124 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8002004: 2300 movs r3, #0 8002006: f8c7 3128 str.w r3, [r7, #296] ; 0x128 GPIO_InitStruct.Alternate = GPIO_AF8_UART8; 800200a: 2308 movs r3, #8 800200c: f8c7 312c str.w r3, [r7, #300] ; 0x12c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8002010: f507 738e add.w r3, r7, #284 ; 0x11c 8002014: 4619 mov r1, r3 8002016: 4894 ldr r0, [pc, #592] ; (8002268 ) 8002018: f002 ff54 bl 8004ec4 } 800201c: e231 b.n 8002482 else if(huart->Instance==UART9) 800201e: 1d3b adds r3, r7, #4 8002020: 681b ldr r3, [r3, #0] 8002022: 681b ldr r3, [r3, #0] 8002024: 4a91 ldr r2, [pc, #580] ; (800226c ) 8002026: 4293 cmp r3, r2 8002028: f040 809c bne.w 8002164 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART9; 800202c: 2301 movs r3, #1 800202e: 667b str r3, [r7, #100] ; 0x64 PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16910CLKSOURCE_D2PCLK2; 8002030: 2300 movs r3, #0 8002032: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8002036: f107 0364 add.w r3, r7, #100 ; 0x64 800203a: 4618 mov r0, r3 800203c: f005 fa48 bl 80074d0 8002040: 4603 mov r3, r0 8002042: 2b00 cmp r3, #0 8002044: d001 beq.n 800204a Error_Handler(); 8002046: f7ff fc6b bl 8001920 __HAL_RCC_UART9_CLK_ENABLE(); 800204a: 4b85 ldr r3, [pc, #532] ; (8002260 ) 800204c: f8d3 3150 ldr.w r3, [r3, #336] ; 0x150 8002050: 4a83 ldr r2, [pc, #524] ; (8002260 ) 8002052: f043 0340 orr.w r3, r3, #64 ; 0x40 8002056: f8c2 3150 str.w r3, [r2, #336] ; 0x150 800205a: 4b81 ldr r3, [pc, #516] ; (8002260 ) 800205c: f8d3 3150 ldr.w r3, [r3, #336] ; 0x150 8002060: f003 0240 and.w r2, r3, #64 ; 0x40 8002064: f107 0330 add.w r3, r7, #48 ; 0x30 8002068: 601a str r2, [r3, #0] 800206a: f107 0330 add.w r3, r7, #48 ; 0x30 800206e: 681b ldr r3, [r3, #0] __HAL_RCC_GPIOD_CLK_ENABLE(); 8002070: 4b7b ldr r3, [pc, #492] ; (8002260 ) 8002072: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8002076: 4a7a ldr r2, [pc, #488] ; (8002260 ) 8002078: f043 0308 orr.w r3, r3, #8 800207c: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8002080: 4b77 ldr r3, [pc, #476] ; (8002260 ) 8002082: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8002086: f003 0208 and.w r2, r3, #8 800208a: f107 032c add.w r3, r7, #44 ; 0x2c 800208e: 601a str r2, [r3, #0] 8002090: f107 032c add.w r3, r7, #44 ; 0x2c 8002094: 681b ldr r3, [r3, #0] __HAL_RCC_GPIOJ_CLK_ENABLE(); 8002096: 4b72 ldr r3, [pc, #456] ; (8002260 ) 8002098: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 800209c: 4a70 ldr r2, [pc, #448] ; (8002260 ) 800209e: f443 7300 orr.w r3, r3, #512 ; 0x200 80020a2: f8c2 3140 str.w r3, [r2, #320] ; 0x140 80020a6: 4b6e ldr r3, [pc, #440] ; (8002260 ) 80020a8: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80020ac: f403 7200 and.w r2, r3, #512 ; 0x200 80020b0: f107 0328 add.w r3, r7, #40 ; 0x28 80020b4: 601a str r2, [r3, #0] 80020b6: f107 0328 add.w r3, r7, #40 ; 0x28 80020ba: 681b ldr r3, [r3, #0] __HAL_RCC_GPIOG_CLK_ENABLE(); 80020bc: 4b68 ldr r3, [pc, #416] ; (8002260 ) 80020be: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80020c2: 4a67 ldr r2, [pc, #412] ; (8002260 ) 80020c4: f043 0340 orr.w r3, r3, #64 ; 0x40 80020c8: f8c2 3140 str.w r3, [r2, #320] ; 0x140 80020cc: 4b64 ldr r3, [pc, #400] ; (8002260 ) 80020ce: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80020d2: f003 0240 and.w r2, r3, #64 ; 0x40 80020d6: f107 0324 add.w r3, r7, #36 ; 0x24 80020da: 601a str r2, [r3, #0] 80020dc: f107 0324 add.w r3, r7, #36 ; 0x24 80020e0: 681b ldr r3, [r3, #0] GPIO_InitStruct.Pin = GPIO_PIN_13; 80020e2: f44f 5300 mov.w r3, #8192 ; 0x2000 80020e6: f8c7 311c str.w r3, [r7, #284] ; 0x11c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80020ea: 2302 movs r3, #2 80020ec: f8c7 3120 str.w r3, [r7, #288] ; 0x120 GPIO_InitStruct.Pull = GPIO_NOPULL; 80020f0: 2300 movs r3, #0 80020f2: f8c7 3124 str.w r3, [r7, #292] ; 0x124 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80020f6: 2300 movs r3, #0 80020f8: f8c7 3128 str.w r3, [r7, #296] ; 0x128 GPIO_InitStruct.Alternate = GPIO_AF11_UART9; 80020fc: 230b movs r3, #11 80020fe: f8c7 312c str.w r3, [r7, #300] ; 0x12c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8002102: f507 738e add.w r3, r7, #284 ; 0x11c 8002106: 4619 mov r1, r3 8002108: 4857 ldr r0, [pc, #348] ; (8002268 ) 800210a: f002 fedb bl 8004ec4 GPIO_InitStruct.Pin = GPIO_PIN_4; 800210e: 2310 movs r3, #16 8002110: f8c7 311c str.w r3, [r7, #284] ; 0x11c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002114: 2302 movs r3, #2 8002116: f8c7 3120 str.w r3, [r7, #288] ; 0x120 GPIO_InitStruct.Pull = GPIO_NOPULL; 800211a: 2300 movs r3, #0 800211c: f8c7 3124 str.w r3, [r7, #292] ; 0x124 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8002120: 2300 movs r3, #0 8002122: f8c7 3128 str.w r3, [r7, #296] ; 0x128 GPIO_InitStruct.Alternate = GPIO_AF11_UART9; 8002126: 230b movs r3, #11 8002128: f8c7 312c str.w r3, [r7, #300] ; 0x12c HAL_GPIO_Init(GPIOJ, &GPIO_InitStruct); 800212c: f507 738e add.w r3, r7, #284 ; 0x11c 8002130: 4619 mov r1, r3 8002132: 484c ldr r0, [pc, #304] ; (8002264 ) 8002134: f002 fec6 bl 8004ec4 GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_0; 8002138: 2303 movs r3, #3 800213a: f8c7 311c str.w r3, [r7, #284] ; 0x11c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800213e: 2302 movs r3, #2 8002140: f8c7 3120 str.w r3, [r7, #288] ; 0x120 GPIO_InitStruct.Pull = GPIO_NOPULL; 8002144: 2300 movs r3, #0 8002146: f8c7 3124 str.w r3, [r7, #292] ; 0x124 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800214a: 2300 movs r3, #0 800214c: f8c7 3128 str.w r3, [r7, #296] ; 0x128 GPIO_InitStruct.Alternate = GPIO_AF11_UART9; 8002150: 230b movs r3, #11 8002152: f8c7 312c str.w r3, [r7, #300] ; 0x12c HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 8002156: f507 738e add.w r3, r7, #284 ; 0x11c 800215a: 4619 mov r1, r3 800215c: 4844 ldr r0, [pc, #272] ; (8002270 ) 800215e: f002 feb1 bl 8004ec4 } 8002162: e18e b.n 8002482 else if(huart->Instance==USART1) 8002164: 1d3b adds r3, r7, #4 8002166: 681b ldr r3, [r3, #0] 8002168: 681b ldr r3, [r3, #0] 800216a: 4a42 ldr r2, [pc, #264] ; (8002274 ) 800216c: 4293 cmp r3, r2 800216e: f040 8087 bne.w 8002280 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1; 8002172: 2301 movs r3, #1 8002174: 667b str r3, [r7, #100] ; 0x64 PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16910CLKSOURCE_D2PCLK2; 8002176: 2300 movs r3, #0 8002178: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 800217c: f107 0364 add.w r3, r7, #100 ; 0x64 8002180: 4618 mov r0, r3 8002182: f005 f9a5 bl 80074d0 8002186: 4603 mov r3, r0 8002188: 2b00 cmp r3, #0 800218a: d001 beq.n 8002190 Error_Handler(); 800218c: f7ff fbc8 bl 8001920 __HAL_RCC_USART1_CLK_ENABLE(); 8002190: 4b33 ldr r3, [pc, #204] ; (8002260 ) 8002192: f8d3 3150 ldr.w r3, [r3, #336] ; 0x150 8002196: 4a32 ldr r2, [pc, #200] ; (8002260 ) 8002198: f043 0310 orr.w r3, r3, #16 800219c: f8c2 3150 str.w r3, [r2, #336] ; 0x150 80021a0: 4b2f ldr r3, [pc, #188] ; (8002260 ) 80021a2: f8d3 3150 ldr.w r3, [r3, #336] ; 0x150 80021a6: f003 0210 and.w r2, r3, #16 80021aa: f107 0320 add.w r3, r7, #32 80021ae: 601a str r2, [r3, #0] 80021b0: f107 0320 add.w r3, r7, #32 80021b4: 681b ldr r3, [r3, #0] __HAL_RCC_GPIOA_CLK_ENABLE(); 80021b6: 4b2a ldr r3, [pc, #168] ; (8002260 ) 80021b8: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80021bc: 4a28 ldr r2, [pc, #160] ; (8002260 ) 80021be: f043 0301 orr.w r3, r3, #1 80021c2: f8c2 3140 str.w r3, [r2, #320] ; 0x140 80021c6: 4b26 ldr r3, [pc, #152] ; (8002260 ) 80021c8: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80021cc: f003 0201 and.w r2, r3, #1 80021d0: f107 031c add.w r3, r7, #28 80021d4: 601a str r2, [r3, #0] 80021d6: f107 031c add.w r3, r7, #28 80021da: 681b ldr r3, [r3, #0] __HAL_RCC_GPIOB_CLK_ENABLE(); 80021dc: 4b20 ldr r3, [pc, #128] ; (8002260 ) 80021de: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80021e2: 4a1f ldr r2, [pc, #124] ; (8002260 ) 80021e4: f043 0302 orr.w r3, r3, #2 80021e8: f8c2 3140 str.w r3, [r2, #320] ; 0x140 80021ec: 4b1c ldr r3, [pc, #112] ; (8002260 ) 80021ee: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80021f2: f003 0202 and.w r2, r3, #2 80021f6: f107 0318 add.w r3, r7, #24 80021fa: 601a str r2, [r3, #0] 80021fc: f107 0318 add.w r3, r7, #24 8002200: 681b ldr r3, [r3, #0] GPIO_InitStruct.Pin = GPIO_PIN_9; 8002202: f44f 7300 mov.w r3, #512 ; 0x200 8002206: f8c7 311c str.w r3, [r7, #284] ; 0x11c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800220a: 2302 movs r3, #2 800220c: f8c7 3120 str.w r3, [r7, #288] ; 0x120 GPIO_InitStruct.Pull = GPIO_NOPULL; 8002210: 2300 movs r3, #0 8002212: f8c7 3124 str.w r3, [r7, #292] ; 0x124 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8002216: 2300 movs r3, #0 8002218: f8c7 3128 str.w r3, [r7, #296] ; 0x128 GPIO_InitStruct.Alternate = GPIO_AF7_USART1; 800221c: 2307 movs r3, #7 800221e: f8c7 312c str.w r3, [r7, #300] ; 0x12c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8002222: f507 738e add.w r3, r7, #284 ; 0x11c 8002226: 4619 mov r1, r3 8002228: 4813 ldr r0, [pc, #76] ; (8002278 ) 800222a: f002 fe4b bl 8004ec4 GPIO_InitStruct.Pin = GPIO_PIN_15; 800222e: f44f 4300 mov.w r3, #32768 ; 0x8000 8002232: f8c7 311c str.w r3, [r7, #284] ; 0x11c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002236: 2302 movs r3, #2 8002238: f8c7 3120 str.w r3, [r7, #288] ; 0x120 GPIO_InitStruct.Pull = GPIO_NOPULL; 800223c: 2300 movs r3, #0 800223e: f8c7 3124 str.w r3, [r7, #292] ; 0x124 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8002242: 2300 movs r3, #0 8002244: f8c7 3128 str.w r3, [r7, #296] ; 0x128 GPIO_InitStruct.Alternate = GPIO_AF4_USART1; 8002248: 2304 movs r3, #4 800224a: f8c7 312c str.w r3, [r7, #300] ; 0x12c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800224e: f507 738e add.w r3, r7, #284 ; 0x11c 8002252: 4619 mov r1, r3 8002254: 4809 ldr r0, [pc, #36] ; (800227c ) 8002256: f002 fe35 bl 8004ec4 } 800225a: e112 b.n 8002482 800225c: 40007c00 .word 0x40007c00 8002260: 58024400 .word 0x58024400 8002264: 58022400 .word 0x58022400 8002268: 58020c00 .word 0x58020c00 800226c: 40011800 .word 0x40011800 8002270: 58021800 .word 0x58021800 8002274: 40011000 .word 0x40011000 8002278: 58020000 .word 0x58020000 800227c: 58020400 .word 0x58020400 else if(huart->Instance==USART2) 8002280: 1d3b adds r3, r7, #4 8002282: 681b ldr r3, [r3, #0] 8002284: 681b ldr r3, [r3, #0] 8002286: 4a81 ldr r2, [pc, #516] ; (800248c ) 8002288: 4293 cmp r3, r2 800228a: f040 80a9 bne.w 80023e0 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART2; 800228e: 2302 movs r3, #2 8002290: 667b str r3, [r7, #100] ; 0x64 PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; 8002292: 2300 movs r3, #0 8002294: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8002298: f107 0364 add.w r3, r7, #100 ; 0x64 800229c: 4618 mov r0, r3 800229e: f005 f917 bl 80074d0 80022a2: 4603 mov r3, r0 80022a4: 2b00 cmp r3, #0 80022a6: d001 beq.n 80022ac Error_Handler(); 80022a8: f7ff fb3a bl 8001920 __HAL_RCC_USART2_CLK_ENABLE(); 80022ac: 4b78 ldr r3, [pc, #480] ; (8002490 ) 80022ae: f8d3 3148 ldr.w r3, [r3, #328] ; 0x148 80022b2: 4a77 ldr r2, [pc, #476] ; (8002490 ) 80022b4: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80022b8: f8c2 3148 str.w r3, [r2, #328] ; 0x148 80022bc: 4b74 ldr r3, [pc, #464] ; (8002490 ) 80022be: f8d3 3148 ldr.w r3, [r3, #328] ; 0x148 80022c2: f403 3200 and.w r2, r3, #131072 ; 0x20000 80022c6: f107 0314 add.w r3, r7, #20 80022ca: 601a str r2, [r3, #0] 80022cc: f107 0314 add.w r3, r7, #20 80022d0: 681b ldr r3, [r3, #0] __HAL_RCC_GPIOD_CLK_ENABLE(); 80022d2: 4b6f ldr r3, [pc, #444] ; (8002490 ) 80022d4: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80022d8: 4a6d ldr r2, [pc, #436] ; (8002490 ) 80022da: f043 0308 orr.w r3, r3, #8 80022de: f8c2 3140 str.w r3, [r2, #320] ; 0x140 80022e2: 4b6b ldr r3, [pc, #428] ; (8002490 ) 80022e4: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80022e8: f003 0208 and.w r2, r3, #8 80022ec: f107 0310 add.w r3, r7, #16 80022f0: 601a str r2, [r3, #0] 80022f2: f107 0310 add.w r3, r7, #16 80022f6: 681b ldr r3, [r3, #0] GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_3; 80022f8: 2368 movs r3, #104 ; 0x68 80022fa: f8c7 311c str.w r3, [r7, #284] ; 0x11c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80022fe: 2302 movs r3, #2 8002300: f8c7 3120 str.w r3, [r7, #288] ; 0x120 GPIO_InitStruct.Pull = GPIO_NOPULL; 8002304: 2300 movs r3, #0 8002306: f8c7 3124 str.w r3, [r7, #292] ; 0x124 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800230a: 2300 movs r3, #0 800230c: f8c7 3128 str.w r3, [r7, #296] ; 0x128 GPIO_InitStruct.Alternate = GPIO_AF7_USART2; 8002310: 2307 movs r3, #7 8002312: f8c7 312c str.w r3, [r7, #300] ; 0x12c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8002316: f507 738e add.w r3, r7, #284 ; 0x11c 800231a: 4619 mov r1, r3 800231c: 485d ldr r0, [pc, #372] ; (8002494 ) 800231e: f002 fdd1 bl 8004ec4 hdma_usart2_rx.Instance = DMA1_Stream2; 8002322: 4b5d ldr r3, [pc, #372] ; (8002498 ) 8002324: 4a5d ldr r2, [pc, #372] ; (800249c ) 8002326: 601a str r2, [r3, #0] hdma_usart2_rx.Init.Request = DMA_REQUEST_USART2_RX; 8002328: 4b5b ldr r3, [pc, #364] ; (8002498 ) 800232a: 222b movs r2, #43 ; 0x2b 800232c: 605a str r2, [r3, #4] hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 800232e: 4b5a ldr r3, [pc, #360] ; (8002498 ) 8002330: 2200 movs r2, #0 8002332: 609a str r2, [r3, #8] hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8002334: 4b58 ldr r3, [pc, #352] ; (8002498 ) 8002336: 2200 movs r2, #0 8002338: 60da str r2, [r3, #12] hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE; 800233a: 4b57 ldr r3, [pc, #348] ; (8002498 ) 800233c: f44f 6280 mov.w r2, #1024 ; 0x400 8002340: 611a str r2, [r3, #16] hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8002342: 4b55 ldr r3, [pc, #340] ; (8002498 ) 8002344: 2200 movs r2, #0 8002346: 615a str r2, [r3, #20] hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8002348: 4b53 ldr r3, [pc, #332] ; (8002498 ) 800234a: 2200 movs r2, #0 800234c: 619a str r2, [r3, #24] hdma_usart2_rx.Init.Mode = DMA_NORMAL; 800234e: 4b52 ldr r3, [pc, #328] ; (8002498 ) 8002350: 2200 movs r2, #0 8002352: 61da str r2, [r3, #28] hdma_usart2_rx.Init.Priority = DMA_PRIORITY_LOW; 8002354: 4b50 ldr r3, [pc, #320] ; (8002498 ) 8002356: 2200 movs r2, #0 8002358: 621a str r2, [r3, #32] hdma_usart2_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 800235a: 4b4f ldr r3, [pc, #316] ; (8002498 ) 800235c: 2200 movs r2, #0 800235e: 625a str r2, [r3, #36] ; 0x24 if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK) 8002360: 484d ldr r0, [pc, #308] ; (8002498 ) 8002362: f001 f881 bl 8003468 8002366: 4603 mov r3, r0 8002368: 2b00 cmp r3, #0 800236a: d001 beq.n 8002370 Error_Handler(); 800236c: f7ff fad8 bl 8001920 __HAL_LINKDMA(huart,hdmarx,hdma_usart2_rx); 8002370: 1d3b adds r3, r7, #4 8002372: 681b ldr r3, [r3, #0] 8002374: 4a48 ldr r2, [pc, #288] ; (8002498 ) 8002376: 67da str r2, [r3, #124] ; 0x7c 8002378: 4a47 ldr r2, [pc, #284] ; (8002498 ) 800237a: 1d3b adds r3, r7, #4 800237c: 681b ldr r3, [r3, #0] 800237e: 6393 str r3, [r2, #56] ; 0x38 hdma_usart2_tx.Instance = DMA1_Stream3; 8002380: 4b47 ldr r3, [pc, #284] ; (80024a0 ) 8002382: 4a48 ldr r2, [pc, #288] ; (80024a4 ) 8002384: 601a str r2, [r3, #0] hdma_usart2_tx.Init.Request = DMA_REQUEST_USART2_TX; 8002386: 4b46 ldr r3, [pc, #280] ; (80024a0 ) 8002388: 222c movs r2, #44 ; 0x2c 800238a: 605a str r2, [r3, #4] hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 800238c: 4b44 ldr r3, [pc, #272] ; (80024a0 ) 800238e: 2240 movs r2, #64 ; 0x40 8002390: 609a str r2, [r3, #8] hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8002392: 4b43 ldr r3, [pc, #268] ; (80024a0 ) 8002394: 2200 movs r2, #0 8002396: 60da str r2, [r3, #12] hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; 8002398: 4b41 ldr r3, [pc, #260] ; (80024a0 ) 800239a: f44f 6280 mov.w r2, #1024 ; 0x400 800239e: 611a str r2, [r3, #16] hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 80023a0: 4b3f ldr r3, [pc, #252] ; (80024a0 ) 80023a2: 2200 movs r2, #0 80023a4: 615a str r2, [r3, #20] hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 80023a6: 4b3e ldr r3, [pc, #248] ; (80024a0 ) 80023a8: 2200 movs r2, #0 80023aa: 619a str r2, [r3, #24] hdma_usart2_tx.Init.Mode = DMA_NORMAL; 80023ac: 4b3c ldr r3, [pc, #240] ; (80024a0 ) 80023ae: 2200 movs r2, #0 80023b0: 61da str r2, [r3, #28] hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW; 80023b2: 4b3b ldr r3, [pc, #236] ; (80024a0 ) 80023b4: 2200 movs r2, #0 80023b6: 621a str r2, [r3, #32] hdma_usart2_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 80023b8: 4b39 ldr r3, [pc, #228] ; (80024a0 ) 80023ba: 2200 movs r2, #0 80023bc: 625a str r2, [r3, #36] ; 0x24 if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) 80023be: 4838 ldr r0, [pc, #224] ; (80024a0 ) 80023c0: f001 f852 bl 8003468 80023c4: 4603 mov r3, r0 80023c6: 2b00 cmp r3, #0 80023c8: d001 beq.n 80023ce Error_Handler(); 80023ca: f7ff faa9 bl 8001920 __HAL_LINKDMA(huart,hdmatx,hdma_usart2_tx); 80023ce: 1d3b adds r3, r7, #4 80023d0: 681b ldr r3, [r3, #0] 80023d2: 4a33 ldr r2, [pc, #204] ; (80024a0 ) 80023d4: 679a str r2, [r3, #120] ; 0x78 80023d6: 4a32 ldr r2, [pc, #200] ; (80024a0 ) 80023d8: 1d3b adds r3, r7, #4 80023da: 681b ldr r3, [r3, #0] 80023dc: 6393 str r3, [r2, #56] ; 0x38 } 80023de: e050 b.n 8002482 else if(huart->Instance==USART3) 80023e0: 1d3b adds r3, r7, #4 80023e2: 681b ldr r3, [r3, #0] 80023e4: 681b ldr r3, [r3, #0] 80023e6: 4a30 ldr r2, [pc, #192] ; (80024a8 ) 80023e8: 4293 cmp r3, r2 80023ea: d14a bne.n 8002482 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3; 80023ec: 2302 movs r3, #2 80023ee: 667b str r3, [r7, #100] ; 0x64 PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; 80023f0: 2300 movs r3, #0 80023f2: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 80023f6: f107 0364 add.w r3, r7, #100 ; 0x64 80023fa: 4618 mov r0, r3 80023fc: f005 f868 bl 80074d0 8002400: 4603 mov r3, r0 8002402: 2b00 cmp r3, #0 8002404: d001 beq.n 800240a Error_Handler(); 8002406: f7ff fa8b bl 8001920 __HAL_RCC_USART3_CLK_ENABLE(); 800240a: 4b21 ldr r3, [pc, #132] ; (8002490 ) 800240c: f8d3 3148 ldr.w r3, [r3, #328] ; 0x148 8002410: 4a1f ldr r2, [pc, #124] ; (8002490 ) 8002412: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8002416: f8c2 3148 str.w r3, [r2, #328] ; 0x148 800241a: 4b1d ldr r3, [pc, #116] ; (8002490 ) 800241c: f8d3 3148 ldr.w r3, [r3, #328] ; 0x148 8002420: f403 2280 and.w r2, r3, #262144 ; 0x40000 8002424: f107 030c add.w r3, r7, #12 8002428: 601a str r2, [r3, #0] 800242a: f107 030c add.w r3, r7, #12 800242e: 681b ldr r3, [r3, #0] __HAL_RCC_GPIOD_CLK_ENABLE(); 8002430: 4b17 ldr r3, [pc, #92] ; (8002490 ) 8002432: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8002436: 4a16 ldr r2, [pc, #88] ; (8002490 ) 8002438: f043 0308 orr.w r3, r3, #8 800243c: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8002440: 4b13 ldr r3, [pc, #76] ; (8002490 ) 8002442: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8002446: f003 0208 and.w r2, r3, #8 800244a: f107 0308 add.w r3, r7, #8 800244e: 601a str r2, [r3, #0] 8002450: f107 0308 add.w r3, r7, #8 8002454: 681b ldr r3, [r3, #0] GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_9; 8002456: f44f 53d8 mov.w r3, #6912 ; 0x1b00 800245a: f8c7 311c str.w r3, [r7, #284] ; 0x11c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800245e: 2302 movs r3, #2 8002460: f8c7 3120 str.w r3, [r7, #288] ; 0x120 GPIO_InitStruct.Pull = GPIO_NOPULL; 8002464: 2300 movs r3, #0 8002466: f8c7 3124 str.w r3, [r7, #292] ; 0x124 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800246a: 2300 movs r3, #0 800246c: f8c7 3128 str.w r3, [r7, #296] ; 0x128 GPIO_InitStruct.Alternate = GPIO_AF7_USART3; 8002470: 2307 movs r3, #7 8002472: f8c7 312c str.w r3, [r7, #300] ; 0x12c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8002476: f507 738e add.w r3, r7, #284 ; 0x11c 800247a: 4619 mov r1, r3 800247c: 4805 ldr r0, [pc, #20] ; (8002494 ) 800247e: f002 fd21 bl 8004ec4 } 8002482: bf00 nop 8002484: f507 7798 add.w r7, r7, #304 ; 0x130 8002488: 46bd mov sp, r7 800248a: bd80 pop {r7, pc} 800248c: 40004400 .word 0x40004400 8002490: 58024400 .word 0x58024400 8002494: 58020c00 .word 0x58020c00 8002498: 2000009c .word 0x2000009c 800249c: 40020040 .word 0x40020040 80024a0: 20000674 .word 0x20000674 80024a4: 40020058 .word 0x40020058 80024a8: 40004800 .word 0x40004800 080024ac : * This function configures the hardware resources used in this example * @param husart: USART handle pointer * @retval None */ void HAL_USART_MspInit(USART_HandleTypeDef* husart) { 80024ac: b580 push {r7, lr} 80024ae: b0bc sub sp, #240 ; 0xf0 80024b0: af00 add r7, sp, #0 80024b2: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80024b4: f107 03dc add.w r3, r7, #220 ; 0xdc 80024b8: 2200 movs r2, #0 80024ba: 601a str r2, [r3, #0] 80024bc: 605a str r2, [r3, #4] 80024be: 609a str r2, [r3, #8] 80024c0: 60da str r2, [r3, #12] 80024c2: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 80024c4: f107 0324 add.w r3, r7, #36 ; 0x24 80024c8: 22b8 movs r2, #184 ; 0xb8 80024ca: 2100 movs r1, #0 80024cc: 4618 mov r0, r3 80024ce: f00c f8a9 bl 800e624 if(husart->Instance==USART6) 80024d2: 687b ldr r3, [r7, #4] 80024d4: 681b ldr r3, [r3, #0] 80024d6: 4a6d ldr r2, [pc, #436] ; (800268c ) 80024d8: 4293 cmp r3, r2 80024da: d167 bne.n 80025ac /* USER CODE END USART6_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART6; 80024dc: 2301 movs r3, #1 80024de: 627b str r3, [r7, #36] ; 0x24 PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16910CLKSOURCE_D2PCLK2; 80024e0: 2300 movs r3, #0 80024e2: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 80024e6: f107 0324 add.w r3, r7, #36 ; 0x24 80024ea: 4618 mov r0, r3 80024ec: f004 fff0 bl 80074d0 80024f0: 4603 mov r3, r0 80024f2: 2b00 cmp r3, #0 80024f4: d001 beq.n 80024fa { Error_Handler(); 80024f6: f7ff fa13 bl 8001920 } /* Peripheral clock enable */ __HAL_RCC_USART6_CLK_ENABLE(); 80024fa: 4b65 ldr r3, [pc, #404] ; (8002690 ) 80024fc: f8d3 3150 ldr.w r3, [r3, #336] ; 0x150 8002500: 4a63 ldr r2, [pc, #396] ; (8002690 ) 8002502: f043 0320 orr.w r3, r3, #32 8002506: f8c2 3150 str.w r3, [r2, #336] ; 0x150 800250a: 4b61 ldr r3, [pc, #388] ; (8002690 ) 800250c: f8d3 3150 ldr.w r3, [r3, #336] ; 0x150 8002510: f003 0320 and.w r3, r3, #32 8002514: 623b str r3, [r7, #32] 8002516: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOG_CLK_ENABLE(); 8002518: 4b5d ldr r3, [pc, #372] ; (8002690 ) 800251a: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 800251e: 4a5c ldr r2, [pc, #368] ; (8002690 ) 8002520: f043 0340 orr.w r3, r3, #64 ; 0x40 8002524: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8002528: 4b59 ldr r3, [pc, #356] ; (8002690 ) 800252a: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 800252e: f003 0340 and.w r3, r3, #64 ; 0x40 8002532: 61fb str r3, [r7, #28] 8002534: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOC_CLK_ENABLE(); 8002536: 4b56 ldr r3, [pc, #344] ; (8002690 ) 8002538: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 800253c: 4a54 ldr r2, [pc, #336] ; (8002690 ) 800253e: f043 0304 orr.w r3, r3, #4 8002542: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8002546: 4b52 ldr r3, [pc, #328] ; (8002690 ) 8002548: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 800254c: f003 0304 and.w r3, r3, #4 8002550: 61bb str r3, [r7, #24] 8002552: 69bb ldr r3, [r7, #24] PG13 ------> USART6_CTS PC7 ------> USART6_RX PG8 ------> USART6_RTS PG7 ------> USART6_CK */ GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_13|GPIO_PIN_8|GPIO_PIN_7; 8002554: f44f 43c3 mov.w r3, #24960 ; 0x6180 8002558: f8c7 30dc str.w r3, [r7, #220] ; 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800255c: 2302 movs r3, #2 800255e: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 8002562: 2300 movs r3, #0 8002564: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8002568: 2300 movs r3, #0 800256a: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8 GPIO_InitStruct.Alternate = GPIO_AF7_USART6; 800256e: 2307 movs r3, #7 8002570: f8c7 30ec str.w r3, [r7, #236] ; 0xec HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 8002574: f107 03dc add.w r3, r7, #220 ; 0xdc 8002578: 4619 mov r1, r3 800257a: 4846 ldr r0, [pc, #280] ; (8002694 ) 800257c: f002 fca2 bl 8004ec4 GPIO_InitStruct.Pin = GPIO_PIN_7; 8002580: 2380 movs r3, #128 ; 0x80 8002582: f8c7 30dc str.w r3, [r7, #220] ; 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002586: 2302 movs r3, #2 8002588: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 800258c: 2300 movs r3, #0 800258e: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8002592: 2300 movs r3, #0 8002594: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8 GPIO_InitStruct.Alternate = GPIO_AF7_USART6; 8002598: 2307 movs r3, #7 800259a: f8c7 30ec str.w r3, [r7, #236] ; 0xec HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800259e: f107 03dc add.w r3, r7, #220 ; 0xdc 80025a2: 4619 mov r1, r3 80025a4: 483c ldr r0, [pc, #240] ; (8002698 ) 80025a6: f002 fc8d bl 8004ec4 /* USER CODE BEGIN USART10_MspInit 1 */ /* USER CODE END USART10_MspInit 1 */ } } 80025aa: e06b b.n 8002684 else if(husart->Instance==USART10) 80025ac: 687b ldr r3, [r7, #4] 80025ae: 681b ldr r3, [r3, #0] 80025b0: 4a3a ldr r2, [pc, #232] ; (800269c ) 80025b2: 4293 cmp r3, r2 80025b4: d166 bne.n 8002684 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART10; 80025b6: 2301 movs r3, #1 80025b8: 627b str r3, [r7, #36] ; 0x24 PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16910CLKSOURCE_D2PCLK2; 80025ba: 2300 movs r3, #0 80025bc: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 80025c0: f107 0324 add.w r3, r7, #36 ; 0x24 80025c4: 4618 mov r0, r3 80025c6: f004 ff83 bl 80074d0 80025ca: 4603 mov r3, r0 80025cc: 2b00 cmp r3, #0 80025ce: d001 beq.n 80025d4 Error_Handler(); 80025d0: f7ff f9a6 bl 8001920 __HAL_RCC_USART10_CLK_ENABLE(); 80025d4: 4b2e ldr r3, [pc, #184] ; (8002690 ) 80025d6: f8d3 3150 ldr.w r3, [r3, #336] ; 0x150 80025da: 4a2d ldr r2, [pc, #180] ; (8002690 ) 80025dc: f043 0380 orr.w r3, r3, #128 ; 0x80 80025e0: f8c2 3150 str.w r3, [r2, #336] ; 0x150 80025e4: 4b2a ldr r3, [pc, #168] ; (8002690 ) 80025e6: f8d3 3150 ldr.w r3, [r3, #336] ; 0x150 80025ea: f003 0380 and.w r3, r3, #128 ; 0x80 80025ee: 617b str r3, [r7, #20] 80025f0: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOG_CLK_ENABLE(); 80025f2: 4b27 ldr r3, [pc, #156] ; (8002690 ) 80025f4: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80025f8: 4a25 ldr r2, [pc, #148] ; (8002690 ) 80025fa: f043 0340 orr.w r3, r3, #64 ; 0x40 80025fe: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8002602: 4b23 ldr r3, [pc, #140] ; (8002690 ) 8002604: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8002608: f003 0340 and.w r3, r3, #64 ; 0x40 800260c: 613b str r3, [r7, #16] 800260e: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOE_CLK_ENABLE(); 8002610: 4b1f ldr r3, [pc, #124] ; (8002690 ) 8002612: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8002616: 4a1e ldr r2, [pc, #120] ; (8002690 ) 8002618: f043 0310 orr.w r3, r3, #16 800261c: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8002620: 4b1b ldr r3, [pc, #108] ; (8002690 ) 8002622: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8002626: f003 0310 and.w r3, r3, #16 800262a: 60fb str r3, [r7, #12] 800262c: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_15; 800262e: f44f 4300 mov.w r3, #32768 ; 0x8000 8002632: f8c7 30dc str.w r3, [r7, #220] ; 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002636: 2302 movs r3, #2 8002638: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 800263c: 2300 movs r3, #0 800263e: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8002642: 2300 movs r3, #0 8002644: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8 GPIO_InitStruct.Alternate = GPIO_AF11_USART10; 8002648: 230b movs r3, #11 800264a: f8c7 30ec str.w r3, [r7, #236] ; 0xec HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 800264e: f107 03dc add.w r3, r7, #220 ; 0xdc 8002652: 4619 mov r1, r3 8002654: 480f ldr r0, [pc, #60] ; (8002694 ) 8002656: f002 fc35 bl 8004ec4 GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_2; 800265a: 230c movs r3, #12 800265c: f8c7 30dc str.w r3, [r7, #220] ; 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002660: 2302 movs r3, #2 8002662: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 8002666: 2300 movs r3, #0 8002668: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800266c: 2300 movs r3, #0 800266e: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8 GPIO_InitStruct.Alternate = GPIO_AF11_USART10; 8002672: 230b movs r3, #11 8002674: f8c7 30ec str.w r3, [r7, #236] ; 0xec HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8002678: f107 03dc add.w r3, r7, #220 ; 0xdc 800267c: 4619 mov r1, r3 800267e: 4808 ldr r0, [pc, #32] ; (80026a0 ) 8002680: f002 fc20 bl 8004ec4 } 8002684: bf00 nop 8002686: 37f0 adds r7, #240 ; 0xf0 8002688: 46bd mov sp, r7 800268a: bd80 pop {r7, pc} 800268c: 40011400 .word 0x40011400 8002690: 58024400 .word 0x58024400 8002694: 58021800 .word 0x58021800 8002698: 58020800 .word 0x58020800 800269c: 40011c00 .word 0x40011c00 80026a0: 58021000 .word 0x58021000 080026a4 : * This function configures the hardware resources used in this example * @param hospi: OSPI handle pointer * @retval None */ void HAL_OSPI_MspInit(OSPI_HandleTypeDef* hospi) { 80026a4: b580 push {r7, lr} 80026a6: b0c4 sub sp, #272 ; 0x110 80026a8: af00 add r7, sp, #0 80026aa: 1d3b adds r3, r7, #4 80026ac: 6018 str r0, [r3, #0] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80026ae: f107 03fc add.w r3, r7, #252 ; 0xfc 80026b2: 2200 movs r2, #0 80026b4: 601a str r2, [r3, #0] 80026b6: 605a str r2, [r3, #4] 80026b8: 609a str r2, [r3, #8] 80026ba: 60da str r2, [r3, #12] 80026bc: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 80026be: f107 0344 add.w r3, r7, #68 ; 0x44 80026c2: 22b8 movs r2, #184 ; 0xb8 80026c4: 2100 movs r1, #0 80026c6: 4618 mov r0, r3 80026c8: f00b ffac bl 800e624 if(hospi->Instance==OCTOSPI1) 80026cc: 1d3b adds r3, r7, #4 80026ce: 681b ldr r3, [r3, #0] 80026d0: 681b ldr r3, [r3, #0] 80026d2: 4ab6 ldr r2, [pc, #728] ; (80029ac ) 80026d4: 4293 cmp r3, r2 80026d6: f040 817b bne.w 80029d0 /* USER CODE BEGIN OCTOSPI1_MspInit 0 */ /* USER CODE END OCTOSPI1_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_OSPI; 80026da: f04f 7300 mov.w r3, #33554432 ; 0x2000000 80026de: 647b str r3, [r7, #68] ; 0x44 PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_D1HCLK; 80026e0: 2300 movs r3, #0 80026e2: f8c7 308c str.w r3, [r7, #140] ; 0x8c if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 80026e6: f107 0344 add.w r3, r7, #68 ; 0x44 80026ea: 4618 mov r0, r3 80026ec: f004 fef0 bl 80074d0 80026f0: 4603 mov r3, r0 80026f2: 2b00 cmp r3, #0 80026f4: d001 beq.n 80026fa { Error_Handler(); 80026f6: f7ff f913 bl 8001920 } /* Peripheral clock enable */ HAL_RCC_OCTOSPIM_CLK_ENABLED++; 80026fa: 4bad ldr r3, [pc, #692] ; (80029b0 ) 80026fc: 681b ldr r3, [r3, #0] 80026fe: 3301 adds r3, #1 8002700: 4aab ldr r2, [pc, #684] ; (80029b0 ) 8002702: 6013 str r3, [r2, #0] if(HAL_RCC_OCTOSPIM_CLK_ENABLED==1){ 8002704: 4baa ldr r3, [pc, #680] ; (80029b0 ) 8002706: 681b ldr r3, [r3, #0] 8002708: 2b01 cmp r3, #1 800270a: d10e bne.n 800272a __HAL_RCC_OCTOSPIM_CLK_ENABLE(); 800270c: 4ba9 ldr r3, [pc, #676] ; (80029b4 ) 800270e: f8d3 3134 ldr.w r3, [r3, #308] ; 0x134 8002712: 4aa8 ldr r2, [pc, #672] ; (80029b4 ) 8002714: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 8002718: f8c2 3134 str.w r3, [r2, #308] ; 0x134 800271c: 4ba5 ldr r3, [pc, #660] ; (80029b4 ) 800271e: f8d3 3134 ldr.w r3, [r3, #308] ; 0x134 8002722: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8002726: 643b str r3, [r7, #64] ; 0x40 8002728: 6c3b ldr r3, [r7, #64] ; 0x40 } __HAL_RCC_OSPI1_CLK_ENABLE(); 800272a: 4ba2 ldr r3, [pc, #648] ; (80029b4 ) 800272c: f8d3 3134 ldr.w r3, [r3, #308] ; 0x134 8002730: 4aa0 ldr r2, [pc, #640] ; (80029b4 ) 8002732: f443 4380 orr.w r3, r3, #16384 ; 0x4000 8002736: f8c2 3134 str.w r3, [r2, #308] ; 0x134 800273a: 4b9e ldr r3, [pc, #632] ; (80029b4 ) 800273c: f8d3 3134 ldr.w r3, [r3, #308] ; 0x134 8002740: f403 4380 and.w r3, r3, #16384 ; 0x4000 8002744: 63fb str r3, [r7, #60] ; 0x3c 8002746: 6bfb ldr r3, [r7, #60] ; 0x3c __HAL_RCC_GPIOD_CLK_ENABLE(); 8002748: 4b9a ldr r3, [pc, #616] ; (80029b4 ) 800274a: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 800274e: 4a99 ldr r2, [pc, #612] ; (80029b4 ) 8002750: f043 0308 orr.w r3, r3, #8 8002754: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8002758: 4b96 ldr r3, [pc, #600] ; (80029b4 ) 800275a: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 800275e: f003 0308 and.w r3, r3, #8 8002762: 63bb str r3, [r7, #56] ; 0x38 8002764: 6bbb ldr r3, [r7, #56] ; 0x38 __HAL_RCC_GPIOF_CLK_ENABLE(); 8002766: 4b93 ldr r3, [pc, #588] ; (80029b4 ) 8002768: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 800276c: 4a91 ldr r2, [pc, #580] ; (80029b4 ) 800276e: f043 0320 orr.w r3, r3, #32 8002772: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8002776: 4b8f ldr r3, [pc, #572] ; (80029b4 ) 8002778: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 800277c: f003 0320 and.w r3, r3, #32 8002780: 637b str r3, [r7, #52] ; 0x34 8002782: 6b7b ldr r3, [r7, #52] ; 0x34 __HAL_RCC_GPIOC_CLK_ENABLE(); 8002784: 4b8b ldr r3, [pc, #556] ; (80029b4 ) 8002786: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 800278a: 4a8a ldr r2, [pc, #552] ; (80029b4 ) 800278c: f043 0304 orr.w r3, r3, #4 8002790: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8002794: 4b87 ldr r3, [pc, #540] ; (80029b4 ) 8002796: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 800279a: f003 0304 and.w r3, r3, #4 800279e: 633b str r3, [r7, #48] ; 0x30 80027a0: 6b3b ldr r3, [r7, #48] ; 0x30 __HAL_RCC_GPIOH_CLK_ENABLE(); 80027a2: 4b84 ldr r3, [pc, #528] ; (80029b4 ) 80027a4: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80027a8: 4a82 ldr r2, [pc, #520] ; (80029b4 ) 80027aa: f043 0380 orr.w r3, r3, #128 ; 0x80 80027ae: f8c2 3140 str.w r3, [r2, #320] ; 0x140 80027b2: 4b80 ldr r3, [pc, #512] ; (80029b4 ) 80027b4: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80027b8: f003 0380 and.w r3, r3, #128 ; 0x80 80027bc: 62fb str r3, [r7, #44] ; 0x2c 80027be: 6afb ldr r3, [r7, #44] ; 0x2c __HAL_RCC_GPIOE_CLK_ENABLE(); 80027c0: 4b7c ldr r3, [pc, #496] ; (80029b4 ) 80027c2: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80027c6: 4a7b ldr r2, [pc, #492] ; (80029b4 ) 80027c8: f043 0310 orr.w r3, r3, #16 80027cc: f8c2 3140 str.w r3, [r2, #320] ; 0x140 80027d0: 4b78 ldr r3, [pc, #480] ; (80029b4 ) 80027d2: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80027d6: f003 0310 and.w r3, r3, #16 80027da: 62bb str r3, [r7, #40] ; 0x28 80027dc: 6abb ldr r3, [r7, #40] ; 0x28 __HAL_RCC_GPIOA_CLK_ENABLE(); 80027de: 4b75 ldr r3, [pc, #468] ; (80029b4 ) 80027e0: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80027e4: 4a73 ldr r2, [pc, #460] ; (80029b4 ) 80027e6: f043 0301 orr.w r3, r3, #1 80027ea: f8c2 3140 str.w r3, [r2, #320] ; 0x140 80027ee: 4b71 ldr r3, [pc, #452] ; (80029b4 ) 80027f0: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 80027f4: f003 0301 and.w r3, r3, #1 80027f8: 627b str r3, [r7, #36] ; 0x24 80027fa: 6a7b ldr r3, [r7, #36] ; 0x24 PE10 ------> OCTOSPIM_P1_IO7 PA1 ------> OCTOSPIM_P1_IO3 PA7 ------> OCTOSPIM_P1_IO2 PE11 ------> OCTOSPIM_P1_NCS */ GPIO_InitStruct.Pin = GPIO_PIN_4; 80027fc: 2310 movs r3, #16 80027fe: f8c7 30fc str.w r3, [r7, #252] ; 0xfc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002802: 2302 movs r3, #2 8002804: f8c7 3100 str.w r3, [r7, #256] ; 0x100 GPIO_InitStruct.Pull = GPIO_NOPULL; 8002808: 2300 movs r3, #0 800280a: f8c7 3104 str.w r3, [r7, #260] ; 0x104 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 800280e: 2303 movs r3, #3 8002810: f8c7 3108 str.w r3, [r7, #264] ; 0x108 GPIO_InitStruct.Alternate = GPIO_AF10_OCTOSPIM_P1; 8002814: 230a movs r3, #10 8002816: f8c7 310c str.w r3, [r7, #268] ; 0x10c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800281a: f107 03fc add.w r3, r7, #252 ; 0xfc 800281e: 4619 mov r1, r3 8002820: 4865 ldr r0, [pc, #404] ; (80029b8 ) 8002822: f002 fb4f bl 8004ec4 GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; 8002826: f44f 7340 mov.w r3, #768 ; 0x300 800282a: f8c7 30fc str.w r3, [r7, #252] ; 0xfc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800282e: 2302 movs r3, #2 8002830: f8c7 3100 str.w r3, [r7, #256] ; 0x100 GPIO_InitStruct.Pull = GPIO_NOPULL; 8002834: 2300 movs r3, #0 8002836: f8c7 3104 str.w r3, [r7, #260] ; 0x104 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 800283a: 2303 movs r3, #3 800283c: f8c7 3108 str.w r3, [r7, #264] ; 0x108 GPIO_InitStruct.Alternate = GPIO_AF10_OCTOSPIM_P1; 8002840: 230a movs r3, #10 8002842: f8c7 310c str.w r3, [r7, #268] ; 0x10c HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 8002846: f107 03fc add.w r3, r7, #252 ; 0xfc 800284a: 4619 mov r1, r3 800284c: 485b ldr r0, [pc, #364] ; (80029bc ) 800284e: f002 fb39 bl 8004ec4 GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; 8002852: f44f 6340 mov.w r3, #3072 ; 0xc00 8002856: f8c7 30fc str.w r3, [r7, #252] ; 0xfc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800285a: 2302 movs r3, #2 800285c: f8c7 3100 str.w r3, [r7, #256] ; 0x100 GPIO_InitStruct.Pull = GPIO_NOPULL; 8002860: 2300 movs r3, #0 8002862: f8c7 3104 str.w r3, [r7, #260] ; 0x104 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8002866: 2303 movs r3, #3 8002868: f8c7 3108 str.w r3, [r7, #264] ; 0x108 GPIO_InitStruct.Alternate = GPIO_AF9_OCTOSPIM_P1; 800286c: 2309 movs r3, #9 800286e: f8c7 310c str.w r3, [r7, #268] ; 0x10c HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 8002872: f107 03fc add.w r3, r7, #252 ; 0xfc 8002876: 4619 mov r1, r3 8002878: 4850 ldr r0, [pc, #320] ; (80029bc ) 800287a: f002 fb23 bl 8004ec4 GPIO_InitStruct.Pin = GPIO_PIN_3; 800287e: 2308 movs r3, #8 8002880: f8c7 30fc str.w r3, [r7, #252] ; 0xfc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002884: 2302 movs r3, #2 8002886: f8c7 3100 str.w r3, [r7, #256] ; 0x100 GPIO_InitStruct.Pull = GPIO_NOPULL; 800288a: 2300 movs r3, #0 800288c: f8c7 3104 str.w r3, [r7, #260] ; 0x104 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8002890: 2303 movs r3, #3 8002892: f8c7 3108 str.w r3, [r7, #264] ; 0x108 GPIO_InitStruct.Alternate = GPIO_AF11_OCTOSPIM_P1; 8002896: 230b movs r3, #11 8002898: f8c7 310c str.w r3, [r7, #268] ; 0x10c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800289c: f107 03fc add.w r3, r7, #252 ; 0xfc 80028a0: 4619 mov r1, r3 80028a2: 4847 ldr r0, [pc, #284] ; (80029c0 ) 80028a4: f002 fb0e bl 8004ec4 GPIO_InitStruct.Pin = GPIO_PIN_3; 80028a8: 2308 movs r3, #8 80028aa: f8c7 30fc str.w r3, [r7, #252] ; 0xfc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80028ae: 2302 movs r3, #2 80028b0: f8c7 3100 str.w r3, [r7, #256] ; 0x100 GPIO_InitStruct.Pull = GPIO_NOPULL; 80028b4: 2300 movs r3, #0 80028b6: f8c7 3104 str.w r3, [r7, #260] ; 0x104 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80028ba: 2303 movs r3, #3 80028bc: f8c7 3108 str.w r3, [r7, #264] ; 0x108 GPIO_InitStruct.Alternate = GPIO_AF9_OCTOSPIM_P1; 80028c0: 2309 movs r3, #9 80028c2: f8c7 310c str.w r3, [r7, #268] ; 0x10c HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); 80028c6: f107 03fc add.w r3, r7, #252 ; 0xfc 80028ca: 4619 mov r1, r3 80028cc: 483d ldr r0, [pc, #244] ; (80029c4 ) 80028ce: f002 faf9 bl 8004ec4 GPIO_InitStruct.Pin = GPIO_PIN_5; 80028d2: 2320 movs r3, #32 80028d4: f8c7 30fc str.w r3, [r7, #252] ; 0xfc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80028d8: 2302 movs r3, #2 80028da: f8c7 3100 str.w r3, [r7, #256] ; 0x100 GPIO_InitStruct.Pull = GPIO_NOPULL; 80028de: 2300 movs r3, #0 80028e0: f8c7 3104 str.w r3, [r7, #260] ; 0x104 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80028e4: 2303 movs r3, #3 80028e6: f8c7 3108 str.w r3, [r7, #264] ; 0x108 GPIO_InitStruct.Alternate = GPIO_AF10_OCTOSPIM_P1; 80028ea: 230a movs r3, #10 80028ec: f8c7 310c str.w r3, [r7, #268] ; 0x10c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80028f0: f107 03fc add.w r3, r7, #252 ; 0xfc 80028f4: 4619 mov r1, r3 80028f6: 4832 ldr r0, [pc, #200] ; (80029c0 ) 80028f8: f002 fae4 bl 8004ec4 GPIO_InitStruct.Pin = GPIO_PIN_10; 80028fc: f44f 6380 mov.w r3, #1024 ; 0x400 8002900: f8c7 30fc str.w r3, [r7, #252] ; 0xfc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002904: 2302 movs r3, #2 8002906: f8c7 3100 str.w r3, [r7, #256] ; 0x100 GPIO_InitStruct.Pull = GPIO_NOPULL; 800290a: 2300 movs r3, #0 800290c: f8c7 3104 str.w r3, [r7, #260] ; 0x104 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8002910: 2303 movs r3, #3 8002912: f8c7 3108 str.w r3, [r7, #264] ; 0x108 GPIO_InitStruct.Alternate = GPIO_AF10_OCTOSPIM_P1; 8002916: 230a movs r3, #10 8002918: f8c7 310c str.w r3, [r7, #268] ; 0x10c HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 800291c: f107 03fc add.w r3, r7, #252 ; 0xfc 8002920: 4619 mov r1, r3 8002922: 4829 ldr r0, [pc, #164] ; (80029c8 ) 8002924: f002 face bl 8004ec4 GPIO_InitStruct.Pin = GPIO_PIN_1; 8002928: 2302 movs r3, #2 800292a: f8c7 30fc str.w r3, [r7, #252] ; 0xfc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800292e: 2302 movs r3, #2 8002930: f8c7 3100 str.w r3, [r7, #256] ; 0x100 GPIO_InitStruct.Pull = GPIO_NOPULL; 8002934: 2300 movs r3, #0 8002936: f8c7 3104 str.w r3, [r7, #260] ; 0x104 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 800293a: 2303 movs r3, #3 800293c: f8c7 3108 str.w r3, [r7, #264] ; 0x108 GPIO_InitStruct.Alternate = GPIO_AF9_OCTOSPIM_P1; 8002940: 2309 movs r3, #9 8002942: f8c7 310c str.w r3, [r7, #268] ; 0x10c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8002946: f107 03fc add.w r3, r7, #252 ; 0xfc 800294a: 4619 mov r1, r3 800294c: 481f ldr r0, [pc, #124] ; (80029cc ) 800294e: f002 fab9 bl 8004ec4 GPIO_InitStruct.Pin = GPIO_PIN_7; 8002952: 2380 movs r3, #128 ; 0x80 8002954: f8c7 30fc str.w r3, [r7, #252] ; 0xfc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002958: 2302 movs r3, #2 800295a: f8c7 3100 str.w r3, [r7, #256] ; 0x100 GPIO_InitStruct.Pull = GPIO_NOPULL; 800295e: 2300 movs r3, #0 8002960: f8c7 3104 str.w r3, [r7, #260] ; 0x104 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8002964: 2303 movs r3, #3 8002966: f8c7 3108 str.w r3, [r7, #264] ; 0x108 GPIO_InitStruct.Alternate = GPIO_AF10_OCTOSPIM_P1; 800296a: 230a movs r3, #10 800296c: f8c7 310c str.w r3, [r7, #268] ; 0x10c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8002970: f107 03fc add.w r3, r7, #252 ; 0xfc 8002974: 4619 mov r1, r3 8002976: 4815 ldr r0, [pc, #84] ; (80029cc ) 8002978: f002 faa4 bl 8004ec4 GPIO_InitStruct.Pin = GPIO_PIN_11; 800297c: f44f 6300 mov.w r3, #2048 ; 0x800 8002980: f8c7 30fc str.w r3, [r7, #252] ; 0xfc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002984: 2302 movs r3, #2 8002986: f8c7 3100 str.w r3, [r7, #256] ; 0x100 GPIO_InitStruct.Pull = GPIO_NOPULL; 800298a: 2300 movs r3, #0 800298c: f8c7 3104 str.w r3, [r7, #260] ; 0x104 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8002990: 2303 movs r3, #3 8002992: f8c7 3108 str.w r3, [r7, #264] ; 0x108 GPIO_InitStruct.Alternate = GPIO_AF11_OCTOSPIM_P1; 8002996: 230b movs r3, #11 8002998: f8c7 310c str.w r3, [r7, #268] ; 0x10c HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 800299c: f107 03fc add.w r3, r7, #252 ; 0xfc 80029a0: 4619 mov r1, r3 80029a2: 4809 ldr r0, [pc, #36] ; (80029c8 ) 80029a4: f002 fa8e bl 8004ec4 /* USER CODE BEGIN OCTOSPI2_MspInit 1 */ /* USER CODE END OCTOSPI2_MspInit 1 */ } } 80029a8: e0e9 b.n 8002b7e 80029aa: bf00 nop 80029ac: 52005000 .word 0x52005000 80029b0: 2000002c .word 0x2000002c 80029b4: 58024400 .word 0x58024400 80029b8: 58020c00 .word 0x58020c00 80029bc: 58021400 .word 0x58021400 80029c0: 58020800 .word 0x58020800 80029c4: 58021c00 .word 0x58021c00 80029c8: 58021000 .word 0x58021000 80029cc: 58020000 .word 0x58020000 else if(hospi->Instance==OCTOSPI2) 80029d0: 1d3b adds r3, r7, #4 80029d2: 681b ldr r3, [r3, #0] 80029d4: 681b ldr r3, [r3, #0] 80029d6: 4a6c ldr r2, [pc, #432] ; (8002b88 ) 80029d8: 4293 cmp r3, r2 80029da: f040 80d0 bne.w 8002b7e PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_OSPI; 80029de: f04f 7300 mov.w r3, #33554432 ; 0x2000000 80029e2: 647b str r3, [r7, #68] ; 0x44 PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_D1HCLK; 80029e4: 2300 movs r3, #0 80029e6: f8c7 308c str.w r3, [r7, #140] ; 0x8c if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 80029ea: f107 0344 add.w r3, r7, #68 ; 0x44 80029ee: 4618 mov r0, r3 80029f0: f004 fd6e bl 80074d0 80029f4: 4603 mov r3, r0 80029f6: 2b00 cmp r3, #0 80029f8: d001 beq.n 80029fe Error_Handler(); 80029fa: f7fe ff91 bl 8001920 HAL_RCC_OCTOSPIM_CLK_ENABLED++; 80029fe: 4b63 ldr r3, [pc, #396] ; (8002b8c ) 8002a00: 681b ldr r3, [r3, #0] 8002a02: 3301 adds r3, #1 8002a04: 4a61 ldr r2, [pc, #388] ; (8002b8c ) 8002a06: 6013 str r3, [r2, #0] if(HAL_RCC_OCTOSPIM_CLK_ENABLED==1){ 8002a08: 4b60 ldr r3, [pc, #384] ; (8002b8c ) 8002a0a: 681b ldr r3, [r3, #0] 8002a0c: 2b01 cmp r3, #1 8002a0e: d10e bne.n 8002a2e __HAL_RCC_OCTOSPIM_CLK_ENABLE(); 8002a10: 4b5f ldr r3, [pc, #380] ; (8002b90 ) 8002a12: f8d3 3134 ldr.w r3, [r3, #308] ; 0x134 8002a16: 4a5e ldr r2, [pc, #376] ; (8002b90 ) 8002a18: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 8002a1c: f8c2 3134 str.w r3, [r2, #308] ; 0x134 8002a20: 4b5b ldr r3, [pc, #364] ; (8002b90 ) 8002a22: f8d3 3134 ldr.w r3, [r3, #308] ; 0x134 8002a26: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8002a2a: 623b str r3, [r7, #32] 8002a2c: 6a3b ldr r3, [r7, #32] __HAL_RCC_OSPI2_CLK_ENABLE(); 8002a2e: 4b58 ldr r3, [pc, #352] ; (8002b90 ) 8002a30: f8d3 3134 ldr.w r3, [r3, #308] ; 0x134 8002a34: 4a56 ldr r2, [pc, #344] ; (8002b90 ) 8002a36: f443 2300 orr.w r3, r3, #524288 ; 0x80000 8002a3a: f8c2 3134 str.w r3, [r2, #308] ; 0x134 8002a3e: 4b54 ldr r3, [pc, #336] ; (8002b90 ) 8002a40: f8d3 3134 ldr.w r3, [r3, #308] ; 0x134 8002a44: f403 2300 and.w r3, r3, #524288 ; 0x80000 8002a48: 61fb str r3, [r7, #28] 8002a4a: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOK_CLK_ENABLE(); 8002a4c: 4b50 ldr r3, [pc, #320] ; (8002b90 ) 8002a4e: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8002a52: 4a4f ldr r2, [pc, #316] ; (8002b90 ) 8002a54: f443 6380 orr.w r3, r3, #1024 ; 0x400 8002a58: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8002a5c: 4b4c ldr r3, [pc, #304] ; (8002b90 ) 8002a5e: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8002a62: f403 6380 and.w r3, r3, #1024 ; 0x400 8002a66: 61bb str r3, [r7, #24] 8002a68: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOI_CLK_ENABLE(); 8002a6a: 4b49 ldr r3, [pc, #292] ; (8002b90 ) 8002a6c: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8002a70: 4a47 ldr r2, [pc, #284] ; (8002b90 ) 8002a72: f443 7380 orr.w r3, r3, #256 ; 0x100 8002a76: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8002a7a: 4b45 ldr r3, [pc, #276] ; (8002b90 ) 8002a7c: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8002a80: f403 7380 and.w r3, r3, #256 ; 0x100 8002a84: 617b str r3, [r7, #20] 8002a86: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOF_CLK_ENABLE(); 8002a88: 4b41 ldr r3, [pc, #260] ; (8002b90 ) 8002a8a: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8002a8e: 4a40 ldr r2, [pc, #256] ; (8002b90 ) 8002a90: f043 0320 orr.w r3, r3, #32 8002a94: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8002a98: 4b3d ldr r3, [pc, #244] ; (8002b90 ) 8002a9a: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8002a9e: f003 0220 and.w r2, r3, #32 8002aa2: f107 0310 add.w r3, r7, #16 8002aa6: 601a str r2, [r3, #0] 8002aa8: f107 0310 add.w r3, r7, #16 8002aac: 681b ldr r3, [r3, #0] __HAL_RCC_GPIOJ_CLK_ENABLE(); 8002aae: 4b38 ldr r3, [pc, #224] ; (8002b90 ) 8002ab0: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8002ab4: 4a36 ldr r2, [pc, #216] ; (8002b90 ) 8002ab6: f443 7300 orr.w r3, r3, #512 ; 0x200 8002aba: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8002abe: 4b34 ldr r3, [pc, #208] ; (8002b90 ) 8002ac0: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8002ac4: f403 7200 and.w r2, r3, #512 ; 0x200 8002ac8: f107 030c add.w r3, r7, #12 8002acc: 601a str r2, [r3, #0] 8002ace: f107 030c add.w r3, r7, #12 8002ad2: 681b ldr r3, [r3, #0] GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_3|GPIO_PIN_4; 8002ad4: 2378 movs r3, #120 ; 0x78 8002ad6: f8c7 30fc str.w r3, [r7, #252] ; 0xfc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002ada: 2302 movs r3, #2 8002adc: f8c7 3100 str.w r3, [r7, #256] ; 0x100 GPIO_InitStruct.Pull = GPIO_NOPULL; 8002ae0: 2300 movs r3, #0 8002ae2: f8c7 3104 str.w r3, [r7, #260] ; 0x104 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8002ae6: 2303 movs r3, #3 8002ae8: f8c7 3108 str.w r3, [r7, #264] ; 0x108 GPIO_InitStruct.Alternate = GPIO_AF3_OCTOSPIM_P2; 8002aec: 2303 movs r3, #3 8002aee: f8c7 310c str.w r3, [r7, #268] ; 0x10c HAL_GPIO_Init(GPIOK, &GPIO_InitStruct); 8002af2: f107 03fc add.w r3, r7, #252 ; 0xfc 8002af6: 4619 mov r1, r3 8002af8: 4826 ldr r0, [pc, #152] ; (8002b94 ) 8002afa: f002 f9e3 bl 8004ec4 GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12 8002afe: f44f 43bc mov.w r3, #24064 ; 0x5e00 8002b02: f8c7 30fc str.w r3, [r7, #252] ; 0xfc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002b06: 2302 movs r3, #2 8002b08: f8c7 3100 str.w r3, [r7, #256] ; 0x100 GPIO_InitStruct.Pull = GPIO_NOPULL; 8002b0c: 2300 movs r3, #0 8002b0e: f8c7 3104 str.w r3, [r7, #260] ; 0x104 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8002b12: 2303 movs r3, #3 8002b14: f8c7 3108 str.w r3, [r7, #264] ; 0x108 GPIO_InitStruct.Alternate = GPIO_AF3_OCTOSPIM_P2; 8002b18: 2303 movs r3, #3 8002b1a: f8c7 310c str.w r3, [r7, #268] ; 0x10c HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); 8002b1e: f107 03fc add.w r3, r7, #252 ; 0xfc 8002b22: 4619 mov r1, r3 8002b24: 481c ldr r0, [pc, #112] ; (8002b98 ) 8002b26: f002 f9cd bl 8004ec4 GPIO_InitStruct.Pin = GPIO_PIN_4; 8002b2a: 2310 movs r3, #16 8002b2c: f8c7 30fc str.w r3, [r7, #252] ; 0xfc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002b30: 2302 movs r3, #2 8002b32: f8c7 3100 str.w r3, [r7, #256] ; 0x100 GPIO_InitStruct.Pull = GPIO_NOPULL; 8002b36: 2300 movs r3, #0 8002b38: f8c7 3104 str.w r3, [r7, #260] ; 0x104 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8002b3c: 2303 movs r3, #3 8002b3e: f8c7 3108 str.w r3, [r7, #264] ; 0x108 GPIO_InitStruct.Alternate = GPIO_AF9_OCTOSPIM_P2; 8002b42: 2309 movs r3, #9 8002b44: f8c7 310c str.w r3, [r7, #268] ; 0x10c HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 8002b48: f107 03fc add.w r3, r7, #252 ; 0xfc 8002b4c: 4619 mov r1, r3 8002b4e: 4813 ldr r0, [pc, #76] ; (8002b9c ) 8002b50: f002 f9b8 bl 8004ec4 GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2; 8002b54: 2306 movs r3, #6 8002b56: f8c7 30fc str.w r3, [r7, #252] ; 0xfc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002b5a: 2302 movs r3, #2 8002b5c: f8c7 3100 str.w r3, [r7, #256] ; 0x100 GPIO_InitStruct.Pull = GPIO_NOPULL; 8002b60: 2300 movs r3, #0 8002b62: f8c7 3104 str.w r3, [r7, #260] ; 0x104 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8002b66: 2303 movs r3, #3 8002b68: f8c7 3108 str.w r3, [r7, #264] ; 0x108 GPIO_InitStruct.Alternate = GPIO_AF3_OCTOSPIM_P2; 8002b6c: 2303 movs r3, #3 8002b6e: f8c7 310c str.w r3, [r7, #268] ; 0x10c HAL_GPIO_Init(GPIOJ, &GPIO_InitStruct); 8002b72: f107 03fc add.w r3, r7, #252 ; 0xfc 8002b76: 4619 mov r1, r3 8002b78: 4809 ldr r0, [pc, #36] ; (8002ba0 ) 8002b7a: f002 f9a3 bl 8004ec4 } 8002b7e: bf00 nop 8002b80: f507 7788 add.w r7, r7, #272 ; 0x110 8002b84: 46bd mov sp, r7 8002b86: bd80 pop {r7, pc} 8002b88: 5200a000 .word 0x5200a000 8002b8c: 2000002c .word 0x2000002c 8002b90: 58024400 .word 0x58024400 8002b94: 58022800 .word 0x58022800 8002b98: 58022000 .word 0x58022000 8002b9c: 58021400 .word 0x58021400 8002ba0: 58022400 .word 0x58022400 08002ba4 : * This function configures the hardware resources used in this example * @param hrtc: RTC handle pointer * @retval None */ void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) { 8002ba4: b580 push {r7, lr} 8002ba6: b0b0 sub sp, #192 ; 0xc0 8002ba8: af00 add r7, sp, #0 8002baa: 6078 str r0, [r7, #4] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8002bac: f107 0308 add.w r3, r7, #8 8002bb0: 22b8 movs r2, #184 ; 0xb8 8002bb2: 2100 movs r1, #0 8002bb4: 4618 mov r0, r3 8002bb6: f00b fd35 bl 800e624 if(hrtc->Instance==RTC) 8002bba: 687b ldr r3, [r7, #4] 8002bbc: 681b ldr r3, [r3, #0] 8002bbe: 4a0f ldr r2, [pc, #60] ; (8002bfc ) 8002bc0: 4293 cmp r3, r2 8002bc2: d116 bne.n 8002bf2 /* USER CODE BEGIN RTC_MspInit 0 */ /* USER CODE END RTC_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; 8002bc4: f44f 0380 mov.w r3, #4194304 ; 0x400000 8002bc8: 60bb str r3, [r7, #8] PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; 8002bca: f44f 7300 mov.w r3, #512 ; 0x200 8002bce: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8002bd2: f107 0308 add.w r3, r7, #8 8002bd6: 4618 mov r0, r3 8002bd8: f004 fc7a bl 80074d0 8002bdc: 4603 mov r3, r0 8002bde: 2b00 cmp r3, #0 8002be0: d001 beq.n 8002be6 { Error_Handler(); 8002be2: f7fe fe9d bl 8001920 } /* Peripheral clock enable */ __HAL_RCC_RTC_ENABLE(); 8002be6: 4b06 ldr r3, [pc, #24] ; (8002c00 ) 8002be8: 6f1b ldr r3, [r3, #112] ; 0x70 8002bea: 4a05 ldr r2, [pc, #20] ; (8002c00 ) 8002bec: f443 4300 orr.w r3, r3, #32768 ; 0x8000 8002bf0: 6713 str r3, [r2, #112] ; 0x70 /* USER CODE BEGIN RTC_MspInit 1 */ /* USER CODE END RTC_MspInit 1 */ } } 8002bf2: bf00 nop 8002bf4: 37c0 adds r7, #192 ; 0xc0 8002bf6: 46bd mov sp, r7 8002bf8: bd80 pop {r7, pc} 8002bfa: bf00 nop 8002bfc: 58004000 .word 0x58004000 8002c00: 58024400 .word 0x58024400 08002c04 : * This function configures the hardware resources used in this example * @param hsd: SD handle pointer * @retval None */ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) { 8002c04: b580 push {r7, lr} 8002c06: b0b8 sub sp, #224 ; 0xe0 8002c08: af00 add r7, sp, #0 8002c0a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8002c0c: f107 03cc add.w r3, r7, #204 ; 0xcc 8002c10: 2200 movs r2, #0 8002c12: 601a str r2, [r3, #0] 8002c14: 605a str r2, [r3, #4] 8002c16: 609a str r2, [r3, #8] 8002c18: 60da str r2, [r3, #12] 8002c1a: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8002c1c: f107 0314 add.w r3, r7, #20 8002c20: 22b8 movs r2, #184 ; 0xb8 8002c22: 2100 movs r1, #0 8002c24: 4618 mov r0, r3 8002c26: f00b fcfd bl 800e624 if(hsd->Instance==SDMMC1) 8002c2a: 687b ldr r3, [r7, #4] 8002c2c: 681b ldr r3, [r3, #0] 8002c2e: 4a37 ldr r2, [pc, #220] ; (8002d0c ) 8002c30: 4293 cmp r3, r2 8002c32: d166 bne.n 8002d02 /* USER CODE BEGIN SDMMC1_MspInit 0 */ /* USER CODE END SDMMC1_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC; 8002c34: f44f 3380 mov.w r3, #65536 ; 0x10000 8002c38: 617b str r3, [r7, #20] PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL; 8002c3a: 2300 movs r3, #0 8002c3c: 663b str r3, [r7, #96] ; 0x60 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8002c3e: f107 0314 add.w r3, r7, #20 8002c42: 4618 mov r0, r3 8002c44: f004 fc44 bl 80074d0 8002c48: 4603 mov r3, r0 8002c4a: 2b00 cmp r3, #0 8002c4c: d001 beq.n 8002c52 { Error_Handler(); 8002c4e: f7fe fe67 bl 8001920 } /* Peripheral clock enable */ __HAL_RCC_SDMMC1_CLK_ENABLE(); 8002c52: 4b2f ldr r3, [pc, #188] ; (8002d10 ) 8002c54: f8d3 3134 ldr.w r3, [r3, #308] ; 0x134 8002c58: 4a2d ldr r2, [pc, #180] ; (8002d10 ) 8002c5a: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8002c5e: f8c2 3134 str.w r3, [r2, #308] ; 0x134 8002c62: 4b2b ldr r3, [pc, #172] ; (8002d10 ) 8002c64: f8d3 3134 ldr.w r3, [r3, #308] ; 0x134 8002c68: f403 3380 and.w r3, r3, #65536 ; 0x10000 8002c6c: 613b str r3, [r7, #16] 8002c6e: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 8002c70: 4b27 ldr r3, [pc, #156] ; (8002d10 ) 8002c72: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8002c76: 4a26 ldr r2, [pc, #152] ; (8002d10 ) 8002c78: f043 0304 orr.w r3, r3, #4 8002c7c: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8002c80: 4b23 ldr r3, [pc, #140] ; (8002d10 ) 8002c82: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8002c86: f003 0304 and.w r3, r3, #4 8002c8a: 60fb str r3, [r7, #12] 8002c8c: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOD_CLK_ENABLE(); 8002c8e: 4b20 ldr r3, [pc, #128] ; (8002d10 ) 8002c90: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8002c94: 4a1e ldr r2, [pc, #120] ; (8002d10 ) 8002c96: f043 0308 orr.w r3, r3, #8 8002c9a: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8002c9e: 4b1c ldr r3, [pc, #112] ; (8002d10 ) 8002ca0: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8002ca4: f003 0308 and.w r3, r3, #8 8002ca8: 60bb str r3, [r7, #8] 8002caa: 68bb ldr r3, [r7, #8] PC12 ------> SDMMC1_CK PC11 ------> SDMMC1_D3 PC9 ------> SDMMC1_D1 PC8 ------> SDMMC1_D0 */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_9 8002cac: f44f 53f8 mov.w r3, #7936 ; 0x1f00 8002cb0: f8c7 30cc str.w r3, [r7, #204] ; 0xcc |GPIO_PIN_8; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002cb4: 2302 movs r3, #2 8002cb6: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 GPIO_InitStruct.Pull = GPIO_NOPULL; 8002cba: 2300 movs r3, #0 8002cbc: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8002cc0: 2303 movs r3, #3 8002cc2: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8 GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1; 8002cc6: 230c movs r3, #12 8002cc8: f8c7 30dc str.w r3, [r7, #220] ; 0xdc HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8002ccc: f107 03cc add.w r3, r7, #204 ; 0xcc 8002cd0: 4619 mov r1, r3 8002cd2: 4810 ldr r0, [pc, #64] ; (8002d14 ) 8002cd4: f002 f8f6 bl 8004ec4 GPIO_InitStruct.Pin = GPIO_PIN_2; 8002cd8: 2304 movs r3, #4 8002cda: f8c7 30cc str.w r3, [r7, #204] ; 0xcc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002cde: 2302 movs r3, #2 8002ce0: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 GPIO_InitStruct.Pull = GPIO_NOPULL; 8002ce4: 2300 movs r3, #0 8002ce6: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8002cea: 2303 movs r3, #3 8002cec: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8 GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1; 8002cf0: 230c movs r3, #12 8002cf2: f8c7 30dc str.w r3, [r7, #220] ; 0xdc HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8002cf6: f107 03cc add.w r3, r7, #204 ; 0xcc 8002cfa: 4619 mov r1, r3 8002cfc: 4806 ldr r0, [pc, #24] ; (8002d18 ) 8002cfe: f002 f8e1 bl 8004ec4 /* USER CODE BEGIN SDMMC1_MspInit 1 */ /* USER CODE END SDMMC1_MspInit 1 */ } } 8002d02: bf00 nop 8002d04: 37e0 adds r7, #224 ; 0xe0 8002d06: 46bd mov sp, r7 8002d08: bd80 pop {r7, pc} 8002d0a: bf00 nop 8002d0c: 52007000 .word 0x52007000 8002d10: 58024400 .word 0x58024400 8002d14: 58020800 .word 0x58020800 8002d18: 58020c00 .word 0x58020c00 08002d1c : * This function configures the hardware resources used in this example * @param hspi: SPI handle pointer * @retval None */ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) { 8002d1c: b580 push {r7, lr} 8002d1e: b0ba sub sp, #232 ; 0xe8 8002d20: af00 add r7, sp, #0 8002d22: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8002d24: f107 03d4 add.w r3, r7, #212 ; 0xd4 8002d28: 2200 movs r2, #0 8002d2a: 601a str r2, [r3, #0] 8002d2c: 605a str r2, [r3, #4] 8002d2e: 609a str r2, [r3, #8] 8002d30: 60da str r2, [r3, #12] 8002d32: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8002d34: f107 031c add.w r3, r7, #28 8002d38: 22b8 movs r2, #184 ; 0xb8 8002d3a: 2100 movs r1, #0 8002d3c: 4618 mov r0, r3 8002d3e: f00b fc71 bl 800e624 if(hspi->Instance==SPI2) 8002d42: 687b ldr r3, [r7, #4] 8002d44: 681b ldr r3, [r3, #0] 8002d46: 4a5c ldr r2, [pc, #368] ; (8002eb8 ) 8002d48: 4293 cmp r3, r2 8002d4a: d167 bne.n 8002e1c /* USER CODE BEGIN SPI2_MspInit 0 */ /* USER CODE END SPI2_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SPI2; 8002d4c: f44f 5380 mov.w r3, #4096 ; 0x1000 8002d50: 61fb str r3, [r7, #28] PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL; 8002d52: 2300 movs r3, #0 8002d54: 67fb str r3, [r7, #124] ; 0x7c if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8002d56: f107 031c add.w r3, r7, #28 8002d5a: 4618 mov r0, r3 8002d5c: f004 fbb8 bl 80074d0 8002d60: 4603 mov r3, r0 8002d62: 2b00 cmp r3, #0 8002d64: d001 beq.n 8002d6a { Error_Handler(); 8002d66: f7fe fddb bl 8001920 } /* Peripheral clock enable */ __HAL_RCC_SPI2_CLK_ENABLE(); 8002d6a: 4b54 ldr r3, [pc, #336] ; (8002ebc ) 8002d6c: f8d3 3148 ldr.w r3, [r3, #328] ; 0x148 8002d70: 4a52 ldr r2, [pc, #328] ; (8002ebc ) 8002d72: f443 4380 orr.w r3, r3, #16384 ; 0x4000 8002d76: f8c2 3148 str.w r3, [r2, #328] ; 0x148 8002d7a: 4b50 ldr r3, [pc, #320] ; (8002ebc ) 8002d7c: f8d3 3148 ldr.w r3, [r3, #328] ; 0x148 8002d80: f403 4380 and.w r3, r3, #16384 ; 0x4000 8002d84: 61bb str r3, [r7, #24] 8002d86: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOI_CLK_ENABLE(); 8002d88: 4b4c ldr r3, [pc, #304] ; (8002ebc ) 8002d8a: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8002d8e: 4a4b ldr r2, [pc, #300] ; (8002ebc ) 8002d90: f443 7380 orr.w r3, r3, #256 ; 0x100 8002d94: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8002d98: 4b48 ldr r3, [pc, #288] ; (8002ebc ) 8002d9a: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8002d9e: f403 7380 and.w r3, r3, #256 ; 0x100 8002da2: 617b str r3, [r7, #20] 8002da4: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOB_CLK_ENABLE(); 8002da6: 4b45 ldr r3, [pc, #276] ; (8002ebc ) 8002da8: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8002dac: 4a43 ldr r2, [pc, #268] ; (8002ebc ) 8002dae: f043 0302 orr.w r3, r3, #2 8002db2: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8002db6: 4b41 ldr r3, [pc, #260] ; (8002ebc ) 8002db8: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8002dbc: f003 0302 and.w r3, r3, #2 8002dc0: 613b str r3, [r7, #16] 8002dc2: 693b ldr r3, [r7, #16] /**SPI2 GPIO Configuration PI3 ------> SPI2_MOSI PI2 ------> SPI2_MISO PB10 ------> SPI2_SCK */ GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_2; 8002dc4: 230c movs r3, #12 8002dc6: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002dca: 2302 movs r3, #2 8002dcc: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8 GPIO_InitStruct.Pull = GPIO_NOPULL; 8002dd0: 2300 movs r3, #0 8002dd2: f8c7 30dc str.w r3, [r7, #220] ; 0xdc GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8002dd6: 2300 movs r3, #0 8002dd8: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; 8002ddc: 2305 movs r3, #5 8002dde: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); 8002de2: f107 03d4 add.w r3, r7, #212 ; 0xd4 8002de6: 4619 mov r1, r3 8002de8: 4835 ldr r0, [pc, #212] ; (8002ec0 ) 8002dea: f002 f86b bl 8004ec4 GPIO_InitStruct.Pin = GPIO_PIN_10; 8002dee: f44f 6380 mov.w r3, #1024 ; 0x400 8002df2: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002df6: 2302 movs r3, #2 8002df8: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8 GPIO_InitStruct.Pull = GPIO_NOPULL; 8002dfc: 2300 movs r3, #0 8002dfe: f8c7 30dc str.w r3, [r7, #220] ; 0xdc GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8002e02: 2300 movs r3, #0 8002e04: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; 8002e08: 2305 movs r3, #5 8002e0a: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8002e0e: f107 03d4 add.w r3, r7, #212 ; 0xd4 8002e12: 4619 mov r1, r3 8002e14: 482b ldr r0, [pc, #172] ; (8002ec4 ) 8002e16: f002 f855 bl 8004ec4 /* USER CODE BEGIN SPI4_MspInit 1 */ /* USER CODE END SPI4_MspInit 1 */ } } 8002e1a: e048 b.n 8002eae else if(hspi->Instance==SPI4) 8002e1c: 687b ldr r3, [r7, #4] 8002e1e: 681b ldr r3, [r3, #0] 8002e20: 4a29 ldr r2, [pc, #164] ; (8002ec8 ) 8002e22: 4293 cmp r3, r2 8002e24: d143 bne.n 8002eae PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SPI4; 8002e26: f44f 5300 mov.w r3, #8192 ; 0x2000 8002e2a: 61fb str r3, [r7, #28] PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_D2PCLK1; 8002e2c: 2300 movs r3, #0 8002e2e: f8c7 3080 str.w r3, [r7, #128] ; 0x80 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8002e32: f107 031c add.w r3, r7, #28 8002e36: 4618 mov r0, r3 8002e38: f004 fb4a bl 80074d0 8002e3c: 4603 mov r3, r0 8002e3e: 2b00 cmp r3, #0 8002e40: d001 beq.n 8002e46 Error_Handler(); 8002e42: f7fe fd6d bl 8001920 __HAL_RCC_SPI4_CLK_ENABLE(); 8002e46: 4b1d ldr r3, [pc, #116] ; (8002ebc ) 8002e48: f8d3 3150 ldr.w r3, [r3, #336] ; 0x150 8002e4c: 4a1b ldr r2, [pc, #108] ; (8002ebc ) 8002e4e: f443 5300 orr.w r3, r3, #8192 ; 0x2000 8002e52: f8c2 3150 str.w r3, [r2, #336] ; 0x150 8002e56: 4b19 ldr r3, [pc, #100] ; (8002ebc ) 8002e58: f8d3 3150 ldr.w r3, [r3, #336] ; 0x150 8002e5c: f403 5300 and.w r3, r3, #8192 ; 0x2000 8002e60: 60fb str r3, [r7, #12] 8002e62: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOE_CLK_ENABLE(); 8002e64: 4b15 ldr r3, [pc, #84] ; (8002ebc ) 8002e66: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8002e6a: 4a14 ldr r2, [pc, #80] ; (8002ebc ) 8002e6c: f043 0310 orr.w r3, r3, #16 8002e70: f8c2 3140 str.w r3, [r2, #320] ; 0x140 8002e74: 4b11 ldr r3, [pc, #68] ; (8002ebc ) 8002e76: f8d3 3140 ldr.w r3, [r3, #320] ; 0x140 8002e7a: f003 0310 and.w r3, r3, #16 8002e7e: 60bb str r3, [r7, #8] 8002e80: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14; 8002e82: f44f 43e0 mov.w r3, #28672 ; 0x7000 8002e86: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002e8a: 2302 movs r3, #2 8002e8c: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8 GPIO_InitStruct.Pull = GPIO_NOPULL; 8002e90: 2300 movs r3, #0 8002e92: f8c7 30dc str.w r3, [r7, #220] ; 0xdc GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8002e96: 2300 movs r3, #0 8002e98: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 GPIO_InitStruct.Alternate = GPIO_AF5_SPI4; 8002e9c: 2305 movs r3, #5 8002e9e: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8002ea2: f107 03d4 add.w r3, r7, #212 ; 0xd4 8002ea6: 4619 mov r1, r3 8002ea8: 4808 ldr r0, [pc, #32] ; (8002ecc ) 8002eaa: f002 f80b bl 8004ec4 } 8002eae: bf00 nop 8002eb0: 37e8 adds r7, #232 ; 0xe8 8002eb2: 46bd mov sp, r7 8002eb4: bd80 pop {r7, pc} 8002eb6: bf00 nop 8002eb8: 40003800 .word 0x40003800 8002ebc: 58024400 .word 0x58024400 8002ec0: 58022000 .word 0x58022000 8002ec4: 58020400 .word 0x58020400 8002ec8: 40013400 .word 0x40013400 8002ecc: 58021000 .word 0x58021000 08002ed0 : * This function configures the hardware resources used in this example * @param hwwdg: WWDG handle pointer * @retval None */ void HAL_WWDG_MspInit(WWDG_HandleTypeDef* hwwdg) { 8002ed0: b480 push {r7} 8002ed2: b085 sub sp, #20 8002ed4: af00 add r7, sp, #0 8002ed6: 6078 str r0, [r7, #4] if(hwwdg->Instance==WWDG1) 8002ed8: 687b ldr r3, [r7, #4] 8002eda: 681b ldr r3, [r3, #0] 8002edc: 4a0b ldr r2, [pc, #44] ; (8002f0c ) 8002ede: 4293 cmp r3, r2 8002ee0: d10e bne.n 8002f00 { /* USER CODE BEGIN WWDG1_MspInit 0 */ /* USER CODE END WWDG1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_WWDG1_CLK_ENABLE(); 8002ee2: 4b0b ldr r3, [pc, #44] ; (8002f10 ) 8002ee4: f8d3 3144 ldr.w r3, [r3, #324] ; 0x144 8002ee8: 4a09 ldr r2, [pc, #36] ; (8002f10 ) 8002eea: f043 0340 orr.w r3, r3, #64 ; 0x40 8002eee: f8c2 3144 str.w r3, [r2, #324] ; 0x144 8002ef2: 4b07 ldr r3, [pc, #28] ; (8002f10 ) 8002ef4: f8d3 3144 ldr.w r3, [r3, #324] ; 0x144 8002ef8: f003 0340 and.w r3, r3, #64 ; 0x40 8002efc: 60fb str r3, [r7, #12] 8002efe: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN WWDG1_MspInit 1 */ /* USER CODE END WWDG1_MspInit 1 */ } } 8002f00: bf00 nop 8002f02: 3714 adds r7, #20 8002f04: 46bd mov sp, r7 8002f06: f85d 7b04 ldr.w r7, [sp], #4 8002f0a: 4770 bx lr 8002f0c: 50003000 .word 0x50003000 8002f10: 58024400 .word 0x58024400 08002f14 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8002f14: b480 push {r7} 8002f16: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8002f18: e7fe b.n 8002f18 08002f1a : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8002f1a: b480 push {r7} 8002f1c: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8002f1e: e7fe b.n 8002f1e 08002f20 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8002f20: b480 push {r7} 8002f22: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8002f24: e7fe b.n 8002f24 08002f26 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 8002f26: b480 push {r7} 8002f28: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8002f2a: e7fe b.n 8002f2a 08002f2c : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8002f2c: b480 push {r7} 8002f2e: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8002f30: e7fe b.n 8002f30 08002f32 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8002f32: b480 push {r7} 8002f34: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8002f36: bf00 nop 8002f38: 46bd mov sp, r7 8002f3a: f85d 7b04 ldr.w r7, [sp], #4 8002f3e: 4770 bx lr 08002f40 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8002f40: b480 push {r7} 8002f42: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8002f44: bf00 nop 8002f46: 46bd mov sp, r7 8002f48: f85d 7b04 ldr.w r7, [sp], #4 8002f4c: 4770 bx lr 08002f4e : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8002f4e: b480 push {r7} 8002f50: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8002f52: bf00 nop 8002f54: 46bd mov sp, r7 8002f56: f85d 7b04 ldr.w r7, [sp], #4 8002f5a: 4770 bx lr 08002f5c : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8002f5c: b580 push {r7, lr} 8002f5e: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8002f60: f000 f92e bl 80031c0 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8002f64: bf00 nop 8002f66: bd80 pop {r7, pc} 08002f68 : /** * @brief This function handles DMA1 stream2 global interrupt. */ void DMA1_Stream2_IRQHandler(void) { 8002f68: b580 push {r7, lr} 8002f6a: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */ /* USER CODE END DMA1_Stream2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_rx); 8002f6c: 4802 ldr r0, [pc, #8] ; (8002f78 ) 8002f6e: f000 fe0b bl 8003b88 /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */ /* USER CODE END DMA1_Stream2_IRQn 1 */ } 8002f72: bf00 nop 8002f74: bd80 pop {r7, pc} 8002f76: bf00 nop 8002f78: 2000009c .word 0x2000009c 08002f7c : /** * @brief This function handles DMA1 stream3 global interrupt. */ void DMA1_Stream3_IRQHandler(void) { 8002f7c: b580 push {r7, lr} 8002f7e: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream3_IRQn 0 */ /* USER CODE END DMA1_Stream3_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_tx); 8002f80: 4802 ldr r0, [pc, #8] ; (8002f8c ) 8002f82: f000 fe01 bl 8003b88 /* USER CODE BEGIN DMA1_Stream3_IRQn 1 */ /* USER CODE END DMA1_Stream3_IRQn 1 */ } 8002f86: bf00 nop 8002f88: bd80 pop {r7, pc} 8002f8a: bf00 nop 8002f8c: 20000674 .word 0x20000674 08002f90 : * configuration. * @param None * @retval None */ void SystemInit (void) { 8002f90: b480 push {r7} 8002f92: af00 add r7, sp, #0 __IO uint32_t tmpreg; #endif /* DATA_IN_D2_SRAM */ /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ 8002f94: 4b34 ldr r3, [pc, #208] ; (8003068 ) 8002f96: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8002f9a: 4a33 ldr r2, [pc, #204] ; (8003068 ) 8002f9c: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 8002fa0: f8c2 3088 str.w r3, [r2, #136] ; 0x88 #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Increasing the CPU frequency */ if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 8002fa4: 4b31 ldr r3, [pc, #196] ; (800306c ) 8002fa6: 681b ldr r3, [r3, #0] 8002fa8: f003 030f and.w r3, r3, #15 8002fac: 2b02 cmp r3, #2 8002fae: d807 bhi.n 8002fc0 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 8002fb0: 4b2e ldr r3, [pc, #184] ; (800306c ) 8002fb2: 681b ldr r3, [r3, #0] 8002fb4: f023 030f bic.w r3, r3, #15 8002fb8: 4a2c ldr r2, [pc, #176] ; (800306c ) 8002fba: f043 0303 orr.w r3, r3, #3 8002fbe: 6013 str r3, [r2, #0] } /* Set HSION bit */ RCC->CR |= RCC_CR_HSION; 8002fc0: 4b2b ldr r3, [pc, #172] ; (8003070 ) 8002fc2: 681b ldr r3, [r3, #0] 8002fc4: 4a2a ldr r2, [pc, #168] ; (8003070 ) 8002fc6: f043 0301 orr.w r3, r3, #1 8002fca: 6013 str r3, [r2, #0] /* Reset CFGR register */ RCC->CFGR = 0x00000000; 8002fcc: 4b28 ldr r3, [pc, #160] ; (8003070 ) 8002fce: 2200 movs r2, #0 8002fd0: 611a str r2, [r3, #16] /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ RCC->CR &= 0xEAF6ED7FU; 8002fd2: 4b27 ldr r3, [pc, #156] ; (8003070 ) 8002fd4: 681a ldr r2, [r3, #0] 8002fd6: 4926 ldr r1, [pc, #152] ; (8003070 ) 8002fd8: 4b26 ldr r3, [pc, #152] ; (8003074 ) 8002fda: 4013 ands r3, r2 8002fdc: 600b str r3, [r1, #0] /* Decreasing the number of wait states because of lower CPU frequency */ if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 8002fde: 4b23 ldr r3, [pc, #140] ; (800306c ) 8002fe0: 681b ldr r3, [r3, #0] 8002fe2: f003 030c and.w r3, r3, #12 8002fe6: 2b00 cmp r3, #0 8002fe8: d007 beq.n 8002ffa { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 8002fea: 4b20 ldr r3, [pc, #128] ; (800306c ) 8002fec: 681b ldr r3, [r3, #0] 8002fee: f023 030f bic.w r3, r3, #15 8002ff2: 4a1e ldr r2, [pc, #120] ; (800306c ) 8002ff4: f043 0303 orr.w r3, r3, #3 8002ff8: 6013 str r3, [r2, #0] /* Reset D3CFGR register */ RCC->D3CFGR = 0x00000000; #else /* Reset CDCFGR1 register */ RCC->CDCFGR1 = 0x00000000; 8002ffa: 4b1d ldr r3, [pc, #116] ; (8003070 ) 8002ffc: 2200 movs r2, #0 8002ffe: 619a str r2, [r3, #24] /* Reset CDCFGR2 register */ RCC->CDCFGR2 = 0x00000000; 8003000: 4b1b ldr r3, [pc, #108] ; (8003070 ) 8003002: 2200 movs r2, #0 8003004: 61da str r2, [r3, #28] /* Reset SRDCFGR register */ RCC->SRDCFGR = 0x00000000; 8003006: 4b1a ldr r3, [pc, #104] ; (8003070 ) 8003008: 2200 movs r2, #0 800300a: 621a str r2, [r3, #32] #endif /* Reset PLLCKSELR register */ RCC->PLLCKSELR = 0x02020200; 800300c: 4b18 ldr r3, [pc, #96] ; (8003070 ) 800300e: 4a1a ldr r2, [pc, #104] ; (8003078 ) 8003010: 629a str r2, [r3, #40] ; 0x28 /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x01FF0000; 8003012: 4b17 ldr r3, [pc, #92] ; (8003070 ) 8003014: 4a19 ldr r2, [pc, #100] ; (800307c ) 8003016: 62da str r2, [r3, #44] ; 0x2c /* Reset PLL1DIVR register */ RCC->PLL1DIVR = 0x01010280; 8003018: 4b15 ldr r3, [pc, #84] ; (8003070 ) 800301a: 4a19 ldr r2, [pc, #100] ; (8003080 ) 800301c: 631a str r2, [r3, #48] ; 0x30 /* Reset PLL1FRACR register */ RCC->PLL1FRACR = 0x00000000; 800301e: 4b14 ldr r3, [pc, #80] ; (8003070 ) 8003020: 2200 movs r2, #0 8003022: 635a str r2, [r3, #52] ; 0x34 /* Reset PLL2DIVR register */ RCC->PLL2DIVR = 0x01010280; 8003024: 4b12 ldr r3, [pc, #72] ; (8003070 ) 8003026: 4a16 ldr r2, [pc, #88] ; (8003080 ) 8003028: 639a str r2, [r3, #56] ; 0x38 /* Reset PLL2FRACR register */ RCC->PLL2FRACR = 0x00000000; 800302a: 4b11 ldr r3, [pc, #68] ; (8003070 ) 800302c: 2200 movs r2, #0 800302e: 63da str r2, [r3, #60] ; 0x3c /* Reset PLL3DIVR register */ RCC->PLL3DIVR = 0x01010280; 8003030: 4b0f ldr r3, [pc, #60] ; (8003070 ) 8003032: 4a13 ldr r2, [pc, #76] ; (8003080 ) 8003034: 641a str r2, [r3, #64] ; 0x40 /* Reset PLL3FRACR register */ RCC->PLL3FRACR = 0x00000000; 8003036: 4b0e ldr r3, [pc, #56] ; (8003070 ) 8003038: 2200 movs r2, #0 800303a: 645a str r2, [r3, #68] ; 0x44 /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; 800303c: 4b0c ldr r3, [pc, #48] ; (8003070 ) 800303e: 681b ldr r3, [r3, #0] 8003040: 4a0b ldr r2, [pc, #44] ; (8003070 ) 8003042: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8003046: 6013 str r3, [r2, #0] /* Disable all interrupts */ RCC->CIER = 0x00000000; 8003048: 4b09 ldr r3, [pc, #36] ; (8003070 ) 800304a: 2200 movs r2, #0 800304c: 661a str r2, [r3, #96] ; 0x60 /* * Disable the FMC bank1 (enabled after reset). * This, prevents CPU speculation access on this bank which blocks the use of FMC during * 24us. During this time the others FMC master (such as LTDC) cannot use it! */ FMC_Bank1_R->BTCR[0] = 0x000030D2; 800304e: 4b0d ldr r3, [pc, #52] ; (8003084 ) 8003050: f243 02d2 movw r2, #12498 ; 0x30d2 8003054: 601a str r2, [r3, #0] /* Configure the Vector Table location add offset address for cortex-M7 ------------------*/ #ifdef VECT_TAB_SRAM SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */ #else SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ 8003056: 4b04 ldr r3, [pc, #16] ; (8003068 ) 8003058: f04f 6200 mov.w r2, #134217728 ; 0x8000000 800305c: 609a str r2, [r3, #8] #endif #endif /*DUAL_CORE && CORE_CM4*/ } 800305e: bf00 nop 8003060: 46bd mov sp, r7 8003062: f85d 7b04 ldr.w r7, [sp], #4 8003066: 4770 bx lr 8003068: e000ed00 .word 0xe000ed00 800306c: 52002000 .word 0x52002000 8003070: 58024400 .word 0x58024400 8003074: eaf6ed7f .word 0xeaf6ed7f 8003078: 02020200 .word 0x02020200 800307c: 01ff0000 .word 0x01ff0000 8003080: 01010280 .word 0x01010280 8003084: 52004000 .word 0x52004000 08003088 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 8003088: f8df d034 ldr.w sp, [pc, #52] ; 80030c0 /* Call the clock system initialization function.*/ bl SystemInit 800308c: f7ff ff80 bl 8002f90 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8003090: 480c ldr r0, [pc, #48] ; (80030c4 ) ldr r1, =_edata 8003092: 490d ldr r1, [pc, #52] ; (80030c8 ) ldr r2, =_sidata 8003094: 4a0d ldr r2, [pc, #52] ; (80030cc ) movs r3, #0 8003096: 2300 movs r3, #0 b LoopCopyDataInit 8003098: e002 b.n 80030a0 0800309a : CopyDataInit: ldr r4, [r2, r3] 800309a: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 800309c: 50c4 str r4, [r0, r3] adds r3, r3, #4 800309e: 3304 adds r3, #4 080030a0 : LoopCopyDataInit: adds r4, r0, r3 80030a0: 18c4 adds r4, r0, r3 cmp r4, r1 80030a2: 428c cmp r4, r1 bcc CopyDataInit 80030a4: d3f9 bcc.n 800309a /* Zero fill the bss segment. */ ldr r2, =_sbss 80030a6: 4a0a ldr r2, [pc, #40] ; (80030d0 ) ldr r4, =_ebss 80030a8: 4c0a ldr r4, [pc, #40] ; (80030d4 ) movs r3, #0 80030aa: 2300 movs r3, #0 b LoopFillZerobss 80030ac: e001 b.n 80030b2 080030ae : FillZerobss: str r3, [r2] 80030ae: 6013 str r3, [r2, #0] adds r2, r2, #4 80030b0: 3204 adds r2, #4 080030b2 : LoopFillZerobss: cmp r2, r4 80030b2: 42a2 cmp r2, r4 bcc FillZerobss 80030b4: d3fb bcc.n 80030ae /* Call static constructors */ bl __libc_init_array 80030b6: f00b fa91 bl 800e5dc <__libc_init_array> /* Call the application's entry point.*/ bl main 80030ba: f7fd fa93 bl 80005e4
bx lr 80030be: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 80030c0: 20020000 .word 0x20020000 ldr r0, =_sdata 80030c4: 20000000 .word 0x20000000 ldr r1, =_edata 80030c8: 20000010 .word 0x20000010 ldr r2, =_sidata 80030cc: 0800e6c0 .word 0x0800e6c0 ldr r2, =_sbss 80030d0: 20000010 .word 0x20000010 ldr r4, =_ebss 80030d4: 20000f54 .word 0x20000f54 080030d8 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80030d8: e7fe b.n 80030d8 ... 080030dc : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80030dc: b580 push {r7, lr} 80030de: b082 sub sp, #8 80030e0: af00 add r7, sp, #0 __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */ __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */ #endif /* DUAL_CORE && CORE_CM4 */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 80030e2: 2003 movs r0, #3 80030e4: f000 f980 bl 80033e8 /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); #else common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); 80030e8: f004 f81c bl 8007124 80030ec: 4602 mov r2, r0 80030ee: 4b15 ldr r3, [pc, #84] ; (8003144 ) 80030f0: 699b ldr r3, [r3, #24] 80030f2: 0a1b lsrs r3, r3, #8 80030f4: f003 030f and.w r3, r3, #15 80030f8: 4913 ldr r1, [pc, #76] ; (8003148 ) 80030fa: 5ccb ldrb r3, [r1, r3] 80030fc: f003 031f and.w r3, r3, #31 8003100: fa22 f303 lsr.w r3, r2, r3 8003104: 607b str r3, [r7, #4] /* Update the SystemD2Clock global variable */ #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); #else SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); 8003106: 4b0f ldr r3, [pc, #60] ; (8003144 ) 8003108: 699b ldr r3, [r3, #24] 800310a: f003 030f and.w r3, r3, #15 800310e: 4a0e ldr r2, [pc, #56] ; (8003148 ) 8003110: 5cd3 ldrb r3, [r2, r3] 8003112: f003 031f and.w r3, r3, #31 8003116: 687a ldr r2, [r7, #4] 8003118: fa22 f303 lsr.w r3, r2, r3 800311c: 4a0b ldr r2, [pc, #44] ; (800314c ) 800311e: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 8003120: 4a0b ldr r2, [pc, #44] ; (8003150 ) 8003122: 687b ldr r3, [r7, #4] 8003124: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 8003126: 2000 movs r0, #0 8003128: f000 f814 bl 8003154 800312c: 4603 mov r3, r0 800312e: 2b00 cmp r3, #0 8003130: d001 beq.n 8003136 { return HAL_ERROR; 8003132: 2301 movs r3, #1 8003134: e002 b.n 800313c } /* Init the low level hardware */ HAL_MspInit(); 8003136: f7fe fbf9 bl 800192c /* Return function status */ return HAL_OK; 800313a: 2300 movs r3, #0 } 800313c: 4618 mov r0, r3 800313e: 3708 adds r7, #8 8003140: 46bd mov sp, r7 8003142: bd80 pop {r7, pc} 8003144: 58024400 .word 0x58024400 8003148: 0800e64c .word 0x0800e64c 800314c: 20000004 .word 0x20000004 8003150: 20000000 .word 0x20000000 08003154 : * implementation in user file. * @param TickPriority: Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8003154: b580 push {r7, lr} 8003156: b082 sub sp, #8 8003158: af00 add r7, sp, #0 800315a: 6078 str r0, [r7, #4] /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/ if((uint32_t)uwTickFreq == 0UL) 800315c: 4b15 ldr r3, [pc, #84] ; (80031b4 ) 800315e: 781b ldrb r3, [r3, #0] 8003160: 2b00 cmp r3, #0 8003162: d101 bne.n 8003168 { return HAL_ERROR; 8003164: 2301 movs r3, #1 8003166: e021 b.n 80031ac } /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U) 8003168: 4b13 ldr r3, [pc, #76] ; (80031b8 ) 800316a: 681a ldr r2, [r3, #0] 800316c: 4b11 ldr r3, [pc, #68] ; (80031b4 ) 800316e: 781b ldrb r3, [r3, #0] 8003170: 4619 mov r1, r3 8003172: f44f 737a mov.w r3, #1000 ; 0x3e8 8003176: fbb3 f3f1 udiv r3, r3, r1 800317a: fbb2 f3f3 udiv r3, r2, r3 800317e: 4618 mov r0, r3 8003180: f000 f965 bl 800344e 8003184: 4603 mov r3, r0 8003186: 2b00 cmp r3, #0 8003188: d001 beq.n 800318e { return HAL_ERROR; 800318a: 2301 movs r3, #1 800318c: e00e b.n 80031ac } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800318e: 687b ldr r3, [r7, #4] 8003190: 2b0f cmp r3, #15 8003192: d80a bhi.n 80031aa { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8003194: 2200 movs r2, #0 8003196: 6879 ldr r1, [r7, #4] 8003198: f04f 30ff mov.w r0, #4294967295 800319c: f000 f92f bl 80033fe uwTickPrio = TickPriority; 80031a0: 4a06 ldr r2, [pc, #24] ; (80031bc ) 80031a2: 687b ldr r3, [r7, #4] 80031a4: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 80031a6: 2300 movs r3, #0 80031a8: e000 b.n 80031ac return HAL_ERROR; 80031aa: 2301 movs r3, #1 } 80031ac: 4618 mov r0, r3 80031ae: 3708 adds r7, #8 80031b0: 46bd mov sp, r7 80031b2: bd80 pop {r7, pc} 80031b4: 2000000c .word 0x2000000c 80031b8: 20000000 .word 0x20000000 80031bc: 20000008 .word 0x20000008 080031c0 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 80031c0: b480 push {r7} 80031c2: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; 80031c4: 4b06 ldr r3, [pc, #24] ; (80031e0 ) 80031c6: 781b ldrb r3, [r3, #0] 80031c8: 461a mov r2, r3 80031ca: 4b06 ldr r3, [pc, #24] ; (80031e4 ) 80031cc: 681b ldr r3, [r3, #0] 80031ce: 4413 add r3, r2 80031d0: 4a04 ldr r2, [pc, #16] ; (80031e4 ) 80031d2: 6013 str r3, [r2, #0] } 80031d4: bf00 nop 80031d6: 46bd mov sp, r7 80031d8: f85d 7b04 ldr.w r7, [sp], #4 80031dc: 4770 bx lr 80031de: bf00 nop 80031e0: 2000000c .word 0x2000000c 80031e4: 20000ae8 .word 0x20000ae8 080031e8 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 80031e8: b480 push {r7} 80031ea: af00 add r7, sp, #0 return uwTick; 80031ec: 4b03 ldr r3, [pc, #12] ; (80031fc ) 80031ee: 681b ldr r3, [r3, #0] } 80031f0: 4618 mov r0, r3 80031f2: 46bd mov sp, r7 80031f4: f85d 7b04 ldr.w r7, [sp], #4 80031f8: 4770 bx lr 80031fa: bf00 nop 80031fc: 20000ae8 .word 0x20000ae8 08003200 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8003200: b580 push {r7, lr} 8003202: b084 sub sp, #16 8003204: af00 add r7, sp, #0 8003206: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8003208: f7ff ffee bl 80031e8 800320c: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800320e: 687b ldr r3, [r7, #4] 8003210: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8003212: 68fb ldr r3, [r7, #12] 8003214: f1b3 3fff cmp.w r3, #4294967295 8003218: d005 beq.n 8003226 { wait += (uint32_t)(uwTickFreq); 800321a: 4b0a ldr r3, [pc, #40] ; (8003244 ) 800321c: 781b ldrb r3, [r3, #0] 800321e: 461a mov r2, r3 8003220: 68fb ldr r3, [r7, #12] 8003222: 4413 add r3, r2 8003224: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 8003226: bf00 nop 8003228: f7ff ffde bl 80031e8 800322c: 4602 mov r2, r0 800322e: 68bb ldr r3, [r7, #8] 8003230: 1ad3 subs r3, r2, r3 8003232: 68fa ldr r2, [r7, #12] 8003234: 429a cmp r2, r3 8003236: d8f7 bhi.n 8003228 { } } 8003238: bf00 nop 800323a: bf00 nop 800323c: 3710 adds r7, #16 800323e: 46bd mov sp, r7 8003240: bd80 pop {r7, pc} 8003242: bf00 nop 8003244: 2000000c .word 0x2000000c 08003248 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8003248: b480 push {r7} 800324a: b085 sub sp, #20 800324c: af00 add r7, sp, #0 800324e: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8003250: 687b ldr r3, [r7, #4] 8003252: f003 0307 and.w r3, r3, #7 8003256: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8003258: 4b0b ldr r3, [pc, #44] ; (8003288 <__NVIC_SetPriorityGrouping+0x40>) 800325a: 68db ldr r3, [r3, #12] 800325c: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 800325e: 68ba ldr r2, [r7, #8] 8003260: f64f 03ff movw r3, #63743 ; 0xf8ff 8003264: 4013 ands r3, r2 8003266: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8003268: 68fb ldr r3, [r7, #12] 800326a: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800326c: 68bb ldr r3, [r7, #8] 800326e: 431a orrs r2, r3 reg_value = (reg_value | 8003270: 4b06 ldr r3, [pc, #24] ; (800328c <__NVIC_SetPriorityGrouping+0x44>) 8003272: 4313 orrs r3, r2 8003274: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8003276: 4a04 ldr r2, [pc, #16] ; (8003288 <__NVIC_SetPriorityGrouping+0x40>) 8003278: 68bb ldr r3, [r7, #8] 800327a: 60d3 str r3, [r2, #12] } 800327c: bf00 nop 800327e: 3714 adds r7, #20 8003280: 46bd mov sp, r7 8003282: f85d 7b04 ldr.w r7, [sp], #4 8003286: 4770 bx lr 8003288: e000ed00 .word 0xe000ed00 800328c: 05fa0000 .word 0x05fa0000 08003290 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8003290: b480 push {r7} 8003292: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8003294: 4b04 ldr r3, [pc, #16] ; (80032a8 <__NVIC_GetPriorityGrouping+0x18>) 8003296: 68db ldr r3, [r3, #12] 8003298: 0a1b lsrs r3, r3, #8 800329a: f003 0307 and.w r3, r3, #7 } 800329e: 4618 mov r0, r3 80032a0: 46bd mov sp, r7 80032a2: f85d 7b04 ldr.w r7, [sp], #4 80032a6: 4770 bx lr 80032a8: e000ed00 .word 0xe000ed00 080032ac <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 80032ac: b480 push {r7} 80032ae: b083 sub sp, #12 80032b0: af00 add r7, sp, #0 80032b2: 4603 mov r3, r0 80032b4: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 80032b6: f9b7 3006 ldrsh.w r3, [r7, #6] 80032ba: 2b00 cmp r3, #0 80032bc: db0b blt.n 80032d6 <__NVIC_EnableIRQ+0x2a> { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 80032be: 88fb ldrh r3, [r7, #6] 80032c0: f003 021f and.w r2, r3, #31 80032c4: 4907 ldr r1, [pc, #28] ; (80032e4 <__NVIC_EnableIRQ+0x38>) 80032c6: f9b7 3006 ldrsh.w r3, [r7, #6] 80032ca: 095b lsrs r3, r3, #5 80032cc: 2001 movs r0, #1 80032ce: fa00 f202 lsl.w r2, r0, r2 80032d2: f841 2023 str.w r2, [r1, r3, lsl #2] __COMPILER_BARRIER(); } } 80032d6: bf00 nop 80032d8: 370c adds r7, #12 80032da: 46bd mov sp, r7 80032dc: f85d 7b04 ldr.w r7, [sp], #4 80032e0: 4770 bx lr 80032e2: bf00 nop 80032e4: e000e100 .word 0xe000e100 080032e8 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 80032e8: b480 push {r7} 80032ea: b083 sub sp, #12 80032ec: af00 add r7, sp, #0 80032ee: 4603 mov r3, r0 80032f0: 6039 str r1, [r7, #0] 80032f2: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 80032f4: f9b7 3006 ldrsh.w r3, [r7, #6] 80032f8: 2b00 cmp r3, #0 80032fa: db0a blt.n 8003312 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80032fc: 683b ldr r3, [r7, #0] 80032fe: b2da uxtb r2, r3 8003300: 490c ldr r1, [pc, #48] ; (8003334 <__NVIC_SetPriority+0x4c>) 8003302: f9b7 3006 ldrsh.w r3, [r7, #6] 8003306: 0112 lsls r2, r2, #4 8003308: b2d2 uxtb r2, r2 800330a: 440b add r3, r1 800330c: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8003310: e00a b.n 8003328 <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8003312: 683b ldr r3, [r7, #0] 8003314: b2da uxtb r2, r3 8003316: 4908 ldr r1, [pc, #32] ; (8003338 <__NVIC_SetPriority+0x50>) 8003318: 88fb ldrh r3, [r7, #6] 800331a: f003 030f and.w r3, r3, #15 800331e: 3b04 subs r3, #4 8003320: 0112 lsls r2, r2, #4 8003322: b2d2 uxtb r2, r2 8003324: 440b add r3, r1 8003326: 761a strb r2, [r3, #24] } 8003328: bf00 nop 800332a: 370c adds r7, #12 800332c: 46bd mov sp, r7 800332e: f85d 7b04 ldr.w r7, [sp], #4 8003332: 4770 bx lr 8003334: e000e100 .word 0xe000e100 8003338: e000ed00 .word 0xe000ed00 0800333c : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 800333c: b480 push {r7} 800333e: b089 sub sp, #36 ; 0x24 8003340: af00 add r7, sp, #0 8003342: 60f8 str r0, [r7, #12] 8003344: 60b9 str r1, [r7, #8] 8003346: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8003348: 68fb ldr r3, [r7, #12] 800334a: f003 0307 and.w r3, r3, #7 800334e: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8003350: 69fb ldr r3, [r7, #28] 8003352: f1c3 0307 rsb r3, r3, #7 8003356: 2b04 cmp r3, #4 8003358: bf28 it cs 800335a: 2304 movcs r3, #4 800335c: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 800335e: 69fb ldr r3, [r7, #28] 8003360: 3304 adds r3, #4 8003362: 2b06 cmp r3, #6 8003364: d902 bls.n 800336c 8003366: 69fb ldr r3, [r7, #28] 8003368: 3b03 subs r3, #3 800336a: e000 b.n 800336e 800336c: 2300 movs r3, #0 800336e: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8003370: f04f 32ff mov.w r2, #4294967295 8003374: 69bb ldr r3, [r7, #24] 8003376: fa02 f303 lsl.w r3, r2, r3 800337a: 43da mvns r2, r3 800337c: 68bb ldr r3, [r7, #8] 800337e: 401a ands r2, r3 8003380: 697b ldr r3, [r7, #20] 8003382: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8003384: f04f 31ff mov.w r1, #4294967295 8003388: 697b ldr r3, [r7, #20] 800338a: fa01 f303 lsl.w r3, r1, r3 800338e: 43d9 mvns r1, r3 8003390: 687b ldr r3, [r7, #4] 8003392: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8003394: 4313 orrs r3, r2 ); } 8003396: 4618 mov r0, r3 8003398: 3724 adds r7, #36 ; 0x24 800339a: 46bd mov sp, r7 800339c: f85d 7b04 ldr.w r7, [sp], #4 80033a0: 4770 bx lr ... 080033a4 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 80033a4: b580 push {r7, lr} 80033a6: b082 sub sp, #8 80033a8: af00 add r7, sp, #0 80033aa: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 80033ac: 687b ldr r3, [r7, #4] 80033ae: 3b01 subs r3, #1 80033b0: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 80033b4: d301 bcc.n 80033ba { return (1UL); /* Reload value impossible */ 80033b6: 2301 movs r3, #1 80033b8: e00f b.n 80033da } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 80033ba: 4a0a ldr r2, [pc, #40] ; (80033e4 ) 80033bc: 687b ldr r3, [r7, #4] 80033be: 3b01 subs r3, #1 80033c0: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 80033c2: 210f movs r1, #15 80033c4: f04f 30ff mov.w r0, #4294967295 80033c8: f7ff ff8e bl 80032e8 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 80033cc: 4b05 ldr r3, [pc, #20] ; (80033e4 ) 80033ce: 2200 movs r2, #0 80033d0: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 80033d2: 4b04 ldr r3, [pc, #16] ; (80033e4 ) 80033d4: 2207 movs r2, #7 80033d6: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 80033d8: 2300 movs r3, #0 } 80033da: 4618 mov r0, r3 80033dc: 3708 adds r7, #8 80033de: 46bd mov sp, r7 80033e0: bd80 pop {r7, pc} 80033e2: bf00 nop 80033e4: e000e010 .word 0xe000e010 080033e8 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80033e8: b580 push {r7, lr} 80033ea: b082 sub sp, #8 80033ec: af00 add r7, sp, #0 80033ee: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 80033f0: 6878 ldr r0, [r7, #4] 80033f2: f7ff ff29 bl 8003248 <__NVIC_SetPriorityGrouping> } 80033f6: bf00 nop 80033f8: 3708 adds r7, #8 80033fa: 46bd mov sp, r7 80033fc: bd80 pop {r7, pc} 080033fe : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 80033fe: b580 push {r7, lr} 8003400: b086 sub sp, #24 8003402: af00 add r7, sp, #0 8003404: 4603 mov r3, r0 8003406: 60b9 str r1, [r7, #8] 8003408: 607a str r2, [r7, #4] 800340a: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 800340c: f7ff ff40 bl 8003290 <__NVIC_GetPriorityGrouping> 8003410: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8003412: 687a ldr r2, [r7, #4] 8003414: 68b9 ldr r1, [r7, #8] 8003416: 6978 ldr r0, [r7, #20] 8003418: f7ff ff90 bl 800333c 800341c: 4602 mov r2, r0 800341e: f9b7 300e ldrsh.w r3, [r7, #14] 8003422: 4611 mov r1, r2 8003424: 4618 mov r0, r3 8003426: f7ff ff5f bl 80032e8 <__NVIC_SetPriority> } 800342a: bf00 nop 800342c: 3718 adds r7, #24 800342e: 46bd mov sp, r7 8003430: bd80 pop {r7, pc} 08003432 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8003432: b580 push {r7, lr} 8003434: b082 sub sp, #8 8003436: af00 add r7, sp, #0 8003438: 4603 mov r3, r0 800343a: 80fb strh r3, [r7, #6] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 800343c: f9b7 3006 ldrsh.w r3, [r7, #6] 8003440: 4618 mov r0, r3 8003442: f7ff ff33 bl 80032ac <__NVIC_EnableIRQ> } 8003446: bf00 nop 8003448: 3708 adds r7, #8 800344a: 46bd mov sp, r7 800344c: bd80 pop {r7, pc} 0800344e : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 800344e: b580 push {r7, lr} 8003450: b082 sub sp, #8 8003452: af00 add r7, sp, #0 8003454: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8003456: 6878 ldr r0, [r7, #4] 8003458: f7ff ffa4 bl 80033a4 800345c: 4603 mov r3, r0 } 800345e: 4618 mov r0, r3 8003460: 3708 adds r7, #8 8003462: 46bd mov sp, r7 8003464: bd80 pop {r7, pc} ... 08003468 : * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 8003468: b580 push {r7, lr} 800346a: b086 sub sp, #24 800346c: af00 add r7, sp, #0 800346e: 6078 str r0, [r7, #4] uint32_t registerValue; uint32_t tickstart = HAL_GetTick(); 8003470: f7ff feba bl 80031e8 8003474: 6138 str r0, [r7, #16] DMA_Base_Registers *regs_dma; BDMA_Base_Registers *regs_bdma; /* Check the DMA peripheral handle */ if(hdma == NULL) 8003476: 687b ldr r3, [r7, #4] 8003478: 2b00 cmp r3, #0 800347a: d101 bne.n 8003480 { return HAL_ERROR; 800347c: 2301 movs r3, #1 800347e: e37f b.n 8003b80 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8003480: 687b ldr r3, [r7, #4] 8003482: 681b ldr r3, [r3, #0] 8003484: 4a66 ldr r2, [pc, #408] ; (8003620 ) 8003486: 4293 cmp r3, r2 8003488: d04a beq.n 8003520 800348a: 687b ldr r3, [r7, #4] 800348c: 681b ldr r3, [r3, #0] 800348e: 4a65 ldr r2, [pc, #404] ; (8003624 ) 8003490: 4293 cmp r3, r2 8003492: d045 beq.n 8003520 8003494: 687b ldr r3, [r7, #4] 8003496: 681b ldr r3, [r3, #0] 8003498: 4a63 ldr r2, [pc, #396] ; (8003628 ) 800349a: 4293 cmp r3, r2 800349c: d040 beq.n 8003520 800349e: 687b ldr r3, [r7, #4] 80034a0: 681b ldr r3, [r3, #0] 80034a2: 4a62 ldr r2, [pc, #392] ; (800362c ) 80034a4: 4293 cmp r3, r2 80034a6: d03b beq.n 8003520 80034a8: 687b ldr r3, [r7, #4] 80034aa: 681b ldr r3, [r3, #0] 80034ac: 4a60 ldr r2, [pc, #384] ; (8003630 ) 80034ae: 4293 cmp r3, r2 80034b0: d036 beq.n 8003520 80034b2: 687b ldr r3, [r7, #4] 80034b4: 681b ldr r3, [r3, #0] 80034b6: 4a5f ldr r2, [pc, #380] ; (8003634 ) 80034b8: 4293 cmp r3, r2 80034ba: d031 beq.n 8003520 80034bc: 687b ldr r3, [r7, #4] 80034be: 681b ldr r3, [r3, #0] 80034c0: 4a5d ldr r2, [pc, #372] ; (8003638 ) 80034c2: 4293 cmp r3, r2 80034c4: d02c beq.n 8003520 80034c6: 687b ldr r3, [r7, #4] 80034c8: 681b ldr r3, [r3, #0] 80034ca: 4a5c ldr r2, [pc, #368] ; (800363c ) 80034cc: 4293 cmp r3, r2 80034ce: d027 beq.n 8003520 80034d0: 687b ldr r3, [r7, #4] 80034d2: 681b ldr r3, [r3, #0] 80034d4: 4a5a ldr r2, [pc, #360] ; (8003640 ) 80034d6: 4293 cmp r3, r2 80034d8: d022 beq.n 8003520 80034da: 687b ldr r3, [r7, #4] 80034dc: 681b ldr r3, [r3, #0] 80034de: 4a59 ldr r2, [pc, #356] ; (8003644 ) 80034e0: 4293 cmp r3, r2 80034e2: d01d beq.n 8003520 80034e4: 687b ldr r3, [r7, #4] 80034e6: 681b ldr r3, [r3, #0] 80034e8: 4a57 ldr r2, [pc, #348] ; (8003648 ) 80034ea: 4293 cmp r3, r2 80034ec: d018 beq.n 8003520 80034ee: 687b ldr r3, [r7, #4] 80034f0: 681b ldr r3, [r3, #0] 80034f2: 4a56 ldr r2, [pc, #344] ; (800364c ) 80034f4: 4293 cmp r3, r2 80034f6: d013 beq.n 8003520 80034f8: 687b ldr r3, [r7, #4] 80034fa: 681b ldr r3, [r3, #0] 80034fc: 4a54 ldr r2, [pc, #336] ; (8003650 ) 80034fe: 4293 cmp r3, r2 8003500: d00e beq.n 8003520 8003502: 687b ldr r3, [r7, #4] 8003504: 681b ldr r3, [r3, #0] 8003506: 4a53 ldr r2, [pc, #332] ; (8003654 ) 8003508: 4293 cmp r3, r2 800350a: d009 beq.n 8003520 800350c: 687b ldr r3, [r7, #4] 800350e: 681b ldr r3, [r3, #0] 8003510: 4a51 ldr r2, [pc, #324] ; (8003658 ) 8003512: 4293 cmp r3, r2 8003514: d004 beq.n 8003520 8003516: 687b ldr r3, [r7, #4] 8003518: 681b ldr r3, [r3, #0] 800351a: 4a50 ldr r2, [pc, #320] ; (800365c ) 800351c: 4293 cmp r3, r2 800351e: d101 bne.n 8003524 8003520: 2301 movs r3, #1 8003522: e000 b.n 8003526 8003524: 2300 movs r3, #0 8003526: 2b00 cmp r3, #0 8003528: f000 813c beq.w 80037a4 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 800352c: 687b ldr r3, [r7, #4] 800352e: 2202 movs r2, #2 8003530: f883 2035 strb.w r2, [r3, #53] ; 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 8003534: 687b ldr r3, [r7, #4] 8003536: 2200 movs r2, #0 8003538: f883 2034 strb.w r2, [r3, #52] ; 0x34 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 800353c: 687b ldr r3, [r7, #4] 800353e: 681b ldr r3, [r3, #0] 8003540: 4a37 ldr r2, [pc, #220] ; (8003620 ) 8003542: 4293 cmp r3, r2 8003544: d04a beq.n 80035dc 8003546: 687b ldr r3, [r7, #4] 8003548: 681b ldr r3, [r3, #0] 800354a: 4a36 ldr r2, [pc, #216] ; (8003624 ) 800354c: 4293 cmp r3, r2 800354e: d045 beq.n 80035dc 8003550: 687b ldr r3, [r7, #4] 8003552: 681b ldr r3, [r3, #0] 8003554: 4a34 ldr r2, [pc, #208] ; (8003628 ) 8003556: 4293 cmp r3, r2 8003558: d040 beq.n 80035dc 800355a: 687b ldr r3, [r7, #4] 800355c: 681b ldr r3, [r3, #0] 800355e: 4a33 ldr r2, [pc, #204] ; (800362c ) 8003560: 4293 cmp r3, r2 8003562: d03b beq.n 80035dc 8003564: 687b ldr r3, [r7, #4] 8003566: 681b ldr r3, [r3, #0] 8003568: 4a31 ldr r2, [pc, #196] ; (8003630 ) 800356a: 4293 cmp r3, r2 800356c: d036 beq.n 80035dc 800356e: 687b ldr r3, [r7, #4] 8003570: 681b ldr r3, [r3, #0] 8003572: 4a30 ldr r2, [pc, #192] ; (8003634 ) 8003574: 4293 cmp r3, r2 8003576: d031 beq.n 80035dc 8003578: 687b ldr r3, [r7, #4] 800357a: 681b ldr r3, [r3, #0] 800357c: 4a2e ldr r2, [pc, #184] ; (8003638 ) 800357e: 4293 cmp r3, r2 8003580: d02c beq.n 80035dc 8003582: 687b ldr r3, [r7, #4] 8003584: 681b ldr r3, [r3, #0] 8003586: 4a2d ldr r2, [pc, #180] ; (800363c ) 8003588: 4293 cmp r3, r2 800358a: d027 beq.n 80035dc 800358c: 687b ldr r3, [r7, #4] 800358e: 681b ldr r3, [r3, #0] 8003590: 4a2b ldr r2, [pc, #172] ; (8003640 ) 8003592: 4293 cmp r3, r2 8003594: d022 beq.n 80035dc 8003596: 687b ldr r3, [r7, #4] 8003598: 681b ldr r3, [r3, #0] 800359a: 4a2a ldr r2, [pc, #168] ; (8003644 ) 800359c: 4293 cmp r3, r2 800359e: d01d beq.n 80035dc 80035a0: 687b ldr r3, [r7, #4] 80035a2: 681b ldr r3, [r3, #0] 80035a4: 4a28 ldr r2, [pc, #160] ; (8003648 ) 80035a6: 4293 cmp r3, r2 80035a8: d018 beq.n 80035dc 80035aa: 687b ldr r3, [r7, #4] 80035ac: 681b ldr r3, [r3, #0] 80035ae: 4a27 ldr r2, [pc, #156] ; (800364c ) 80035b0: 4293 cmp r3, r2 80035b2: d013 beq.n 80035dc 80035b4: 687b ldr r3, [r7, #4] 80035b6: 681b ldr r3, [r3, #0] 80035b8: 4a25 ldr r2, [pc, #148] ; (8003650 ) 80035ba: 4293 cmp r3, r2 80035bc: d00e beq.n 80035dc 80035be: 687b ldr r3, [r7, #4] 80035c0: 681b ldr r3, [r3, #0] 80035c2: 4a24 ldr r2, [pc, #144] ; (8003654 ) 80035c4: 4293 cmp r3, r2 80035c6: d009 beq.n 80035dc 80035c8: 687b ldr r3, [r7, #4] 80035ca: 681b ldr r3, [r3, #0] 80035cc: 4a22 ldr r2, [pc, #136] ; (8003658 ) 80035ce: 4293 cmp r3, r2 80035d0: d004 beq.n 80035dc 80035d2: 687b ldr r3, [r7, #4] 80035d4: 681b ldr r3, [r3, #0] 80035d6: 4a21 ldr r2, [pc, #132] ; (800365c ) 80035d8: 4293 cmp r3, r2 80035da: d108 bne.n 80035ee 80035dc: 687b ldr r3, [r7, #4] 80035de: 681b ldr r3, [r3, #0] 80035e0: 681a ldr r2, [r3, #0] 80035e2: 687b ldr r3, [r7, #4] 80035e4: 681b ldr r3, [r3, #0] 80035e6: f022 0201 bic.w r2, r2, #1 80035ea: 601a str r2, [r3, #0] 80035ec: e007 b.n 80035fe 80035ee: 687b ldr r3, [r7, #4] 80035f0: 681b ldr r3, [r3, #0] 80035f2: 681a ldr r2, [r3, #0] 80035f4: 687b ldr r3, [r7, #4] 80035f6: 681b ldr r3, [r3, #0] 80035f8: f022 0201 bic.w r2, r2, #1 80035fc: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 80035fe: e02f b.n 8003660 { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 8003600: f7ff fdf2 bl 80031e8 8003604: 4602 mov r2, r0 8003606: 693b ldr r3, [r7, #16] 8003608: 1ad3 subs r3, r2, r3 800360a: 2b05 cmp r3, #5 800360c: d928 bls.n 8003660 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 800360e: 687b ldr r3, [r7, #4] 8003610: 2220 movs r2, #32 8003612: 655a str r2, [r3, #84] ; 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_ERROR; 8003614: 687b ldr r3, [r7, #4] 8003616: 2203 movs r2, #3 8003618: f883 2035 strb.w r2, [r3, #53] ; 0x35 return HAL_ERROR; 800361c: 2301 movs r3, #1 800361e: e2af b.n 8003b80 8003620: 40020010 .word 0x40020010 8003624: 40020028 .word 0x40020028 8003628: 40020040 .word 0x40020040 800362c: 40020058 .word 0x40020058 8003630: 40020070 .word 0x40020070 8003634: 40020088 .word 0x40020088 8003638: 400200a0 .word 0x400200a0 800363c: 400200b8 .word 0x400200b8 8003640: 40020410 .word 0x40020410 8003644: 40020428 .word 0x40020428 8003648: 40020440 .word 0x40020440 800364c: 40020458 .word 0x40020458 8003650: 40020470 .word 0x40020470 8003654: 40020488 .word 0x40020488 8003658: 400204a0 .word 0x400204a0 800365c: 400204b8 .word 0x400204b8 while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 8003660: 687b ldr r3, [r7, #4] 8003662: 681b ldr r3, [r3, #0] 8003664: 681b ldr r3, [r3, #0] 8003666: f003 0301 and.w r3, r3, #1 800366a: 2b00 cmp r3, #0 800366c: d1c8 bne.n 8003600 } } /* Get the CR register value */ registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->CR; 800366e: 687b ldr r3, [r7, #4] 8003670: 681b ldr r3, [r3, #0] 8003672: 681b ldr r3, [r3, #0] 8003674: 617b str r3, [r7, #20] /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ 8003676: 697a ldr r2, [r7, #20] 8003678: 4b73 ldr r3, [pc, #460] ; (8003848 ) 800367a: 4013 ands r3, r2 800367c: 617b str r3, [r7, #20] DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); /* Prepare the DMA Stream configuration */ registerValue |= hdma->Init.Direction | 800367e: 687b ldr r3, [r7, #4] 8003680: 689a ldr r2, [r3, #8] hdma->Init.PeriphInc | hdma->Init.MemInc | 8003682: 687b ldr r3, [r7, #4] 8003684: 68db ldr r3, [r3, #12] registerValue |= hdma->Init.Direction | 8003686: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 8003688: 687b ldr r3, [r7, #4] 800368a: 691b ldr r3, [r3, #16] 800368c: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800368e: 687b ldr r3, [r7, #4] 8003690: 695b ldr r3, [r3, #20] hdma->Init.PeriphInc | hdma->Init.MemInc | 8003692: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8003694: 687b ldr r3, [r7, #4] 8003696: 699b ldr r3, [r3, #24] 8003698: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 800369a: 687b ldr r3, [r7, #4] 800369c: 69db ldr r3, [r3, #28] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800369e: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 80036a0: 687b ldr r3, [r7, #4] 80036a2: 6a1b ldr r3, [r3, #32] 80036a4: 4313 orrs r3, r2 registerValue |= hdma->Init.Direction | 80036a6: 697a ldr r2, [r7, #20] 80036a8: 4313 orrs r3, r2 80036aa: 617b str r3, [r7, #20] /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 80036ac: 687b ldr r3, [r7, #4] 80036ae: 6a5b ldr r3, [r3, #36] ; 0x24 80036b0: 2b04 cmp r3, #4 80036b2: d107 bne.n 80036c4 { /* Get memory burst and peripheral burst */ registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; 80036b4: 687b ldr r3, [r7, #4] 80036b6: 6ada ldr r2, [r3, #44] ; 0x2c 80036b8: 687b ldr r3, [r7, #4] 80036ba: 6b1b ldr r3, [r3, #48] ; 0x30 80036bc: 4313 orrs r3, r2 80036be: 697a ldr r2, [r7, #20] 80036c0: 4313 orrs r3, r2 80036c2: 617b str r3, [r7, #20] lock when transferring data to/from USART/UART */ #if (STM32H7_DEV_ID == 0x450UL) if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U) { #endif /* STM32H7_DEV_ID == 0x450UL */ if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U) 80036c4: 687b ldr r3, [r7, #4] 80036c6: 685b ldr r3, [r3, #4] 80036c8: 2b28 cmp r3, #40 ; 0x28 80036ca: d903 bls.n 80036d4 80036cc: 687b ldr r3, [r7, #4] 80036ce: 685b ldr r3, [r3, #4] 80036d0: 2b2e cmp r3, #46 ; 0x2e 80036d2: d91f bls.n 8003714 80036d4: 687b ldr r3, [r7, #4] 80036d6: 685b ldr r3, [r3, #4] 80036d8: 2b3e cmp r3, #62 ; 0x3e 80036da: d903 bls.n 80036e4 80036dc: 687b ldr r3, [r7, #4] 80036de: 685b ldr r3, [r3, #4] 80036e0: 2b42 cmp r3, #66 ; 0x42 80036e2: d917 bls.n 8003714 80036e4: 687b ldr r3, [r7, #4] 80036e6: 685b ldr r3, [r3, #4] 80036e8: 2b46 cmp r3, #70 ; 0x46 80036ea: d903 bls.n 80036f4 80036ec: 687b ldr r3, [r7, #4] 80036ee: 685b ldr r3, [r3, #4] 80036f0: 2b48 cmp r3, #72 ; 0x48 80036f2: d90f bls.n 8003714 80036f4: 687b ldr r3, [r7, #4] 80036f6: 685b ldr r3, [r3, #4] 80036f8: 2b4e cmp r3, #78 ; 0x4e 80036fa: d903 bls.n 8003704 80036fc: 687b ldr r3, [r7, #4] 80036fe: 685b ldr r3, [r3, #4] 8003700: 2b52 cmp r3, #82 ; 0x52 8003702: d907 bls.n 8003714 8003704: 687b ldr r3, [r7, #4] 8003706: 685b ldr r3, [r3, #4] 8003708: 2b73 cmp r3, #115 ; 0x73 800370a: d905 bls.n 8003718 800370c: 687b ldr r3, [r7, #4] 800370e: 685b ldr r3, [r3, #4] 8003710: 2b77 cmp r3, #119 ; 0x77 8003712: d801 bhi.n 8003718 8003714: 2301 movs r3, #1 8003716: e000 b.n 800371a 8003718: 2300 movs r3, #0 800371a: 2b00 cmp r3, #0 800371c: d003 beq.n 8003726 { registerValue |= DMA_SxCR_TRBUFF; 800371e: 697b ldr r3, [r7, #20] 8003720: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 8003724: 617b str r3, [r7, #20] #if (STM32H7_DEV_ID == 0x450UL) } #endif /* STM32H7_DEV_ID == 0x450UL */ /* Write to DMA Stream CR register */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue; 8003726: 687b ldr r3, [r7, #4] 8003728: 681b ldr r3, [r3, #0] 800372a: 697a ldr r2, [r7, #20] 800372c: 601a str r2, [r3, #0] /* Get the FCR register value */ registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR; 800372e: 687b ldr r3, [r7, #4] 8003730: 681b ldr r3, [r3, #0] 8003732: 695b ldr r3, [r3, #20] 8003734: 617b str r3, [r7, #20] /* Clear Direct mode and FIFO threshold bits */ registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); 8003736: 697b ldr r3, [r7, #20] 8003738: f023 0307 bic.w r3, r3, #7 800373c: 617b str r3, [r7, #20] /* Prepare the DMA Stream FIFO configuration */ registerValue |= hdma->Init.FIFOMode; 800373e: 687b ldr r3, [r7, #4] 8003740: 6a5b ldr r3, [r3, #36] ; 0x24 8003742: 697a ldr r2, [r7, #20] 8003744: 4313 orrs r3, r2 8003746: 617b str r3, [r7, #20] /* the FIFO threshold is not used when the FIFO mode is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8003748: 687b ldr r3, [r7, #4] 800374a: 6a5b ldr r3, [r3, #36] ; 0x24 800374c: 2b04 cmp r3, #4 800374e: d117 bne.n 8003780 { /* Get the FIFO threshold */ registerValue |= hdma->Init.FIFOThreshold; 8003750: 687b ldr r3, [r7, #4] 8003752: 6a9b ldr r3, [r3, #40] ; 0x28 8003754: 697a ldr r2, [r7, #20] 8003756: 4313 orrs r3, r2 8003758: 617b str r3, [r7, #20] /* Check compatibility between FIFO threshold level and size of the memory burst */ /* for INCR4, INCR8, INCR16 */ if(hdma->Init.MemBurst != DMA_MBURST_SINGLE) 800375a: 687b ldr r3, [r7, #4] 800375c: 6adb ldr r3, [r3, #44] ; 0x2c 800375e: 2b00 cmp r3, #0 8003760: d00e beq.n 8003780 { if (DMA_CheckFifoParam(hdma) != HAL_OK) 8003762: 6878 ldr r0, [r7, #4] 8003764: f001 fa24 bl 8004bb0 8003768: 4603 mov r3, r0 800376a: 2b00 cmp r3, #0 800376c: d008 beq.n 8003780 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 800376e: 687b ldr r3, [r7, #4] 8003770: 2240 movs r2, #64 ; 0x40 8003772: 655a str r2, [r3, #84] ; 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8003774: 687b ldr r3, [r7, #4] 8003776: 2201 movs r2, #1 8003778: f883 2035 strb.w r2, [r3, #53] ; 0x35 return HAL_ERROR; 800377c: 2301 movs r3, #1 800377e: e1ff b.n 8003b80 } } } /* Write to DMA Stream FCR */ ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = registerValue; 8003780: 687b ldr r3, [r7, #4] 8003782: 681b ldr r3, [r3, #0] 8003784: 697a ldr r2, [r7, #20] 8003786: 615a str r2, [r3, #20] /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 8003788: 6878 ldr r0, [r7, #4] 800378a: f001 f95f bl 8004a4c 800378e: 4603 mov r3, r0 8003790: 60bb str r3, [r7, #8] /* Clear all interrupt flags */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 8003792: 687b ldr r3, [r7, #4] 8003794: 6ddb ldr r3, [r3, #92] ; 0x5c 8003796: f003 031f and.w r3, r3, #31 800379a: 223f movs r2, #63 ; 0x3f 800379c: 409a lsls r2, r3 800379e: 68bb ldr r3, [r7, #8] 80037a0: 609a str r2, [r3, #8] 80037a2: e0fe b.n 80039a2 } else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 80037a4: 687b ldr r3, [r7, #4] 80037a6: 681b ldr r3, [r3, #0] 80037a8: 4a28 ldr r2, [pc, #160] ; (800384c ) 80037aa: 4293 cmp r3, r2 80037ac: d04a beq.n 8003844 80037ae: 687b ldr r3, [r7, #4] 80037b0: 681b ldr r3, [r3, #0] 80037b2: 4a27 ldr r2, [pc, #156] ; (8003850 ) 80037b4: 4293 cmp r3, r2 80037b6: d045 beq.n 8003844 80037b8: 687b ldr r3, [r7, #4] 80037ba: 681b ldr r3, [r3, #0] 80037bc: 4a25 ldr r2, [pc, #148] ; (8003854 ) 80037be: 4293 cmp r3, r2 80037c0: d040 beq.n 8003844 80037c2: 687b ldr r3, [r7, #4] 80037c4: 681b ldr r3, [r3, #0] 80037c6: 4a24 ldr r2, [pc, #144] ; (8003858 ) 80037c8: 4293 cmp r3, r2 80037ca: d03b beq.n 8003844 80037cc: 687b ldr r3, [r7, #4] 80037ce: 681b ldr r3, [r3, #0] 80037d0: 4a22 ldr r2, [pc, #136] ; (800385c ) 80037d2: 4293 cmp r3, r2 80037d4: d036 beq.n 8003844 80037d6: 687b ldr r3, [r7, #4] 80037d8: 681b ldr r3, [r3, #0] 80037da: 4a21 ldr r2, [pc, #132] ; (8003860 ) 80037dc: 4293 cmp r3, r2 80037de: d031 beq.n 8003844 80037e0: 687b ldr r3, [r7, #4] 80037e2: 681b ldr r3, [r3, #0] 80037e4: 4a1f ldr r2, [pc, #124] ; (8003864 ) 80037e6: 4293 cmp r3, r2 80037e8: d02c beq.n 8003844 80037ea: 687b ldr r3, [r7, #4] 80037ec: 681b ldr r3, [r3, #0] 80037ee: 4a1e ldr r2, [pc, #120] ; (8003868 ) 80037f0: 4293 cmp r3, r2 80037f2: d027 beq.n 8003844 80037f4: 687b ldr r3, [r7, #4] 80037f6: 681b ldr r3, [r3, #0] 80037f8: 4a1c ldr r2, [pc, #112] ; (800386c ) 80037fa: 4293 cmp r3, r2 80037fc: d022 beq.n 8003844 80037fe: 687b ldr r3, [r7, #4] 8003800: 681b ldr r3, [r3, #0] 8003802: 4a1b ldr r2, [pc, #108] ; (8003870 ) 8003804: 4293 cmp r3, r2 8003806: d01d beq.n 8003844 8003808: 687b ldr r3, [r7, #4] 800380a: 681b ldr r3, [r3, #0] 800380c: 4a19 ldr r2, [pc, #100] ; (8003874 ) 800380e: 4293 cmp r3, r2 8003810: d018 beq.n 8003844 8003812: 687b ldr r3, [r7, #4] 8003814: 681b ldr r3, [r3, #0] 8003816: 4a18 ldr r2, [pc, #96] ; (8003878 ) 8003818: 4293 cmp r3, r2 800381a: d013 beq.n 8003844 800381c: 687b ldr r3, [r7, #4] 800381e: 681b ldr r3, [r3, #0] 8003820: 4a16 ldr r2, [pc, #88] ; (800387c ) 8003822: 4293 cmp r3, r2 8003824: d00e beq.n 8003844 8003826: 687b ldr r3, [r7, #4] 8003828: 681b ldr r3, [r3, #0] 800382a: 4a15 ldr r2, [pc, #84] ; (8003880 ) 800382c: 4293 cmp r3, r2 800382e: d009 beq.n 8003844 8003830: 687b ldr r3, [r7, #4] 8003832: 681b ldr r3, [r3, #0] 8003834: 4a13 ldr r2, [pc, #76] ; (8003884 ) 8003836: 4293 cmp r3, r2 8003838: d004 beq.n 8003844 800383a: 687b ldr r3, [r7, #4] 800383c: 681b ldr r3, [r3, #0] 800383e: 4a12 ldr r2, [pc, #72] ; (8003888 ) 8003840: 4293 cmp r3, r2 8003842: d123 bne.n 800388c 8003844: 2301 movs r3, #1 8003846: e022 b.n 800388e 8003848: fe10803f .word 0xfe10803f 800384c: 48022c08 .word 0x48022c08 8003850: 48022c1c .word 0x48022c1c 8003854: 48022c30 .word 0x48022c30 8003858: 48022c44 .word 0x48022c44 800385c: 48022c58 .word 0x48022c58 8003860: 48022c6c .word 0x48022c6c 8003864: 48022c80 .word 0x48022c80 8003868: 48022c94 .word 0x48022c94 800386c: 58025408 .word 0x58025408 8003870: 5802541c .word 0x5802541c 8003874: 58025430 .word 0x58025430 8003878: 58025444 .word 0x58025444 800387c: 58025458 .word 0x58025458 8003880: 5802546c .word 0x5802546c 8003884: 58025480 .word 0x58025480 8003888: 58025494 .word 0x58025494 800388c: 2300 movs r3, #0 800388e: 2b00 cmp r3, #0 8003890: d07e beq.n 8003990 { if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 8003892: 687b ldr r3, [r7, #4] 8003894: 681b ldr r3, [r3, #0] 8003896: 4a80 ldr r2, [pc, #512] ; (8003a98 ) 8003898: 4293 cmp r3, r2 800389a: d021 beq.n 80038e0 800389c: 687b ldr r3, [r7, #4] 800389e: 681b ldr r3, [r3, #0] 80038a0: 4a7e ldr r2, [pc, #504] ; (8003a9c ) 80038a2: 4293 cmp r3, r2 80038a4: d01c beq.n 80038e0 80038a6: 687b ldr r3, [r7, #4] 80038a8: 681b ldr r3, [r3, #0] 80038aa: 4a7d ldr r2, [pc, #500] ; (8003aa0 ) 80038ac: 4293 cmp r3, r2 80038ae: d017 beq.n 80038e0 80038b0: 687b ldr r3, [r7, #4] 80038b2: 681b ldr r3, [r3, #0] 80038b4: 4a7b ldr r2, [pc, #492] ; (8003aa4 ) 80038b6: 4293 cmp r3, r2 80038b8: d012 beq.n 80038e0 80038ba: 687b ldr r3, [r7, #4] 80038bc: 681b ldr r3, [r3, #0] 80038be: 4a7a ldr r2, [pc, #488] ; (8003aa8 ) 80038c0: 4293 cmp r3, r2 80038c2: d00d beq.n 80038e0 80038c4: 687b ldr r3, [r7, #4] 80038c6: 681b ldr r3, [r3, #0] 80038c8: 4a78 ldr r2, [pc, #480] ; (8003aac ) 80038ca: 4293 cmp r3, r2 80038cc: d008 beq.n 80038e0 80038ce: 687b ldr r3, [r7, #4] 80038d0: 681b ldr r3, [r3, #0] 80038d2: 4a77 ldr r2, [pc, #476] ; (8003ab0 ) 80038d4: 4293 cmp r3, r2 80038d6: d003 beq.n 80038e0 80038d8: 687b ldr r3, [r7, #4] 80038da: 681b ldr r3, [r3, #0] 80038dc: 4a75 ldr r2, [pc, #468] ; (8003ab4 ) 80038de: 4293 cmp r3, r2 80038e0: bf00 nop /* Check the request parameter */ assert_param(IS_BDMA_REQUEST(hdma->Init.Request)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 80038e2: 687b ldr r3, [r7, #4] 80038e4: 2202 movs r2, #2 80038e6: f883 2035 strb.w r2, [r3, #53] ; 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 80038ea: 687b ldr r3, [r7, #4] 80038ec: 2200 movs r2, #0 80038ee: f883 2034 strb.w r2, [r3, #52] ; 0x34 /* Get the CR register value */ registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR; 80038f2: 687b ldr r3, [r7, #4] 80038f4: 681b ldr r3, [r3, #0] 80038f6: 681b ldr r3, [r3, #0] 80038f8: 617b str r3, [r7, #20] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, MEM2MEM, DBM and CT bits */ registerValue &= ((uint32_t)~(BDMA_CCR_PL | BDMA_CCR_MSIZE | BDMA_CCR_PSIZE | \ 80038fa: 697a ldr r2, [r7, #20] 80038fc: 4b6e ldr r3, [pc, #440] ; (8003ab8 ) 80038fe: 4013 ands r3, r2 8003900: 617b str r3, [r7, #20] BDMA_CCR_MINC | BDMA_CCR_PINC | BDMA_CCR_CIRC | \ BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_DBM | \ BDMA_CCR_CT)); /* Prepare the DMA Channel configuration */ registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 8003902: 687b ldr r3, [r7, #4] 8003904: 689b ldr r3, [r3, #8] 8003906: 2b40 cmp r3, #64 ; 0x40 8003908: d008 beq.n 800391c 800390a: 687b ldr r3, [r7, #4] 800390c: 689b ldr r3, [r3, #8] 800390e: 2b80 cmp r3, #128 ; 0x80 8003910: d102 bne.n 8003918 8003912: f44f 4380 mov.w r3, #16384 ; 0x4000 8003916: e002 b.n 800391e 8003918: 2300 movs r3, #0 800391a: e000 b.n 800391e 800391c: 2310 movs r3, #16 DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | 800391e: 687a ldr r2, [r7, #4] 8003920: 68d2 ldr r2, [r2, #12] 8003922: 08d2 lsrs r2, r2, #3 registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 8003924: 431a orrs r2, r3 DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | 8003926: 687b ldr r3, [r7, #4] 8003928: 691b ldr r3, [r3, #16] 800392a: 08db lsrs r3, r3, #3 DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | 800392c: 431a orrs r2, r3 DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | 800392e: 687b ldr r3, [r7, #4] 8003930: 695b ldr r3, [r3, #20] 8003932: 08db lsrs r3, r3, #3 DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | 8003934: 431a orrs r2, r3 DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | 8003936: 687b ldr r3, [r7, #4] 8003938: 699b ldr r3, [r3, #24] 800393a: 08db lsrs r3, r3, #3 DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | 800393c: 431a orrs r2, r3 DMA_TO_BDMA_MODE(hdma->Init.Mode) | 800393e: 687b ldr r3, [r7, #4] 8003940: 69db ldr r3, [r3, #28] 8003942: 08db lsrs r3, r3, #3 DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | 8003944: 431a orrs r2, r3 DMA_TO_BDMA_PRIORITY(hdma->Init.Priority); 8003946: 687b ldr r3, [r7, #4] 8003948: 6a1b ldr r3, [r3, #32] 800394a: 091b lsrs r3, r3, #4 DMA_TO_BDMA_MODE(hdma->Init.Mode) | 800394c: 4313 orrs r3, r2 registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 800394e: 697a ldr r2, [r7, #20] 8003950: 4313 orrs r3, r2 8003952: 617b str r3, [r7, #20] /* Write to DMA Channel CR register */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue; 8003954: 687b ldr r3, [r7, #4] 8003956: 681b ldr r3, [r3, #0] 8003958: 697a ldr r2, [r7, #20] 800395a: 601a str r2, [r3, #0] /* calculation of the channel index */ hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U; 800395c: 687b ldr r3, [r7, #4] 800395e: 681b ldr r3, [r3, #0] 8003960: 461a mov r2, r3 8003962: 4b56 ldr r3, [pc, #344] ; (8003abc ) 8003964: 4413 add r3, r2 8003966: 4a56 ldr r2, [pc, #344] ; (8003ac0 ) 8003968: fba2 2303 umull r2, r3, r2, r3 800396c: 091b lsrs r3, r3, #4 800396e: 009a lsls r2, r3, #2 8003970: 687b ldr r3, [r7, #4] 8003972: 65da str r2, [r3, #92] ; 0x5c /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 8003974: 6878 ldr r0, [r7, #4] 8003976: f001 f869 bl 8004a4c 800397a: 4603 mov r3, r0 800397c: 60fb str r3, [r7, #12] /* Clear all interrupt flags */ regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 800397e: 687b ldr r3, [r7, #4] 8003980: 6ddb ldr r3, [r3, #92] ; 0x5c 8003982: f003 031f and.w r3, r3, #31 8003986: 2201 movs r2, #1 8003988: 409a lsls r2, r3 800398a: 68fb ldr r3, [r7, #12] 800398c: 605a str r2, [r3, #4] 800398e: e008 b.n 80039a2 } else { hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 8003990: 687b ldr r3, [r7, #4] 8003992: 2240 movs r2, #64 ; 0x40 8003994: 655a str r2, [r3, #84] ; 0x54 hdma->State = HAL_DMA_STATE_ERROR; 8003996: 687b ldr r3, [r7, #4] 8003998: 2203 movs r2, #3 800399a: f883 2035 strb.w r2, [r3, #53] ; 0x35 return HAL_ERROR; 800399e: 2301 movs r3, #1 80039a0: e0ee b.n 8003b80 } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 80039a2: 687b ldr r3, [r7, #4] 80039a4: 681b ldr r3, [r3, #0] 80039a6: 4a47 ldr r2, [pc, #284] ; (8003ac4 ) 80039a8: 4293 cmp r3, r2 80039aa: d072 beq.n 8003a92 80039ac: 687b ldr r3, [r7, #4] 80039ae: 681b ldr r3, [r3, #0] 80039b0: 4a45 ldr r2, [pc, #276] ; (8003ac8 ) 80039b2: 4293 cmp r3, r2 80039b4: d06d beq.n 8003a92 80039b6: 687b ldr r3, [r7, #4] 80039b8: 681b ldr r3, [r3, #0] 80039ba: 4a44 ldr r2, [pc, #272] ; (8003acc ) 80039bc: 4293 cmp r3, r2 80039be: d068 beq.n 8003a92 80039c0: 687b ldr r3, [r7, #4] 80039c2: 681b ldr r3, [r3, #0] 80039c4: 4a42 ldr r2, [pc, #264] ; (8003ad0 ) 80039c6: 4293 cmp r3, r2 80039c8: d063 beq.n 8003a92 80039ca: 687b ldr r3, [r7, #4] 80039cc: 681b ldr r3, [r3, #0] 80039ce: 4a41 ldr r2, [pc, #260] ; (8003ad4 ) 80039d0: 4293 cmp r3, r2 80039d2: d05e beq.n 8003a92 80039d4: 687b ldr r3, [r7, #4] 80039d6: 681b ldr r3, [r3, #0] 80039d8: 4a3f ldr r2, [pc, #252] ; (8003ad8 ) 80039da: 4293 cmp r3, r2 80039dc: d059 beq.n 8003a92 80039de: 687b ldr r3, [r7, #4] 80039e0: 681b ldr r3, [r3, #0] 80039e2: 4a3e ldr r2, [pc, #248] ; (8003adc ) 80039e4: 4293 cmp r3, r2 80039e6: d054 beq.n 8003a92 80039e8: 687b ldr r3, [r7, #4] 80039ea: 681b ldr r3, [r3, #0] 80039ec: 4a3c ldr r2, [pc, #240] ; (8003ae0 ) 80039ee: 4293 cmp r3, r2 80039f0: d04f beq.n 8003a92 80039f2: 687b ldr r3, [r7, #4] 80039f4: 681b ldr r3, [r3, #0] 80039f6: 4a3b ldr r2, [pc, #236] ; (8003ae4 ) 80039f8: 4293 cmp r3, r2 80039fa: d04a beq.n 8003a92 80039fc: 687b ldr r3, [r7, #4] 80039fe: 681b ldr r3, [r3, #0] 8003a00: 4a39 ldr r2, [pc, #228] ; (8003ae8 ) 8003a02: 4293 cmp r3, r2 8003a04: d045 beq.n 8003a92 8003a06: 687b ldr r3, [r7, #4] 8003a08: 681b ldr r3, [r3, #0] 8003a0a: 4a38 ldr r2, [pc, #224] ; (8003aec ) 8003a0c: 4293 cmp r3, r2 8003a0e: d040 beq.n 8003a92 8003a10: 687b ldr r3, [r7, #4] 8003a12: 681b ldr r3, [r3, #0] 8003a14: 4a36 ldr r2, [pc, #216] ; (8003af0 ) 8003a16: 4293 cmp r3, r2 8003a18: d03b beq.n 8003a92 8003a1a: 687b ldr r3, [r7, #4] 8003a1c: 681b ldr r3, [r3, #0] 8003a1e: 4a35 ldr r2, [pc, #212] ; (8003af4 ) 8003a20: 4293 cmp r3, r2 8003a22: d036 beq.n 8003a92 8003a24: 687b ldr r3, [r7, #4] 8003a26: 681b ldr r3, [r3, #0] 8003a28: 4a33 ldr r2, [pc, #204] ; (8003af8 ) 8003a2a: 4293 cmp r3, r2 8003a2c: d031 beq.n 8003a92 8003a2e: 687b ldr r3, [r7, #4] 8003a30: 681b ldr r3, [r3, #0] 8003a32: 4a32 ldr r2, [pc, #200] ; (8003afc ) 8003a34: 4293 cmp r3, r2 8003a36: d02c beq.n 8003a92 8003a38: 687b ldr r3, [r7, #4] 8003a3a: 681b ldr r3, [r3, #0] 8003a3c: 4a30 ldr r2, [pc, #192] ; (8003b00 ) 8003a3e: 4293 cmp r3, r2 8003a40: d027 beq.n 8003a92 8003a42: 687b ldr r3, [r7, #4] 8003a44: 681b ldr r3, [r3, #0] 8003a46: 4a14 ldr r2, [pc, #80] ; (8003a98 ) 8003a48: 4293 cmp r3, r2 8003a4a: d022 beq.n 8003a92 8003a4c: 687b ldr r3, [r7, #4] 8003a4e: 681b ldr r3, [r3, #0] 8003a50: 4a12 ldr r2, [pc, #72] ; (8003a9c ) 8003a52: 4293 cmp r3, r2 8003a54: d01d beq.n 8003a92 8003a56: 687b ldr r3, [r7, #4] 8003a58: 681b ldr r3, [r3, #0] 8003a5a: 4a11 ldr r2, [pc, #68] ; (8003aa0 ) 8003a5c: 4293 cmp r3, r2 8003a5e: d018 beq.n 8003a92 8003a60: 687b ldr r3, [r7, #4] 8003a62: 681b ldr r3, [r3, #0] 8003a64: 4a0f ldr r2, [pc, #60] ; (8003aa4 ) 8003a66: 4293 cmp r3, r2 8003a68: d013 beq.n 8003a92 8003a6a: 687b ldr r3, [r7, #4] 8003a6c: 681b ldr r3, [r3, #0] 8003a6e: 4a0e ldr r2, [pc, #56] ; (8003aa8 ) 8003a70: 4293 cmp r3, r2 8003a72: d00e beq.n 8003a92 8003a74: 687b ldr r3, [r7, #4] 8003a76: 681b ldr r3, [r3, #0] 8003a78: 4a0c ldr r2, [pc, #48] ; (8003aac ) 8003a7a: 4293 cmp r3, r2 8003a7c: d009 beq.n 8003a92 8003a7e: 687b ldr r3, [r7, #4] 8003a80: 681b ldr r3, [r3, #0] 8003a82: 4a0b ldr r2, [pc, #44] ; (8003ab0 ) 8003a84: 4293 cmp r3, r2 8003a86: d004 beq.n 8003a92 8003a88: 687b ldr r3, [r7, #4] 8003a8a: 681b ldr r3, [r3, #0] 8003a8c: 4a09 ldr r2, [pc, #36] ; (8003ab4 ) 8003a8e: 4293 cmp r3, r2 8003a90: d138 bne.n 8003b04 8003a92: 2301 movs r3, #1 8003a94: e037 b.n 8003b06 8003a96: bf00 nop 8003a98: 58025408 .word 0x58025408 8003a9c: 5802541c .word 0x5802541c 8003aa0: 58025430 .word 0x58025430 8003aa4: 58025444 .word 0x58025444 8003aa8: 58025458 .word 0x58025458 8003aac: 5802546c .word 0x5802546c 8003ab0: 58025480 .word 0x58025480 8003ab4: 58025494 .word 0x58025494 8003ab8: fffe000f .word 0xfffe000f 8003abc: a7fdabf8 .word 0xa7fdabf8 8003ac0: cccccccd .word 0xcccccccd 8003ac4: 40020010 .word 0x40020010 8003ac8: 40020028 .word 0x40020028 8003acc: 40020040 .word 0x40020040 8003ad0: 40020058 .word 0x40020058 8003ad4: 40020070 .word 0x40020070 8003ad8: 40020088 .word 0x40020088 8003adc: 400200a0 .word 0x400200a0 8003ae0: 400200b8 .word 0x400200b8 8003ae4: 40020410 .word 0x40020410 8003ae8: 40020428 .word 0x40020428 8003aec: 40020440 .word 0x40020440 8003af0: 40020458 .word 0x40020458 8003af4: 40020470 .word 0x40020470 8003af8: 40020488 .word 0x40020488 8003afc: 400204a0 .word 0x400204a0 8003b00: 400204b8 .word 0x400204b8 8003b04: 2300 movs r3, #0 8003b06: 2b00 cmp r3, #0 8003b08: d032 beq.n 8003b70 { /* Initialize parameters for DMAMUX channel : DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ DMA_CalcDMAMUXChannelBaseAndMask(hdma); 8003b0a: 6878 ldr r0, [r7, #4] 8003b0c: f001 f8cc bl 8004ca8 if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) 8003b10: 687b ldr r3, [r7, #4] 8003b12: 689b ldr r3, [r3, #8] 8003b14: 2b80 cmp r3, #128 ; 0x80 8003b16: d102 bne.n 8003b1e { /* if memory to memory force the request to 0*/ hdma->Init.Request = DMA_REQUEST_MEM2MEM; 8003b18: 687b ldr r3, [r7, #4] 8003b1a: 2200 movs r2, #0 8003b1c: 605a str r2, [r3, #4] } /* Set peripheral request to DMAMUX channel */ hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 8003b1e: 687b ldr r3, [r7, #4] 8003b20: 685a ldr r2, [r3, #4] 8003b22: 687b ldr r3, [r7, #4] 8003b24: 6e1b ldr r3, [r3, #96] ; 0x60 8003b26: b2d2 uxtb r2, r2 8003b28: 601a str r2, [r3, #0] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8003b2a: 687b ldr r3, [r7, #4] 8003b2c: 6e5b ldr r3, [r3, #100] ; 0x64 8003b2e: 687a ldr r2, [r7, #4] 8003b30: 6e92 ldr r2, [r2, #104] ; 0x68 8003b32: 605a str r2, [r3, #4] /* Initialize parameters for DMAMUX request generator : if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7 */ if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) 8003b34: 687b ldr r3, [r7, #4] 8003b36: 685b ldr r3, [r3, #4] 8003b38: 2b00 cmp r3, #0 8003b3a: d010 beq.n 8003b5e 8003b3c: 687b ldr r3, [r7, #4] 8003b3e: 685b ldr r3, [r3, #4] 8003b40: 2b08 cmp r3, #8 8003b42: d80c bhi.n 8003b5e { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); 8003b44: 6878 ldr r0, [r7, #4] 8003b46: f001 f949 bl 8004ddc /* Reset the DMAMUX request generator register */ hdma->DMAmuxRequestGen->RGCR = 0U; 8003b4a: 687b ldr r3, [r7, #4] 8003b4c: 6edb ldr r3, [r3, #108] ; 0x6c 8003b4e: 2200 movs r2, #0 8003b50: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8003b52: 687b ldr r3, [r7, #4] 8003b54: 6f1b ldr r3, [r3, #112] ; 0x70 8003b56: 687a ldr r2, [r7, #4] 8003b58: 6f52 ldr r2, [r2, #116] ; 0x74 8003b5a: 605a str r2, [r3, #4] 8003b5c: e008 b.n 8003b70 } else { hdma->DMAmuxRequestGen = 0U; 8003b5e: 687b ldr r3, [r7, #4] 8003b60: 2200 movs r2, #0 8003b62: 66da str r2, [r3, #108] ; 0x6c hdma->DMAmuxRequestGenStatus = 0U; 8003b64: 687b ldr r3, [r7, #4] 8003b66: 2200 movs r2, #0 8003b68: 671a str r2, [r3, #112] ; 0x70 hdma->DMAmuxRequestGenStatusMask = 0U; 8003b6a: 687b ldr r3, [r7, #4] 8003b6c: 2200 movs r2, #0 8003b6e: 675a str r2, [r3, #116] ; 0x74 } } /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8003b70: 687b ldr r3, [r7, #4] 8003b72: 2200 movs r2, #0 8003b74: 655a str r2, [r3, #84] ; 0x54 /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8003b76: 687b ldr r3, [r7, #4] 8003b78: 2201 movs r2, #1 8003b7a: f883 2035 strb.w r2, [r3, #53] ; 0x35 return HAL_OK; 8003b7e: 2300 movs r3, #0 } 8003b80: 4618 mov r0, r3 8003b82: 3718 adds r7, #24 8003b84: 46bd mov sp, r7 8003b86: bd80 pop {r7, pc} 08003b88 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 8003b88: b580 push {r7, lr} 8003b8a: b08a sub sp, #40 ; 0x28 8003b8c: af00 add r7, sp, #0 8003b8e: 6078 str r0, [r7, #4] uint32_t tmpisr_dma, tmpisr_bdma; uint32_t ccr_reg; __IO uint32_t count = 0U; 8003b90: 2300 movs r3, #0 8003b92: 60fb str r3, [r7, #12] uint32_t timeout = SystemCoreClock / 9600U; 8003b94: 4b67 ldr r3, [pc, #412] ; (8003d34 ) 8003b96: 681b ldr r3, [r3, #0] 8003b98: 4a67 ldr r2, [pc, #412] ; (8003d38 ) 8003b9a: fba2 2303 umull r2, r3, r2, r3 8003b9e: 0a9b lsrs r3, r3, #10 8003ba0: 627b str r3, [r7, #36] ; 0x24 /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8003ba2: 687b ldr r3, [r7, #4] 8003ba4: 6d9b ldr r3, [r3, #88] ; 0x58 8003ba6: 623b str r3, [r7, #32] BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 8003ba8: 687b ldr r3, [r7, #4] 8003baa: 6d9b ldr r3, [r3, #88] ; 0x58 8003bac: 61fb str r3, [r7, #28] tmpisr_dma = regs_dma->ISR; 8003bae: 6a3b ldr r3, [r7, #32] 8003bb0: 681b ldr r3, [r3, #0] 8003bb2: 61bb str r3, [r7, #24] tmpisr_bdma = regs_bdma->ISR; 8003bb4: 69fb ldr r3, [r7, #28] 8003bb6: 681b ldr r3, [r3, #0] 8003bb8: 617b str r3, [r7, #20] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8003bba: 687b ldr r3, [r7, #4] 8003bbc: 681b ldr r3, [r3, #0] 8003bbe: 4a5f ldr r2, [pc, #380] ; (8003d3c ) 8003bc0: 4293 cmp r3, r2 8003bc2: d04a beq.n 8003c5a 8003bc4: 687b ldr r3, [r7, #4] 8003bc6: 681b ldr r3, [r3, #0] 8003bc8: 4a5d ldr r2, [pc, #372] ; (8003d40 ) 8003bca: 4293 cmp r3, r2 8003bcc: d045 beq.n 8003c5a 8003bce: 687b ldr r3, [r7, #4] 8003bd0: 681b ldr r3, [r3, #0] 8003bd2: 4a5c ldr r2, [pc, #368] ; (8003d44 ) 8003bd4: 4293 cmp r3, r2 8003bd6: d040 beq.n 8003c5a 8003bd8: 687b ldr r3, [r7, #4] 8003bda: 681b ldr r3, [r3, #0] 8003bdc: 4a5a ldr r2, [pc, #360] ; (8003d48 ) 8003bde: 4293 cmp r3, r2 8003be0: d03b beq.n 8003c5a 8003be2: 687b ldr r3, [r7, #4] 8003be4: 681b ldr r3, [r3, #0] 8003be6: 4a59 ldr r2, [pc, #356] ; (8003d4c ) 8003be8: 4293 cmp r3, r2 8003bea: d036 beq.n 8003c5a 8003bec: 687b ldr r3, [r7, #4] 8003bee: 681b ldr r3, [r3, #0] 8003bf0: 4a57 ldr r2, [pc, #348] ; (8003d50 ) 8003bf2: 4293 cmp r3, r2 8003bf4: d031 beq.n 8003c5a 8003bf6: 687b ldr r3, [r7, #4] 8003bf8: 681b ldr r3, [r3, #0] 8003bfa: 4a56 ldr r2, [pc, #344] ; (8003d54 ) 8003bfc: 4293 cmp r3, r2 8003bfe: d02c beq.n 8003c5a 8003c00: 687b ldr r3, [r7, #4] 8003c02: 681b ldr r3, [r3, #0] 8003c04: 4a54 ldr r2, [pc, #336] ; (8003d58 ) 8003c06: 4293 cmp r3, r2 8003c08: d027 beq.n 8003c5a 8003c0a: 687b ldr r3, [r7, #4] 8003c0c: 681b ldr r3, [r3, #0] 8003c0e: 4a53 ldr r2, [pc, #332] ; (8003d5c ) 8003c10: 4293 cmp r3, r2 8003c12: d022 beq.n 8003c5a 8003c14: 687b ldr r3, [r7, #4] 8003c16: 681b ldr r3, [r3, #0] 8003c18: 4a51 ldr r2, [pc, #324] ; (8003d60 ) 8003c1a: 4293 cmp r3, r2 8003c1c: d01d beq.n 8003c5a 8003c1e: 687b ldr r3, [r7, #4] 8003c20: 681b ldr r3, [r3, #0] 8003c22: 4a50 ldr r2, [pc, #320] ; (8003d64 ) 8003c24: 4293 cmp r3, r2 8003c26: d018 beq.n 8003c5a 8003c28: 687b ldr r3, [r7, #4] 8003c2a: 681b ldr r3, [r3, #0] 8003c2c: 4a4e ldr r2, [pc, #312] ; (8003d68 ) 8003c2e: 4293 cmp r3, r2 8003c30: d013 beq.n 8003c5a 8003c32: 687b ldr r3, [r7, #4] 8003c34: 681b ldr r3, [r3, #0] 8003c36: 4a4d ldr r2, [pc, #308] ; (8003d6c ) 8003c38: 4293 cmp r3, r2 8003c3a: d00e beq.n 8003c5a 8003c3c: 687b ldr r3, [r7, #4] 8003c3e: 681b ldr r3, [r3, #0] 8003c40: 4a4b ldr r2, [pc, #300] ; (8003d70 ) 8003c42: 4293 cmp r3, r2 8003c44: d009 beq.n 8003c5a 8003c46: 687b ldr r3, [r7, #4] 8003c48: 681b ldr r3, [r3, #0] 8003c4a: 4a4a ldr r2, [pc, #296] ; (8003d74 ) 8003c4c: 4293 cmp r3, r2 8003c4e: d004 beq.n 8003c5a 8003c50: 687b ldr r3, [r7, #4] 8003c52: 681b ldr r3, [r3, #0] 8003c54: 4a48 ldr r2, [pc, #288] ; (8003d78 ) 8003c56: 4293 cmp r3, r2 8003c58: d101 bne.n 8003c5e 8003c5a: 2301 movs r3, #1 8003c5c: e000 b.n 8003c60 8003c5e: 2300 movs r3, #0 8003c60: 2b00 cmp r3, #0 8003c62: f000 842b beq.w 80044bc { /* Transfer Error Interrupt management ***************************************/ if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8003c66: 687b ldr r3, [r7, #4] 8003c68: 6ddb ldr r3, [r3, #92] ; 0x5c 8003c6a: f003 031f and.w r3, r3, #31 8003c6e: 2208 movs r2, #8 8003c70: 409a lsls r2, r3 8003c72: 69bb ldr r3, [r7, #24] 8003c74: 4013 ands r3, r2 8003c76: 2b00 cmp r3, #0 8003c78: f000 80a2 beq.w 8003dc0 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U) 8003c7c: 687b ldr r3, [r7, #4] 8003c7e: 681b ldr r3, [r3, #0] 8003c80: 4a2e ldr r2, [pc, #184] ; (8003d3c ) 8003c82: 4293 cmp r3, r2 8003c84: d04a beq.n 8003d1c 8003c86: 687b ldr r3, [r7, #4] 8003c88: 681b ldr r3, [r3, #0] 8003c8a: 4a2d ldr r2, [pc, #180] ; (8003d40 ) 8003c8c: 4293 cmp r3, r2 8003c8e: d045 beq.n 8003d1c 8003c90: 687b ldr r3, [r7, #4] 8003c92: 681b ldr r3, [r3, #0] 8003c94: 4a2b ldr r2, [pc, #172] ; (8003d44 ) 8003c96: 4293 cmp r3, r2 8003c98: d040 beq.n 8003d1c 8003c9a: 687b ldr r3, [r7, #4] 8003c9c: 681b ldr r3, [r3, #0] 8003c9e: 4a2a ldr r2, [pc, #168] ; (8003d48 ) 8003ca0: 4293 cmp r3, r2 8003ca2: d03b beq.n 8003d1c 8003ca4: 687b ldr r3, [r7, #4] 8003ca6: 681b ldr r3, [r3, #0] 8003ca8: 4a28 ldr r2, [pc, #160] ; (8003d4c ) 8003caa: 4293 cmp r3, r2 8003cac: d036 beq.n 8003d1c 8003cae: 687b ldr r3, [r7, #4] 8003cb0: 681b ldr r3, [r3, #0] 8003cb2: 4a27 ldr r2, [pc, #156] ; (8003d50 ) 8003cb4: 4293 cmp r3, r2 8003cb6: d031 beq.n 8003d1c 8003cb8: 687b ldr r3, [r7, #4] 8003cba: 681b ldr r3, [r3, #0] 8003cbc: 4a25 ldr r2, [pc, #148] ; (8003d54 ) 8003cbe: 4293 cmp r3, r2 8003cc0: d02c beq.n 8003d1c 8003cc2: 687b ldr r3, [r7, #4] 8003cc4: 681b ldr r3, [r3, #0] 8003cc6: 4a24 ldr r2, [pc, #144] ; (8003d58 ) 8003cc8: 4293 cmp r3, r2 8003cca: d027 beq.n 8003d1c 8003ccc: 687b ldr r3, [r7, #4] 8003cce: 681b ldr r3, [r3, #0] 8003cd0: 4a22 ldr r2, [pc, #136] ; (8003d5c ) 8003cd2: 4293 cmp r3, r2 8003cd4: d022 beq.n 8003d1c 8003cd6: 687b ldr r3, [r7, #4] 8003cd8: 681b ldr r3, [r3, #0] 8003cda: 4a21 ldr r2, [pc, #132] ; (8003d60 ) 8003cdc: 4293 cmp r3, r2 8003cde: d01d beq.n 8003d1c 8003ce0: 687b ldr r3, [r7, #4] 8003ce2: 681b ldr r3, [r3, #0] 8003ce4: 4a1f ldr r2, [pc, #124] ; (8003d64 ) 8003ce6: 4293 cmp r3, r2 8003ce8: d018 beq.n 8003d1c 8003cea: 687b ldr r3, [r7, #4] 8003cec: 681b ldr r3, [r3, #0] 8003cee: 4a1e ldr r2, [pc, #120] ; (8003d68 ) 8003cf0: 4293 cmp r3, r2 8003cf2: d013 beq.n 8003d1c 8003cf4: 687b ldr r3, [r7, #4] 8003cf6: 681b ldr r3, [r3, #0] 8003cf8: 4a1c ldr r2, [pc, #112] ; (8003d6c ) 8003cfa: 4293 cmp r3, r2 8003cfc: d00e beq.n 8003d1c 8003cfe: 687b ldr r3, [r7, #4] 8003d00: 681b ldr r3, [r3, #0] 8003d02: 4a1b ldr r2, [pc, #108] ; (8003d70 ) 8003d04: 4293 cmp r3, r2 8003d06: d009 beq.n 8003d1c 8003d08: 687b ldr r3, [r7, #4] 8003d0a: 681b ldr r3, [r3, #0] 8003d0c: 4a19 ldr r2, [pc, #100] ; (8003d74 ) 8003d0e: 4293 cmp r3, r2 8003d10: d004 beq.n 8003d1c 8003d12: 687b ldr r3, [r7, #4] 8003d14: 681b ldr r3, [r3, #0] 8003d16: 4a18 ldr r2, [pc, #96] ; (8003d78 ) 8003d18: 4293 cmp r3, r2 8003d1a: d12f bne.n 8003d7c 8003d1c: 687b ldr r3, [r7, #4] 8003d1e: 681b ldr r3, [r3, #0] 8003d20: 681b ldr r3, [r3, #0] 8003d22: f003 0304 and.w r3, r3, #4 8003d26: 2b00 cmp r3, #0 8003d28: bf14 ite ne 8003d2a: 2301 movne r3, #1 8003d2c: 2300 moveq r3, #0 8003d2e: b2db uxtb r3, r3 8003d30: e02e b.n 8003d90 8003d32: bf00 nop 8003d34: 20000000 .word 0x20000000 8003d38: 1b4e81b5 .word 0x1b4e81b5 8003d3c: 40020010 .word 0x40020010 8003d40: 40020028 .word 0x40020028 8003d44: 40020040 .word 0x40020040 8003d48: 40020058 .word 0x40020058 8003d4c: 40020070 .word 0x40020070 8003d50: 40020088 .word 0x40020088 8003d54: 400200a0 .word 0x400200a0 8003d58: 400200b8 .word 0x400200b8 8003d5c: 40020410 .word 0x40020410 8003d60: 40020428 .word 0x40020428 8003d64: 40020440 .word 0x40020440 8003d68: 40020458 .word 0x40020458 8003d6c: 40020470 .word 0x40020470 8003d70: 40020488 .word 0x40020488 8003d74: 400204a0 .word 0x400204a0 8003d78: 400204b8 .word 0x400204b8 8003d7c: 687b ldr r3, [r7, #4] 8003d7e: 681b ldr r3, [r3, #0] 8003d80: 681b ldr r3, [r3, #0] 8003d82: f003 0308 and.w r3, r3, #8 8003d86: 2b00 cmp r3, #0 8003d88: bf14 ite ne 8003d8a: 2301 movne r3, #1 8003d8c: 2300 moveq r3, #0 8003d8e: b2db uxtb r3, r3 8003d90: 2b00 cmp r3, #0 8003d92: d015 beq.n 8003dc0 { /* Disable the transfer error interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TE); 8003d94: 687b ldr r3, [r7, #4] 8003d96: 681b ldr r3, [r3, #0] 8003d98: 681a ldr r2, [r3, #0] 8003d9a: 687b ldr r3, [r7, #4] 8003d9c: 681b ldr r3, [r3, #0] 8003d9e: f022 0204 bic.w r2, r2, #4 8003da2: 601a str r2, [r3, #0] /* Clear the transfer error flag */ regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); 8003da4: 687b ldr r3, [r7, #4] 8003da6: 6ddb ldr r3, [r3, #92] ; 0x5c 8003da8: f003 031f and.w r3, r3, #31 8003dac: 2208 movs r2, #8 8003dae: 409a lsls r2, r3 8003db0: 6a3b ldr r3, [r7, #32] 8003db2: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; 8003db4: 687b ldr r3, [r7, #4] 8003db6: 6d5b ldr r3, [r3, #84] ; 0x54 8003db8: f043 0201 orr.w r2, r3, #1 8003dbc: 687b ldr r3, [r7, #4] 8003dbe: 655a str r2, [r3, #84] ; 0x54 } } /* FIFO Error Interrupt management ******************************************/ if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8003dc0: 687b ldr r3, [r7, #4] 8003dc2: 6ddb ldr r3, [r3, #92] ; 0x5c 8003dc4: f003 031f and.w r3, r3, #31 8003dc8: 69ba ldr r2, [r7, #24] 8003dca: fa22 f303 lsr.w r3, r2, r3 8003dce: f003 0301 and.w r3, r3, #1 8003dd2: 2b00 cmp r3, #0 8003dd4: d06e beq.n 8003eb4 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U) 8003dd6: 687b ldr r3, [r7, #4] 8003dd8: 681b ldr r3, [r3, #0] 8003dda: 4a69 ldr r2, [pc, #420] ; (8003f80 ) 8003ddc: 4293 cmp r3, r2 8003dde: d04a beq.n 8003e76 8003de0: 687b ldr r3, [r7, #4] 8003de2: 681b ldr r3, [r3, #0] 8003de4: 4a67 ldr r2, [pc, #412] ; (8003f84 ) 8003de6: 4293 cmp r3, r2 8003de8: d045 beq.n 8003e76 8003dea: 687b ldr r3, [r7, #4] 8003dec: 681b ldr r3, [r3, #0] 8003dee: 4a66 ldr r2, [pc, #408] ; (8003f88 ) 8003df0: 4293 cmp r3, r2 8003df2: d040 beq.n 8003e76 8003df4: 687b ldr r3, [r7, #4] 8003df6: 681b ldr r3, [r3, #0] 8003df8: 4a64 ldr r2, [pc, #400] ; (8003f8c ) 8003dfa: 4293 cmp r3, r2 8003dfc: d03b beq.n 8003e76 8003dfe: 687b ldr r3, [r7, #4] 8003e00: 681b ldr r3, [r3, #0] 8003e02: 4a63 ldr r2, [pc, #396] ; (8003f90 ) 8003e04: 4293 cmp r3, r2 8003e06: d036 beq.n 8003e76 8003e08: 687b ldr r3, [r7, #4] 8003e0a: 681b ldr r3, [r3, #0] 8003e0c: 4a61 ldr r2, [pc, #388] ; (8003f94 ) 8003e0e: 4293 cmp r3, r2 8003e10: d031 beq.n 8003e76 8003e12: 687b ldr r3, [r7, #4] 8003e14: 681b ldr r3, [r3, #0] 8003e16: 4a60 ldr r2, [pc, #384] ; (8003f98 ) 8003e18: 4293 cmp r3, r2 8003e1a: d02c beq.n 8003e76 8003e1c: 687b ldr r3, [r7, #4] 8003e1e: 681b ldr r3, [r3, #0] 8003e20: 4a5e ldr r2, [pc, #376] ; (8003f9c ) 8003e22: 4293 cmp r3, r2 8003e24: d027 beq.n 8003e76 8003e26: 687b ldr r3, [r7, #4] 8003e28: 681b ldr r3, [r3, #0] 8003e2a: 4a5d ldr r2, [pc, #372] ; (8003fa0 ) 8003e2c: 4293 cmp r3, r2 8003e2e: d022 beq.n 8003e76 8003e30: 687b ldr r3, [r7, #4] 8003e32: 681b ldr r3, [r3, #0] 8003e34: 4a5b ldr r2, [pc, #364] ; (8003fa4 ) 8003e36: 4293 cmp r3, r2 8003e38: d01d beq.n 8003e76 8003e3a: 687b ldr r3, [r7, #4] 8003e3c: 681b ldr r3, [r3, #0] 8003e3e: 4a5a ldr r2, [pc, #360] ; (8003fa8 ) 8003e40: 4293 cmp r3, r2 8003e42: d018 beq.n 8003e76 8003e44: 687b ldr r3, [r7, #4] 8003e46: 681b ldr r3, [r3, #0] 8003e48: 4a58 ldr r2, [pc, #352] ; (8003fac ) 8003e4a: 4293 cmp r3, r2 8003e4c: d013 beq.n 8003e76 8003e4e: 687b ldr r3, [r7, #4] 8003e50: 681b ldr r3, [r3, #0] 8003e52: 4a57 ldr r2, [pc, #348] ; (8003fb0 ) 8003e54: 4293 cmp r3, r2 8003e56: d00e beq.n 8003e76 8003e58: 687b ldr r3, [r7, #4] 8003e5a: 681b ldr r3, [r3, #0] 8003e5c: 4a55 ldr r2, [pc, #340] ; (8003fb4 ) 8003e5e: 4293 cmp r3, r2 8003e60: d009 beq.n 8003e76 8003e62: 687b ldr r3, [r7, #4] 8003e64: 681b ldr r3, [r3, #0] 8003e66: 4a54 ldr r2, [pc, #336] ; (8003fb8 ) 8003e68: 4293 cmp r3, r2 8003e6a: d004 beq.n 8003e76 8003e6c: 687b ldr r3, [r7, #4] 8003e6e: 681b ldr r3, [r3, #0] 8003e70: 4a52 ldr r2, [pc, #328] ; (8003fbc ) 8003e72: 4293 cmp r3, r2 8003e74: d10a bne.n 8003e8c 8003e76: 687b ldr r3, [r7, #4] 8003e78: 681b ldr r3, [r3, #0] 8003e7a: 695b ldr r3, [r3, #20] 8003e7c: f003 0380 and.w r3, r3, #128 ; 0x80 8003e80: 2b00 cmp r3, #0 8003e82: bf14 ite ne 8003e84: 2301 movne r3, #1 8003e86: 2300 moveq r3, #0 8003e88: b2db uxtb r3, r3 8003e8a: e003 b.n 8003e94 8003e8c: 687b ldr r3, [r7, #4] 8003e8e: 681b ldr r3, [r3, #0] 8003e90: 681b ldr r3, [r3, #0] 8003e92: 2300 movs r3, #0 8003e94: 2b00 cmp r3, #0 8003e96: d00d beq.n 8003eb4 { /* Clear the FIFO error flag */ regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); 8003e98: 687b ldr r3, [r7, #4] 8003e9a: 6ddb ldr r3, [r3, #92] ; 0x5c 8003e9c: f003 031f and.w r3, r3, #31 8003ea0: 2201 movs r2, #1 8003ea2: 409a lsls r2, r3 8003ea4: 6a3b ldr r3, [r7, #32] 8003ea6: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; 8003ea8: 687b ldr r3, [r7, #4] 8003eaa: 6d5b ldr r3, [r3, #84] ; 0x54 8003eac: f043 0202 orr.w r2, r3, #2 8003eb0: 687b ldr r3, [r7, #4] 8003eb2: 655a str r2, [r3, #84] ; 0x54 } } /* Direct Mode Error Interrupt management ***********************************/ if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8003eb4: 687b ldr r3, [r7, #4] 8003eb6: 6ddb ldr r3, [r3, #92] ; 0x5c 8003eb8: f003 031f and.w r3, r3, #31 8003ebc: 2204 movs r2, #4 8003ebe: 409a lsls r2, r3 8003ec0: 69bb ldr r3, [r7, #24] 8003ec2: 4013 ands r3, r2 8003ec4: 2b00 cmp r3, #0 8003ec6: f000 808f beq.w 8003fe8 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U) 8003eca: 687b ldr r3, [r7, #4] 8003ecc: 681b ldr r3, [r3, #0] 8003ece: 4a2c ldr r2, [pc, #176] ; (8003f80 ) 8003ed0: 4293 cmp r3, r2 8003ed2: d04a beq.n 8003f6a 8003ed4: 687b ldr r3, [r7, #4] 8003ed6: 681b ldr r3, [r3, #0] 8003ed8: 4a2a ldr r2, [pc, #168] ; (8003f84 ) 8003eda: 4293 cmp r3, r2 8003edc: d045 beq.n 8003f6a 8003ede: 687b ldr r3, [r7, #4] 8003ee0: 681b ldr r3, [r3, #0] 8003ee2: 4a29 ldr r2, [pc, #164] ; (8003f88 ) 8003ee4: 4293 cmp r3, r2 8003ee6: d040 beq.n 8003f6a 8003ee8: 687b ldr r3, [r7, #4] 8003eea: 681b ldr r3, [r3, #0] 8003eec: 4a27 ldr r2, [pc, #156] ; (8003f8c ) 8003eee: 4293 cmp r3, r2 8003ef0: d03b beq.n 8003f6a 8003ef2: 687b ldr r3, [r7, #4] 8003ef4: 681b ldr r3, [r3, #0] 8003ef6: 4a26 ldr r2, [pc, #152] ; (8003f90 ) 8003ef8: 4293 cmp r3, r2 8003efa: d036 beq.n 8003f6a 8003efc: 687b ldr r3, [r7, #4] 8003efe: 681b ldr r3, [r3, #0] 8003f00: 4a24 ldr r2, [pc, #144] ; (8003f94 ) 8003f02: 4293 cmp r3, r2 8003f04: d031 beq.n 8003f6a 8003f06: 687b ldr r3, [r7, #4] 8003f08: 681b ldr r3, [r3, #0] 8003f0a: 4a23 ldr r2, [pc, #140] ; (8003f98 ) 8003f0c: 4293 cmp r3, r2 8003f0e: d02c beq.n 8003f6a 8003f10: 687b ldr r3, [r7, #4] 8003f12: 681b ldr r3, [r3, #0] 8003f14: 4a21 ldr r2, [pc, #132] ; (8003f9c ) 8003f16: 4293 cmp r3, r2 8003f18: d027 beq.n 8003f6a 8003f1a: 687b ldr r3, [r7, #4] 8003f1c: 681b ldr r3, [r3, #0] 8003f1e: 4a20 ldr r2, [pc, #128] ; (8003fa0 ) 8003f20: 4293 cmp r3, r2 8003f22: d022 beq.n 8003f6a 8003f24: 687b ldr r3, [r7, #4] 8003f26: 681b ldr r3, [r3, #0] 8003f28: 4a1e ldr r2, [pc, #120] ; (8003fa4 ) 8003f2a: 4293 cmp r3, r2 8003f2c: d01d beq.n 8003f6a 8003f2e: 687b ldr r3, [r7, #4] 8003f30: 681b ldr r3, [r3, #0] 8003f32: 4a1d ldr r2, [pc, #116] ; (8003fa8 ) 8003f34: 4293 cmp r3, r2 8003f36: d018 beq.n 8003f6a 8003f38: 687b ldr r3, [r7, #4] 8003f3a: 681b ldr r3, [r3, #0] 8003f3c: 4a1b ldr r2, [pc, #108] ; (8003fac ) 8003f3e: 4293 cmp r3, r2 8003f40: d013 beq.n 8003f6a 8003f42: 687b ldr r3, [r7, #4] 8003f44: 681b ldr r3, [r3, #0] 8003f46: 4a1a ldr r2, [pc, #104] ; (8003fb0 ) 8003f48: 4293 cmp r3, r2 8003f4a: d00e beq.n 8003f6a 8003f4c: 687b ldr r3, [r7, #4] 8003f4e: 681b ldr r3, [r3, #0] 8003f50: 4a18 ldr r2, [pc, #96] ; (8003fb4 ) 8003f52: 4293 cmp r3, r2 8003f54: d009 beq.n 8003f6a 8003f56: 687b ldr r3, [r7, #4] 8003f58: 681b ldr r3, [r3, #0] 8003f5a: 4a17 ldr r2, [pc, #92] ; (8003fb8 ) 8003f5c: 4293 cmp r3, r2 8003f5e: d004 beq.n 8003f6a 8003f60: 687b ldr r3, [r7, #4] 8003f62: 681b ldr r3, [r3, #0] 8003f64: 4a15 ldr r2, [pc, #84] ; (8003fbc ) 8003f66: 4293 cmp r3, r2 8003f68: d12a bne.n 8003fc0 8003f6a: 687b ldr r3, [r7, #4] 8003f6c: 681b ldr r3, [r3, #0] 8003f6e: 681b ldr r3, [r3, #0] 8003f70: f003 0302 and.w r3, r3, #2 8003f74: 2b00 cmp r3, #0 8003f76: bf14 ite ne 8003f78: 2301 movne r3, #1 8003f7a: 2300 moveq r3, #0 8003f7c: b2db uxtb r3, r3 8003f7e: e023 b.n 8003fc8 8003f80: 40020010 .word 0x40020010 8003f84: 40020028 .word 0x40020028 8003f88: 40020040 .word 0x40020040 8003f8c: 40020058 .word 0x40020058 8003f90: 40020070 .word 0x40020070 8003f94: 40020088 .word 0x40020088 8003f98: 400200a0 .word 0x400200a0 8003f9c: 400200b8 .word 0x400200b8 8003fa0: 40020410 .word 0x40020410 8003fa4: 40020428 .word 0x40020428 8003fa8: 40020440 .word 0x40020440 8003fac: 40020458 .word 0x40020458 8003fb0: 40020470 .word 0x40020470 8003fb4: 40020488 .word 0x40020488 8003fb8: 400204a0 .word 0x400204a0 8003fbc: 400204b8 .word 0x400204b8 8003fc0: 687b ldr r3, [r7, #4] 8003fc2: 681b ldr r3, [r3, #0] 8003fc4: 681b ldr r3, [r3, #0] 8003fc6: 2300 movs r3, #0 8003fc8: 2b00 cmp r3, #0 8003fca: d00d beq.n 8003fe8 { /* Clear the direct mode error flag */ regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); 8003fcc: 687b ldr r3, [r7, #4] 8003fce: 6ddb ldr r3, [r3, #92] ; 0x5c 8003fd0: f003 031f and.w r3, r3, #31 8003fd4: 2204 movs r2, #4 8003fd6: 409a lsls r2, r3 8003fd8: 6a3b ldr r3, [r7, #32] 8003fda: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; 8003fdc: 687b ldr r3, [r7, #4] 8003fde: 6d5b ldr r3, [r3, #84] ; 0x54 8003fe0: f043 0204 orr.w r2, r3, #4 8003fe4: 687b ldr r3, [r7, #4] 8003fe6: 655a str r2, [r3, #84] ; 0x54 } } /* Half Transfer Complete Interrupt management ******************************/ if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8003fe8: 687b ldr r3, [r7, #4] 8003fea: 6ddb ldr r3, [r3, #92] ; 0x5c 8003fec: f003 031f and.w r3, r3, #31 8003ff0: 2210 movs r2, #16 8003ff2: 409a lsls r2, r3 8003ff4: 69bb ldr r3, [r7, #24] 8003ff6: 4013 ands r3, r2 8003ff8: 2b00 cmp r3, #0 8003ffa: f000 80a6 beq.w 800414a { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) 8003ffe: 687b ldr r3, [r7, #4] 8004000: 681b ldr r3, [r3, #0] 8004002: 4a85 ldr r2, [pc, #532] ; (8004218 ) 8004004: 4293 cmp r3, r2 8004006: d04a beq.n 800409e 8004008: 687b ldr r3, [r7, #4] 800400a: 681b ldr r3, [r3, #0] 800400c: 4a83 ldr r2, [pc, #524] ; (800421c ) 800400e: 4293 cmp r3, r2 8004010: d045 beq.n 800409e 8004012: 687b ldr r3, [r7, #4] 8004014: 681b ldr r3, [r3, #0] 8004016: 4a82 ldr r2, [pc, #520] ; (8004220 ) 8004018: 4293 cmp r3, r2 800401a: d040 beq.n 800409e 800401c: 687b ldr r3, [r7, #4] 800401e: 681b ldr r3, [r3, #0] 8004020: 4a80 ldr r2, [pc, #512] ; (8004224 ) 8004022: 4293 cmp r3, r2 8004024: d03b beq.n 800409e 8004026: 687b ldr r3, [r7, #4] 8004028: 681b ldr r3, [r3, #0] 800402a: 4a7f ldr r2, [pc, #508] ; (8004228 ) 800402c: 4293 cmp r3, r2 800402e: d036 beq.n 800409e 8004030: 687b ldr r3, [r7, #4] 8004032: 681b ldr r3, [r3, #0] 8004034: 4a7d ldr r2, [pc, #500] ; (800422c ) 8004036: 4293 cmp r3, r2 8004038: d031 beq.n 800409e 800403a: 687b ldr r3, [r7, #4] 800403c: 681b ldr r3, [r3, #0] 800403e: 4a7c ldr r2, [pc, #496] ; (8004230 ) 8004040: 4293 cmp r3, r2 8004042: d02c beq.n 800409e 8004044: 687b ldr r3, [r7, #4] 8004046: 681b ldr r3, [r3, #0] 8004048: 4a7a ldr r2, [pc, #488] ; (8004234 ) 800404a: 4293 cmp r3, r2 800404c: d027 beq.n 800409e 800404e: 687b ldr r3, [r7, #4] 8004050: 681b ldr r3, [r3, #0] 8004052: 4a79 ldr r2, [pc, #484] ; (8004238 ) 8004054: 4293 cmp r3, r2 8004056: d022 beq.n 800409e 8004058: 687b ldr r3, [r7, #4] 800405a: 681b ldr r3, [r3, #0] 800405c: 4a77 ldr r2, [pc, #476] ; (800423c ) 800405e: 4293 cmp r3, r2 8004060: d01d beq.n 800409e 8004062: 687b ldr r3, [r7, #4] 8004064: 681b ldr r3, [r3, #0] 8004066: 4a76 ldr r2, [pc, #472] ; (8004240 ) 8004068: 4293 cmp r3, r2 800406a: d018 beq.n 800409e 800406c: 687b ldr r3, [r7, #4] 800406e: 681b ldr r3, [r3, #0] 8004070: 4a74 ldr r2, [pc, #464] ; (8004244 ) 8004072: 4293 cmp r3, r2 8004074: d013 beq.n 800409e 8004076: 687b ldr r3, [r7, #4] 8004078: 681b ldr r3, [r3, #0] 800407a: 4a73 ldr r2, [pc, #460] ; (8004248 ) 800407c: 4293 cmp r3, r2 800407e: d00e beq.n 800409e 8004080: 687b ldr r3, [r7, #4] 8004082: 681b ldr r3, [r3, #0] 8004084: 4a71 ldr r2, [pc, #452] ; (800424c ) 8004086: 4293 cmp r3, r2 8004088: d009 beq.n 800409e 800408a: 687b ldr r3, [r7, #4] 800408c: 681b ldr r3, [r3, #0] 800408e: 4a70 ldr r2, [pc, #448] ; (8004250 ) 8004090: 4293 cmp r3, r2 8004092: d004 beq.n 800409e 8004094: 687b ldr r3, [r7, #4] 8004096: 681b ldr r3, [r3, #0] 8004098: 4a6e ldr r2, [pc, #440] ; (8004254 ) 800409a: 4293 cmp r3, r2 800409c: d10a bne.n 80040b4 800409e: 687b ldr r3, [r7, #4] 80040a0: 681b ldr r3, [r3, #0] 80040a2: 681b ldr r3, [r3, #0] 80040a4: f003 0308 and.w r3, r3, #8 80040a8: 2b00 cmp r3, #0 80040aa: bf14 ite ne 80040ac: 2301 movne r3, #1 80040ae: 2300 moveq r3, #0 80040b0: b2db uxtb r3, r3 80040b2: e009 b.n 80040c8 80040b4: 687b ldr r3, [r7, #4] 80040b6: 681b ldr r3, [r3, #0] 80040b8: 681b ldr r3, [r3, #0] 80040ba: f003 0304 and.w r3, r3, #4 80040be: 2b00 cmp r3, #0 80040c0: bf14 ite ne 80040c2: 2301 movne r3, #1 80040c4: 2300 moveq r3, #0 80040c6: b2db uxtb r3, r3 80040c8: 2b00 cmp r3, #0 80040ca: d03e beq.n 800414a { /* Clear the half transfer complete flag */ regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); 80040cc: 687b ldr r3, [r7, #4] 80040ce: 6ddb ldr r3, [r3, #92] ; 0x5c 80040d0: f003 031f and.w r3, r3, #31 80040d4: 2210 movs r2, #16 80040d6: 409a lsls r2, r3 80040d8: 6a3b ldr r3, [r7, #32] 80040da: 609a str r2, [r3, #8] /* Multi_Buffering mode enabled */ if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 80040dc: 687b ldr r3, [r7, #4] 80040de: 681b ldr r3, [r3, #0] 80040e0: 681b ldr r3, [r3, #0] 80040e2: f403 2380 and.w r3, r3, #262144 ; 0x40000 80040e6: 2b00 cmp r3, #0 80040e8: d018 beq.n 800411c { /* Current memory buffer used is Memory 0 */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 80040ea: 687b ldr r3, [r7, #4] 80040ec: 681b ldr r3, [r3, #0] 80040ee: 681b ldr r3, [r3, #0] 80040f0: f403 2300 and.w r3, r3, #524288 ; 0x80000 80040f4: 2b00 cmp r3, #0 80040f6: d108 bne.n 800410a { if(hdma->XferHalfCpltCallback != NULL) 80040f8: 687b ldr r3, [r7, #4] 80040fa: 6c1b ldr r3, [r3, #64] ; 0x40 80040fc: 2b00 cmp r3, #0 80040fe: d024 beq.n 800414a { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8004100: 687b ldr r3, [r7, #4] 8004102: 6c1b ldr r3, [r3, #64] ; 0x40 8004104: 6878 ldr r0, [r7, #4] 8004106: 4798 blx r3 8004108: e01f b.n 800414a } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferM1HalfCpltCallback != NULL) 800410a: 687b ldr r3, [r7, #4] 800410c: 6c9b ldr r3, [r3, #72] ; 0x48 800410e: 2b00 cmp r3, #0 8004110: d01b beq.n 800414a { /* Half transfer callback */ hdma->XferM1HalfCpltCallback(hdma); 8004112: 687b ldr r3, [r7, #4] 8004114: 6c9b ldr r3, [r3, #72] ; 0x48 8004116: 6878 ldr r0, [r7, #4] 8004118: 4798 blx r3 800411a: e016 b.n 800414a } } else { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) 800411c: 687b ldr r3, [r7, #4] 800411e: 681b ldr r3, [r3, #0] 8004120: 681b ldr r3, [r3, #0] 8004122: f403 7380 and.w r3, r3, #256 ; 0x100 8004126: 2b00 cmp r3, #0 8004128: d107 bne.n 800413a { /* Disable the half transfer interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); 800412a: 687b ldr r3, [r7, #4] 800412c: 681b ldr r3, [r3, #0] 800412e: 681a ldr r2, [r3, #0] 8004130: 687b ldr r3, [r7, #4] 8004132: 681b ldr r3, [r3, #0] 8004134: f022 0208 bic.w r2, r2, #8 8004138: 601a str r2, [r3, #0] } if(hdma->XferHalfCpltCallback != NULL) 800413a: 687b ldr r3, [r7, #4] 800413c: 6c1b ldr r3, [r3, #64] ; 0x40 800413e: 2b00 cmp r3, #0 8004140: d003 beq.n 800414a { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8004142: 687b ldr r3, [r7, #4] 8004144: 6c1b ldr r3, [r3, #64] ; 0x40 8004146: 6878 ldr r0, [r7, #4] 8004148: 4798 blx r3 } } } } /* Transfer Complete Interrupt management ***********************************/ if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 800414a: 687b ldr r3, [r7, #4] 800414c: 6ddb ldr r3, [r3, #92] ; 0x5c 800414e: f003 031f and.w r3, r3, #31 8004152: 2220 movs r2, #32 8004154: 409a lsls r2, r3 8004156: 69bb ldr r3, [r7, #24] 8004158: 4013 ands r3, r2 800415a: 2b00 cmp r3, #0 800415c: f000 8110 beq.w 8004380 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) 8004160: 687b ldr r3, [r7, #4] 8004162: 681b ldr r3, [r3, #0] 8004164: 4a2c ldr r2, [pc, #176] ; (8004218 ) 8004166: 4293 cmp r3, r2 8004168: d04a beq.n 8004200 800416a: 687b ldr r3, [r7, #4] 800416c: 681b ldr r3, [r3, #0] 800416e: 4a2b ldr r2, [pc, #172] ; (800421c ) 8004170: 4293 cmp r3, r2 8004172: d045 beq.n 8004200 8004174: 687b ldr r3, [r7, #4] 8004176: 681b ldr r3, [r3, #0] 8004178: 4a29 ldr r2, [pc, #164] ; (8004220 ) 800417a: 4293 cmp r3, r2 800417c: d040 beq.n 8004200 800417e: 687b ldr r3, [r7, #4] 8004180: 681b ldr r3, [r3, #0] 8004182: 4a28 ldr r2, [pc, #160] ; (8004224 ) 8004184: 4293 cmp r3, r2 8004186: d03b beq.n 8004200 8004188: 687b ldr r3, [r7, #4] 800418a: 681b ldr r3, [r3, #0] 800418c: 4a26 ldr r2, [pc, #152] ; (8004228 ) 800418e: 4293 cmp r3, r2 8004190: d036 beq.n 8004200 8004192: 687b ldr r3, [r7, #4] 8004194: 681b ldr r3, [r3, #0] 8004196: 4a25 ldr r2, [pc, #148] ; (800422c ) 8004198: 4293 cmp r3, r2 800419a: d031 beq.n 8004200 800419c: 687b ldr r3, [r7, #4] 800419e: 681b ldr r3, [r3, #0] 80041a0: 4a23 ldr r2, [pc, #140] ; (8004230 ) 80041a2: 4293 cmp r3, r2 80041a4: d02c beq.n 8004200 80041a6: 687b ldr r3, [r7, #4] 80041a8: 681b ldr r3, [r3, #0] 80041aa: 4a22 ldr r2, [pc, #136] ; (8004234 ) 80041ac: 4293 cmp r3, r2 80041ae: d027 beq.n 8004200 80041b0: 687b ldr r3, [r7, #4] 80041b2: 681b ldr r3, [r3, #0] 80041b4: 4a20 ldr r2, [pc, #128] ; (8004238 ) 80041b6: 4293 cmp r3, r2 80041b8: d022 beq.n 8004200 80041ba: 687b ldr r3, [r7, #4] 80041bc: 681b ldr r3, [r3, #0] 80041be: 4a1f ldr r2, [pc, #124] ; (800423c ) 80041c0: 4293 cmp r3, r2 80041c2: d01d beq.n 8004200 80041c4: 687b ldr r3, [r7, #4] 80041c6: 681b ldr r3, [r3, #0] 80041c8: 4a1d ldr r2, [pc, #116] ; (8004240 ) 80041ca: 4293 cmp r3, r2 80041cc: d018 beq.n 8004200 80041ce: 687b ldr r3, [r7, #4] 80041d0: 681b ldr r3, [r3, #0] 80041d2: 4a1c ldr r2, [pc, #112] ; (8004244 ) 80041d4: 4293 cmp r3, r2 80041d6: d013 beq.n 8004200 80041d8: 687b ldr r3, [r7, #4] 80041da: 681b ldr r3, [r3, #0] 80041dc: 4a1a ldr r2, [pc, #104] ; (8004248 ) 80041de: 4293 cmp r3, r2 80041e0: d00e beq.n 8004200 80041e2: 687b ldr r3, [r7, #4] 80041e4: 681b ldr r3, [r3, #0] 80041e6: 4a19 ldr r2, [pc, #100] ; (800424c ) 80041e8: 4293 cmp r3, r2 80041ea: d009 beq.n 8004200 80041ec: 687b ldr r3, [r7, #4] 80041ee: 681b ldr r3, [r3, #0] 80041f0: 4a17 ldr r2, [pc, #92] ; (8004250 ) 80041f2: 4293 cmp r3, r2 80041f4: d004 beq.n 8004200 80041f6: 687b ldr r3, [r7, #4] 80041f8: 681b ldr r3, [r3, #0] 80041fa: 4a16 ldr r2, [pc, #88] ; (8004254 ) 80041fc: 4293 cmp r3, r2 80041fe: d12b bne.n 8004258 8004200: 687b ldr r3, [r7, #4] 8004202: 681b ldr r3, [r3, #0] 8004204: 681b ldr r3, [r3, #0] 8004206: f003 0310 and.w r3, r3, #16 800420a: 2b00 cmp r3, #0 800420c: bf14 ite ne 800420e: 2301 movne r3, #1 8004210: 2300 moveq r3, #0 8004212: b2db uxtb r3, r3 8004214: e02a b.n 800426c 8004216: bf00 nop 8004218: 40020010 .word 0x40020010 800421c: 40020028 .word 0x40020028 8004220: 40020040 .word 0x40020040 8004224: 40020058 .word 0x40020058 8004228: 40020070 .word 0x40020070 800422c: 40020088 .word 0x40020088 8004230: 400200a0 .word 0x400200a0 8004234: 400200b8 .word 0x400200b8 8004238: 40020410 .word 0x40020410 800423c: 40020428 .word 0x40020428 8004240: 40020440 .word 0x40020440 8004244: 40020458 .word 0x40020458 8004248: 40020470 .word 0x40020470 800424c: 40020488 .word 0x40020488 8004250: 400204a0 .word 0x400204a0 8004254: 400204b8 .word 0x400204b8 8004258: 687b ldr r3, [r7, #4] 800425a: 681b ldr r3, [r3, #0] 800425c: 681b ldr r3, [r3, #0] 800425e: f003 0302 and.w r3, r3, #2 8004262: 2b00 cmp r3, #0 8004264: bf14 ite ne 8004266: 2301 movne r3, #1 8004268: 2300 moveq r3, #0 800426a: b2db uxtb r3, r3 800426c: 2b00 cmp r3, #0 800426e: f000 8087 beq.w 8004380 { /* Clear the transfer complete flag */ regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); 8004272: 687b ldr r3, [r7, #4] 8004274: 6ddb ldr r3, [r3, #92] ; 0x5c 8004276: f003 031f and.w r3, r3, #31 800427a: 2220 movs r2, #32 800427c: 409a lsls r2, r3 800427e: 6a3b ldr r3, [r7, #32] 8004280: 609a str r2, [r3, #8] if(HAL_DMA_STATE_ABORT == hdma->State) 8004282: 687b ldr r3, [r7, #4] 8004284: f893 3035 ldrb.w r3, [r3, #53] ; 0x35 8004288: b2db uxtb r3, r3 800428a: 2b04 cmp r3, #4 800428c: d139 bne.n 8004302 { /* Disable all the transfer interrupts */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 800428e: 687b ldr r3, [r7, #4] 8004290: 681b ldr r3, [r3, #0] 8004292: 681a ldr r2, [r3, #0] 8004294: 687b ldr r3, [r7, #4] 8004296: 681b ldr r3, [r3, #0] 8004298: f022 0216 bic.w r2, r2, #22 800429c: 601a str r2, [r3, #0] ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 800429e: 687b ldr r3, [r7, #4] 80042a0: 681b ldr r3, [r3, #0] 80042a2: 695a ldr r2, [r3, #20] 80042a4: 687b ldr r3, [r7, #4] 80042a6: 681b ldr r3, [r3, #0] 80042a8: f022 0280 bic.w r2, r2, #128 ; 0x80 80042ac: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 80042ae: 687b ldr r3, [r7, #4] 80042b0: 6c1b ldr r3, [r3, #64] ; 0x40 80042b2: 2b00 cmp r3, #0 80042b4: d103 bne.n 80042be 80042b6: 687b ldr r3, [r7, #4] 80042b8: 6c9b ldr r3, [r3, #72] ; 0x48 80042ba: 2b00 cmp r3, #0 80042bc: d007 beq.n 80042ce { ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); 80042be: 687b ldr r3, [r7, #4] 80042c0: 681b ldr r3, [r3, #0] 80042c2: 681a ldr r2, [r3, #0] 80042c4: 687b ldr r3, [r7, #4] 80042c6: 681b ldr r3, [r3, #0] 80042c8: f022 0208 bic.w r2, r2, #8 80042cc: 601a str r2, [r3, #0] } /* Clear all interrupt flags at correct offset within the register */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 80042ce: 687b ldr r3, [r7, #4] 80042d0: 6ddb ldr r3, [r3, #92] ; 0x5c 80042d2: f003 031f and.w r3, r3, #31 80042d6: 223f movs r2, #63 ; 0x3f 80042d8: 409a lsls r2, r3 80042da: 6a3b ldr r3, [r7, #32] 80042dc: 609a str r2, [r3, #8] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80042de: 687b ldr r3, [r7, #4] 80042e0: 2201 movs r2, #1 80042e2: f883 2035 strb.w r2, [r3, #53] ; 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80042e6: 687b ldr r3, [r7, #4] 80042e8: 2200 movs r2, #0 80042ea: f883 2034 strb.w r2, [r3, #52] ; 0x34 if(hdma->XferAbortCallback != NULL) 80042ee: 687b ldr r3, [r7, #4] 80042f0: 6d1b ldr r3, [r3, #80] ; 0x50 80042f2: 2b00 cmp r3, #0 80042f4: f000 8382 beq.w 80049fc { hdma->XferAbortCallback(hdma); 80042f8: 687b ldr r3, [r7, #4] 80042fa: 6d1b ldr r3, [r3, #80] ; 0x50 80042fc: 6878 ldr r0, [r7, #4] 80042fe: 4798 blx r3 } return; 8004300: e37c b.n 80049fc } if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 8004302: 687b ldr r3, [r7, #4] 8004304: 681b ldr r3, [r3, #0] 8004306: 681b ldr r3, [r3, #0] 8004308: f403 2380 and.w r3, r3, #262144 ; 0x40000 800430c: 2b00 cmp r3, #0 800430e: d018 beq.n 8004342 { /* Current memory buffer used is Memory 0 */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 8004310: 687b ldr r3, [r7, #4] 8004312: 681b ldr r3, [r3, #0] 8004314: 681b ldr r3, [r3, #0] 8004316: f403 2300 and.w r3, r3, #524288 ; 0x80000 800431a: 2b00 cmp r3, #0 800431c: d108 bne.n 8004330 { if(hdma->XferM1CpltCallback != NULL) 800431e: 687b ldr r3, [r7, #4] 8004320: 6c5b ldr r3, [r3, #68] ; 0x44 8004322: 2b00 cmp r3, #0 8004324: d02c beq.n 8004380 { /* Transfer complete Callback for memory1 */ hdma->XferM1CpltCallback(hdma); 8004326: 687b ldr r3, [r7, #4] 8004328: 6c5b ldr r3, [r3, #68] ; 0x44 800432a: 6878 ldr r0, [r7, #4] 800432c: 4798 blx r3 800432e: e027 b.n 8004380 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 8004330: 687b ldr r3, [r7, #4] 8004332: 6bdb ldr r3, [r3, #60] ; 0x3c 8004334: 2b00 cmp r3, #0 8004336: d023 beq.n 8004380 { /* Transfer complete Callback for memory0 */ hdma->XferCpltCallback(hdma); 8004338: 687b ldr r3, [r7, #4] 800433a: 6bdb ldr r3, [r3, #60] ; 0x3c 800433c: 6878 ldr r0, [r7, #4] 800433e: 4798 blx r3 8004340: e01e b.n 8004380 } } /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ else { if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) 8004342: 687b ldr r3, [r7, #4] 8004344: 681b ldr r3, [r3, #0] 8004346: 681b ldr r3, [r3, #0] 8004348: f403 7380 and.w r3, r3, #256 ; 0x100 800434c: 2b00 cmp r3, #0 800434e: d10f bne.n 8004370 { /* Disable the transfer complete interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC); 8004350: 687b ldr r3, [r7, #4] 8004352: 681b ldr r3, [r3, #0] 8004354: 681a ldr r2, [r3, #0] 8004356: 687b ldr r3, [r7, #4] 8004358: 681b ldr r3, [r3, #0] 800435a: f022 0210 bic.w r2, r2, #16 800435e: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8004360: 687b ldr r3, [r7, #4] 8004362: 2201 movs r2, #1 8004364: f883 2035 strb.w r2, [r3, #53] ; 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8004368: 687b ldr r3, [r7, #4] 800436a: 2200 movs r2, #0 800436c: f883 2034 strb.w r2, [r3, #52] ; 0x34 } if(hdma->XferCpltCallback != NULL) 8004370: 687b ldr r3, [r7, #4] 8004372: 6bdb ldr r3, [r3, #60] ; 0x3c 8004374: 2b00 cmp r3, #0 8004376: d003 beq.n 8004380 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8004378: 687b ldr r3, [r7, #4] 800437a: 6bdb ldr r3, [r3, #60] ; 0x3c 800437c: 6878 ldr r0, [r7, #4] 800437e: 4798 blx r3 } } } /* manage error case */ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) 8004380: 687b ldr r3, [r7, #4] 8004382: 6d5b ldr r3, [r3, #84] ; 0x54 8004384: 2b00 cmp r3, #0 8004386: f000 833e beq.w 8004a06 { if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U) 800438a: 687b ldr r3, [r7, #4] 800438c: 6d5b ldr r3, [r3, #84] ; 0x54 800438e: f003 0301 and.w r3, r3, #1 8004392: 2b00 cmp r3, #0 8004394: f000 8088 beq.w 80044a8 { hdma->State = HAL_DMA_STATE_ABORT; 8004398: 687b ldr r3, [r7, #4] 800439a: 2204 movs r2, #4 800439c: f883 2035 strb.w r2, [r3, #53] ; 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 80043a0: 687b ldr r3, [r7, #4] 80043a2: 681b ldr r3, [r3, #0] 80043a4: 4a8e ldr r2, [pc, #568] ; (80045e0 ) 80043a6: 4293 cmp r3, r2 80043a8: d04a beq.n 8004440 80043aa: 687b ldr r3, [r7, #4] 80043ac: 681b ldr r3, [r3, #0] 80043ae: 4a8d ldr r2, [pc, #564] ; (80045e4 ) 80043b0: 4293 cmp r3, r2 80043b2: d045 beq.n 8004440 80043b4: 687b ldr r3, [r7, #4] 80043b6: 681b ldr r3, [r3, #0] 80043b8: 4a8b ldr r2, [pc, #556] ; (80045e8 ) 80043ba: 4293 cmp r3, r2 80043bc: d040 beq.n 8004440 80043be: 687b ldr r3, [r7, #4] 80043c0: 681b ldr r3, [r3, #0] 80043c2: 4a8a ldr r2, [pc, #552] ; (80045ec ) 80043c4: 4293 cmp r3, r2 80043c6: d03b beq.n 8004440 80043c8: 687b ldr r3, [r7, #4] 80043ca: 681b ldr r3, [r3, #0] 80043cc: 4a88 ldr r2, [pc, #544] ; (80045f0 ) 80043ce: 4293 cmp r3, r2 80043d0: d036 beq.n 8004440 80043d2: 687b ldr r3, [r7, #4] 80043d4: 681b ldr r3, [r3, #0] 80043d6: 4a87 ldr r2, [pc, #540] ; (80045f4 ) 80043d8: 4293 cmp r3, r2 80043da: d031 beq.n 8004440 80043dc: 687b ldr r3, [r7, #4] 80043de: 681b ldr r3, [r3, #0] 80043e0: 4a85 ldr r2, [pc, #532] ; (80045f8 ) 80043e2: 4293 cmp r3, r2 80043e4: d02c beq.n 8004440 80043e6: 687b ldr r3, [r7, #4] 80043e8: 681b ldr r3, [r3, #0] 80043ea: 4a84 ldr r2, [pc, #528] ; (80045fc ) 80043ec: 4293 cmp r3, r2 80043ee: d027 beq.n 8004440 80043f0: 687b ldr r3, [r7, #4] 80043f2: 681b ldr r3, [r3, #0] 80043f4: 4a82 ldr r2, [pc, #520] ; (8004600 ) 80043f6: 4293 cmp r3, r2 80043f8: d022 beq.n 8004440 80043fa: 687b ldr r3, [r7, #4] 80043fc: 681b ldr r3, [r3, #0] 80043fe: 4a81 ldr r2, [pc, #516] ; (8004604 ) 8004400: 4293 cmp r3, r2 8004402: d01d beq.n 8004440 8004404: 687b ldr r3, [r7, #4] 8004406: 681b ldr r3, [r3, #0] 8004408: 4a7f ldr r2, [pc, #508] ; (8004608 ) 800440a: 4293 cmp r3, r2 800440c: d018 beq.n 8004440 800440e: 687b ldr r3, [r7, #4] 8004410: 681b ldr r3, [r3, #0] 8004412: 4a7e ldr r2, [pc, #504] ; (800460c ) 8004414: 4293 cmp r3, r2 8004416: d013 beq.n 8004440 8004418: 687b ldr r3, [r7, #4] 800441a: 681b ldr r3, [r3, #0] 800441c: 4a7c ldr r2, [pc, #496] ; (8004610 ) 800441e: 4293 cmp r3, r2 8004420: d00e beq.n 8004440 8004422: 687b ldr r3, [r7, #4] 8004424: 681b ldr r3, [r3, #0] 8004426: 4a7b ldr r2, [pc, #492] ; (8004614 ) 8004428: 4293 cmp r3, r2 800442a: d009 beq.n 8004440 800442c: 687b ldr r3, [r7, #4] 800442e: 681b ldr r3, [r3, #0] 8004430: 4a79 ldr r2, [pc, #484] ; (8004618 ) 8004432: 4293 cmp r3, r2 8004434: d004 beq.n 8004440 8004436: 687b ldr r3, [r7, #4] 8004438: 681b ldr r3, [r3, #0] 800443a: 4a78 ldr r2, [pc, #480] ; (800461c ) 800443c: 4293 cmp r3, r2 800443e: d108 bne.n 8004452 8004440: 687b ldr r3, [r7, #4] 8004442: 681b ldr r3, [r3, #0] 8004444: 681a ldr r2, [r3, #0] 8004446: 687b ldr r3, [r7, #4] 8004448: 681b ldr r3, [r3, #0] 800444a: f022 0201 bic.w r2, r2, #1 800444e: 601a str r2, [r3, #0] 8004450: e007 b.n 8004462 8004452: 687b ldr r3, [r7, #4] 8004454: 681b ldr r3, [r3, #0] 8004456: 681a ldr r2, [r3, #0] 8004458: 687b ldr r3, [r7, #4] 800445a: 681b ldr r3, [r3, #0] 800445c: f022 0201 bic.w r2, r2, #1 8004460: 601a str r2, [r3, #0] do { if (++count > timeout) 8004462: 68fb ldr r3, [r7, #12] 8004464: 3301 adds r3, #1 8004466: 60fb str r3, [r7, #12] 8004468: 6a7a ldr r2, [r7, #36] ; 0x24 800446a: 429a cmp r2, r3 800446c: d307 bcc.n 800447e { break; } } while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U); 800446e: 687b ldr r3, [r7, #4] 8004470: 681b ldr r3, [r3, #0] 8004472: 681b ldr r3, [r3, #0] 8004474: f003 0301 and.w r3, r3, #1 8004478: 2b00 cmp r3, #0 800447a: d1f2 bne.n 8004462 800447c: e000 b.n 8004480 break; 800447e: bf00 nop if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 8004480: 687b ldr r3, [r7, #4] 8004482: 681b ldr r3, [r3, #0] 8004484: 681b ldr r3, [r3, #0] 8004486: f003 0301 and.w r3, r3, #1 800448a: 2b00 cmp r3, #0 800448c: d004 beq.n 8004498 { /* Change the DMA state to error if DMA disable fails */ hdma->State = HAL_DMA_STATE_ERROR; 800448e: 687b ldr r3, [r7, #4] 8004490: 2203 movs r2, #3 8004492: f883 2035 strb.w r2, [r3, #53] ; 0x35 8004496: e003 b.n 80044a0 } else { /* Change the DMA state to Ready if DMA disable success */ hdma->State = HAL_DMA_STATE_READY; 8004498: 687b ldr r3, [r7, #4] 800449a: 2201 movs r2, #1 800449c: f883 2035 strb.w r2, [r3, #53] ; 0x35 } /* Process Unlocked */ __HAL_UNLOCK(hdma); 80044a0: 687b ldr r3, [r7, #4] 80044a2: 2200 movs r2, #0 80044a4: f883 2034 strb.w r2, [r3, #52] ; 0x34 } if(hdma->XferErrorCallback != NULL) 80044a8: 687b ldr r3, [r7, #4] 80044aa: 6cdb ldr r3, [r3, #76] ; 0x4c 80044ac: 2b00 cmp r3, #0 80044ae: f000 82aa beq.w 8004a06 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 80044b2: 687b ldr r3, [r7, #4] 80044b4: 6cdb ldr r3, [r3, #76] ; 0x4c 80044b6: 6878 ldr r0, [r7, #4] 80044b8: 4798 blx r3 80044ba: e2a4 b.n 8004a06 } } } else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 80044bc: 687b ldr r3, [r7, #4] 80044be: 681b ldr r3, [r3, #0] 80044c0: 4a57 ldr r2, [pc, #348] ; (8004620 ) 80044c2: 4293 cmp r3, r2 80044c4: d04a beq.n 800455c 80044c6: 687b ldr r3, [r7, #4] 80044c8: 681b ldr r3, [r3, #0] 80044ca: 4a56 ldr r2, [pc, #344] ; (8004624 ) 80044cc: 4293 cmp r3, r2 80044ce: d045 beq.n 800455c 80044d0: 687b ldr r3, [r7, #4] 80044d2: 681b ldr r3, [r3, #0] 80044d4: 4a54 ldr r2, [pc, #336] ; (8004628 ) 80044d6: 4293 cmp r3, r2 80044d8: d040 beq.n 800455c 80044da: 687b ldr r3, [r7, #4] 80044dc: 681b ldr r3, [r3, #0] 80044de: 4a53 ldr r2, [pc, #332] ; (800462c ) 80044e0: 4293 cmp r3, r2 80044e2: d03b beq.n 800455c 80044e4: 687b ldr r3, [r7, #4] 80044e6: 681b ldr r3, [r3, #0] 80044e8: 4a51 ldr r2, [pc, #324] ; (8004630 ) 80044ea: 4293 cmp r3, r2 80044ec: d036 beq.n 800455c 80044ee: 687b ldr r3, [r7, #4] 80044f0: 681b ldr r3, [r3, #0] 80044f2: 4a50 ldr r2, [pc, #320] ; (8004634 ) 80044f4: 4293 cmp r3, r2 80044f6: d031 beq.n 800455c 80044f8: 687b ldr r3, [r7, #4] 80044fa: 681b ldr r3, [r3, #0] 80044fc: 4a4e ldr r2, [pc, #312] ; (8004638 ) 80044fe: 4293 cmp r3, r2 8004500: d02c beq.n 800455c 8004502: 687b ldr r3, [r7, #4] 8004504: 681b ldr r3, [r3, #0] 8004506: 4a4d ldr r2, [pc, #308] ; (800463c ) 8004508: 4293 cmp r3, r2 800450a: d027 beq.n 800455c 800450c: 687b ldr r3, [r7, #4] 800450e: 681b ldr r3, [r3, #0] 8004510: 4a4b ldr r2, [pc, #300] ; (8004640 ) 8004512: 4293 cmp r3, r2 8004514: d022 beq.n 800455c 8004516: 687b ldr r3, [r7, #4] 8004518: 681b ldr r3, [r3, #0] 800451a: 4a4a ldr r2, [pc, #296] ; (8004644 ) 800451c: 4293 cmp r3, r2 800451e: d01d beq.n 800455c 8004520: 687b ldr r3, [r7, #4] 8004522: 681b ldr r3, [r3, #0] 8004524: 4a48 ldr r2, [pc, #288] ; (8004648 ) 8004526: 4293 cmp r3, r2 8004528: d018 beq.n 800455c 800452a: 687b ldr r3, [r7, #4] 800452c: 681b ldr r3, [r3, #0] 800452e: 4a47 ldr r2, [pc, #284] ; (800464c ) 8004530: 4293 cmp r3, r2 8004532: d013 beq.n 800455c 8004534: 687b ldr r3, [r7, #4] 8004536: 681b ldr r3, [r3, #0] 8004538: 4a45 ldr r2, [pc, #276] ; (8004650 ) 800453a: 4293 cmp r3, r2 800453c: d00e beq.n 800455c 800453e: 687b ldr r3, [r7, #4] 8004540: 681b ldr r3, [r3, #0] 8004542: 4a44 ldr r2, [pc, #272] ; (8004654 ) 8004544: 4293 cmp r3, r2 8004546: d009 beq.n 800455c 8004548: 687b ldr r3, [r7, #4] 800454a: 681b ldr r3, [r3, #0] 800454c: 4a42 ldr r2, [pc, #264] ; (8004658 ) 800454e: 4293 cmp r3, r2 8004550: d004 beq.n 800455c 8004552: 687b ldr r3, [r7, #4] 8004554: 681b ldr r3, [r3, #0] 8004556: 4a41 ldr r2, [pc, #260] ; (800465c ) 8004558: 4293 cmp r3, r2 800455a: d101 bne.n 8004560 800455c: 2301 movs r3, #1 800455e: e000 b.n 8004562 8004560: 2300 movs r3, #0 8004562: 2b00 cmp r3, #0 8004564: f000 824f beq.w 8004a06 { ccr_reg = (((BDMA_Channel_TypeDef *)hdma->Instance)->CCR); 8004568: 687b ldr r3, [r7, #4] 800456a: 681b ldr r3, [r3, #0] 800456c: 681b ldr r3, [r3, #0] 800456e: 613b str r3, [r7, #16] /* Half Transfer Complete Interrupt management ******************************/ if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U)) 8004570: 687b ldr r3, [r7, #4] 8004572: 6ddb ldr r3, [r3, #92] ; 0x5c 8004574: f003 031f and.w r3, r3, #31 8004578: 2204 movs r2, #4 800457a: 409a lsls r2, r3 800457c: 697b ldr r3, [r7, #20] 800457e: 4013 ands r3, r2 8004580: 2b00 cmp r3, #0 8004582: f000 80dd beq.w 8004740 8004586: 693b ldr r3, [r7, #16] 8004588: f003 0304 and.w r3, r3, #4 800458c: 2b00 cmp r3, #0 800458e: f000 80d7 beq.w 8004740 { /* Clear the half transfer complete flag */ regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU)); 8004592: 687b ldr r3, [r7, #4] 8004594: 6ddb ldr r3, [r3, #92] ; 0x5c 8004596: f003 031f and.w r3, r3, #31 800459a: 2204 movs r2, #4 800459c: 409a lsls r2, r3 800459e: 69fb ldr r3, [r7, #28] 80045a0: 605a str r2, [r3, #4] /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ if((ccr_reg & BDMA_CCR_DBM) != 0U) 80045a2: 693b ldr r3, [r7, #16] 80045a4: f403 4300 and.w r3, r3, #32768 ; 0x8000 80045a8: 2b00 cmp r3, #0 80045aa: d059 beq.n 8004660 { /* Current memory buffer used is Memory 0 */ if((ccr_reg & BDMA_CCR_CT) == 0U) 80045ac: 693b ldr r3, [r7, #16] 80045ae: f403 3380 and.w r3, r3, #65536 ; 0x10000 80045b2: 2b00 cmp r3, #0 80045b4: d109 bne.n 80045ca { if(hdma->XferM1HalfCpltCallback != NULL) 80045b6: 687b ldr r3, [r7, #4] 80045b8: 6c9b ldr r3, [r3, #72] ; 0x48 80045ba: 2b00 cmp r3, #0 80045bc: f000 8220 beq.w 8004a00 { /* Half transfer Callback for Memory 1 */ hdma->XferM1HalfCpltCallback(hdma); 80045c0: 687b ldr r3, [r7, #4] 80045c2: 6c9b ldr r3, [r3, #72] ; 0x48 80045c4: 6878 ldr r0, [r7, #4] 80045c6: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 80045c8: e21a b.n 8004a00 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferHalfCpltCallback != NULL) 80045ca: 687b ldr r3, [r7, #4] 80045cc: 6c1b ldr r3, [r3, #64] ; 0x40 80045ce: 2b00 cmp r3, #0 80045d0: f000 8216 beq.w 8004a00 { /* Half transfer Callback for Memory 0 */ hdma->XferHalfCpltCallback(hdma); 80045d4: 687b ldr r3, [r7, #4] 80045d6: 6c1b ldr r3, [r3, #64] ; 0x40 80045d8: 6878 ldr r0, [r7, #4] 80045da: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 80045dc: e210 b.n 8004a00 80045de: bf00 nop 80045e0: 40020010 .word 0x40020010 80045e4: 40020028 .word 0x40020028 80045e8: 40020040 .word 0x40020040 80045ec: 40020058 .word 0x40020058 80045f0: 40020070 .word 0x40020070 80045f4: 40020088 .word 0x40020088 80045f8: 400200a0 .word 0x400200a0 80045fc: 400200b8 .word 0x400200b8 8004600: 40020410 .word 0x40020410 8004604: 40020428 .word 0x40020428 8004608: 40020440 .word 0x40020440 800460c: 40020458 .word 0x40020458 8004610: 40020470 .word 0x40020470 8004614: 40020488 .word 0x40020488 8004618: 400204a0 .word 0x400204a0 800461c: 400204b8 .word 0x400204b8 8004620: 48022c08 .word 0x48022c08 8004624: 48022c1c .word 0x48022c1c 8004628: 48022c30 .word 0x48022c30 800462c: 48022c44 .word 0x48022c44 8004630: 48022c58 .word 0x48022c58 8004634: 48022c6c .word 0x48022c6c 8004638: 48022c80 .word 0x48022c80 800463c: 48022c94 .word 0x48022c94 8004640: 58025408 .word 0x58025408 8004644: 5802541c .word 0x5802541c 8004648: 58025430 .word 0x58025430 800464c: 58025444 .word 0x58025444 8004650: 58025458 .word 0x58025458 8004654: 5802546c .word 0x5802546c 8004658: 58025480 .word 0x58025480 800465c: 58025494 .word 0x58025494 } } } else { if((ccr_reg & BDMA_CCR_CIRC) == 0U) 8004660: 693b ldr r3, [r7, #16] 8004662: f003 0320 and.w r3, r3, #32 8004666: 2b00 cmp r3, #0 8004668: d160 bne.n 800472c { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 800466a: 687b ldr r3, [r7, #4] 800466c: 681b ldr r3, [r3, #0] 800466e: 4a8c ldr r2, [pc, #560] ; (80048a0 ) 8004670: 4293 cmp r3, r2 8004672: d04a beq.n 800470a 8004674: 687b ldr r3, [r7, #4] 8004676: 681b ldr r3, [r3, #0] 8004678: 4a8a ldr r2, [pc, #552] ; (80048a4 ) 800467a: 4293 cmp r3, r2 800467c: d045 beq.n 800470a 800467e: 687b ldr r3, [r7, #4] 8004680: 681b ldr r3, [r3, #0] 8004682: 4a89 ldr r2, [pc, #548] ; (80048a8 ) 8004684: 4293 cmp r3, r2 8004686: d040 beq.n 800470a 8004688: 687b ldr r3, [r7, #4] 800468a: 681b ldr r3, [r3, #0] 800468c: 4a87 ldr r2, [pc, #540] ; (80048ac ) 800468e: 4293 cmp r3, r2 8004690: d03b beq.n 800470a 8004692: 687b ldr r3, [r7, #4] 8004694: 681b ldr r3, [r3, #0] 8004696: 4a86 ldr r2, [pc, #536] ; (80048b0 ) 8004698: 4293 cmp r3, r2 800469a: d036 beq.n 800470a 800469c: 687b ldr r3, [r7, #4] 800469e: 681b ldr r3, [r3, #0] 80046a0: 4a84 ldr r2, [pc, #528] ; (80048b4 ) 80046a2: 4293 cmp r3, r2 80046a4: d031 beq.n 800470a 80046a6: 687b ldr r3, [r7, #4] 80046a8: 681b ldr r3, [r3, #0] 80046aa: 4a83 ldr r2, [pc, #524] ; (80048b8 ) 80046ac: 4293 cmp r3, r2 80046ae: d02c beq.n 800470a 80046b0: 687b ldr r3, [r7, #4] 80046b2: 681b ldr r3, [r3, #0] 80046b4: 4a81 ldr r2, [pc, #516] ; (80048bc ) 80046b6: 4293 cmp r3, r2 80046b8: d027 beq.n 800470a 80046ba: 687b ldr r3, [r7, #4] 80046bc: 681b ldr r3, [r3, #0] 80046be: 4a80 ldr r2, [pc, #512] ; (80048c0 ) 80046c0: 4293 cmp r3, r2 80046c2: d022 beq.n 800470a 80046c4: 687b ldr r3, [r7, #4] 80046c6: 681b ldr r3, [r3, #0] 80046c8: 4a7e ldr r2, [pc, #504] ; (80048c4 ) 80046ca: 4293 cmp r3, r2 80046cc: d01d beq.n 800470a 80046ce: 687b ldr r3, [r7, #4] 80046d0: 681b ldr r3, [r3, #0] 80046d2: 4a7d ldr r2, [pc, #500] ; (80048c8 ) 80046d4: 4293 cmp r3, r2 80046d6: d018 beq.n 800470a 80046d8: 687b ldr r3, [r7, #4] 80046da: 681b ldr r3, [r3, #0] 80046dc: 4a7b ldr r2, [pc, #492] ; (80048cc ) 80046de: 4293 cmp r3, r2 80046e0: d013 beq.n 800470a 80046e2: 687b ldr r3, [r7, #4] 80046e4: 681b ldr r3, [r3, #0] 80046e6: 4a7a ldr r2, [pc, #488] ; (80048d0 ) 80046e8: 4293 cmp r3, r2 80046ea: d00e beq.n 800470a 80046ec: 687b ldr r3, [r7, #4] 80046ee: 681b ldr r3, [r3, #0] 80046f0: 4a78 ldr r2, [pc, #480] ; (80048d4 ) 80046f2: 4293 cmp r3, r2 80046f4: d009 beq.n 800470a 80046f6: 687b ldr r3, [r7, #4] 80046f8: 681b ldr r3, [r3, #0] 80046fa: 4a77 ldr r2, [pc, #476] ; (80048d8 ) 80046fc: 4293 cmp r3, r2 80046fe: d004 beq.n 800470a 8004700: 687b ldr r3, [r7, #4] 8004702: 681b ldr r3, [r3, #0] 8004704: 4a75 ldr r2, [pc, #468] ; (80048dc ) 8004706: 4293 cmp r3, r2 8004708: d108 bne.n 800471c 800470a: 687b ldr r3, [r7, #4] 800470c: 681b ldr r3, [r3, #0] 800470e: 681a ldr r2, [r3, #0] 8004710: 687b ldr r3, [r7, #4] 8004712: 681b ldr r3, [r3, #0] 8004714: f022 0208 bic.w r2, r2, #8 8004718: 601a str r2, [r3, #0] 800471a: e007 b.n 800472c 800471c: 687b ldr r3, [r7, #4] 800471e: 681b ldr r3, [r3, #0] 8004720: 681a ldr r2, [r3, #0] 8004722: 687b ldr r3, [r7, #4] 8004724: 681b ldr r3, [r3, #0] 8004726: f022 0204 bic.w r2, r2, #4 800472a: 601a str r2, [r3, #0] } /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if(hdma->XferHalfCpltCallback != NULL) 800472c: 687b ldr r3, [r7, #4] 800472e: 6c1b ldr r3, [r3, #64] ; 0x40 8004730: 2b00 cmp r3, #0 8004732: f000 8165 beq.w 8004a00 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8004736: 687b ldr r3, [r7, #4] 8004738: 6c1b ldr r3, [r3, #64] ; 0x40 800473a: 6878 ldr r0, [r7, #4] 800473c: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800473e: e15f b.n 8004a00 } } } /* Transfer Complete Interrupt management ***********************************/ else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U)) 8004740: 687b ldr r3, [r7, #4] 8004742: 6ddb ldr r3, [r3, #92] ; 0x5c 8004744: f003 031f and.w r3, r3, #31 8004748: 2202 movs r2, #2 800474a: 409a lsls r2, r3 800474c: 697b ldr r3, [r7, #20] 800474e: 4013 ands r3, r2 8004750: 2b00 cmp r3, #0 8004752: f000 80c5 beq.w 80048e0 8004756: 693b ldr r3, [r7, #16] 8004758: f003 0302 and.w r3, r3, #2 800475c: 2b00 cmp r3, #0 800475e: f000 80bf beq.w 80048e0 { /* Clear the transfer complete flag */ regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU); 8004762: 687b ldr r3, [r7, #4] 8004764: 6ddb ldr r3, [r3, #92] ; 0x5c 8004766: f003 031f and.w r3, r3, #31 800476a: 2202 movs r2, #2 800476c: 409a lsls r2, r3 800476e: 69fb ldr r3, [r7, #28] 8004770: 605a str r2, [r3, #4] /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ if((ccr_reg & BDMA_CCR_DBM) != 0U) 8004772: 693b ldr r3, [r7, #16] 8004774: f403 4300 and.w r3, r3, #32768 ; 0x8000 8004778: 2b00 cmp r3, #0 800477a: d018 beq.n 80047ae { /* Current memory buffer used is Memory 0 */ if((ccr_reg & BDMA_CCR_CT) == 0U) 800477c: 693b ldr r3, [r7, #16] 800477e: f403 3380 and.w r3, r3, #65536 ; 0x10000 8004782: 2b00 cmp r3, #0 8004784: d109 bne.n 800479a { if(hdma->XferM1CpltCallback != NULL) 8004786: 687b ldr r3, [r7, #4] 8004788: 6c5b ldr r3, [r3, #68] ; 0x44 800478a: 2b00 cmp r3, #0 800478c: f000 813a beq.w 8004a04 { /* Transfer complete Callback for Memory 1 */ hdma->XferM1CpltCallback(hdma); 8004790: 687b ldr r3, [r7, #4] 8004792: 6c5b ldr r3, [r3, #68] ; 0x44 8004794: 6878 ldr r0, [r7, #4] 8004796: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 8004798: e134 b.n 8004a04 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 800479a: 687b ldr r3, [r7, #4] 800479c: 6bdb ldr r3, [r3, #60] ; 0x3c 800479e: 2b00 cmp r3, #0 80047a0: f000 8130 beq.w 8004a04 { /* Transfer complete Callback for Memory 0 */ hdma->XferCpltCallback(hdma); 80047a4: 687b ldr r3, [r7, #4] 80047a6: 6bdb ldr r3, [r3, #60] ; 0x3c 80047a8: 6878 ldr r0, [r7, #4] 80047aa: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 80047ac: e12a b.n 8004a04 } } } else { if((ccr_reg & BDMA_CCR_CIRC) == 0U) 80047ae: 693b ldr r3, [r7, #16] 80047b0: f003 0320 and.w r3, r3, #32 80047b4: 2b00 cmp r3, #0 80047b6: d168 bne.n 800488a { /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 80047b8: 687b ldr r3, [r7, #4] 80047ba: 681b ldr r3, [r3, #0] 80047bc: 4a38 ldr r2, [pc, #224] ; (80048a0 ) 80047be: 4293 cmp r3, r2 80047c0: d04a beq.n 8004858 80047c2: 687b ldr r3, [r7, #4] 80047c4: 681b ldr r3, [r3, #0] 80047c6: 4a37 ldr r2, [pc, #220] ; (80048a4 ) 80047c8: 4293 cmp r3, r2 80047ca: d045 beq.n 8004858 80047cc: 687b ldr r3, [r7, #4] 80047ce: 681b ldr r3, [r3, #0] 80047d0: 4a35 ldr r2, [pc, #212] ; (80048a8 ) 80047d2: 4293 cmp r3, r2 80047d4: d040 beq.n 8004858 80047d6: 687b ldr r3, [r7, #4] 80047d8: 681b ldr r3, [r3, #0] 80047da: 4a34 ldr r2, [pc, #208] ; (80048ac ) 80047dc: 4293 cmp r3, r2 80047de: d03b beq.n 8004858 80047e0: 687b ldr r3, [r7, #4] 80047e2: 681b ldr r3, [r3, #0] 80047e4: 4a32 ldr r2, [pc, #200] ; (80048b0 ) 80047e6: 4293 cmp r3, r2 80047e8: d036 beq.n 8004858 80047ea: 687b ldr r3, [r7, #4] 80047ec: 681b ldr r3, [r3, #0] 80047ee: 4a31 ldr r2, [pc, #196] ; (80048b4 ) 80047f0: 4293 cmp r3, r2 80047f2: d031 beq.n 8004858 80047f4: 687b ldr r3, [r7, #4] 80047f6: 681b ldr r3, [r3, #0] 80047f8: 4a2f ldr r2, [pc, #188] ; (80048b8 ) 80047fa: 4293 cmp r3, r2 80047fc: d02c beq.n 8004858 80047fe: 687b ldr r3, [r7, #4] 8004800: 681b ldr r3, [r3, #0] 8004802: 4a2e ldr r2, [pc, #184] ; (80048bc ) 8004804: 4293 cmp r3, r2 8004806: d027 beq.n 8004858 8004808: 687b ldr r3, [r7, #4] 800480a: 681b ldr r3, [r3, #0] 800480c: 4a2c ldr r2, [pc, #176] ; (80048c0 ) 800480e: 4293 cmp r3, r2 8004810: d022 beq.n 8004858 8004812: 687b ldr r3, [r7, #4] 8004814: 681b ldr r3, [r3, #0] 8004816: 4a2b ldr r2, [pc, #172] ; (80048c4 ) 8004818: 4293 cmp r3, r2 800481a: d01d beq.n 8004858 800481c: 687b ldr r3, [r7, #4] 800481e: 681b ldr r3, [r3, #0] 8004820: 4a29 ldr r2, [pc, #164] ; (80048c8 ) 8004822: 4293 cmp r3, r2 8004824: d018 beq.n 8004858 8004826: 687b ldr r3, [r7, #4] 8004828: 681b ldr r3, [r3, #0] 800482a: 4a28 ldr r2, [pc, #160] ; (80048cc ) 800482c: 4293 cmp r3, r2 800482e: d013 beq.n 8004858 8004830: 687b ldr r3, [r7, #4] 8004832: 681b ldr r3, [r3, #0] 8004834: 4a26 ldr r2, [pc, #152] ; (80048d0 ) 8004836: 4293 cmp r3, r2 8004838: d00e beq.n 8004858 800483a: 687b ldr r3, [r7, #4] 800483c: 681b ldr r3, [r3, #0] 800483e: 4a25 ldr r2, [pc, #148] ; (80048d4 ) 8004840: 4293 cmp r3, r2 8004842: d009 beq.n 8004858 8004844: 687b ldr r3, [r7, #4] 8004846: 681b ldr r3, [r3, #0] 8004848: 4a23 ldr r2, [pc, #140] ; (80048d8 ) 800484a: 4293 cmp r3, r2 800484c: d004 beq.n 8004858 800484e: 687b ldr r3, [r7, #4] 8004850: 681b ldr r3, [r3, #0] 8004852: 4a22 ldr r2, [pc, #136] ; (80048dc ) 8004854: 4293 cmp r3, r2 8004856: d108 bne.n 800486a 8004858: 687b ldr r3, [r7, #4] 800485a: 681b ldr r3, [r3, #0] 800485c: 681a ldr r2, [r3, #0] 800485e: 687b ldr r3, [r7, #4] 8004860: 681b ldr r3, [r3, #0] 8004862: f022 0214 bic.w r2, r2, #20 8004866: 601a str r2, [r3, #0] 8004868: e007 b.n 800487a 800486a: 687b ldr r3, [r7, #4] 800486c: 681b ldr r3, [r3, #0] 800486e: 681a ldr r2, [r3, #0] 8004870: 687b ldr r3, [r7, #4] 8004872: 681b ldr r3, [r3, #0] 8004874: f022 020a bic.w r2, r2, #10 8004878: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800487a: 687b ldr r3, [r7, #4] 800487c: 2201 movs r2, #1 800487e: f883 2035 strb.w r2, [r3, #53] ; 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8004882: 687b ldr r3, [r7, #4] 8004884: 2200 movs r2, #0 8004886: f883 2034 strb.w r2, [r3, #52] ; 0x34 } if(hdma->XferCpltCallback != NULL) 800488a: 687b ldr r3, [r7, #4] 800488c: 6bdb ldr r3, [r3, #60] ; 0x3c 800488e: 2b00 cmp r3, #0 8004890: f000 80b8 beq.w 8004a04 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8004894: 687b ldr r3, [r7, #4] 8004896: 6bdb ldr r3, [r3, #60] ; 0x3c 8004898: 6878 ldr r0, [r7, #4] 800489a: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800489c: e0b2 b.n 8004a04 800489e: bf00 nop 80048a0: 40020010 .word 0x40020010 80048a4: 40020028 .word 0x40020028 80048a8: 40020040 .word 0x40020040 80048ac: 40020058 .word 0x40020058 80048b0: 40020070 .word 0x40020070 80048b4: 40020088 .word 0x40020088 80048b8: 400200a0 .word 0x400200a0 80048bc: 400200b8 .word 0x400200b8 80048c0: 40020410 .word 0x40020410 80048c4: 40020428 .word 0x40020428 80048c8: 40020440 .word 0x40020440 80048cc: 40020458 .word 0x40020458 80048d0: 40020470 .word 0x40020470 80048d4: 40020488 .word 0x40020488 80048d8: 400204a0 .word 0x400204a0 80048dc: 400204b8 .word 0x400204b8 } } } /* Transfer Error Interrupt management **************************************/ else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U)) 80048e0: 687b ldr r3, [r7, #4] 80048e2: 6ddb ldr r3, [r3, #92] ; 0x5c 80048e4: f003 031f and.w r3, r3, #31 80048e8: 2208 movs r2, #8 80048ea: 409a lsls r2, r3 80048ec: 697b ldr r3, [r7, #20] 80048ee: 4013 ands r3, r2 80048f0: 2b00 cmp r3, #0 80048f2: f000 8088 beq.w 8004a06 80048f6: 693b ldr r3, [r7, #16] 80048f8: f003 0308 and.w r3, r3, #8 80048fc: 2b00 cmp r3, #0 80048fe: f000 8082 beq.w 8004a06 { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8004902: 687b ldr r3, [r7, #4] 8004904: 681b ldr r3, [r3, #0] 8004906: 4a41 ldr r2, [pc, #260] ; (8004a0c ) 8004908: 4293 cmp r3, r2 800490a: d04a beq.n 80049a2 800490c: 687b ldr r3, [r7, #4] 800490e: 681b ldr r3, [r3, #0] 8004910: 4a3f ldr r2, [pc, #252] ; (8004a10 ) 8004912: 4293 cmp r3, r2 8004914: d045 beq.n 80049a2 8004916: 687b ldr r3, [r7, #4] 8004918: 681b ldr r3, [r3, #0] 800491a: 4a3e ldr r2, [pc, #248] ; (8004a14 ) 800491c: 4293 cmp r3, r2 800491e: d040 beq.n 80049a2 8004920: 687b ldr r3, [r7, #4] 8004922: 681b ldr r3, [r3, #0] 8004924: 4a3c ldr r2, [pc, #240] ; (8004a18 ) 8004926: 4293 cmp r3, r2 8004928: d03b beq.n 80049a2 800492a: 687b ldr r3, [r7, #4] 800492c: 681b ldr r3, [r3, #0] 800492e: 4a3b ldr r2, [pc, #236] ; (8004a1c ) 8004930: 4293 cmp r3, r2 8004932: d036 beq.n 80049a2 8004934: 687b ldr r3, [r7, #4] 8004936: 681b ldr r3, [r3, #0] 8004938: 4a39 ldr r2, [pc, #228] ; (8004a20 ) 800493a: 4293 cmp r3, r2 800493c: d031 beq.n 80049a2 800493e: 687b ldr r3, [r7, #4] 8004940: 681b ldr r3, [r3, #0] 8004942: 4a38 ldr r2, [pc, #224] ; (8004a24 ) 8004944: 4293 cmp r3, r2 8004946: d02c beq.n 80049a2 8004948: 687b ldr r3, [r7, #4] 800494a: 681b ldr r3, [r3, #0] 800494c: 4a36 ldr r2, [pc, #216] ; (8004a28 ) 800494e: 4293 cmp r3, r2 8004950: d027 beq.n 80049a2 8004952: 687b ldr r3, [r7, #4] 8004954: 681b ldr r3, [r3, #0] 8004956: 4a35 ldr r2, [pc, #212] ; (8004a2c ) 8004958: 4293 cmp r3, r2 800495a: d022 beq.n 80049a2 800495c: 687b ldr r3, [r7, #4] 800495e: 681b ldr r3, [r3, #0] 8004960: 4a33 ldr r2, [pc, #204] ; (8004a30 ) 8004962: 4293 cmp r3, r2 8004964: d01d beq.n 80049a2 8004966: 687b ldr r3, [r7, #4] 8004968: 681b ldr r3, [r3, #0] 800496a: 4a32 ldr r2, [pc, #200] ; (8004a34 ) 800496c: 4293 cmp r3, r2 800496e: d018 beq.n 80049a2 8004970: 687b ldr r3, [r7, #4] 8004972: 681b ldr r3, [r3, #0] 8004974: 4a30 ldr r2, [pc, #192] ; (8004a38 ) 8004976: 4293 cmp r3, r2 8004978: d013 beq.n 80049a2 800497a: 687b ldr r3, [r7, #4] 800497c: 681b ldr r3, [r3, #0] 800497e: 4a2f ldr r2, [pc, #188] ; (8004a3c ) 8004980: 4293 cmp r3, r2 8004982: d00e beq.n 80049a2 8004984: 687b ldr r3, [r7, #4] 8004986: 681b ldr r3, [r3, #0] 8004988: 4a2d ldr r2, [pc, #180] ; (8004a40 ) 800498a: 4293 cmp r3, r2 800498c: d009 beq.n 80049a2 800498e: 687b ldr r3, [r7, #4] 8004990: 681b ldr r3, [r3, #0] 8004992: 4a2c ldr r2, [pc, #176] ; (8004a44 ) 8004994: 4293 cmp r3, r2 8004996: d004 beq.n 80049a2 8004998: 687b ldr r3, [r7, #4] 800499a: 681b ldr r3, [r3, #0] 800499c: 4a2a ldr r2, [pc, #168] ; (8004a48 ) 800499e: 4293 cmp r3, r2 80049a0: d108 bne.n 80049b4 80049a2: 687b ldr r3, [r7, #4] 80049a4: 681b ldr r3, [r3, #0] 80049a6: 681a ldr r2, [r3, #0] 80049a8: 687b ldr r3, [r7, #4] 80049aa: 681b ldr r3, [r3, #0] 80049ac: f022 021c bic.w r2, r2, #28 80049b0: 601a str r2, [r3, #0] 80049b2: e007 b.n 80049c4 80049b4: 687b ldr r3, [r7, #4] 80049b6: 681b ldr r3, [r3, #0] 80049b8: 681a ldr r2, [r3, #0] 80049ba: 687b ldr r3, [r7, #4] 80049bc: 681b ldr r3, [r3, #0] 80049be: f022 020e bic.w r2, r2, #14 80049c2: 601a str r2, [r3, #0] /* Clear all flags */ regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); 80049c4: 687b ldr r3, [r7, #4] 80049c6: 6ddb ldr r3, [r3, #92] ; 0x5c 80049c8: f003 031f and.w r3, r3, #31 80049cc: 2201 movs r2, #1 80049ce: 409a lsls r2, r3 80049d0: 69fb ldr r3, [r7, #28] 80049d2: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 80049d4: 687b ldr r3, [r7, #4] 80049d6: 2201 movs r2, #1 80049d8: 655a str r2, [r3, #84] ; 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80049da: 687b ldr r3, [r7, #4] 80049dc: 2201 movs r2, #1 80049de: f883 2035 strb.w r2, [r3, #53] ; 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80049e2: 687b ldr r3, [r7, #4] 80049e4: 2200 movs r2, #0 80049e6: f883 2034 strb.w r2, [r3, #52] ; 0x34 if (hdma->XferErrorCallback != NULL) 80049ea: 687b ldr r3, [r7, #4] 80049ec: 6cdb ldr r3, [r3, #76] ; 0x4c 80049ee: 2b00 cmp r3, #0 80049f0: d009 beq.n 8004a06 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 80049f2: 687b ldr r3, [r7, #4] 80049f4: 6cdb ldr r3, [r3, #76] ; 0x4c 80049f6: 6878 ldr r0, [r7, #4] 80049f8: 4798 blx r3 80049fa: e004 b.n 8004a06 return; 80049fc: bf00 nop 80049fe: e002 b.n 8004a06 if((ccr_reg & BDMA_CCR_DBM) != 0U) 8004a00: bf00 nop 8004a02: e000 b.n 8004a06 if((ccr_reg & BDMA_CCR_DBM) != 0U) 8004a04: bf00 nop } else { /* Nothing To Do */ } } 8004a06: 3728 adds r7, #40 ; 0x28 8004a08: 46bd mov sp, r7 8004a0a: bd80 pop {r7, pc} 8004a0c: 40020010 .word 0x40020010 8004a10: 40020028 .word 0x40020028 8004a14: 40020040 .word 0x40020040 8004a18: 40020058 .word 0x40020058 8004a1c: 40020070 .word 0x40020070 8004a20: 40020088 .word 0x40020088 8004a24: 400200a0 .word 0x400200a0 8004a28: 400200b8 .word 0x400200b8 8004a2c: 40020410 .word 0x40020410 8004a30: 40020428 .word 0x40020428 8004a34: 40020440 .word 0x40020440 8004a38: 40020458 .word 0x40020458 8004a3c: 40020470 .word 0x40020470 8004a40: 40020488 .word 0x40020488 8004a44: 400204a0 .word 0x400204a0 8004a48: 400204b8 .word 0x400204b8 08004a4c : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval Stream base address */ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { 8004a4c: b480 push {r7} 8004a4e: b085 sub sp, #20 8004a50: af00 add r7, sp, #0 8004a52: 6078 str r0, [r7, #4] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8004a54: 687b ldr r3, [r7, #4] 8004a56: 681b ldr r3, [r3, #0] 8004a58: 4a42 ldr r2, [pc, #264] ; (8004b64 ) 8004a5a: 4293 cmp r3, r2 8004a5c: d04a beq.n 8004af4 8004a5e: 687b ldr r3, [r7, #4] 8004a60: 681b ldr r3, [r3, #0] 8004a62: 4a41 ldr r2, [pc, #260] ; (8004b68 ) 8004a64: 4293 cmp r3, r2 8004a66: d045 beq.n 8004af4 8004a68: 687b ldr r3, [r7, #4] 8004a6a: 681b ldr r3, [r3, #0] 8004a6c: 4a3f ldr r2, [pc, #252] ; (8004b6c ) 8004a6e: 4293 cmp r3, r2 8004a70: d040 beq.n 8004af4 8004a72: 687b ldr r3, [r7, #4] 8004a74: 681b ldr r3, [r3, #0] 8004a76: 4a3e ldr r2, [pc, #248] ; (8004b70 ) 8004a78: 4293 cmp r3, r2 8004a7a: d03b beq.n 8004af4 8004a7c: 687b ldr r3, [r7, #4] 8004a7e: 681b ldr r3, [r3, #0] 8004a80: 4a3c ldr r2, [pc, #240] ; (8004b74 ) 8004a82: 4293 cmp r3, r2 8004a84: d036 beq.n 8004af4 8004a86: 687b ldr r3, [r7, #4] 8004a88: 681b ldr r3, [r3, #0] 8004a8a: 4a3b ldr r2, [pc, #236] ; (8004b78 ) 8004a8c: 4293 cmp r3, r2 8004a8e: d031 beq.n 8004af4 8004a90: 687b ldr r3, [r7, #4] 8004a92: 681b ldr r3, [r3, #0] 8004a94: 4a39 ldr r2, [pc, #228] ; (8004b7c ) 8004a96: 4293 cmp r3, r2 8004a98: d02c beq.n 8004af4 8004a9a: 687b ldr r3, [r7, #4] 8004a9c: 681b ldr r3, [r3, #0] 8004a9e: 4a38 ldr r2, [pc, #224] ; (8004b80 ) 8004aa0: 4293 cmp r3, r2 8004aa2: d027 beq.n 8004af4 8004aa4: 687b ldr r3, [r7, #4] 8004aa6: 681b ldr r3, [r3, #0] 8004aa8: 4a36 ldr r2, [pc, #216] ; (8004b84 ) 8004aaa: 4293 cmp r3, r2 8004aac: d022 beq.n 8004af4 8004aae: 687b ldr r3, [r7, #4] 8004ab0: 681b ldr r3, [r3, #0] 8004ab2: 4a35 ldr r2, [pc, #212] ; (8004b88 ) 8004ab4: 4293 cmp r3, r2 8004ab6: d01d beq.n 8004af4 8004ab8: 687b ldr r3, [r7, #4] 8004aba: 681b ldr r3, [r3, #0] 8004abc: 4a33 ldr r2, [pc, #204] ; (8004b8c ) 8004abe: 4293 cmp r3, r2 8004ac0: d018 beq.n 8004af4 8004ac2: 687b ldr r3, [r7, #4] 8004ac4: 681b ldr r3, [r3, #0] 8004ac6: 4a32 ldr r2, [pc, #200] ; (8004b90 ) 8004ac8: 4293 cmp r3, r2 8004aca: d013 beq.n 8004af4 8004acc: 687b ldr r3, [r7, #4] 8004ace: 681b ldr r3, [r3, #0] 8004ad0: 4a30 ldr r2, [pc, #192] ; (8004b94 ) 8004ad2: 4293 cmp r3, r2 8004ad4: d00e beq.n 8004af4 8004ad6: 687b ldr r3, [r7, #4] 8004ad8: 681b ldr r3, [r3, #0] 8004ada: 4a2f ldr r2, [pc, #188] ; (8004b98 ) 8004adc: 4293 cmp r3, r2 8004ade: d009 beq.n 8004af4 8004ae0: 687b ldr r3, [r7, #4] 8004ae2: 681b ldr r3, [r3, #0] 8004ae4: 4a2d ldr r2, [pc, #180] ; (8004b9c ) 8004ae6: 4293 cmp r3, r2 8004ae8: d004 beq.n 8004af4 8004aea: 687b ldr r3, [r7, #4] 8004aec: 681b ldr r3, [r3, #0] 8004aee: 4a2c ldr r2, [pc, #176] ; (8004ba0 ) 8004af0: 4293 cmp r3, r2 8004af2: d101 bne.n 8004af8 8004af4: 2301 movs r3, #1 8004af6: e000 b.n 8004afa 8004af8: 2300 movs r3, #0 8004afa: 2b00 cmp r3, #0 8004afc: d024 beq.n 8004b48 { uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 8004afe: 687b ldr r3, [r7, #4] 8004b00: 681b ldr r3, [r3, #0] 8004b02: b2db uxtb r3, r3 8004b04: 3b10 subs r3, #16 8004b06: 4a27 ldr r2, [pc, #156] ; (8004ba4 ) 8004b08: fba2 2303 umull r2, r3, r2, r3 8004b0c: 091b lsrs r3, r3, #4 8004b0e: 60fb str r3, [r7, #12] /* lookup table for necessary bitshift of flags within status registers */ static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U]; 8004b10: 68fb ldr r3, [r7, #12] 8004b12: f003 0307 and.w r3, r3, #7 8004b16: 4a24 ldr r2, [pc, #144] ; (8004ba8 ) 8004b18: 5cd3 ldrb r3, [r2, r3] 8004b1a: 461a mov r2, r3 8004b1c: 687b ldr r3, [r7, #4] 8004b1e: 65da str r2, [r3, #92] ; 0x5c if (stream_number > 3U) 8004b20: 68fb ldr r3, [r7, #12] 8004b22: 2b03 cmp r3, #3 8004b24: d908 bls.n 8004b38 { /* return pointer to HISR and HIFCR */ hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U); 8004b26: 687b ldr r3, [r7, #4] 8004b28: 681b ldr r3, [r3, #0] 8004b2a: 461a mov r2, r3 8004b2c: 4b1f ldr r3, [pc, #124] ; (8004bac ) 8004b2e: 4013 ands r3, r2 8004b30: 1d1a adds r2, r3, #4 8004b32: 687b ldr r3, [r7, #4] 8004b34: 659a str r2, [r3, #88] ; 0x58 8004b36: e00d b.n 8004b54 } else { /* return pointer to LISR and LIFCR */ hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)); 8004b38: 687b ldr r3, [r7, #4] 8004b3a: 681b ldr r3, [r3, #0] 8004b3c: 461a mov r2, r3 8004b3e: 4b1b ldr r3, [pc, #108] ; (8004bac ) 8004b40: 4013 ands r3, r2 8004b42: 687a ldr r2, [r7, #4] 8004b44: 6593 str r3, [r2, #88] ; 0x58 8004b46: e005 b.n 8004b54 } } else /* BDMA instance(s) */ { /* return pointer to ISR and IFCR */ hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU)); 8004b48: 687b ldr r3, [r7, #4] 8004b4a: 681b ldr r3, [r3, #0] 8004b4c: f023 02ff bic.w r2, r3, #255 ; 0xff 8004b50: 687b ldr r3, [r7, #4] 8004b52: 659a str r2, [r3, #88] ; 0x58 } return hdma->StreamBaseAddress; 8004b54: 687b ldr r3, [r7, #4] 8004b56: 6d9b ldr r3, [r3, #88] ; 0x58 } 8004b58: 4618 mov r0, r3 8004b5a: 3714 adds r7, #20 8004b5c: 46bd mov sp, r7 8004b5e: f85d 7b04 ldr.w r7, [sp], #4 8004b62: 4770 bx lr 8004b64: 40020010 .word 0x40020010 8004b68: 40020028 .word 0x40020028 8004b6c: 40020040 .word 0x40020040 8004b70: 40020058 .word 0x40020058 8004b74: 40020070 .word 0x40020070 8004b78: 40020088 .word 0x40020088 8004b7c: 400200a0 .word 0x400200a0 8004b80: 400200b8 .word 0x400200b8 8004b84: 40020410 .word 0x40020410 8004b88: 40020428 .word 0x40020428 8004b8c: 40020440 .word 0x40020440 8004b90: 40020458 .word 0x40020458 8004b94: 40020470 .word 0x40020470 8004b98: 40020488 .word 0x40020488 8004b9c: 400204a0 .word 0x400204a0 8004ba0: 400204b8 .word 0x400204b8 8004ba4: aaaaaaab .word 0xaaaaaaab 8004ba8: 0800e65c .word 0x0800e65c 8004bac: fffffc00 .word 0xfffffc00 08004bb0 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) { 8004bb0: b480 push {r7} 8004bb2: b085 sub sp, #20 8004bb4: af00 add r7, sp, #0 8004bb6: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8004bb8: 2300 movs r3, #0 8004bba: 73fb strb r3, [r7, #15] /* Memory Data size equal to Byte */ if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) 8004bbc: 687b ldr r3, [r7, #4] 8004bbe: 699b ldr r3, [r3, #24] 8004bc0: 2b00 cmp r3, #0 8004bc2: d120 bne.n 8004c06 { switch (hdma->Init.FIFOThreshold) 8004bc4: 687b ldr r3, [r7, #4] 8004bc6: 6a9b ldr r3, [r3, #40] ; 0x28 8004bc8: 2b03 cmp r3, #3 8004bca: d858 bhi.n 8004c7e 8004bcc: a201 add r2, pc, #4 ; (adr r2, 8004bd4 ) 8004bce: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004bd2: bf00 nop 8004bd4: 08004be5 .word 0x08004be5 8004bd8: 08004bf7 .word 0x08004bf7 8004bdc: 08004be5 .word 0x08004be5 8004be0: 08004c7f .word 0x08004c7f { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8004be4: 687b ldr r3, [r7, #4] 8004be6: 6adb ldr r3, [r3, #44] ; 0x2c 8004be8: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 8004bec: 2b00 cmp r3, #0 8004bee: d048 beq.n 8004c82 { status = HAL_ERROR; 8004bf0: 2301 movs r3, #1 8004bf2: 73fb strb r3, [r7, #15] } break; 8004bf4: e045 b.n 8004c82 case DMA_FIFO_THRESHOLD_HALFFULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 8004bf6: 687b ldr r3, [r7, #4] 8004bf8: 6adb ldr r3, [r3, #44] ; 0x2c 8004bfa: f1b3 7fc0 cmp.w r3, #25165824 ; 0x1800000 8004bfe: d142 bne.n 8004c86 { status = HAL_ERROR; 8004c00: 2301 movs r3, #1 8004c02: 73fb strb r3, [r7, #15] } break; 8004c04: e03f b.n 8004c86 break; } } /* Memory Data size equal to Half-Word */ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) 8004c06: 687b ldr r3, [r7, #4] 8004c08: 699b ldr r3, [r3, #24] 8004c0a: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 8004c0e: d123 bne.n 8004c58 { switch (hdma->Init.FIFOThreshold) 8004c10: 687b ldr r3, [r7, #4] 8004c12: 6a9b ldr r3, [r3, #40] ; 0x28 8004c14: 2b03 cmp r3, #3 8004c16: d838 bhi.n 8004c8a 8004c18: a201 add r2, pc, #4 ; (adr r2, 8004c20 ) 8004c1a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004c1e: bf00 nop 8004c20: 08004c31 .word 0x08004c31 8004c24: 08004c37 .word 0x08004c37 8004c28: 08004c31 .word 0x08004c31 8004c2c: 08004c49 .word 0x08004c49 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: status = HAL_ERROR; 8004c30: 2301 movs r3, #1 8004c32: 73fb strb r3, [r7, #15] break; 8004c34: e030 b.n 8004c98 case DMA_FIFO_THRESHOLD_HALFFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8004c36: 687b ldr r3, [r7, #4] 8004c38: 6adb ldr r3, [r3, #44] ; 0x2c 8004c3a: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 8004c3e: 2b00 cmp r3, #0 8004c40: d025 beq.n 8004c8e { status = HAL_ERROR; 8004c42: 2301 movs r3, #1 8004c44: 73fb strb r3, [r7, #15] } break; 8004c46: e022 b.n 8004c8e case DMA_FIFO_THRESHOLD_FULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 8004c48: 687b ldr r3, [r7, #4] 8004c4a: 6adb ldr r3, [r3, #44] ; 0x2c 8004c4c: f1b3 7fc0 cmp.w r3, #25165824 ; 0x1800000 8004c50: d11f bne.n 8004c92 { status = HAL_ERROR; 8004c52: 2301 movs r3, #1 8004c54: 73fb strb r3, [r7, #15] } break; 8004c56: e01c b.n 8004c92 } /* Memory Data size equal to Word */ else { switch (hdma->Init.FIFOThreshold) 8004c58: 687b ldr r3, [r7, #4] 8004c5a: 6a9b ldr r3, [r3, #40] ; 0x28 8004c5c: 2b02 cmp r3, #2 8004c5e: d902 bls.n 8004c66 8004c60: 2b03 cmp r3, #3 8004c62: d003 beq.n 8004c6c status = HAL_ERROR; } break; default: break; 8004c64: e018 b.n 8004c98 status = HAL_ERROR; 8004c66: 2301 movs r3, #1 8004c68: 73fb strb r3, [r7, #15] break; 8004c6a: e015 b.n 8004c98 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8004c6c: 687b ldr r3, [r7, #4] 8004c6e: 6adb ldr r3, [r3, #44] ; 0x2c 8004c70: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 8004c74: 2b00 cmp r3, #0 8004c76: d00e beq.n 8004c96 status = HAL_ERROR; 8004c78: 2301 movs r3, #1 8004c7a: 73fb strb r3, [r7, #15] break; 8004c7c: e00b b.n 8004c96 break; 8004c7e: bf00 nop 8004c80: e00a b.n 8004c98 break; 8004c82: bf00 nop 8004c84: e008 b.n 8004c98 break; 8004c86: bf00 nop 8004c88: e006 b.n 8004c98 break; 8004c8a: bf00 nop 8004c8c: e004 b.n 8004c98 break; 8004c8e: bf00 nop 8004c90: e002 b.n 8004c98 break; 8004c92: bf00 nop 8004c94: e000 b.n 8004c98 break; 8004c96: bf00 nop } } return status; 8004c98: 7bfb ldrb r3, [r7, #15] } 8004c9a: 4618 mov r0, r3 8004c9c: 3714 adds r7, #20 8004c9e: 46bd mov sp, r7 8004ca0: f85d 7b04 ldr.w r7, [sp], #4 8004ca4: 4770 bx lr 8004ca6: bf00 nop 08004ca8 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) { 8004ca8: b480 push {r7} 8004caa: b085 sub sp, #20 8004cac: af00 add r7, sp, #0 8004cae: 6078 str r0, [r7, #4] uint32_t stream_number; uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance); 8004cb0: 687b ldr r3, [r7, #4] 8004cb2: 681b ldr r3, [r3, #0] 8004cb4: 60bb str r3, [r7, #8] if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 8004cb6: 687b ldr r3, [r7, #4] 8004cb8: 681b ldr r3, [r3, #0] 8004cba: 4a38 ldr r2, [pc, #224] ; (8004d9c ) 8004cbc: 4293 cmp r3, r2 8004cbe: d022 beq.n 8004d06 8004cc0: 687b ldr r3, [r7, #4] 8004cc2: 681b ldr r3, [r3, #0] 8004cc4: 4a36 ldr r2, [pc, #216] ; (8004da0 ) 8004cc6: 4293 cmp r3, r2 8004cc8: d01d beq.n 8004d06 8004cca: 687b ldr r3, [r7, #4] 8004ccc: 681b ldr r3, [r3, #0] 8004cce: 4a35 ldr r2, [pc, #212] ; (8004da4 ) 8004cd0: 4293 cmp r3, r2 8004cd2: d018 beq.n 8004d06 8004cd4: 687b ldr r3, [r7, #4] 8004cd6: 681b ldr r3, [r3, #0] 8004cd8: 4a33 ldr r2, [pc, #204] ; (8004da8 ) 8004cda: 4293 cmp r3, r2 8004cdc: d013 beq.n 8004d06 8004cde: 687b ldr r3, [r7, #4] 8004ce0: 681b ldr r3, [r3, #0] 8004ce2: 4a32 ldr r2, [pc, #200] ; (8004dac ) 8004ce4: 4293 cmp r3, r2 8004ce6: d00e beq.n 8004d06 8004ce8: 687b ldr r3, [r7, #4] 8004cea: 681b ldr r3, [r3, #0] 8004cec: 4a30 ldr r2, [pc, #192] ; (8004db0 ) 8004cee: 4293 cmp r3, r2 8004cf0: d009 beq.n 8004d06 8004cf2: 687b ldr r3, [r7, #4] 8004cf4: 681b ldr r3, [r3, #0] 8004cf6: 4a2f ldr r2, [pc, #188] ; (8004db4 ) 8004cf8: 4293 cmp r3, r2 8004cfa: d004 beq.n 8004d06 8004cfc: 687b ldr r3, [r7, #4] 8004cfe: 681b ldr r3, [r3, #0] 8004d00: 4a2d ldr r2, [pc, #180] ; (8004db8 ) 8004d02: 4293 cmp r3, r2 8004d04: d101 bne.n 8004d0a 8004d06: 2301 movs r3, #1 8004d08: e000 b.n 8004d0c 8004d0a: 2300 movs r3, #0 8004d0c: 2b00 cmp r3, #0 8004d0e: d01a beq.n 8004d46 { /* BDMA Channels are connected to DMAMUX2 channels */ stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U; 8004d10: 687b ldr r3, [r7, #4] 8004d12: 681b ldr r3, [r3, #0] 8004d14: b2db uxtb r3, r3 8004d16: 3b08 subs r3, #8 8004d18: 4a28 ldr r2, [pc, #160] ; (8004dbc ) 8004d1a: fba2 2303 umull r2, r3, r2, r3 8004d1e: 091b lsrs r3, r3, #4 8004d20: 60fb str r3, [r7, #12] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U))); 8004d22: 68fa ldr r2, [r7, #12] 8004d24: 4b26 ldr r3, [pc, #152] ; (8004dc0 ) 8004d26: 4413 add r3, r2 8004d28: 009b lsls r3, r3, #2 8004d2a: 461a mov r2, r3 8004d2c: 687b ldr r3, [r7, #4] 8004d2e: 661a str r2, [r3, #96] ; 0x60 hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus; 8004d30: 687b ldr r3, [r7, #4] 8004d32: 4a24 ldr r2, [pc, #144] ; (8004dc4 ) 8004d34: 665a str r2, [r3, #100] ; 0x64 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 8004d36: 68fb ldr r3, [r7, #12] 8004d38: f003 031f and.w r3, r3, #31 8004d3c: 2201 movs r2, #1 8004d3e: 409a lsls r2, r3 8004d40: 687b ldr r3, [r7, #4] 8004d42: 669a str r2, [r3, #104] ; 0x68 } hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); } } 8004d44: e024 b.n 8004d90 stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 8004d46: 687b ldr r3, [r7, #4] 8004d48: 681b ldr r3, [r3, #0] 8004d4a: b2db uxtb r3, r3 8004d4c: 3b10 subs r3, #16 8004d4e: 4a1e ldr r2, [pc, #120] ; (8004dc8 ) 8004d50: fba2 2303 umull r2, r3, r2, r3 8004d54: 091b lsrs r3, r3, #4 8004d56: 60fb str r3, [r7, #12] if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \ 8004d58: 68bb ldr r3, [r7, #8] 8004d5a: 4a1c ldr r2, [pc, #112] ; (8004dcc ) 8004d5c: 4293 cmp r3, r2 8004d5e: d806 bhi.n 8004d6e 8004d60: 68bb ldr r3, [r7, #8] 8004d62: 4a1b ldr r2, [pc, #108] ; (8004dd0 ) 8004d64: 4293 cmp r3, r2 8004d66: d902 bls.n 8004d6e stream_number += 8U; 8004d68: 68fb ldr r3, [r7, #12] 8004d6a: 3308 adds r3, #8 8004d6c: 60fb str r3, [r7, #12] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); 8004d6e: 68fa ldr r2, [r7, #12] 8004d70: 4b18 ldr r3, [pc, #96] ; (8004dd4 ) 8004d72: 4413 add r3, r2 8004d74: 009b lsls r3, r3, #2 8004d76: 461a mov r2, r3 8004d78: 687b ldr r3, [r7, #4] 8004d7a: 661a str r2, [r3, #96] ; 0x60 hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; 8004d7c: 687b ldr r3, [r7, #4] 8004d7e: 4a16 ldr r2, [pc, #88] ; (8004dd8 ) 8004d80: 665a str r2, [r3, #100] ; 0x64 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 8004d82: 68fb ldr r3, [r7, #12] 8004d84: f003 031f and.w r3, r3, #31 8004d88: 2201 movs r2, #1 8004d8a: 409a lsls r2, r3 8004d8c: 687b ldr r3, [r7, #4] 8004d8e: 669a str r2, [r3, #104] ; 0x68 } 8004d90: bf00 nop 8004d92: 3714 adds r7, #20 8004d94: 46bd mov sp, r7 8004d96: f85d 7b04 ldr.w r7, [sp], #4 8004d9a: 4770 bx lr 8004d9c: 58025408 .word 0x58025408 8004da0: 5802541c .word 0x5802541c 8004da4: 58025430 .word 0x58025430 8004da8: 58025444 .word 0x58025444 8004dac: 58025458 .word 0x58025458 8004db0: 5802546c .word 0x5802546c 8004db4: 58025480 .word 0x58025480 8004db8: 58025494 .word 0x58025494 8004dbc: cccccccd .word 0xcccccccd 8004dc0: 16009600 .word 0x16009600 8004dc4: 58025880 .word 0x58025880 8004dc8: aaaaaaab .word 0xaaaaaaab 8004dcc: 400204b8 .word 0x400204b8 8004dd0: 4002040f .word 0x4002040f 8004dd4: 10008200 .word 0x10008200 8004dd8: 40020880 .word 0x40020880 08004ddc : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) { 8004ddc: b480 push {r7} 8004dde: b085 sub sp, #20 8004de0: af00 add r7, sp, #0 8004de2: 6078 str r0, [r7, #4] uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; 8004de4: 687b ldr r3, [r7, #4] 8004de6: 685b ldr r3, [r3, #4] 8004de8: b2db uxtb r3, r3 8004dea: 60fb str r3, [r7, #12] if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7)) 8004dec: 68fb ldr r3, [r7, #12] 8004dee: 2b00 cmp r3, #0 8004df0: d04a beq.n 8004e88 8004df2: 68fb ldr r3, [r7, #12] 8004df4: 2b08 cmp r3, #8 8004df6: d847 bhi.n 8004e88 { if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 8004df8: 687b ldr r3, [r7, #4] 8004dfa: 681b ldr r3, [r3, #0] 8004dfc: 4a25 ldr r2, [pc, #148] ; (8004e94 ) 8004dfe: 4293 cmp r3, r2 8004e00: d022 beq.n 8004e48 8004e02: 687b ldr r3, [r7, #4] 8004e04: 681b ldr r3, [r3, #0] 8004e06: 4a24 ldr r2, [pc, #144] ; (8004e98 ) 8004e08: 4293 cmp r3, r2 8004e0a: d01d beq.n 8004e48 8004e0c: 687b ldr r3, [r7, #4] 8004e0e: 681b ldr r3, [r3, #0] 8004e10: 4a22 ldr r2, [pc, #136] ; (8004e9c ) 8004e12: 4293 cmp r3, r2 8004e14: d018 beq.n 8004e48 8004e16: 687b ldr r3, [r7, #4] 8004e18: 681b ldr r3, [r3, #0] 8004e1a: 4a21 ldr r2, [pc, #132] ; (8004ea0 ) 8004e1c: 4293 cmp r3, r2 8004e1e: d013 beq.n 8004e48 8004e20: 687b ldr r3, [r7, #4] 8004e22: 681b ldr r3, [r3, #0] 8004e24: 4a1f ldr r2, [pc, #124] ; (8004ea4 ) 8004e26: 4293 cmp r3, r2 8004e28: d00e beq.n 8004e48 8004e2a: 687b ldr r3, [r7, #4] 8004e2c: 681b ldr r3, [r3, #0] 8004e2e: 4a1e ldr r2, [pc, #120] ; (8004ea8 ) 8004e30: 4293 cmp r3, r2 8004e32: d009 beq.n 8004e48 8004e34: 687b ldr r3, [r7, #4] 8004e36: 681b ldr r3, [r3, #0] 8004e38: 4a1c ldr r2, [pc, #112] ; (8004eac ) 8004e3a: 4293 cmp r3, r2 8004e3c: d004 beq.n 8004e48 8004e3e: 687b ldr r3, [r7, #4] 8004e40: 681b ldr r3, [r3, #0] 8004e42: 4a1b ldr r2, [pc, #108] ; (8004eb0 ) 8004e44: 4293 cmp r3, r2 8004e46: d101 bne.n 8004e4c 8004e48: 2301 movs r3, #1 8004e4a: e000 b.n 8004e4e 8004e4c: 2300 movs r3, #0 8004e4e: 2b00 cmp r3, #0 8004e50: d00a beq.n 8004e68 { /* BDMA Channels are connected to DMAMUX2 request generator blocks */ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U))); 8004e52: 68fa ldr r2, [r7, #12] 8004e54: 4b17 ldr r3, [pc, #92] ; (8004eb4 ) 8004e56: 4413 add r3, r2 8004e58: 009b lsls r3, r3, #2 8004e5a: 461a mov r2, r3 8004e5c: 687b ldr r3, [r7, #4] 8004e5e: 66da str r2, [r3, #108] ; 0x6c hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus; 8004e60: 687b ldr r3, [r7, #4] 8004e62: 4a15 ldr r2, [pc, #84] ; (8004eb8 ) 8004e64: 671a str r2, [r3, #112] ; 0x70 8004e66: e009 b.n 8004e7c } else { /* DMA1 and DMA2 Streams use DMAMUX1 request generator blocks */ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); 8004e68: 68fa ldr r2, [r7, #12] 8004e6a: 4b14 ldr r3, [pc, #80] ; (8004ebc ) 8004e6c: 4413 add r3, r2 8004e6e: 009b lsls r3, r3, #2 8004e70: 461a mov r2, r3 8004e72: 687b ldr r3, [r7, #4] 8004e74: 66da str r2, [r3, #108] ; 0x6c hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; 8004e76: 687b ldr r3, [r7, #4] 8004e78: 4a11 ldr r2, [pc, #68] ; (8004ec0 ) 8004e7a: 671a str r2, [r3, #112] ; 0x70 } hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U); 8004e7c: 68fb ldr r3, [r7, #12] 8004e7e: 3b01 subs r3, #1 8004e80: 2201 movs r2, #1 8004e82: 409a lsls r2, r3 8004e84: 687b ldr r3, [r7, #4] 8004e86: 675a str r2, [r3, #116] ; 0x74 } } 8004e88: bf00 nop 8004e8a: 3714 adds r7, #20 8004e8c: 46bd mov sp, r7 8004e8e: f85d 7b04 ldr.w r7, [sp], #4 8004e92: 4770 bx lr 8004e94: 58025408 .word 0x58025408 8004e98: 5802541c .word 0x5802541c 8004e9c: 58025430 .word 0x58025430 8004ea0: 58025444 .word 0x58025444 8004ea4: 58025458 .word 0x58025458 8004ea8: 5802546c .word 0x5802546c 8004eac: 58025480 .word 0x58025480 8004eb0: 58025494 .word 0x58025494 8004eb4: 1600963f .word 0x1600963f 8004eb8: 58025940 .word 0x58025940 8004ebc: 1000823f .word 0x1000823f 8004ec0: 40020940 .word 0x40020940 08004ec4 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8004ec4: b480 push {r7} 8004ec6: b089 sub sp, #36 ; 0x24 8004ec8: af00 add r7, sp, #0 8004eca: 6078 str r0, [r7, #4] 8004ecc: 6039 str r1, [r7, #0] uint32_t position = 0x00U; 8004ece: 2300 movs r3, #0 8004ed0: 61fb str r3, [r7, #28] EXTI_Core_TypeDef *EXTI_CurrentCPU; #if defined(DUAL_CORE) && defined(CORE_CM4) EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */ #else EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */ 8004ed2: 4b89 ldr r3, [pc, #548] ; (80050f8 ) 8004ed4: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00U) 8004ed6: e194 b.n 8005202 { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1UL << position); 8004ed8: 683b ldr r3, [r7, #0] 8004eda: 681a ldr r2, [r3, #0] 8004edc: 2101 movs r1, #1 8004ede: 69fb ldr r3, [r7, #28] 8004ee0: fa01 f303 lsl.w r3, r1, r3 8004ee4: 4013 ands r3, r2 8004ee6: 613b str r3, [r7, #16] if (iocurrent != 0x00U) 8004ee8: 693b ldr r3, [r7, #16] 8004eea: 2b00 cmp r3, #0 8004eec: f000 8186 beq.w 80051fc { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 8004ef0: 683b ldr r3, [r7, #0] 8004ef2: 685b ldr r3, [r3, #4] 8004ef4: f003 0303 and.w r3, r3, #3 8004ef8: 2b01 cmp r3, #1 8004efa: d005 beq.n 8004f08 8004efc: 683b ldr r3, [r7, #0] 8004efe: 685b ldr r3, [r3, #4] 8004f00: f003 0303 and.w r3, r3, #3 8004f04: 2b02 cmp r3, #2 8004f06: d130 bne.n 8004f6a { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8004f08: 687b ldr r3, [r7, #4] 8004f0a: 689b ldr r3, [r3, #8] 8004f0c: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 8004f0e: 69fb ldr r3, [r7, #28] 8004f10: 005b lsls r3, r3, #1 8004f12: 2203 movs r2, #3 8004f14: fa02 f303 lsl.w r3, r2, r3 8004f18: 43db mvns r3, r3 8004f1a: 69ba ldr r2, [r7, #24] 8004f1c: 4013 ands r3, r2 8004f1e: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 8004f20: 683b ldr r3, [r7, #0] 8004f22: 68da ldr r2, [r3, #12] 8004f24: 69fb ldr r3, [r7, #28] 8004f26: 005b lsls r3, r3, #1 8004f28: fa02 f303 lsl.w r3, r2, r3 8004f2c: 69ba ldr r2, [r7, #24] 8004f2e: 4313 orrs r3, r2 8004f30: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 8004f32: 687b ldr r3, [r7, #4] 8004f34: 69ba ldr r2, [r7, #24] 8004f36: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8004f38: 687b ldr r3, [r7, #4] 8004f3a: 685b ldr r3, [r3, #4] 8004f3c: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT0 << position) ; 8004f3e: 2201 movs r2, #1 8004f40: 69fb ldr r3, [r7, #28] 8004f42: fa02 f303 lsl.w r3, r2, r3 8004f46: 43db mvns r3, r3 8004f48: 69ba ldr r2, [r7, #24] 8004f4a: 4013 ands r3, r2 8004f4c: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8004f4e: 683b ldr r3, [r7, #0] 8004f50: 685b ldr r3, [r3, #4] 8004f52: 091b lsrs r3, r3, #4 8004f54: f003 0201 and.w r2, r3, #1 8004f58: 69fb ldr r3, [r7, #28] 8004f5a: fa02 f303 lsl.w r3, r2, r3 8004f5e: 69ba ldr r2, [r7, #24] 8004f60: 4313 orrs r3, r2 8004f62: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 8004f64: 687b ldr r3, [r7, #4] 8004f66: 69ba ldr r2, [r7, #24] 8004f68: 605a str r2, [r3, #4] } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8004f6a: 683b ldr r3, [r7, #0] 8004f6c: 685b ldr r3, [r3, #4] 8004f6e: f003 0303 and.w r3, r3, #3 8004f72: 2b03 cmp r3, #3 8004f74: d017 beq.n 8004fa6 { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8004f76: 687b ldr r3, [r7, #4] 8004f78: 68db ldr r3, [r3, #12] 8004f7a: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 8004f7c: 69fb ldr r3, [r7, #28] 8004f7e: 005b lsls r3, r3, #1 8004f80: 2203 movs r2, #3 8004f82: fa02 f303 lsl.w r3, r2, r3 8004f86: 43db mvns r3, r3 8004f88: 69ba ldr r2, [r7, #24] 8004f8a: 4013 ands r3, r2 8004f8c: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 8004f8e: 683b ldr r3, [r7, #0] 8004f90: 689a ldr r2, [r3, #8] 8004f92: 69fb ldr r3, [r7, #28] 8004f94: 005b lsls r3, r3, #1 8004f96: fa02 f303 lsl.w r3, r2, r3 8004f9a: 69ba ldr r2, [r7, #24] 8004f9c: 4313 orrs r3, r2 8004f9e: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 8004fa0: 687b ldr r3, [r7, #4] 8004fa2: 69ba ldr r2, [r7, #24] 8004fa4: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8004fa6: 683b ldr r3, [r7, #0] 8004fa8: 685b ldr r3, [r3, #4] 8004faa: f003 0303 and.w r3, r3, #3 8004fae: 2b02 cmp r3, #2 8004fb0: d123 bne.n 8004ffa /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 8004fb2: 69fb ldr r3, [r7, #28] 8004fb4: 08da lsrs r2, r3, #3 8004fb6: 687b ldr r3, [r7, #4] 8004fb8: 3208 adds r2, #8 8004fba: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8004fbe: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((position & 0x07U) * 4U)); 8004fc0: 69fb ldr r3, [r7, #28] 8004fc2: f003 0307 and.w r3, r3, #7 8004fc6: 009b lsls r3, r3, #2 8004fc8: 220f movs r2, #15 8004fca: fa02 f303 lsl.w r3, r2, r3 8004fce: 43db mvns r3, r3 8004fd0: 69ba ldr r2, [r7, #24] 8004fd2: 4013 ands r3, r2 8004fd4: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 8004fd6: 683b ldr r3, [r7, #0] 8004fd8: 691a ldr r2, [r3, #16] 8004fda: 69fb ldr r3, [r7, #28] 8004fdc: f003 0307 and.w r3, r3, #7 8004fe0: 009b lsls r3, r3, #2 8004fe2: fa02 f303 lsl.w r3, r2, r3 8004fe6: 69ba ldr r2, [r7, #24] 8004fe8: 4313 orrs r3, r2 8004fea: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 8004fec: 69fb ldr r3, [r7, #28] 8004fee: 08da lsrs r2, r3, #3 8004ff0: 687b ldr r3, [r7, #4] 8004ff2: 3208 adds r2, #8 8004ff4: 69b9 ldr r1, [r7, #24] 8004ff6: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8004ffa: 687b ldr r3, [r7, #4] 8004ffc: 681b ldr r3, [r3, #0] 8004ffe: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); 8005000: 69fb ldr r3, [r7, #28] 8005002: 005b lsls r3, r3, #1 8005004: 2203 movs r2, #3 8005006: fa02 f303 lsl.w r3, r2, r3 800500a: 43db mvns r3, r3 800500c: 69ba ldr r2, [r7, #24] 800500e: 4013 ands r3, r2 8005010: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 8005012: 683b ldr r3, [r7, #0] 8005014: 685b ldr r3, [r3, #4] 8005016: f003 0203 and.w r2, r3, #3 800501a: 69fb ldr r3, [r7, #28] 800501c: 005b lsls r3, r3, #1 800501e: fa02 f303 lsl.w r3, r2, r3 8005022: 69ba ldr r2, [r7, #24] 8005024: 4313 orrs r3, r2 8005026: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 8005028: 687b ldr r3, [r7, #4] 800502a: 69ba ldr r2, [r7, #24] 800502c: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 800502e: 683b ldr r3, [r7, #0] 8005030: 685b ldr r3, [r3, #4] 8005032: f403 3340 and.w r3, r3, #196608 ; 0x30000 8005036: 2b00 cmp r3, #0 8005038: f000 80e0 beq.w 80051fc { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 800503c: 4b2f ldr r3, [pc, #188] ; (80050fc ) 800503e: f8d3 3154 ldr.w r3, [r3, #340] ; 0x154 8005042: 4a2e ldr r2, [pc, #184] ; (80050fc ) 8005044: f043 0302 orr.w r3, r3, #2 8005048: f8c2 3154 str.w r3, [r2, #340] ; 0x154 800504c: 4b2b ldr r3, [pc, #172] ; (80050fc ) 800504e: f8d3 3154 ldr.w r3, [r3, #340] ; 0x154 8005052: f003 0302 and.w r3, r3, #2 8005056: 60fb str r3, [r7, #12] 8005058: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 800505a: 4a29 ldr r2, [pc, #164] ; (8005100 ) 800505c: 69fb ldr r3, [r7, #28] 800505e: 089b lsrs r3, r3, #2 8005060: 3302 adds r3, #2 8005062: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8005066: 61bb str r3, [r7, #24] temp &= ~(0x0FUL << (4U * (position & 0x03U))); 8005068: 69fb ldr r3, [r7, #28] 800506a: f003 0303 and.w r3, r3, #3 800506e: 009b lsls r3, r3, #2 8005070: 220f movs r2, #15 8005072: fa02 f303 lsl.w r3, r2, r3 8005076: 43db mvns r3, r3 8005078: 69ba ldr r2, [r7, #24] 800507a: 4013 ands r3, r2 800507c: 61bb str r3, [r7, #24] temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 800507e: 687b ldr r3, [r7, #4] 8005080: 4a20 ldr r2, [pc, #128] ; (8005104 ) 8005082: 4293 cmp r3, r2 8005084: d052 beq.n 800512c 8005086: 687b ldr r3, [r7, #4] 8005088: 4a1f ldr r2, [pc, #124] ; (8005108 ) 800508a: 4293 cmp r3, r2 800508c: d031 beq.n 80050f2 800508e: 687b ldr r3, [r7, #4] 8005090: 4a1e ldr r2, [pc, #120] ; (800510c ) 8005092: 4293 cmp r3, r2 8005094: d02b beq.n 80050ee 8005096: 687b ldr r3, [r7, #4] 8005098: 4a1d ldr r2, [pc, #116] ; (8005110 ) 800509a: 4293 cmp r3, r2 800509c: d025 beq.n 80050ea 800509e: 687b ldr r3, [r7, #4] 80050a0: 4a1c ldr r2, [pc, #112] ; (8005114 ) 80050a2: 4293 cmp r3, r2 80050a4: d01f beq.n 80050e6 80050a6: 687b ldr r3, [r7, #4] 80050a8: 4a1b ldr r2, [pc, #108] ; (8005118 ) 80050aa: 4293 cmp r3, r2 80050ac: d019 beq.n 80050e2 80050ae: 687b ldr r3, [r7, #4] 80050b0: 4a1a ldr r2, [pc, #104] ; (800511c ) 80050b2: 4293 cmp r3, r2 80050b4: d013 beq.n 80050de 80050b6: 687b ldr r3, [r7, #4] 80050b8: 4a19 ldr r2, [pc, #100] ; (8005120 ) 80050ba: 4293 cmp r3, r2 80050bc: d00d beq.n 80050da 80050be: 687b ldr r3, [r7, #4] 80050c0: 4a18 ldr r2, [pc, #96] ; (8005124 ) 80050c2: 4293 cmp r3, r2 80050c4: d007 beq.n 80050d6 80050c6: 687b ldr r3, [r7, #4] 80050c8: 4a17 ldr r2, [pc, #92] ; (8005128 ) 80050ca: 4293 cmp r3, r2 80050cc: d101 bne.n 80050d2 80050ce: 2309 movs r3, #9 80050d0: e02d b.n 800512e 80050d2: 230a movs r3, #10 80050d4: e02b b.n 800512e 80050d6: 2308 movs r3, #8 80050d8: e029 b.n 800512e 80050da: 2307 movs r3, #7 80050dc: e027 b.n 800512e 80050de: 2306 movs r3, #6 80050e0: e025 b.n 800512e 80050e2: 2305 movs r3, #5 80050e4: e023 b.n 800512e 80050e6: 2304 movs r3, #4 80050e8: e021 b.n 800512e 80050ea: 2303 movs r3, #3 80050ec: e01f b.n 800512e 80050ee: 2302 movs r3, #2 80050f0: e01d b.n 800512e 80050f2: 2301 movs r3, #1 80050f4: e01b b.n 800512e 80050f6: bf00 nop 80050f8: 58000080 .word 0x58000080 80050fc: 58024400 .word 0x58024400 8005100: 58000400 .word 0x58000400 8005104: 58020000 .word 0x58020000 8005108: 58020400 .word 0x58020400 800510c: 58020800 .word 0x58020800 8005110: 58020c00 .word 0x58020c00 8005114: 58021000 .word 0x58021000 8005118: 58021400 .word 0x58021400 800511c: 58021800 .word 0x58021800 8005120: 58021c00 .word 0x58021c00 8005124: 58022000 .word 0x58022000 8005128: 58022400 .word 0x58022400 800512c: 2300 movs r3, #0 800512e: 69fa ldr r2, [r7, #28] 8005130: f002 0203 and.w r2, r2, #3 8005134: 0092 lsls r2, r2, #2 8005136: 4093 lsls r3, r2 8005138: 69ba ldr r2, [r7, #24] 800513a: 4313 orrs r3, r2 800513c: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 800513e: 4938 ldr r1, [pc, #224] ; (8005220 ) 8005140: 69fb ldr r3, [r7, #28] 8005142: 089b lsrs r3, r3, #2 8005144: 3302 adds r3, #2 8005146: 69ba ldr r2, [r7, #24] 8005148: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 800514c: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 8005150: 681b ldr r3, [r3, #0] 8005152: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8005154: 693b ldr r3, [r7, #16] 8005156: 43db mvns r3, r3 8005158: 69ba ldr r2, [r7, #24] 800515a: 4013 ands r3, r2 800515c: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 800515e: 683b ldr r3, [r7, #0] 8005160: 685b ldr r3, [r3, #4] 8005162: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8005166: 2b00 cmp r3, #0 8005168: d003 beq.n 8005172 { temp |= iocurrent; 800516a: 69ba ldr r2, [r7, #24] 800516c: 693b ldr r3, [r7, #16] 800516e: 4313 orrs r3, r2 8005170: 61bb str r3, [r7, #24] } EXTI->RTSR1 = temp; 8005172: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 8005176: 69bb ldr r3, [r7, #24] 8005178: 6013 str r3, [r2, #0] temp = EXTI->FTSR1; 800517a: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 800517e: 685b ldr r3, [r3, #4] 8005180: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8005182: 693b ldr r3, [r7, #16] 8005184: 43db mvns r3, r3 8005186: 69ba ldr r2, [r7, #24] 8005188: 4013 ands r3, r2 800518a: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 800518c: 683b ldr r3, [r7, #0] 800518e: 685b ldr r3, [r3, #4] 8005190: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8005194: 2b00 cmp r3, #0 8005196: d003 beq.n 80051a0 { temp |= iocurrent; 8005198: 69ba ldr r2, [r7, #24] 800519a: 693b ldr r3, [r7, #16] 800519c: 4313 orrs r3, r2 800519e: 61bb str r3, [r7, #24] } EXTI->FTSR1 = temp; 80051a0: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 80051a4: 69bb ldr r3, [r7, #24] 80051a6: 6053 str r3, [r2, #4] temp = EXTI_CurrentCPU->EMR1; 80051a8: 697b ldr r3, [r7, #20] 80051aa: 685b ldr r3, [r3, #4] 80051ac: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 80051ae: 693b ldr r3, [r7, #16] 80051b0: 43db mvns r3, r3 80051b2: 69ba ldr r2, [r7, #24] 80051b4: 4013 ands r3, r2 80051b6: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 80051b8: 683b ldr r3, [r7, #0] 80051ba: 685b ldr r3, [r3, #4] 80051bc: f403 3300 and.w r3, r3, #131072 ; 0x20000 80051c0: 2b00 cmp r3, #0 80051c2: d003 beq.n 80051cc { temp |= iocurrent; 80051c4: 69ba ldr r2, [r7, #24] 80051c6: 693b ldr r3, [r7, #16] 80051c8: 4313 orrs r3, r2 80051ca: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->EMR1 = temp; 80051cc: 697b ldr r3, [r7, #20] 80051ce: 69ba ldr r2, [r7, #24] 80051d0: 605a str r2, [r3, #4] /* Clear EXTI line configuration */ temp = EXTI_CurrentCPU->IMR1; 80051d2: 697b ldr r3, [r7, #20] 80051d4: 681b ldr r3, [r3, #0] 80051d6: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 80051d8: 693b ldr r3, [r7, #16] 80051da: 43db mvns r3, r3 80051dc: 69ba ldr r2, [r7, #24] 80051de: 4013 ands r3, r2 80051e0: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) 80051e2: 683b ldr r3, [r7, #0] 80051e4: 685b ldr r3, [r3, #4] 80051e6: f403 3380 and.w r3, r3, #65536 ; 0x10000 80051ea: 2b00 cmp r3, #0 80051ec: d003 beq.n 80051f6 { temp |= iocurrent; 80051ee: 69ba ldr r2, [r7, #24] 80051f0: 693b ldr r3, [r7, #16] 80051f2: 4313 orrs r3, r2 80051f4: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->IMR1 = temp; 80051f6: 697b ldr r3, [r7, #20] 80051f8: 69ba ldr r2, [r7, #24] 80051fa: 601a str r2, [r3, #0] } } position++; 80051fc: 69fb ldr r3, [r7, #28] 80051fe: 3301 adds r3, #1 8005200: 61fb str r3, [r7, #28] while (((GPIO_Init->Pin) >> position) != 0x00U) 8005202: 683b ldr r3, [r7, #0] 8005204: 681a ldr r2, [r3, #0] 8005206: 69fb ldr r3, [r7, #28] 8005208: fa22 f303 lsr.w r3, r2, r3 800520c: 2b00 cmp r3, #0 800520e: f47f ae63 bne.w 8004ed8 } } 8005212: bf00 nop 8005214: bf00 nop 8005216: 3724 adds r7, #36 ; 0x24 8005218: 46bd mov sp, r7 800521a: f85d 7b04 ldr.w r7, [sp], #4 800521e: 4770 bx lr 8005220: 58000400 .word 0x58000400 08005224 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 8005224: b480 push {r7} 8005226: b085 sub sp, #20 8005228: af00 add r7, sp, #0 800522a: 6078 str r0, [r7, #4] 800522c: 460b mov r3, r1 800522e: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != 0x00U) 8005230: 687b ldr r3, [r7, #4] 8005232: 691a ldr r2, [r3, #16] 8005234: 887b ldrh r3, [r7, #2] 8005236: 4013 ands r3, r2 8005238: 2b00 cmp r3, #0 800523a: d002 beq.n 8005242 { bitstatus = GPIO_PIN_SET; 800523c: 2301 movs r3, #1 800523e: 73fb strb r3, [r7, #15] 8005240: e001 b.n 8005246 } else { bitstatus = GPIO_PIN_RESET; 8005242: 2300 movs r3, #0 8005244: 73fb strb r3, [r7, #15] } return bitstatus; 8005246: 7bfb ldrb r3, [r7, #15] } 8005248: 4618 mov r0, r3 800524a: 3714 adds r7, #20 800524c: 46bd mov sp, r7 800524e: f85d 7b04 ldr.w r7, [sp], #4 8005252: 4770 bx lr 08005254 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8005254: b480 push {r7} 8005256: b083 sub sp, #12 8005258: af00 add r7, sp, #0 800525a: 6078 str r0, [r7, #4] 800525c: 460b mov r3, r1 800525e: 807b strh r3, [r7, #2] 8005260: 4613 mov r3, r2 8005262: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8005264: 787b ldrb r3, [r7, #1] 8005266: 2b00 cmp r3, #0 8005268: d003 beq.n 8005272 { GPIOx->BSRR = GPIO_Pin; 800526a: 887a ldrh r2, [r7, #2] 800526c: 687b ldr r3, [r7, #4] 800526e: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; } } 8005270: e003 b.n 800527a GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; 8005272: 887b ldrh r3, [r7, #2] 8005274: 041a lsls r2, r3, #16 8005276: 687b ldr r3, [r7, #4] 8005278: 619a str r2, [r3, #24] } 800527a: bf00 nop 800527c: 370c adds r7, #12 800527e: 46bd mov sp, r7 8005280: f85d 7b04 ldr.w r7, [sp], #4 8005284: 4770 bx lr ... 08005288 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { 8005288: b580 push {r7, lr} 800528a: b082 sub sp, #8 800528c: af00 add r7, sp, #0 800528e: 6078 str r0, [r7, #4] /* Check the I2C handle allocation */ if (hi2c == NULL) 8005290: 687b ldr r3, [r7, #4] 8005292: 2b00 cmp r3, #0 8005294: d101 bne.n 800529a { return HAL_ERROR; 8005296: 2301 movs r3, #1 8005298: e07f b.n 800539a assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); if (hi2c->State == HAL_I2C_STATE_RESET) 800529a: 687b ldr r3, [r7, #4] 800529c: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 80052a0: b2db uxtb r3, r3 80052a2: 2b00 cmp r3, #0 80052a4: d106 bne.n 80052b4 { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; 80052a6: 687b ldr r3, [r7, #4] 80052a8: 2200 movs r2, #0 80052aa: f883 2040 strb.w r2, [r3, #64] ; 0x40 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ hi2c->MspInitCallback(hi2c); #else /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_I2C_MspInit(hi2c); 80052ae: 6878 ldr r0, [r7, #4] 80052b0: f7fc fb56 bl 8001960 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; 80052b4: 687b ldr r3, [r7, #4] 80052b6: 2224 movs r2, #36 ; 0x24 80052b8: f883 2041 strb.w r2, [r3, #65] ; 0x41 /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 80052bc: 687b ldr r3, [r7, #4] 80052be: 681b ldr r3, [r3, #0] 80052c0: 681a ldr r2, [r3, #0] 80052c2: 687b ldr r3, [r7, #4] 80052c4: 681b ldr r3, [r3, #0] 80052c6: f022 0201 bic.w r2, r2, #1 80052ca: 601a str r2, [r3, #0] /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ /* Configure I2Cx: Frequency range */ hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; 80052cc: 687b ldr r3, [r7, #4] 80052ce: 685a ldr r2, [r3, #4] 80052d0: 687b ldr r3, [r7, #4] 80052d2: 681b ldr r3, [r3, #0] 80052d4: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000 80052d8: 611a str r2, [r3, #16] /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Disable Own Address1 before set the Own Address1 configuration */ hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; 80052da: 687b ldr r3, [r7, #4] 80052dc: 681b ldr r3, [r3, #0] 80052de: 689a ldr r2, [r3, #8] 80052e0: 687b ldr r3, [r7, #4] 80052e2: 681b ldr r3, [r3, #0] 80052e4: f422 4200 bic.w r2, r2, #32768 ; 0x8000 80052e8: 609a str r2, [r3, #8] /* Configure I2Cx: Own Address1 and ack own address1 mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) 80052ea: 687b ldr r3, [r7, #4] 80052ec: 68db ldr r3, [r3, #12] 80052ee: 2b01 cmp r3, #1 80052f0: d107 bne.n 8005302 { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); 80052f2: 687b ldr r3, [r7, #4] 80052f4: 689a ldr r2, [r3, #8] 80052f6: 687b ldr r3, [r7, #4] 80052f8: 681b ldr r3, [r3, #0] 80052fa: f442 4200 orr.w r2, r2, #32768 ; 0x8000 80052fe: 609a str r2, [r3, #8] 8005300: e006 b.n 8005310 } else /* I2C_ADDRESSINGMODE_10BIT */ { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); 8005302: 687b ldr r3, [r7, #4] 8005304: 689a ldr r2, [r3, #8] 8005306: 687b ldr r3, [r7, #4] 8005308: 681b ldr r3, [r3, #0] 800530a: f442 4204 orr.w r2, r2, #33792 ; 0x8400 800530e: 609a str r2, [r3, #8] } /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Addressing Master mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) 8005310: 687b ldr r3, [r7, #4] 8005312: 68db ldr r3, [r3, #12] 8005314: 2b02 cmp r3, #2 8005316: d104 bne.n 8005322 { hi2c->Instance->CR2 = (I2C_CR2_ADD10); 8005318: 687b ldr r3, [r7, #4] 800531a: 681b ldr r3, [r3, #0] 800531c: f44f 6200 mov.w r2, #2048 ; 0x800 8005320: 605a str r2, [r3, #4] } /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); 8005322: 687b ldr r3, [r7, #4] 8005324: 681b ldr r3, [r3, #0] 8005326: 6859 ldr r1, [r3, #4] 8005328: 687b ldr r3, [r7, #4] 800532a: 681a ldr r2, [r3, #0] 800532c: 4b1d ldr r3, [pc, #116] ; (80053a4 ) 800532e: 430b orrs r3, r1 8005330: 6053 str r3, [r2, #4] /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Disable Own Address2 before set the Own Address2 configuration */ hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; 8005332: 687b ldr r3, [r7, #4] 8005334: 681b ldr r3, [r3, #0] 8005336: 68da ldr r2, [r3, #12] 8005338: 687b ldr r3, [r7, #4] 800533a: 681b ldr r3, [r3, #0] 800533c: f422 4200 bic.w r2, r2, #32768 ; 0x8000 8005340: 60da str r2, [r3, #12] /* Configure I2Cx: Dual mode and Own Address2 */ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ 8005342: 687b ldr r3, [r7, #4] 8005344: 691a ldr r2, [r3, #16] 8005346: 687b ldr r3, [r7, #4] 8005348: 695b ldr r3, [r3, #20] 800534a: ea42 0103 orr.w r1, r2, r3 (hi2c->Init.OwnAddress2Masks << 8)); 800534e: 687b ldr r3, [r7, #4] 8005350: 699b ldr r3, [r3, #24] 8005352: 021a lsls r2, r3, #8 hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ 8005354: 687b ldr r3, [r7, #4] 8005356: 681b ldr r3, [r3, #0] 8005358: 430a orrs r2, r1 800535a: 60da str r2, [r3, #12] /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); 800535c: 687b ldr r3, [r7, #4] 800535e: 69d9 ldr r1, [r3, #28] 8005360: 687b ldr r3, [r7, #4] 8005362: 6a1a ldr r2, [r3, #32] 8005364: 687b ldr r3, [r7, #4] 8005366: 681b ldr r3, [r3, #0] 8005368: 430a orrs r2, r1 800536a: 601a str r2, [r3, #0] /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 800536c: 687b ldr r3, [r7, #4] 800536e: 681b ldr r3, [r3, #0] 8005370: 681a ldr r2, [r3, #0] 8005372: 687b ldr r3, [r7, #4] 8005374: 681b ldr r3, [r3, #0] 8005376: f042 0201 orr.w r2, r2, #1 800537a: 601a str r2, [r3, #0] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 800537c: 687b ldr r3, [r7, #4] 800537e: 2200 movs r2, #0 8005380: 645a str r2, [r3, #68] ; 0x44 hi2c->State = HAL_I2C_STATE_READY; 8005382: 687b ldr r3, [r7, #4] 8005384: 2220 movs r2, #32 8005386: f883 2041 strb.w r2, [r3, #65] ; 0x41 hi2c->PreviousState = I2C_STATE_NONE; 800538a: 687b ldr r3, [r7, #4] 800538c: 2200 movs r2, #0 800538e: 631a str r2, [r3, #48] ; 0x30 hi2c->Mode = HAL_I2C_MODE_NONE; 8005390: 687b ldr r3, [r7, #4] 8005392: 2200 movs r2, #0 8005394: f883 2042 strb.w r2, [r3, #66] ; 0x42 return HAL_OK; 8005398: 2300 movs r3, #0 } 800539a: 4618 mov r0, r3 800539c: 3708 adds r7, #8 800539e: 46bd mov sp, r7 80053a0: bd80 pop {r7, pc} 80053a2: bf00 nop 80053a4: 02008000 .word 0x02008000 080053a8 : * the configuration information for the specified I2Cx peripheral. * @param AnalogFilter New state of the Analog filter. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) { 80053a8: b480 push {r7} 80053aa: b083 sub sp, #12 80053ac: af00 add r7, sp, #0 80053ae: 6078 str r0, [r7, #4] 80053b0: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); if (hi2c->State == HAL_I2C_STATE_READY) 80053b2: 687b ldr r3, [r7, #4] 80053b4: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 80053b8: b2db uxtb r3, r3 80053ba: 2b20 cmp r3, #32 80053bc: d138 bne.n 8005430 { /* Process Locked */ __HAL_LOCK(hi2c); 80053be: 687b ldr r3, [r7, #4] 80053c0: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 80053c4: 2b01 cmp r3, #1 80053c6: d101 bne.n 80053cc 80053c8: 2302 movs r3, #2 80053ca: e032 b.n 8005432 80053cc: 687b ldr r3, [r7, #4] 80053ce: 2201 movs r2, #1 80053d0: f883 2040 strb.w r2, [r3, #64] ; 0x40 hi2c->State = HAL_I2C_STATE_BUSY; 80053d4: 687b ldr r3, [r7, #4] 80053d6: 2224 movs r2, #36 ; 0x24 80053d8: f883 2041 strb.w r2, [r3, #65] ; 0x41 /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 80053dc: 687b ldr r3, [r7, #4] 80053de: 681b ldr r3, [r3, #0] 80053e0: 681a ldr r2, [r3, #0] 80053e2: 687b ldr r3, [r7, #4] 80053e4: 681b ldr r3, [r3, #0] 80053e6: f022 0201 bic.w r2, r2, #1 80053ea: 601a str r2, [r3, #0] /* Reset I2Cx ANOFF bit */ hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); 80053ec: 687b ldr r3, [r7, #4] 80053ee: 681b ldr r3, [r3, #0] 80053f0: 681a ldr r2, [r3, #0] 80053f2: 687b ldr r3, [r7, #4] 80053f4: 681b ldr r3, [r3, #0] 80053f6: f422 5280 bic.w r2, r2, #4096 ; 0x1000 80053fa: 601a str r2, [r3, #0] /* Set analog filter bit*/ hi2c->Instance->CR1 |= AnalogFilter; 80053fc: 687b ldr r3, [r7, #4] 80053fe: 681b ldr r3, [r3, #0] 8005400: 6819 ldr r1, [r3, #0] 8005402: 687b ldr r3, [r7, #4] 8005404: 681b ldr r3, [r3, #0] 8005406: 683a ldr r2, [r7, #0] 8005408: 430a orrs r2, r1 800540a: 601a str r2, [r3, #0] __HAL_I2C_ENABLE(hi2c); 800540c: 687b ldr r3, [r7, #4] 800540e: 681b ldr r3, [r3, #0] 8005410: 681a ldr r2, [r3, #0] 8005412: 687b ldr r3, [r7, #4] 8005414: 681b ldr r3, [r3, #0] 8005416: f042 0201 orr.w r2, r2, #1 800541a: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 800541c: 687b ldr r3, [r7, #4] 800541e: 2220 movs r2, #32 8005420: f883 2041 strb.w r2, [r3, #65] ; 0x41 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8005424: 687b ldr r3, [r7, #4] 8005426: 2200 movs r2, #0 8005428: f883 2040 strb.w r2, [r3, #64] ; 0x40 return HAL_OK; 800542c: 2300 movs r3, #0 800542e: e000 b.n 8005432 } else { return HAL_BUSY; 8005430: 2302 movs r3, #2 } } 8005432: 4618 mov r0, r3 8005434: 370c adds r7, #12 8005436: 46bd mov sp, r7 8005438: f85d 7b04 ldr.w r7, [sp], #4 800543c: 4770 bx lr 0800543e : * the configuration information for the specified I2Cx peripheral. * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) { 800543e: b480 push {r7} 8005440: b085 sub sp, #20 8005442: af00 add r7, sp, #0 8005444: 6078 str r0, [r7, #4] 8005446: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); if (hi2c->State == HAL_I2C_STATE_READY) 8005448: 687b ldr r3, [r7, #4] 800544a: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 800544e: b2db uxtb r3, r3 8005450: 2b20 cmp r3, #32 8005452: d139 bne.n 80054c8 { /* Process Locked */ __HAL_LOCK(hi2c); 8005454: 687b ldr r3, [r7, #4] 8005456: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 800545a: 2b01 cmp r3, #1 800545c: d101 bne.n 8005462 800545e: 2302 movs r3, #2 8005460: e033 b.n 80054ca 8005462: 687b ldr r3, [r7, #4] 8005464: 2201 movs r2, #1 8005466: f883 2040 strb.w r2, [r3, #64] ; 0x40 hi2c->State = HAL_I2C_STATE_BUSY; 800546a: 687b ldr r3, [r7, #4] 800546c: 2224 movs r2, #36 ; 0x24 800546e: f883 2041 strb.w r2, [r3, #65] ; 0x41 /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8005472: 687b ldr r3, [r7, #4] 8005474: 681b ldr r3, [r3, #0] 8005476: 681a ldr r2, [r3, #0] 8005478: 687b ldr r3, [r7, #4] 800547a: 681b ldr r3, [r3, #0] 800547c: f022 0201 bic.w r2, r2, #1 8005480: 601a str r2, [r3, #0] /* Get the old register value */ tmpreg = hi2c->Instance->CR1; 8005482: 687b ldr r3, [r7, #4] 8005484: 681b ldr r3, [r3, #0] 8005486: 681b ldr r3, [r3, #0] 8005488: 60fb str r3, [r7, #12] /* Reset I2Cx DNF bits [11:8] */ tmpreg &= ~(I2C_CR1_DNF); 800548a: 68fb ldr r3, [r7, #12] 800548c: f423 6370 bic.w r3, r3, #3840 ; 0xf00 8005490: 60fb str r3, [r7, #12] /* Set I2Cx DNF coefficient */ tmpreg |= DigitalFilter << 8U; 8005492: 683b ldr r3, [r7, #0] 8005494: 021b lsls r3, r3, #8 8005496: 68fa ldr r2, [r7, #12] 8005498: 4313 orrs r3, r2 800549a: 60fb str r3, [r7, #12] /* Store the new register value */ hi2c->Instance->CR1 = tmpreg; 800549c: 687b ldr r3, [r7, #4] 800549e: 681b ldr r3, [r3, #0] 80054a0: 68fa ldr r2, [r7, #12] 80054a2: 601a str r2, [r3, #0] __HAL_I2C_ENABLE(hi2c); 80054a4: 687b ldr r3, [r7, #4] 80054a6: 681b ldr r3, [r3, #0] 80054a8: 681a ldr r2, [r3, #0] 80054aa: 687b ldr r3, [r7, #4] 80054ac: 681b ldr r3, [r3, #0] 80054ae: f042 0201 orr.w r2, r2, #1 80054b2: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 80054b4: 687b ldr r3, [r7, #4] 80054b6: 2220 movs r2, #32 80054b8: f883 2041 strb.w r2, [r3, #65] ; 0x41 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80054bc: 687b ldr r3, [r7, #4] 80054be: 2200 movs r2, #0 80054c0: f883 2040 strb.w r2, [r3, #64] ; 0x40 return HAL_OK; 80054c4: 2300 movs r3, #0 80054c6: e000 b.n 80054ca } else { return HAL_BUSY; 80054c8: 2302 movs r3, #2 } } 80054ca: 4618 mov r0, r3 80054cc: 3714 adds r7, #20 80054ce: 46bd mov sp, r7 80054d0: f85d 7b04 ldr.w r7, [sp], #4 80054d4: 4770 bx lr 080054d6 : * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) { 80054d6: b580 push {r7, lr} 80054d8: b084 sub sp, #16 80054da: af00 add r7, sp, #0 80054dc: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check the IWDG handle allocation */ if (hiwdg == NULL) 80054de: 687b ldr r3, [r7, #4] 80054e0: 2b00 cmp r3, #0 80054e2: d101 bne.n 80054e8 { return HAL_ERROR; 80054e4: 2301 movs r3, #1 80054e6: e041 b.n 800556c assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler)); assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window)); /* Enable IWDG. LSI is turned on automatically */ __HAL_IWDG_START(hiwdg); 80054e8: 687b ldr r3, [r7, #4] 80054ea: 681b ldr r3, [r3, #0] 80054ec: f64c 42cc movw r2, #52428 ; 0xcccc 80054f0: 601a str r2, [r3, #0] /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing 0x5555 in KR */ IWDG_ENABLE_WRITE_ACCESS(hiwdg); 80054f2: 687b ldr r3, [r7, #4] 80054f4: 681b ldr r3, [r3, #0] 80054f6: f245 5255 movw r2, #21845 ; 0x5555 80054fa: 601a str r2, [r3, #0] /* Write to IWDG registers the Prescaler & Reload values to work with */ hiwdg->Instance->PR = hiwdg->Init.Prescaler; 80054fc: 687b ldr r3, [r7, #4] 80054fe: 681b ldr r3, [r3, #0] 8005500: 687a ldr r2, [r7, #4] 8005502: 6852 ldr r2, [r2, #4] 8005504: 605a str r2, [r3, #4] hiwdg->Instance->RLR = hiwdg->Init.Reload; 8005506: 687b ldr r3, [r7, #4] 8005508: 681b ldr r3, [r3, #0] 800550a: 687a ldr r2, [r7, #4] 800550c: 6892 ldr r2, [r2, #8] 800550e: 609a str r2, [r3, #8] /* Check pending flag, if previous update not done, return timeout */ tickstart = HAL_GetTick(); 8005510: f7fd fe6a bl 80031e8 8005514: 60f8 str r0, [r7, #12] /* Wait for register to be updated */ while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) 8005516: e00f b.n 8005538 { if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) 8005518: f7fd fe66 bl 80031e8 800551c: 4602 mov r2, r0 800551e: 68fb ldr r3, [r7, #12] 8005520: 1ad3 subs r3, r2, r3 8005522: 2b31 cmp r3, #49 ; 0x31 8005524: d908 bls.n 8005538 { if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) 8005526: 687b ldr r3, [r7, #4] 8005528: 681b ldr r3, [r3, #0] 800552a: 68db ldr r3, [r3, #12] 800552c: f003 0307 and.w r3, r3, #7 8005530: 2b00 cmp r3, #0 8005532: d001 beq.n 8005538 { return HAL_TIMEOUT; 8005534: 2303 movs r3, #3 8005536: e019 b.n 800556c while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) 8005538: 687b ldr r3, [r7, #4] 800553a: 681b ldr r3, [r3, #0] 800553c: 68db ldr r3, [r3, #12] 800553e: f003 0307 and.w r3, r3, #7 8005542: 2b00 cmp r3, #0 8005544: d1e8 bne.n 8005518 } } /* If window parameter is different than current value, modify window register */ if (hiwdg->Instance->WINR != hiwdg->Init.Window) 8005546: 687b ldr r3, [r7, #4] 8005548: 681b ldr r3, [r3, #0] 800554a: 691a ldr r2, [r3, #16] 800554c: 687b ldr r3, [r7, #4] 800554e: 68db ldr r3, [r3, #12] 8005550: 429a cmp r2, r3 8005552: d005 beq.n 8005560 { /* Write to IWDG WINR the IWDG_Window value to compare with. In any case, even if window feature is disabled, Watchdog will be reloaded by writing windows register */ hiwdg->Instance->WINR = hiwdg->Init.Window; 8005554: 687b ldr r3, [r7, #4] 8005556: 681b ldr r3, [r3, #0] 8005558: 687a ldr r2, [r7, #4] 800555a: 68d2 ldr r2, [r2, #12] 800555c: 611a str r2, [r3, #16] 800555e: e004 b.n 800556a } else { /* Reload IWDG counter with value defined in the reload register */ __HAL_IWDG_RELOAD_COUNTER(hiwdg); 8005560: 687b ldr r3, [r7, #4] 8005562: 681b ldr r3, [r3, #0] 8005564: f64a 22aa movw r2, #43690 ; 0xaaaa 8005568: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 800556a: 2300 movs r3, #0 } 800556c: 4618 mov r0, r3 800556e: 3710 adds r7, #16 8005570: 46bd mov sp, r7 8005572: bd80 pop {r7, pc} 08005574 : * LPTIM_InitTypeDef and initialize the associated handle. * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) { 8005574: b580 push {r7, lr} 8005576: b084 sub sp, #16 8005578: af00 add r7, sp, #0 800557a: 6078 str r0, [r7, #4] uint32_t tmpcfgr; /* Check the LPTIM handle allocation */ if (hlptim == NULL) 800557c: 687b ldr r3, [r7, #4] 800557e: 2b00 cmp r3, #0 8005580: d101 bne.n 8005586 { return HAL_ERROR; 8005582: 2301 movs r3, #1 8005584: e097 b.n 80056b6 /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source)); assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler)); if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) 8005586: 687b ldr r3, [r7, #4] 8005588: 685b ldr r3, [r3, #4] 800558a: 2b01 cmp r3, #1 } assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity)); assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode)); assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource)); if (hlptim->State == HAL_LPTIM_STATE_RESET) 800558c: 687b ldr r3, [r7, #4] 800558e: f893 3036 ldrb.w r3, [r3, #54] ; 0x36 8005592: b2db uxtb r3, r3 8005594: 2b00 cmp r3, #0 8005596: d106 bne.n 80055a6 { /* Allocate lock resource and initialize it */ hlptim->Lock = HAL_UNLOCKED; 8005598: 687b ldr r3, [r7, #4] 800559a: 2200 movs r2, #0 800559c: f883 2035 strb.w r2, [r3, #53] ; 0x35 /* Init the low level hardware : GPIO, CLOCK, NVIC */ hlptim->MspInitCallback(hlptim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_LPTIM_MspInit(hlptim); 80055a0: 6878 ldr r0, [r7, #4] 80055a2: f7fc fb01 bl 8001ba8 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; 80055a6: 687b ldr r3, [r7, #4] 80055a8: 2202 movs r2, #2 80055aa: f883 2036 strb.w r2, [r3, #54] ; 0x36 /* Get the LPTIMx CFGR value */ tmpcfgr = hlptim->Instance->CFGR; 80055ae: 687b ldr r3, [r7, #4] 80055b0: 681b ldr r3, [r3, #0] 80055b2: 68db ldr r3, [r3, #12] 80055b4: 60fb str r3, [r7, #12] if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) 80055b6: 687b ldr r3, [r7, #4] 80055b8: 685b ldr r3, [r3, #4] 80055ba: 2b01 cmp r3, #1 80055bc: d004 beq.n 80055c8 || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) 80055be: 687b ldr r3, [r7, #4] 80055c0: 6a9b ldr r3, [r3, #40] ; 0x28 80055c2: f5b3 0f00 cmp.w r3, #8388608 ; 0x800000 80055c6: d103 bne.n 80055d0 { tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT)); 80055c8: 68fb ldr r3, [r7, #12] 80055ca: f023 031e bic.w r3, r3, #30 80055ce: 60fb str r3, [r7, #12] } if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) 80055d0: 687b ldr r3, [r7, #4] 80055d2: 695b ldr r3, [r3, #20] 80055d4: f64f 72ff movw r2, #65535 ; 0xffff 80055d8: 4293 cmp r3, r2 80055da: d003 beq.n 80055e4 { tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL)); 80055dc: 68fa ldr r2, [r7, #12] 80055de: 4b38 ldr r3, [pc, #224] ; (80056c0 ) 80055e0: 4013 ands r3, r2 80055e2: 60fb str r3, [r7, #12] } /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD | 80055e4: 68fa ldr r2, [r7, #12] 80055e6: 4b37 ldr r3, [pc, #220] ; (80056c4 ) 80055e8: 4013 ands r3, r2 80055ea: 60fb str r3, [r7, #12] LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE)); /* Set initialization parameters */ tmpcfgr |= (hlptim->Init.Clock.Source | 80055ec: 687b ldr r3, [r7, #4] 80055ee: 685a ldr r2, [r3, #4] hlptim->Init.Clock.Prescaler | 80055f0: 687b ldr r3, [r7, #4] 80055f2: 689b ldr r3, [r3, #8] tmpcfgr |= (hlptim->Init.Clock.Source | 80055f4: 431a orrs r2, r3 hlptim->Init.OutputPolarity | 80055f6: 687b ldr r3, [r7, #4] 80055f8: 6a1b ldr r3, [r3, #32] hlptim->Init.Clock.Prescaler | 80055fa: 431a orrs r2, r3 hlptim->Init.UpdateMode | 80055fc: 687b ldr r3, [r7, #4] 80055fe: 6a5b ldr r3, [r3, #36] ; 0x24 hlptim->Init.OutputPolarity | 8005600: 431a orrs r2, r3 hlptim->Init.CounterSource); 8005602: 687b ldr r3, [r7, #4] 8005604: 6a9b ldr r3, [r3, #40] ; 0x28 hlptim->Init.UpdateMode | 8005606: 4313 orrs r3, r2 tmpcfgr |= (hlptim->Init.Clock.Source | 8005608: 68fa ldr r2, [r7, #12] 800560a: 4313 orrs r3, r2 800560c: 60fb str r3, [r7, #12] /* Glitch filters for internal triggers and external inputs are configured * only if an internal clock source is provided to the LPTIM */ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) 800560e: 687b ldr r3, [r7, #4] 8005610: 685b ldr r3, [r3, #4] 8005612: 2b00 cmp r3, #0 8005614: d107 bne.n 8005626 { tmpcfgr |= (hlptim->Init.Trigger.SampleTime | 8005616: 687b ldr r3, [r7, #4] 8005618: 69da ldr r2, [r3, #28] hlptim->Init.UltraLowPowerClock.SampleTime); 800561a: 687b ldr r3, [r7, #4] 800561c: 691b ldr r3, [r3, #16] tmpcfgr |= (hlptim->Init.Trigger.SampleTime | 800561e: 4313 orrs r3, r2 8005620: 68fa ldr r2, [r7, #12] 8005622: 4313 orrs r3, r2 8005624: 60fb str r3, [r7, #12] } /* Configure LPTIM external clock polarity and digital filter */ if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) 8005626: 687b ldr r3, [r7, #4] 8005628: 685b ldr r3, [r3, #4] 800562a: 2b01 cmp r3, #1 800562c: d004 beq.n 8005638 || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) 800562e: 687b ldr r3, [r7, #4] 8005630: 6a9b ldr r3, [r3, #40] ; 0x28 8005632: f5b3 0f00 cmp.w r3, #8388608 ; 0x800000 8005636: d107 bne.n 8005648 { tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity | 8005638: 687b ldr r3, [r7, #4] 800563a: 68da ldr r2, [r3, #12] hlptim->Init.UltraLowPowerClock.SampleTime); 800563c: 687b ldr r3, [r7, #4] 800563e: 691b ldr r3, [r3, #16] tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity | 8005640: 4313 orrs r3, r2 8005642: 68fa ldr r2, [r7, #12] 8005644: 4313 orrs r3, r2 8005646: 60fb str r3, [r7, #12] } /* Configure LPTIM external trigger */ if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) 8005648: 687b ldr r3, [r7, #4] 800564a: 695b ldr r3, [r3, #20] 800564c: f64f 72ff movw r2, #65535 ; 0xffff 8005650: 4293 cmp r3, r2 8005652: d00a beq.n 800566a { /* Enable External trigger and set the trigger source */ tmpcfgr |= (hlptim->Init.Trigger.Source | 8005654: 687b ldr r3, [r7, #4] 8005656: 695a ldr r2, [r3, #20] hlptim->Init.Trigger.ActiveEdge | 8005658: 687b ldr r3, [r7, #4] 800565a: 699b ldr r3, [r3, #24] tmpcfgr |= (hlptim->Init.Trigger.Source | 800565c: 431a orrs r2, r3 hlptim->Init.Trigger.SampleTime); 800565e: 687b ldr r3, [r7, #4] 8005660: 69db ldr r3, [r3, #28] hlptim->Init.Trigger.ActiveEdge | 8005662: 4313 orrs r3, r2 tmpcfgr |= (hlptim->Init.Trigger.Source | 8005664: 68fa ldr r2, [r7, #12] 8005666: 4313 orrs r3, r2 8005668: 60fb str r3, [r7, #12] } /* Write to LPTIMx CFGR */ hlptim->Instance->CFGR = tmpcfgr; 800566a: 687b ldr r3, [r7, #4] 800566c: 681b ldr r3, [r3, #0] 800566e: 68fa ldr r2, [r7, #12] 8005670: 60da str r2, [r3, #12] /* Configure LPTIM input sources */ if ((hlptim->Instance == LPTIM1) || (hlptim->Instance == LPTIM2)) 8005672: 687b ldr r3, [r7, #4] 8005674: 681b ldr r3, [r3, #0] 8005676: 4a14 ldr r2, [pc, #80] ; (80056c8 ) 8005678: 4293 cmp r3, r2 800567a: d004 beq.n 8005686 800567c: 687b ldr r3, [r7, #4] 800567e: 681b ldr r3, [r3, #0] 8005680: 4a12 ldr r2, [pc, #72] ; (80056cc ) 8005682: 4293 cmp r3, r2 8005684: d108 bne.n 8005698 /* Check LPTIM Input1 and Input2 sources */ assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source)); assert_param(IS_LPTIM_INPUT2_SOURCE(hlptim->Instance, hlptim->Init.Input2Source)); /* Configure LPTIM Input1 and Input2 sources */ hlptim->Instance->CFGR2 = (hlptim->Init.Input1Source | hlptim->Init.Input2Source); 8005686: 687b ldr r3, [r7, #4] 8005688: 6ad9 ldr r1, [r3, #44] ; 0x2c 800568a: 687b ldr r3, [r7, #4] 800568c: 6b1a ldr r2, [r3, #48] ; 0x30 800568e: 687b ldr r3, [r7, #4] 8005690: 681b ldr r3, [r3, #0] 8005692: 430a orrs r2, r1 8005694: 625a str r2, [r3, #36] ; 0x24 8005696: e009 b.n 80056ac } else { if (hlptim->Instance == LPTIM3) 8005698: 687b ldr r3, [r7, #4] 800569a: 681b ldr r3, [r3, #0] 800569c: 4a0c ldr r2, [pc, #48] ; (80056d0 ) 800569e: 4293 cmp r3, r2 80056a0: d104 bne.n 80056ac { /* Check LPTIM3 Input1 source */ assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source)); /* Configure LPTIM3 Input1 source */ hlptim->Instance->CFGR2 = hlptim->Init.Input1Source; 80056a2: 687b ldr r3, [r7, #4] 80056a4: 681b ldr r3, [r3, #0] 80056a6: 687a ldr r2, [r7, #4] 80056a8: 6ad2 ldr r2, [r2, #44] ; 0x2c 80056aa: 625a str r2, [r3, #36] ; 0x24 } } /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; 80056ac: 687b ldr r3, [r7, #4] 80056ae: 2201 movs r2, #1 80056b0: f883 2036 strb.w r2, [r3, #54] ; 0x36 /* Return function status */ return HAL_OK; 80056b4: 2300 movs r3, #0 } 80056b6: 4618 mov r0, r3 80056b8: 3710 adds r7, #16 80056ba: 46bd mov sp, r7 80056bc: bd80 pop {r7, pc} 80056be: bf00 nop 80056c0: ffff1f3f .word 0xffff1f3f 80056c4: ff19f1fe .word 0xff19f1fe 80056c8: 40002400 .word 0x40002400 80056cc: 58002400 .word 0x58002400 80056d0: 58002800 .word 0x58002800 080056d4 : * in the OSPI_InitTypeDef and initialize the associated handle. * @param hospi : OSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi) { 80056d4: b580 push {r7, lr} 80056d6: b086 sub sp, #24 80056d8: af02 add r7, sp, #8 80056da: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80056dc: 2300 movs r3, #0 80056de: 73fb strb r3, [r7, #15] uint32_t tickstart = HAL_GetTick(); 80056e0: f7fd fd82 bl 80031e8 80056e4: 60b8 str r0, [r7, #8] /* Check the OSPI handle allocation */ if (hospi == NULL) 80056e6: 687b ldr r3, [r7, #4] 80056e8: 2b00 cmp r3, #0 80056ea: d102 bne.n 80056f2 { status = HAL_ERROR; 80056ec: 2301 movs r3, #1 80056ee: 73fb strb r3, [r7, #15] 80056f0: e0a6 b.n 8005840 assert_param(IS_OSPI_CS_BOUNDARY (hospi->Init.ChipSelectBoundary)); assert_param(IS_OSPI_CKCSHT (hospi->Init.ClkChipSelectHighTime)); assert_param(IS_OSPI_MAXTRAN (hospi->Init.MaxTran)); /* Initialize error code */ hospi->ErrorCode = HAL_OSPI_ERROR_NONE; 80056f2: 687b ldr r3, [r7, #4] 80056f4: 2200 movs r2, #0 80056f6: 659a str r2, [r3, #88] ; 0x58 /* Check if the state is the reset state */ if (hospi->State == HAL_OSPI_STATE_RESET) 80056f8: 687b ldr r3, [r7, #4] 80056fa: 6d5b ldr r3, [r3, #84] ; 0x54 80056fc: 2b00 cmp r3, #0 80056fe: f040 809f bne.w 8005840 /* Init the low level hardware */ hospi->MspInitCallback(hospi); #else /* Initialization of the low level hardware */ HAL_OSPI_MspInit(hospi); 8005702: 6878 ldr r0, [r7, #4] 8005704: f7fc ffce bl 80026a4 #endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ /* Configure the default timeout for the OSPI memory access */ (void)HAL_OSPI_SetTimeout(hospi, HAL_OSPI_TIMEOUT_DEFAULT_VALUE); 8005708: f241 3188 movw r1, #5000 ; 0x1388 800570c: 6878 ldr r0, [r7, #4] 800570e: f000 f8de bl 80058ce /* Configure memory type, device size, chip select high time, clocked chip select high time, free running clock, clock mode */ MODIFY_REG(hospi->Instance->DCR1, 8005712: 687b ldr r3, [r7, #4] 8005714: 681b ldr r3, [r3, #0] 8005716: 689a ldr r2, [r3, #8] 8005718: 4b4c ldr r3, [pc, #304] ; (800584c ) 800571a: 4013 ands r3, r2 800571c: 687a ldr r2, [r7, #4] 800571e: 68d1 ldr r1, [r2, #12] 8005720: 687a ldr r2, [r7, #4] 8005722: 6912 ldr r2, [r2, #16] 8005724: 3a01 subs r2, #1 8005726: 0412 lsls r2, r2, #16 8005728: 4311 orrs r1, r2 800572a: 687a ldr r2, [r7, #4] 800572c: 6952 ldr r2, [r2, #20] 800572e: 3a01 subs r2, #1 8005730: 0212 lsls r2, r2, #8 8005732: 4311 orrs r1, r2 8005734: 687a ldr r2, [r7, #4] 8005736: 6b52 ldr r2, [r2, #52] ; 0x34 8005738: 0112 lsls r2, r2, #4 800573a: 4311 orrs r1, r2 800573c: 687a ldr r2, [r7, #4] 800573e: 69d2 ldr r2, [r2, #28] 8005740: 4311 orrs r1, r2 8005742: 687a ldr r2, [r7, #4] 8005744: 6812 ldr r2, [r2, #0] 8005746: 430b orrs r3, r1 8005748: 6093 str r3, [r2, #8] (hospi->Init.MemoryType | ((hospi->Init.DeviceSize - 1U) << OCTOSPI_DCR1_DEVSIZE_Pos) | ((hospi->Init.ChipSelectHighTime - 1U) << OCTOSPI_DCR1_CSHT_Pos) | (hospi->Init.ClkChipSelectHighTime << OCTOSPI_DCR1_CKCSHT_Pos) | hospi->Init.ClockMode)); /* Configure wrap size */ MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_WRAPSIZE, hospi->Init.WrapSize); 800574a: 687b ldr r3, [r7, #4] 800574c: 681b ldr r3, [r3, #0] 800574e: 68db ldr r3, [r3, #12] 8005750: f423 21e0 bic.w r1, r3, #458752 ; 0x70000 8005754: 687b ldr r3, [r7, #4] 8005756: 6a1a ldr r2, [r3, #32] 8005758: 687b ldr r3, [r7, #4] 800575a: 681b ldr r3, [r3, #0] 800575c: 430a orrs r2, r1 800575e: 60da str r2, [r3, #12] /* Configure chip select boundary and maximum transfer */ hospi->Instance->DCR3 = ((hospi->Init.ChipSelectBoundary << OCTOSPI_DCR3_CSBOUND_Pos) | 8005760: 687b ldr r3, [r7, #4] 8005762: 6b1b ldr r3, [r3, #48] ; 0x30 8005764: 0419 lsls r1, r3, #16 (hospi->Init.MaxTran << OCTOSPI_DCR3_MAXTRAN_Pos)); 8005766: 687b ldr r3, [r7, #4] 8005768: 6bda ldr r2, [r3, #60] ; 0x3c hospi->Instance->DCR3 = ((hospi->Init.ChipSelectBoundary << OCTOSPI_DCR3_CSBOUND_Pos) | 800576a: 687b ldr r3, [r7, #4] 800576c: 681b ldr r3, [r3, #0] 800576e: 430a orrs r2, r1 8005770: 611a str r2, [r3, #16] /* Configure refresh */ hospi->Instance->DCR4 = hospi->Init.Refresh; 8005772: 687b ldr r3, [r7, #4] 8005774: 681b ldr r3, [r3, #0] 8005776: 687a ldr r2, [r7, #4] 8005778: 6c12 ldr r2, [r2, #64] ; 0x40 800577a: 615a str r2, [r3, #20] /* Configure FIFO threshold */ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold - 1U) << OCTOSPI_CR_FTHRES_Pos)); 800577c: 687b ldr r3, [r7, #4] 800577e: 681b ldr r3, [r3, #0] 8005780: 681b ldr r3, [r3, #0] 8005782: f423 51f8 bic.w r1, r3, #7936 ; 0x1f00 8005786: 687b ldr r3, [r7, #4] 8005788: 685b ldr r3, [r3, #4] 800578a: 3b01 subs r3, #1 800578c: 021a lsls r2, r3, #8 800578e: 687b ldr r3, [r7, #4] 8005790: 681b ldr r3, [r3, #0] 8005792: 430a orrs r2, r1 8005794: 601a str r2, [r3, #0] /* Wait till busy flag is reset */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); 8005796: 687b ldr r3, [r7, #4] 8005798: 6ddb ldr r3, [r3, #92] ; 0x5c 800579a: 9300 str r3, [sp, #0] 800579c: 68bb ldr r3, [r7, #8] 800579e: 2200 movs r2, #0 80057a0: 2120 movs r1, #32 80057a2: 6878 ldr r0, [r7, #4] 80057a4: f000 fdb8 bl 8006318 80057a8: 4603 mov r3, r0 80057aa: 73fb strb r3, [r7, #15] if (status == HAL_OK) 80057ac: 7bfb ldrb r3, [r7, #15] 80057ae: 2b00 cmp r3, #0 80057b0: d146 bne.n 8005840 { /* Configure clock prescaler */ MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER, 80057b2: 687b ldr r3, [r7, #4] 80057b4: 681b ldr r3, [r3, #0] 80057b6: 68db ldr r3, [r3, #12] 80057b8: f023 01ff bic.w r1, r3, #255 ; 0xff 80057bc: 687b ldr r3, [r7, #4] 80057be: 6a5b ldr r3, [r3, #36] ; 0x24 80057c0: 1e5a subs r2, r3, #1 80057c2: 687b ldr r3, [r7, #4] 80057c4: 681b ldr r3, [r3, #0] 80057c6: 430a orrs r2, r1 80057c8: 60da str r2, [r3, #12] ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos)); /* Configure Dual Quad mode */ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DQM, hospi->Init.DualQuad); 80057ca: 687b ldr r3, [r7, #4] 80057cc: 681b ldr r3, [r3, #0] 80057ce: 681b ldr r3, [r3, #0] 80057d0: f023 0140 bic.w r1, r3, #64 ; 0x40 80057d4: 687b ldr r3, [r7, #4] 80057d6: 689a ldr r2, [r3, #8] 80057d8: 687b ldr r3, [r7, #4] 80057da: 681b ldr r3, [r3, #0] 80057dc: 430a orrs r2, r1 80057de: 601a str r2, [r3, #0] /* Configure sample shifting and delay hold quarter cycle */ MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC), 80057e0: 687b ldr r3, [r7, #4] 80057e2: 681b ldr r3, [r3, #0] 80057e4: f8d3 3108 ldr.w r3, [r3, #264] ; 0x108 80057e8: f023 41a0 bic.w r1, r3, #1342177280 ; 0x50000000 80057ec: 687b ldr r3, [r7, #4] 80057ee: 6a9a ldr r2, [r3, #40] ; 0x28 80057f0: 687b ldr r3, [r7, #4] 80057f2: 6adb ldr r3, [r3, #44] ; 0x2c 80057f4: 431a orrs r2, r3 80057f6: 687b ldr r3, [r7, #4] 80057f8: 681b ldr r3, [r3, #0] 80057fa: 430a orrs r2, r1 80057fc: f8c3 2108 str.w r2, [r3, #264] ; 0x108 (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle)); /* Enable OctoSPI */ __HAL_OSPI_ENABLE(hospi); 8005800: 687b ldr r3, [r7, #4] 8005802: 681b ldr r3, [r3, #0] 8005804: 681a ldr r2, [r3, #0] 8005806: 687b ldr r3, [r7, #4] 8005808: 681b ldr r3, [r3, #0] 800580a: f042 0201 orr.w r2, r2, #1 800580e: 601a str r2, [r3, #0] /* Enable free running clock if needed : must be done after OSPI enable */ if (hospi->Init.FreeRunningClock == HAL_OSPI_FREERUNCLK_ENABLE) 8005810: 687b ldr r3, [r7, #4] 8005812: 699b ldr r3, [r3, #24] 8005814: 2b02 cmp r3, #2 8005816: d107 bne.n 8005828 { SET_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK); 8005818: 687b ldr r3, [r7, #4] 800581a: 681b ldr r3, [r3, #0] 800581c: 689a ldr r2, [r3, #8] 800581e: 687b ldr r3, [r7, #4] 8005820: 681b ldr r3, [r3, #0] 8005822: f042 0202 orr.w r2, r2, #2 8005826: 609a str r2, [r3, #8] } /* Initialize the OSPI state */ if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) 8005828: 687b ldr r3, [r7, #4] 800582a: 68db ldr r3, [r3, #12] 800582c: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000 8005830: d103 bne.n 800583a { hospi->State = HAL_OSPI_STATE_HYPERBUS_INIT; 8005832: 687b ldr r3, [r7, #4] 8005834: 2201 movs r2, #1 8005836: 655a str r2, [r3, #84] ; 0x54 8005838: e002 b.n 8005840 } else { hospi->State = HAL_OSPI_STATE_READY; 800583a: 687b ldr r3, [r7, #4] 800583c: 2202 movs r2, #2 800583e: 655a str r2, [r3, #84] ; 0x54 } } } /* Return function status */ return status; 8005840: 7bfb ldrb r3, [r7, #15] } 8005842: 4618 mov r0, r3 8005844: 3710 adds r7, #16 8005846: 46bd mov sp, r7 8005848: bd80 pop {r7, pc} 800584a: bf00 nop 800584c: f8e0f88c .word 0xf8e0f88c 08005850 : * @param cfg : Structure containing the Hyperbus configuration * @param Timeout : Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout) { 8005850: b580 push {r7, lr} 8005852: b08a sub sp, #40 ; 0x28 8005854: af02 add r7, sp, #8 8005856: 60f8 str r0, [r7, #12] 8005858: 60b9 str r1, [r7, #8] 800585a: 607a str r2, [r7, #4] HAL_StatusTypeDef status; uint32_t state; uint32_t tickstart = HAL_GetTick(); 800585c: f7fd fcc4 bl 80031e8 8005860: 61b8 str r0, [r7, #24] assert_param(IS_OSPI_ACCESS_TIME (cfg->AccessTime)); assert_param(IS_OSPI_WRITE_ZERO_LATENCY(cfg->WriteZeroLatency)); assert_param(IS_OSPI_LATENCY_MODE (cfg->LatencyMode)); /* Check the state of the driver */ state = hospi->State; 8005862: 68fb ldr r3, [r7, #12] 8005864: 6d5b ldr r3, [r3, #84] ; 0x54 8005866: 617b str r3, [r7, #20] if ((state == HAL_OSPI_STATE_HYPERBUS_INIT) || (state == HAL_OSPI_STATE_READY)) 8005868: 697b ldr r3, [r7, #20] 800586a: 2b01 cmp r3, #1 800586c: d002 beq.n 8005874 800586e: 697b ldr r3, [r7, #20] 8005870: 2b02 cmp r3, #2 8005872: d122 bne.n 80058ba { /* Wait till busy flag is reset */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout); 8005874: 687b ldr r3, [r7, #4] 8005876: 9300 str r3, [sp, #0] 8005878: 69bb ldr r3, [r7, #24] 800587a: 2200 movs r2, #0 800587c: 2120 movs r1, #32 800587e: 68f8 ldr r0, [r7, #12] 8005880: f000 fd4a bl 8006318 8005884: 4603 mov r3, r0 8005886: 77fb strb r3, [r7, #31] if (status == HAL_OK) 8005888: 7ffb ldrb r3, [r7, #31] 800588a: 2b00 cmp r3, #0 800588c: d11a bne.n 80058c4 { /* Configure Hyperbus configuration Latency register */ WRITE_REG(hospi->Instance->HLCR, ((cfg->RWRecoveryTime << OCTOSPI_HLCR_TRWR_Pos) | 800588e: 68bb ldr r3, [r7, #8] 8005890: 681b ldr r3, [r3, #0] 8005892: 041a lsls r2, r3, #16 8005894: 68bb ldr r3, [r7, #8] 8005896: 685b ldr r3, [r3, #4] 8005898: 021b lsls r3, r3, #8 800589a: 431a orrs r2, r3 800589c: 68bb ldr r3, [r7, #8] 800589e: 689b ldr r3, [r3, #8] 80058a0: ea42 0103 orr.w r1, r2, r3 80058a4: 68bb ldr r3, [r7, #8] 80058a6: 68da ldr r2, [r3, #12] 80058a8: 68fb ldr r3, [r7, #12] 80058aa: 681b ldr r3, [r3, #0] 80058ac: 430a orrs r2, r1 80058ae: f8c3 2200 str.w r2, [r3, #512] ; 0x200 (cfg->AccessTime << OCTOSPI_HLCR_TACC_Pos) | cfg->WriteZeroLatency | cfg->LatencyMode)); /* Update the state */ hospi->State = HAL_OSPI_STATE_READY; 80058b2: 68fb ldr r3, [r7, #12] 80058b4: 2202 movs r2, #2 80058b6: 655a str r2, [r3, #84] ; 0x54 if (status == HAL_OK) 80058b8: e004 b.n 80058c4 } } else { status = HAL_ERROR; 80058ba: 2301 movs r3, #1 80058bc: 77fb strb r3, [r7, #31] hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; 80058be: 68fb ldr r3, [r7, #12] 80058c0: 2210 movs r2, #16 80058c2: 659a str r2, [r3, #88] ; 0x58 } /* Return function status */ return status; 80058c4: 7ffb ldrb r3, [r7, #31] } 80058c6: 4618 mov r0, r3 80058c8: 3720 adds r7, #32 80058ca: 46bd mov sp, r7 80058cc: bd80 pop {r7, pc} 080058ce : * @param hospi : OSPI handle. * @param Timeout : Timeout for the memory access. * @retval None */ HAL_StatusTypeDef HAL_OSPI_SetTimeout(OSPI_HandleTypeDef *hospi, uint32_t Timeout) { 80058ce: b480 push {r7} 80058d0: b083 sub sp, #12 80058d2: af00 add r7, sp, #0 80058d4: 6078 str r0, [r7, #4] 80058d6: 6039 str r1, [r7, #0] hospi->Timeout = Timeout; 80058d8: 687b ldr r3, [r7, #4] 80058da: 683a ldr r2, [r7, #0] 80058dc: 65da str r2, [r3, #92] ; 0x5c return HAL_OK; 80058de: 2300 movs r3, #0 } 80058e0: 4618 mov r0, r3 80058e2: 370c adds r7, #12 80058e4: 46bd mov sp, r7 80058e6: f85d 7b04 ldr.w r7, [sp], #4 80058ea: 4770 bx lr 080058ec : * @param cfg : Configuration of the IO Manager for the instance * @param Timeout : Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout) { 80058ec: b580 push {r7, lr} 80058ee: b094 sub sp, #80 ; 0x50 80058f0: af00 add r7, sp, #0 80058f2: 60f8 str r0, [r7, #12] 80058f4: 60b9 str r1, [r7, #8] 80058f6: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80058f8: 2300 movs r3, #0 80058fa: f887 304f strb.w r3, [r7, #79] ; 0x4f uint32_t instance; uint8_t index; uint8_t ospi_enabled = 0U; 80058fe: 2300 movs r3, #0 8005900: f887 3046 strb.w r3, [r7, #70] ; 0x46 assert_param(IS_OSPIM_PORT(cfg->NCSPort)); assert_param(IS_OSPIM_IO_PORT(cfg->IOLowPort)); assert_param(IS_OSPIM_IO_PORT(cfg->IOHighPort)); assert_param(IS_OSPIM_REQ2ACKTIME(cfg->Req2AckTime)); if (hospi->Instance == OCTOSPI1) 8005904: 68fb ldr r3, [r7, #12] 8005906: 681b ldr r3, [r3, #0] 8005908: 4aa3 ldr r2, [pc, #652] ; (8005b98 ) 800590a: 4293 cmp r3, r2 800590c: d105 bne.n 800591a { instance = 0U; 800590e: 2300 movs r3, #0 8005910: 64bb str r3, [r7, #72] ; 0x48 other_instance = 1U; 8005912: 2301 movs r3, #1 8005914: f887 3045 strb.w r3, [r7, #69] ; 0x45 8005918: e004 b.n 8005924 } else { instance = 1U; 800591a: 2301 movs r3, #1 800591c: 64bb str r3, [r7, #72] ; 0x48 other_instance = 0U; 800591e: 2300 movs r3, #0 8005920: f887 3045 strb.w r3, [r7, #69] ; 0x45 } /**************** Get current configuration of the instances ****************/ for (index = 0U; index < OSPI_NB_INSTANCE; index++) 8005924: 2300 movs r3, #0 8005926: f887 3047 strb.w r3, [r7, #71] ; 0x47 800592a: e01d b.n 8005968 { if (OSPIM_GetConfig(index+1U, &(IOM_cfg[index])) != HAL_OK) 800592c: f897 3047 ldrb.w r3, [r7, #71] ; 0x47 8005930: 3301 adds r3, #1 8005932: b2d8 uxtb r0, r3 8005934: f897 2047 ldrb.w r2, [r7, #71] ; 0x47 8005938: f107 0114 add.w r1, r7, #20 800593c: 4613 mov r3, r2 800593e: 005b lsls r3, r3, #1 8005940: 4413 add r3, r2 8005942: 00db lsls r3, r3, #3 8005944: 440b add r3, r1 8005946: 4619 mov r1, r3 8005948: f000 fd1e bl 8006388 800594c: 4603 mov r3, r0 800594e: 2b00 cmp r3, #0 8005950: d005 beq.n 800595e { status = HAL_ERROR; 8005952: 2301 movs r3, #1 8005954: f887 304f strb.w r3, [r7, #79] ; 0x4f hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; 8005958: 68fb ldr r3, [r7, #12] 800595a: 2208 movs r2, #8 800595c: 659a str r2, [r3, #88] ; 0x58 for (index = 0U; index < OSPI_NB_INSTANCE; index++) 800595e: f897 3047 ldrb.w r3, [r7, #71] ; 0x47 8005962: 3301 adds r3, #1 8005964: f887 3047 strb.w r3, [r7, #71] ; 0x47 8005968: f897 3047 ldrb.w r3, [r7, #71] ; 0x47 800596c: 2b01 cmp r3, #1 800596e: d9dd bls.n 800592c } } if (status == HAL_OK) 8005970: f897 304f ldrb.w r3, [r7, #79] ; 0x4f 8005974: 2b00 cmp r3, #0 8005976: f040 84c3 bne.w 8006300 { /********** Disable both OctoSPI to configure OctoSPI IO Manager **********/ if ((OCTOSPI1->CR & OCTOSPI_CR_EN) != 0U) 800597a: 4b87 ldr r3, [pc, #540] ; (8005b98 ) 800597c: 681b ldr r3, [r3, #0] 800597e: f003 0301 and.w r3, r3, #1 8005982: 2b00 cmp r3, #0 8005984: d00b beq.n 800599e { CLEAR_BIT(OCTOSPI1->CR, OCTOSPI_CR_EN); 8005986: 4b84 ldr r3, [pc, #528] ; (8005b98 ) 8005988: 681b ldr r3, [r3, #0] 800598a: 4a83 ldr r2, [pc, #524] ; (8005b98 ) 800598c: f023 0301 bic.w r3, r3, #1 8005990: 6013 str r3, [r2, #0] ospi_enabled |= 0x1U; 8005992: f897 3046 ldrb.w r3, [r7, #70] ; 0x46 8005996: f043 0301 orr.w r3, r3, #1 800599a: f887 3046 strb.w r3, [r7, #70] ; 0x46 } if ((OCTOSPI2->CR & OCTOSPI_CR_EN) != 0U) 800599e: 4b7f ldr r3, [pc, #508] ; (8005b9c ) 80059a0: 681b ldr r3, [r3, #0] 80059a2: f003 0301 and.w r3, r3, #1 80059a6: 2b00 cmp r3, #0 80059a8: d00b beq.n 80059c2 { CLEAR_BIT(OCTOSPI2->CR, OCTOSPI_CR_EN); 80059aa: 4b7c ldr r3, [pc, #496] ; (8005b9c ) 80059ac: 681b ldr r3, [r3, #0] 80059ae: 4a7b ldr r2, [pc, #492] ; (8005b9c ) 80059b0: f023 0301 bic.w r3, r3, #1 80059b4: 6013 str r3, [r2, #0] ospi_enabled |= 0x2U; 80059b6: f897 3046 ldrb.w r3, [r7, #70] ; 0x46 80059ba: f043 0302 orr.w r3, r3, #2 80059be: f887 3046 strb.w r3, [r7, #70] ; 0x46 } /***************** Deactivation of previous configuration *****************/ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN); 80059c2: 4977 ldr r1, [pc, #476] ; (8005ba0 ) 80059c4: 6cba ldr r2, [r7, #72] ; 0x48 80059c6: 4613 mov r3, r2 80059c8: 005b lsls r3, r3, #1 80059ca: 4413 add r3, r2 80059cc: 00db lsls r3, r3, #3 80059ce: f107 0250 add.w r2, r7, #80 ; 0x50 80059d2: 4413 add r3, r2 80059d4: 3b34 subs r3, #52 ; 0x34 80059d6: 681b ldr r3, [r3, #0] 80059d8: 3b01 subs r3, #1 80059da: 009b lsls r3, r3, #2 80059dc: 440b add r3, r1 80059de: 6859 ldr r1, [r3, #4] 80059e0: 486f ldr r0, [pc, #444] ; (8005ba0 ) 80059e2: 6cba ldr r2, [r7, #72] ; 0x48 80059e4: 4613 mov r3, r2 80059e6: 005b lsls r3, r3, #1 80059e8: 4413 add r3, r2 80059ea: 00db lsls r3, r3, #3 80059ec: f107 0250 add.w r2, r7, #80 ; 0x50 80059f0: 4413 add r3, r2 80059f2: 3b34 subs r3, #52 ; 0x34 80059f4: 681b ldr r3, [r3, #0] 80059f6: 3b01 subs r3, #1 80059f8: f421 7280 bic.w r2, r1, #256 ; 0x100 80059fc: 009b lsls r3, r3, #2 80059fe: 4403 add r3, r0 8005a00: 605a str r2, [r3, #4] if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) != 0U) 8005a02: 4b67 ldr r3, [pc, #412] ; (8005ba0 ) 8005a04: 681b ldr r3, [r3, #0] 8005a06: f003 0301 and.w r3, r3, #1 8005a0a: 2b00 cmp r3, #0 8005a0c: f000 80ca beq.w 8005ba4 { /* De-multiplexing should be performed */ CLEAR_BIT(OCTOSPIM->CR, OCTOSPIM_CR_MUXEN); 8005a10: 4b63 ldr r3, [pc, #396] ; (8005ba0 ) 8005a12: 681b ldr r3, [r3, #0] 8005a14: 4a62 ldr r2, [pc, #392] ; (8005ba0 ) 8005a16: f023 0301 bic.w r3, r3, #1 8005a1a: 6013 str r3, [r2, #0] if (other_instance == 1U) 8005a1c: f897 3045 ldrb.w r3, [r7, #69] ; 0x45 8005a20: 2b01 cmp r3, #1 8005a22: f040 8178 bne.w 8005d16 { SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKSRC); 8005a26: 495e ldr r1, [pc, #376] ; (8005ba0 ) 8005a28: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005a2c: 4613 mov r3, r2 8005a2e: 005b lsls r3, r3, #1 8005a30: 4413 add r3, r2 8005a32: 00db lsls r3, r3, #3 8005a34: f107 0250 add.w r2, r7, #80 ; 0x50 8005a38: 4413 add r3, r2 8005a3a: 3b3c subs r3, #60 ; 0x3c 8005a3c: 681b ldr r3, [r3, #0] 8005a3e: 3b01 subs r3, #1 8005a40: 009b lsls r3, r3, #2 8005a42: 440b add r3, r1 8005a44: 6859 ldr r1, [r3, #4] 8005a46: 4856 ldr r0, [pc, #344] ; (8005ba0 ) 8005a48: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005a4c: 4613 mov r3, r2 8005a4e: 005b lsls r3, r3, #1 8005a50: 4413 add r3, r2 8005a52: 00db lsls r3, r3, #3 8005a54: f107 0250 add.w r2, r7, #80 ; 0x50 8005a58: 4413 add r3, r2 8005a5a: 3b3c subs r3, #60 ; 0x3c 8005a5c: 681b ldr r3, [r3, #0] 8005a5e: 3b01 subs r3, #1 8005a60: f041 0202 orr.w r2, r1, #2 8005a64: 009b lsls r3, r3, #2 8005a66: 4403 add r3, r0 8005a68: 605a str r2, [r3, #4] if (IOM_cfg[other_instance].DQSPort != 0U) 8005a6a: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005a6e: 4613 mov r3, r2 8005a70: 005b lsls r3, r3, #1 8005a72: 4413 add r3, r2 8005a74: 00db lsls r3, r3, #3 8005a76: f107 0250 add.w r2, r7, #80 ; 0x50 8005a7a: 4413 add r3, r2 8005a7c: 3b38 subs r3, #56 ; 0x38 8005a7e: 681b ldr r3, [r3, #0] 8005a80: 2b00 cmp r3, #0 8005a82: d021 beq.n 8005ac8 { SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSSRC); 8005a84: 4946 ldr r1, [pc, #280] ; (8005ba0 ) 8005a86: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005a8a: 4613 mov r3, r2 8005a8c: 005b lsls r3, r3, #1 8005a8e: 4413 add r3, r2 8005a90: 00db lsls r3, r3, #3 8005a92: f107 0250 add.w r2, r7, #80 ; 0x50 8005a96: 4413 add r3, r2 8005a98: 3b38 subs r3, #56 ; 0x38 8005a9a: 681b ldr r3, [r3, #0] 8005a9c: 3b01 subs r3, #1 8005a9e: 009b lsls r3, r3, #2 8005aa0: 440b add r3, r1 8005aa2: 6859 ldr r1, [r3, #4] 8005aa4: 483e ldr r0, [pc, #248] ; (8005ba0 ) 8005aa6: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005aaa: 4613 mov r3, r2 8005aac: 005b lsls r3, r3, #1 8005aae: 4413 add r3, r2 8005ab0: 00db lsls r3, r3, #3 8005ab2: f107 0250 add.w r2, r7, #80 ; 0x50 8005ab6: 4413 add r3, r2 8005ab8: 3b38 subs r3, #56 ; 0x38 8005aba: 681b ldr r3, [r3, #0] 8005abc: 3b01 subs r3, #1 8005abe: f041 0220 orr.w r2, r1, #32 8005ac2: 009b lsls r3, r3, #2 8005ac4: 4403 add r3, r0 8005ac6: 605a str r2, [r3, #4] } if (IOM_cfg[other_instance].IOLowPort != HAL_OSPIM_IOPORT_NONE) 8005ac8: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005acc: 4613 mov r3, r2 8005ace: 005b lsls r3, r3, #1 8005ad0: 4413 add r3, r2 8005ad2: 00db lsls r3, r3, #3 8005ad4: f107 0250 add.w r2, r7, #80 ; 0x50 8005ad8: 4413 add r3, r2 8005ada: 3b30 subs r3, #48 ; 0x30 8005adc: 681b ldr r3, [r3, #0] 8005ade: 2b00 cmp r3, #0 8005ae0: d025 beq.n 8005b2e { SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLSRC_1); 8005ae2: 492f ldr r1, [pc, #188] ; (8005ba0 ) 8005ae4: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005ae8: 4613 mov r3, r2 8005aea: 005b lsls r3, r3, #1 8005aec: 4413 add r3, r2 8005aee: 00db lsls r3, r3, #3 8005af0: f107 0250 add.w r2, r7, #80 ; 0x50 8005af4: 4413 add r3, r2 8005af6: 3b30 subs r3, #48 ; 0x30 8005af8: 681b ldr r3, [r3, #0] 8005afa: 3b01 subs r3, #1 8005afc: f003 0301 and.w r3, r3, #1 8005b00: 009b lsls r3, r3, #2 8005b02: 440b add r3, r1 8005b04: 6859 ldr r1, [r3, #4] 8005b06: 4826 ldr r0, [pc, #152] ; (8005ba0 ) 8005b08: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005b0c: 4613 mov r3, r2 8005b0e: 005b lsls r3, r3, #1 8005b10: 4413 add r3, r2 8005b12: 00db lsls r3, r3, #3 8005b14: f107 0250 add.w r2, r7, #80 ; 0x50 8005b18: 4413 add r3, r2 8005b1a: 3b30 subs r3, #48 ; 0x30 8005b1c: 681b ldr r3, [r3, #0] 8005b1e: 3b01 subs r3, #1 8005b20: f003 0301 and.w r3, r3, #1 8005b24: f441 2280 orr.w r2, r1, #262144 ; 0x40000 8005b28: 009b lsls r3, r3, #2 8005b2a: 4403 add r3, r0 8005b2c: 605a str r2, [r3, #4] } if (IOM_cfg[other_instance].IOHighPort != HAL_OSPIM_IOPORT_NONE) 8005b2e: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005b32: 4613 mov r3, r2 8005b34: 005b lsls r3, r3, #1 8005b36: 4413 add r3, r2 8005b38: 00db lsls r3, r3, #3 8005b3a: f107 0250 add.w r2, r7, #80 ; 0x50 8005b3e: 4413 add r3, r2 8005b40: 3b2c subs r3, #44 ; 0x2c 8005b42: 681b ldr r3, [r3, #0] 8005b44: 2b00 cmp r3, #0 8005b46: f000 80e6 beq.w 8005d16 { SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHSRC_1); 8005b4a: 4915 ldr r1, [pc, #84] ; (8005ba0 ) 8005b4c: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005b50: 4613 mov r3, r2 8005b52: 005b lsls r3, r3, #1 8005b54: 4413 add r3, r2 8005b56: 00db lsls r3, r3, #3 8005b58: f107 0250 add.w r2, r7, #80 ; 0x50 8005b5c: 4413 add r3, r2 8005b5e: 3b2c subs r3, #44 ; 0x2c 8005b60: 681b ldr r3, [r3, #0] 8005b62: 3b01 subs r3, #1 8005b64: f003 0301 and.w r3, r3, #1 8005b68: 009b lsls r3, r3, #2 8005b6a: 440b add r3, r1 8005b6c: 6859 ldr r1, [r3, #4] 8005b6e: 480c ldr r0, [pc, #48] ; (8005ba0 ) 8005b70: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005b74: 4613 mov r3, r2 8005b76: 005b lsls r3, r3, #1 8005b78: 4413 add r3, r2 8005b7a: 00db lsls r3, r3, #3 8005b7c: f107 0250 add.w r2, r7, #80 ; 0x50 8005b80: 4413 add r3, r2 8005b82: 3b2c subs r3, #44 ; 0x2c 8005b84: 681b ldr r3, [r3, #0] 8005b86: 3b01 subs r3, #1 8005b88: f003 0301 and.w r3, r3, #1 8005b8c: f041 6280 orr.w r2, r1, #67108864 ; 0x4000000 8005b90: 009b lsls r3, r3, #2 8005b92: 4403 add r3, r0 8005b94: 605a str r2, [r3, #4] 8005b96: e0be b.n 8005d16 8005b98: 52005000 .word 0x52005000 8005b9c: 5200a000 .word 0x5200a000 8005ba0: 5200b400 .word 0x5200b400 } } } else { if (IOM_cfg[instance].ClkPort != 0U) 8005ba4: 6cba ldr r2, [r7, #72] ; 0x48 8005ba6: 4613 mov r3, r2 8005ba8: 005b lsls r3, r3, #1 8005baa: 4413 add r3, r2 8005bac: 00db lsls r3, r3, #3 8005bae: f107 0250 add.w r2, r7, #80 ; 0x50 8005bb2: 4413 add r3, r2 8005bb4: 3b3c subs r3, #60 ; 0x3c 8005bb6: 681b ldr r3, [r3, #0] 8005bb8: 2b00 cmp r3, #0 8005bba: f000 80ac beq.w 8005d16 { CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN); 8005bbe: 499d ldr r1, [pc, #628] ; (8005e34 ) 8005bc0: 6cba ldr r2, [r7, #72] ; 0x48 8005bc2: 4613 mov r3, r2 8005bc4: 005b lsls r3, r3, #1 8005bc6: 4413 add r3, r2 8005bc8: 00db lsls r3, r3, #3 8005bca: f107 0250 add.w r2, r7, #80 ; 0x50 8005bce: 4413 add r3, r2 8005bd0: 3b3c subs r3, #60 ; 0x3c 8005bd2: 681b ldr r3, [r3, #0] 8005bd4: 3b01 subs r3, #1 8005bd6: 009b lsls r3, r3, #2 8005bd8: 440b add r3, r1 8005bda: 6859 ldr r1, [r3, #4] 8005bdc: 4895 ldr r0, [pc, #596] ; (8005e34 ) 8005bde: 6cba ldr r2, [r7, #72] ; 0x48 8005be0: 4613 mov r3, r2 8005be2: 005b lsls r3, r3, #1 8005be4: 4413 add r3, r2 8005be6: 00db lsls r3, r3, #3 8005be8: f107 0250 add.w r2, r7, #80 ; 0x50 8005bec: 4413 add r3, r2 8005bee: 3b3c subs r3, #60 ; 0x3c 8005bf0: 681b ldr r3, [r3, #0] 8005bf2: 3b01 subs r3, #1 8005bf4: f021 0201 bic.w r2, r1, #1 8005bf8: 009b lsls r3, r3, #2 8005bfa: 4403 add r3, r0 8005bfc: 605a str r2, [r3, #4] if (IOM_cfg[instance].DQSPort != 0U) 8005bfe: 6cba ldr r2, [r7, #72] ; 0x48 8005c00: 4613 mov r3, r2 8005c02: 005b lsls r3, r3, #1 8005c04: 4413 add r3, r2 8005c06: 00db lsls r3, r3, #3 8005c08: f107 0250 add.w r2, r7, #80 ; 0x50 8005c0c: 4413 add r3, r2 8005c0e: 3b38 subs r3, #56 ; 0x38 8005c10: 681b ldr r3, [r3, #0] 8005c12: 2b00 cmp r3, #0 8005c14: d01f beq.n 8005c56 { CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN); 8005c16: 4987 ldr r1, [pc, #540] ; (8005e34 ) 8005c18: 6cba ldr r2, [r7, #72] ; 0x48 8005c1a: 4613 mov r3, r2 8005c1c: 005b lsls r3, r3, #1 8005c1e: 4413 add r3, r2 8005c20: 00db lsls r3, r3, #3 8005c22: f107 0250 add.w r2, r7, #80 ; 0x50 8005c26: 4413 add r3, r2 8005c28: 3b38 subs r3, #56 ; 0x38 8005c2a: 681b ldr r3, [r3, #0] 8005c2c: 3b01 subs r3, #1 8005c2e: 009b lsls r3, r3, #2 8005c30: 440b add r3, r1 8005c32: 6859 ldr r1, [r3, #4] 8005c34: 487f ldr r0, [pc, #508] ; (8005e34 ) 8005c36: 6cba ldr r2, [r7, #72] ; 0x48 8005c38: 4613 mov r3, r2 8005c3a: 005b lsls r3, r3, #1 8005c3c: 4413 add r3, r2 8005c3e: 00db lsls r3, r3, #3 8005c40: f107 0250 add.w r2, r7, #80 ; 0x50 8005c44: 4413 add r3, r2 8005c46: 3b38 subs r3, #56 ; 0x38 8005c48: 681b ldr r3, [r3, #0] 8005c4a: 3b01 subs r3, #1 8005c4c: f021 0210 bic.w r2, r1, #16 8005c50: 009b lsls r3, r3, #2 8005c52: 4403 add r3, r0 8005c54: 605a str r2, [r3, #4] } if (IOM_cfg[instance].IOLowPort != HAL_OSPIM_IOPORT_NONE) 8005c56: 6cba ldr r2, [r7, #72] ; 0x48 8005c58: 4613 mov r3, r2 8005c5a: 005b lsls r3, r3, #1 8005c5c: 4413 add r3, r2 8005c5e: 00db lsls r3, r3, #3 8005c60: f107 0250 add.w r2, r7, #80 ; 0x50 8005c64: 4413 add r3, r2 8005c66: 3b30 subs r3, #48 ; 0x30 8005c68: 681b ldr r3, [r3, #0] 8005c6a: 2b00 cmp r3, #0 8005c6c: d023 beq.n 8005cb6 { CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN); 8005c6e: 4971 ldr r1, [pc, #452] ; (8005e34 ) 8005c70: 6cba ldr r2, [r7, #72] ; 0x48 8005c72: 4613 mov r3, r2 8005c74: 005b lsls r3, r3, #1 8005c76: 4413 add r3, r2 8005c78: 00db lsls r3, r3, #3 8005c7a: f107 0250 add.w r2, r7, #80 ; 0x50 8005c7e: 4413 add r3, r2 8005c80: 3b30 subs r3, #48 ; 0x30 8005c82: 681b ldr r3, [r3, #0] 8005c84: 3b01 subs r3, #1 8005c86: f003 0301 and.w r3, r3, #1 8005c8a: 009b lsls r3, r3, #2 8005c8c: 440b add r3, r1 8005c8e: 6859 ldr r1, [r3, #4] 8005c90: 4868 ldr r0, [pc, #416] ; (8005e34 ) 8005c92: 6cba ldr r2, [r7, #72] ; 0x48 8005c94: 4613 mov r3, r2 8005c96: 005b lsls r3, r3, #1 8005c98: 4413 add r3, r2 8005c9a: 00db lsls r3, r3, #3 8005c9c: f107 0250 add.w r2, r7, #80 ; 0x50 8005ca0: 4413 add r3, r2 8005ca2: 3b30 subs r3, #48 ; 0x30 8005ca4: 681b ldr r3, [r3, #0] 8005ca6: 3b01 subs r3, #1 8005ca8: f003 0301 and.w r3, r3, #1 8005cac: f421 3280 bic.w r2, r1, #65536 ; 0x10000 8005cb0: 009b lsls r3, r3, #2 8005cb2: 4403 add r3, r0 8005cb4: 605a str r2, [r3, #4] } if (IOM_cfg[instance].IOHighPort != HAL_OSPIM_IOPORT_NONE) 8005cb6: 6cba ldr r2, [r7, #72] ; 0x48 8005cb8: 4613 mov r3, r2 8005cba: 005b lsls r3, r3, #1 8005cbc: 4413 add r3, r2 8005cbe: 00db lsls r3, r3, #3 8005cc0: f107 0250 add.w r2, r7, #80 ; 0x50 8005cc4: 4413 add r3, r2 8005cc6: 3b2c subs r3, #44 ; 0x2c 8005cc8: 681b ldr r3, [r3, #0] 8005cca: 2b00 cmp r3, #0 8005ccc: d023 beq.n 8005d16 { CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN); 8005cce: 4959 ldr r1, [pc, #356] ; (8005e34 ) 8005cd0: 6cba ldr r2, [r7, #72] ; 0x48 8005cd2: 4613 mov r3, r2 8005cd4: 005b lsls r3, r3, #1 8005cd6: 4413 add r3, r2 8005cd8: 00db lsls r3, r3, #3 8005cda: f107 0250 add.w r2, r7, #80 ; 0x50 8005cde: 4413 add r3, r2 8005ce0: 3b2c subs r3, #44 ; 0x2c 8005ce2: 681b ldr r3, [r3, #0] 8005ce4: 3b01 subs r3, #1 8005ce6: f003 0301 and.w r3, r3, #1 8005cea: 009b lsls r3, r3, #2 8005cec: 440b add r3, r1 8005cee: 6859 ldr r1, [r3, #4] 8005cf0: 4850 ldr r0, [pc, #320] ; (8005e34 ) 8005cf2: 6cba ldr r2, [r7, #72] ; 0x48 8005cf4: 4613 mov r3, r2 8005cf6: 005b lsls r3, r3, #1 8005cf8: 4413 add r3, r2 8005cfa: 00db lsls r3, r3, #3 8005cfc: f107 0250 add.w r2, r7, #80 ; 0x50 8005d00: 4413 add r3, r2 8005d02: 3b2c subs r3, #44 ; 0x2c 8005d04: 681b ldr r3, [r3, #0] 8005d06: 3b01 subs r3, #1 8005d08: f003 0301 and.w r3, r3, #1 8005d0c: f021 7280 bic.w r2, r1, #16777216 ; 0x1000000 8005d10: 009b lsls r3, r3, #2 8005d12: 4403 add r3, r0 8005d14: 605a str r2, [r3, #4] } } } /********************* Deactivation of other instance *********************/ if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) || 8005d16: 68bb ldr r3, [r7, #8] 8005d18: 6819 ldr r1, [r3, #0] 8005d1a: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005d1e: 4613 mov r3, r2 8005d20: 005b lsls r3, r3, #1 8005d22: 4413 add r3, r2 8005d24: 00db lsls r3, r3, #3 8005d26: f107 0250 add.w r2, r7, #80 ; 0x50 8005d2a: 4413 add r3, r2 8005d2c: 3b3c subs r3, #60 ; 0x3c 8005d2e: 681b ldr r3, [r3, #0] 8005d30: 4299 cmp r1, r3 8005d32: d03c beq.n 8005dae 8005d34: 68bb ldr r3, [r7, #8] 8005d36: 6859 ldr r1, [r3, #4] 8005d38: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005d3c: 4613 mov r3, r2 8005d3e: 005b lsls r3, r3, #1 8005d40: 4413 add r3, r2 8005d42: 00db lsls r3, r3, #3 8005d44: f107 0250 add.w r2, r7, #80 ; 0x50 8005d48: 4413 add r3, r2 8005d4a: 3b38 subs r3, #56 ; 0x38 8005d4c: 681b ldr r3, [r3, #0] 8005d4e: 4299 cmp r1, r3 8005d50: d02d beq.n 8005dae (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || 8005d52: 68bb ldr r3, [r7, #8] 8005d54: 6899 ldr r1, [r3, #8] 8005d56: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005d5a: 4613 mov r3, r2 8005d5c: 005b lsls r3, r3, #1 8005d5e: 4413 add r3, r2 8005d60: 00db lsls r3, r3, #3 8005d62: f107 0250 add.w r2, r7, #80 ; 0x50 8005d66: 4413 add r3, r2 8005d68: 3b34 subs r3, #52 ; 0x34 8005d6a: 681b ldr r3, [r3, #0] if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) || 8005d6c: 4299 cmp r1, r3 8005d6e: d01e beq.n 8005dae (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || 8005d70: 68bb ldr r3, [r7, #8] 8005d72: 68d9 ldr r1, [r3, #12] 8005d74: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005d78: 4613 mov r3, r2 8005d7a: 005b lsls r3, r3, #1 8005d7c: 4413 add r3, r2 8005d7e: 00db lsls r3, r3, #3 8005d80: f107 0250 add.w r2, r7, #80 ; 0x50 8005d84: 4413 add r3, r2 8005d86: 3b30 subs r3, #48 ; 0x30 8005d88: 681b ldr r3, [r3, #0] 8005d8a: 4299 cmp r1, r3 8005d8c: d00f beq.n 8005dae (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort)) 8005d8e: 68bb ldr r3, [r7, #8] 8005d90: 6919 ldr r1, [r3, #16] 8005d92: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005d96: 4613 mov r3, r2 8005d98: 005b lsls r3, r3, #1 8005d9a: 4413 add r3, r2 8005d9c: 00db lsls r3, r3, #3 8005d9e: f107 0250 add.w r2, r7, #80 ; 0x50 8005da2: 4413 add r3, r2 8005da4: 3b2c subs r3, #44 ; 0x2c 8005da6: 681b ldr r3, [r3, #0] (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || 8005da8: 4299 cmp r1, r3 8005daa: f040 811e bne.w 8005fea { if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) && 8005dae: 68bb ldr r3, [r7, #8] 8005db0: 6819 ldr r1, [r3, #0] 8005db2: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005db6: 4613 mov r3, r2 8005db8: 005b lsls r3, r3, #1 8005dba: 4413 add r3, r2 8005dbc: 00db lsls r3, r3, #3 8005dbe: f107 0250 add.w r2, r7, #80 ; 0x50 8005dc2: 4413 add r3, r2 8005dc4: 3b3c subs r3, #60 ; 0x3c 8005dc6: 681b ldr r3, [r3, #0] 8005dc8: 4299 cmp r1, r3 8005dca: d135 bne.n 8005e38 (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) && 8005dcc: 68bb ldr r3, [r7, #8] 8005dce: 6859 ldr r1, [r3, #4] 8005dd0: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005dd4: 4613 mov r3, r2 8005dd6: 005b lsls r3, r3, #1 8005dd8: 4413 add r3, r2 8005dda: 00db lsls r3, r3, #3 8005ddc: f107 0250 add.w r2, r7, #80 ; 0x50 8005de0: 4413 add r3, r2 8005de2: 3b38 subs r3, #56 ; 0x38 8005de4: 681b ldr r3, [r3, #0] if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) && 8005de6: 4299 cmp r1, r3 8005de8: d126 bne.n 8005e38 (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) && 8005dea: 68bb ldr r3, [r7, #8] 8005dec: 68d9 ldr r1, [r3, #12] 8005dee: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005df2: 4613 mov r3, r2 8005df4: 005b lsls r3, r3, #1 8005df6: 4413 add r3, r2 8005df8: 00db lsls r3, r3, #3 8005dfa: f107 0250 add.w r2, r7, #80 ; 0x50 8005dfe: 4413 add r3, r2 8005e00: 3b30 subs r3, #48 ; 0x30 8005e02: 681b ldr r3, [r3, #0] (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) && 8005e04: 4299 cmp r1, r3 8005e06: d117 bne.n 8005e38 (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort)) 8005e08: 68bb ldr r3, [r7, #8] 8005e0a: 6919 ldr r1, [r3, #16] 8005e0c: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005e10: 4613 mov r3, r2 8005e12: 005b lsls r3, r3, #1 8005e14: 4413 add r3, r2 8005e16: 00db lsls r3, r3, #3 8005e18: f107 0250 add.w r2, r7, #80 ; 0x50 8005e1c: 4413 add r3, r2 8005e1e: 3b2c subs r3, #44 ; 0x2c 8005e20: 681b ldr r3, [r3, #0] (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) && 8005e22: 4299 cmp r1, r3 8005e24: d108 bne.n 8005e38 { /* Multiplexing should be performed */ SET_BIT(OCTOSPIM->CR, OCTOSPIM_CR_MUXEN); 8005e26: 4b03 ldr r3, [pc, #12] ; (8005e34 ) 8005e28: 681b ldr r3, [r3, #0] 8005e2a: 4a02 ldr r2, [pc, #8] ; (8005e34 ) 8005e2c: f043 0301 orr.w r3, r3, #1 8005e30: 6013 str r3, [r2, #0] 8005e32: e0da b.n 8005fea 8005e34: 5200b400 .word 0x5200b400 } else { CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN); 8005e38: 49c2 ldr r1, [pc, #776] ; (8006144 ) 8005e3a: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005e3e: 4613 mov r3, r2 8005e40: 005b lsls r3, r3, #1 8005e42: 4413 add r3, r2 8005e44: 00db lsls r3, r3, #3 8005e46: f107 0250 add.w r2, r7, #80 ; 0x50 8005e4a: 4413 add r3, r2 8005e4c: 3b3c subs r3, #60 ; 0x3c 8005e4e: 681b ldr r3, [r3, #0] 8005e50: 3b01 subs r3, #1 8005e52: 009b lsls r3, r3, #2 8005e54: 440b add r3, r1 8005e56: 6859 ldr r1, [r3, #4] 8005e58: 48ba ldr r0, [pc, #744] ; (8006144 ) 8005e5a: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005e5e: 4613 mov r3, r2 8005e60: 005b lsls r3, r3, #1 8005e62: 4413 add r3, r2 8005e64: 00db lsls r3, r3, #3 8005e66: f107 0250 add.w r2, r7, #80 ; 0x50 8005e6a: 4413 add r3, r2 8005e6c: 3b3c subs r3, #60 ; 0x3c 8005e6e: 681b ldr r3, [r3, #0] 8005e70: 3b01 subs r3, #1 8005e72: f021 0201 bic.w r2, r1, #1 8005e76: 009b lsls r3, r3, #2 8005e78: 4403 add r3, r0 8005e7a: 605a str r2, [r3, #4] if (IOM_cfg[other_instance].DQSPort != 0U) 8005e7c: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005e80: 4613 mov r3, r2 8005e82: 005b lsls r3, r3, #1 8005e84: 4413 add r3, r2 8005e86: 00db lsls r3, r3, #3 8005e88: f107 0250 add.w r2, r7, #80 ; 0x50 8005e8c: 4413 add r3, r2 8005e8e: 3b38 subs r3, #56 ; 0x38 8005e90: 681b ldr r3, [r3, #0] 8005e92: 2b00 cmp r3, #0 8005e94: d021 beq.n 8005eda { CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN); 8005e96: 49ab ldr r1, [pc, #684] ; (8006144 ) 8005e98: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005e9c: 4613 mov r3, r2 8005e9e: 005b lsls r3, r3, #1 8005ea0: 4413 add r3, r2 8005ea2: 00db lsls r3, r3, #3 8005ea4: f107 0250 add.w r2, r7, #80 ; 0x50 8005ea8: 4413 add r3, r2 8005eaa: 3b38 subs r3, #56 ; 0x38 8005eac: 681b ldr r3, [r3, #0] 8005eae: 3b01 subs r3, #1 8005eb0: 009b lsls r3, r3, #2 8005eb2: 440b add r3, r1 8005eb4: 6859 ldr r1, [r3, #4] 8005eb6: 48a3 ldr r0, [pc, #652] ; (8006144 ) 8005eb8: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005ebc: 4613 mov r3, r2 8005ebe: 005b lsls r3, r3, #1 8005ec0: 4413 add r3, r2 8005ec2: 00db lsls r3, r3, #3 8005ec4: f107 0250 add.w r2, r7, #80 ; 0x50 8005ec8: 4413 add r3, r2 8005eca: 3b38 subs r3, #56 ; 0x38 8005ecc: 681b ldr r3, [r3, #0] 8005ece: 3b01 subs r3, #1 8005ed0: f021 0210 bic.w r2, r1, #16 8005ed4: 009b lsls r3, r3, #2 8005ed6: 4403 add r3, r0 8005ed8: 605a str r2, [r3, #4] } CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN); 8005eda: 499a ldr r1, [pc, #616] ; (8006144 ) 8005edc: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005ee0: 4613 mov r3, r2 8005ee2: 005b lsls r3, r3, #1 8005ee4: 4413 add r3, r2 8005ee6: 00db lsls r3, r3, #3 8005ee8: f107 0250 add.w r2, r7, #80 ; 0x50 8005eec: 4413 add r3, r2 8005eee: 3b34 subs r3, #52 ; 0x34 8005ef0: 681b ldr r3, [r3, #0] 8005ef2: 3b01 subs r3, #1 8005ef4: 009b lsls r3, r3, #2 8005ef6: 440b add r3, r1 8005ef8: 6859 ldr r1, [r3, #4] 8005efa: 4892 ldr r0, [pc, #584] ; (8006144 ) 8005efc: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005f00: 4613 mov r3, r2 8005f02: 005b lsls r3, r3, #1 8005f04: 4413 add r3, r2 8005f06: 00db lsls r3, r3, #3 8005f08: f107 0250 add.w r2, r7, #80 ; 0x50 8005f0c: 4413 add r3, r2 8005f0e: 3b34 subs r3, #52 ; 0x34 8005f10: 681b ldr r3, [r3, #0] 8005f12: 3b01 subs r3, #1 8005f14: f421 7280 bic.w r2, r1, #256 ; 0x100 8005f18: 009b lsls r3, r3, #2 8005f1a: 4403 add r3, r0 8005f1c: 605a str r2, [r3, #4] if (IOM_cfg[other_instance].IOLowPort != HAL_OSPIM_IOPORT_NONE) 8005f1e: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005f22: 4613 mov r3, r2 8005f24: 005b lsls r3, r3, #1 8005f26: 4413 add r3, r2 8005f28: 00db lsls r3, r3, #3 8005f2a: f107 0250 add.w r2, r7, #80 ; 0x50 8005f2e: 4413 add r3, r2 8005f30: 3b30 subs r3, #48 ; 0x30 8005f32: 681b ldr r3, [r3, #0] 8005f34: 2b00 cmp r3, #0 8005f36: d025 beq.n 8005f84 { CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], 8005f38: 4982 ldr r1, [pc, #520] ; (8006144 ) 8005f3a: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005f3e: 4613 mov r3, r2 8005f40: 005b lsls r3, r3, #1 8005f42: 4413 add r3, r2 8005f44: 00db lsls r3, r3, #3 8005f46: f107 0250 add.w r2, r7, #80 ; 0x50 8005f4a: 4413 add r3, r2 8005f4c: 3b30 subs r3, #48 ; 0x30 8005f4e: 681b ldr r3, [r3, #0] 8005f50: 3b01 subs r3, #1 8005f52: f003 0301 and.w r3, r3, #1 8005f56: 009b lsls r3, r3, #2 8005f58: 440b add r3, r1 8005f5a: 6859 ldr r1, [r3, #4] 8005f5c: 4879 ldr r0, [pc, #484] ; (8006144 ) 8005f5e: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005f62: 4613 mov r3, r2 8005f64: 005b lsls r3, r3, #1 8005f66: 4413 add r3, r2 8005f68: 00db lsls r3, r3, #3 8005f6a: f107 0250 add.w r2, r7, #80 ; 0x50 8005f6e: 4413 add r3, r2 8005f70: 3b30 subs r3, #48 ; 0x30 8005f72: 681b ldr r3, [r3, #0] 8005f74: 3b01 subs r3, #1 8005f76: f003 0301 and.w r3, r3, #1 8005f7a: f421 3280 bic.w r2, r1, #65536 ; 0x10000 8005f7e: 009b lsls r3, r3, #2 8005f80: 4403 add r3, r0 8005f82: 605a str r2, [r3, #4] OCTOSPIM_PCR_IOLEN); } if (IOM_cfg[other_instance].IOHighPort != HAL_OSPIM_IOPORT_NONE) 8005f84: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005f88: 4613 mov r3, r2 8005f8a: 005b lsls r3, r3, #1 8005f8c: 4413 add r3, r2 8005f8e: 00db lsls r3, r3, #3 8005f90: f107 0250 add.w r2, r7, #80 ; 0x50 8005f94: 4413 add r3, r2 8005f96: 3b2c subs r3, #44 ; 0x2c 8005f98: 681b ldr r3, [r3, #0] 8005f9a: 2b00 cmp r3, #0 8005f9c: d025 beq.n 8005fea { CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], 8005f9e: 4969 ldr r1, [pc, #420] ; (8006144 ) 8005fa0: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005fa4: 4613 mov r3, r2 8005fa6: 005b lsls r3, r3, #1 8005fa8: 4413 add r3, r2 8005faa: 00db lsls r3, r3, #3 8005fac: f107 0250 add.w r2, r7, #80 ; 0x50 8005fb0: 4413 add r3, r2 8005fb2: 3b2c subs r3, #44 ; 0x2c 8005fb4: 681b ldr r3, [r3, #0] 8005fb6: 3b01 subs r3, #1 8005fb8: f003 0301 and.w r3, r3, #1 8005fbc: 009b lsls r3, r3, #2 8005fbe: 440b add r3, r1 8005fc0: 6859 ldr r1, [r3, #4] 8005fc2: 4860 ldr r0, [pc, #384] ; (8006144 ) 8005fc4: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 8005fc8: 4613 mov r3, r2 8005fca: 005b lsls r3, r3, #1 8005fcc: 4413 add r3, r2 8005fce: 00db lsls r3, r3, #3 8005fd0: f107 0250 add.w r2, r7, #80 ; 0x50 8005fd4: 4413 add r3, r2 8005fd6: 3b2c subs r3, #44 ; 0x2c 8005fd8: 681b ldr r3, [r3, #0] 8005fda: 3b01 subs r3, #1 8005fdc: f003 0301 and.w r3, r3, #1 8005fe0: f021 7280 bic.w r2, r1, #16777216 ; 0x1000000 8005fe4: 009b lsls r3, r3, #2 8005fe6: 4403 add r3, r0 8005fe8: 605a str r2, [r3, #4] } } } /******************** Activation of new configuration *********************/ MODIFY_REG(OCTOSPIM->PCR[(cfg->NCSPort - 1U)], (OCTOSPIM_PCR_NCSEN | OCTOSPIM_PCR_NCSSRC), 8005fea: 4a56 ldr r2, [pc, #344] ; (8006144 ) 8005fec: 68bb ldr r3, [r7, #8] 8005fee: 689b ldr r3, [r3, #8] 8005ff0: 3b01 subs r3, #1 8005ff2: 009b lsls r3, r3, #2 8005ff4: 4413 add r3, r2 8005ff6: 685b ldr r3, [r3, #4] 8005ff8: f423 7240 bic.w r2, r3, #768 ; 0x300 8005ffc: 6cbb ldr r3, [r7, #72] ; 0x48 8005ffe: 025b lsls r3, r3, #9 8006000: 431a orrs r2, r3 8006002: 4950 ldr r1, [pc, #320] ; (8006144 ) 8006004: 68bb ldr r3, [r7, #8] 8006006: 689b ldr r3, [r3, #8] 8006008: 3b01 subs r3, #1 800600a: f442 7280 orr.w r2, r2, #256 ; 0x100 800600e: 009b lsls r3, r3, #2 8006010: 440b add r3, r1 8006012: 605a str r2, [r3, #4] (OCTOSPIM_PCR_NCSEN | (instance << OCTOSPIM_PCR_NCSSRC_Pos))); if ((cfg->Req2AckTime - 1U) > ((OCTOSPIM->CR & OCTOSPIM_CR_REQ2ACK_TIME) >> OCTOSPIM_CR_REQ2ACK_TIME_Pos)) 8006014: 68bb ldr r3, [r7, #8] 8006016: 695b ldr r3, [r3, #20] 8006018: 1e5a subs r2, r3, #1 800601a: 4b4a ldr r3, [pc, #296] ; (8006144 ) 800601c: 681b ldr r3, [r3, #0] 800601e: 0c1b lsrs r3, r3, #16 8006020: b2db uxtb r3, r3 8006022: 429a cmp r2, r3 8006024: d90a bls.n 800603c { MODIFY_REG(OCTOSPIM->CR, OCTOSPIM_CR_REQ2ACK_TIME, ((cfg->Req2AckTime - 1U) << OCTOSPIM_CR_REQ2ACK_TIME_Pos)); 8006026: 4b47 ldr r3, [pc, #284] ; (8006144 ) 8006028: 681b ldr r3, [r3, #0] 800602a: f423 027f bic.w r2, r3, #16711680 ; 0xff0000 800602e: 68bb ldr r3, [r7, #8] 8006030: 695b ldr r3, [r3, #20] 8006032: 3b01 subs r3, #1 8006034: 041b lsls r3, r3, #16 8006036: 4943 ldr r1, [pc, #268] ; (8006144 ) 8006038: 4313 orrs r3, r2 800603a: 600b str r3, [r1, #0] } if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) != 0U) 800603c: 4b41 ldr r3, [pc, #260] ; (8006144 ) 800603e: 681b ldr r3, [r3, #0] 8006040: f003 0301 and.w r3, r3, #1 8006044: 2b00 cmp r3, #0 8006046: f000 809b beq.w 8006180 { MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), OCTOSPIM_PCR_CLKEN); 800604a: 4a3e ldr r2, [pc, #248] ; (8006144 ) 800604c: 68bb ldr r3, [r7, #8] 800604e: 681b ldr r3, [r3, #0] 8006050: 3b01 subs r3, #1 8006052: 009b lsls r3, r3, #2 8006054: 4413 add r3, r2 8006056: 685b ldr r3, [r3, #4] 8006058: f023 0203 bic.w r2, r3, #3 800605c: 4939 ldr r1, [pc, #228] ; (8006144 ) 800605e: 68bb ldr r3, [r7, #8] 8006060: 681b ldr r3, [r3, #0] 8006062: 3b01 subs r3, #1 8006064: f042 0201 orr.w r2, r2, #1 8006068: 009b lsls r3, r3, #2 800606a: 440b add r3, r1 800606c: 605a str r2, [r3, #4] if (cfg->DQSPort != 0U) 800606e: 68bb ldr r3, [r7, #8] 8006070: 685b ldr r3, [r3, #4] 8006072: 2b00 cmp r3, #0 8006074: d011 beq.n 800609a { MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), OCTOSPIM_PCR_DQSEN); 8006076: 4a33 ldr r2, [pc, #204] ; (8006144 ) 8006078: 68bb ldr r3, [r7, #8] 800607a: 685b ldr r3, [r3, #4] 800607c: 3b01 subs r3, #1 800607e: 009b lsls r3, r3, #2 8006080: 4413 add r3, r2 8006082: 685b ldr r3, [r3, #4] 8006084: f023 0230 bic.w r2, r3, #48 ; 0x30 8006088: 492e ldr r1, [pc, #184] ; (8006144 ) 800608a: 68bb ldr r3, [r7, #8] 800608c: 685b ldr r3, [r3, #4] 800608e: 3b01 subs r3, #1 8006090: f042 0210 orr.w r2, r2, #16 8006094: 009b lsls r3, r3, #2 8006096: 440b add r3, r1 8006098: 605a str r2, [r3, #4] } if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U) 800609a: 68bb ldr r3, [r7, #8] 800609c: 68db ldr r3, [r3, #12] 800609e: f403 3380 and.w r3, r3, #65536 ; 0x10000 80060a2: 2b00 cmp r3, #0 80060a4: d016 beq.n 80060d4 { MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], 80060a6: 4a27 ldr r2, [pc, #156] ; (8006144 ) 80060a8: 68bb ldr r3, [r7, #8] 80060aa: 68db ldr r3, [r3, #12] 80060ac: 3b01 subs r3, #1 80060ae: f003 0301 and.w r3, r3, #1 80060b2: 009b lsls r3, r3, #2 80060b4: 4413 add r3, r2 80060b6: 685b ldr r3, [r3, #4] 80060b8: f423 22e0 bic.w r2, r3, #458752 ; 0x70000 80060bc: 4921 ldr r1, [pc, #132] ; (8006144 ) 80060be: 68bb ldr r3, [r7, #8] 80060c0: 68db ldr r3, [r3, #12] 80060c2: 3b01 subs r3, #1 80060c4: f003 0301 and.w r3, r3, #1 80060c8: f442 3280 orr.w r2, r2, #65536 ; 0x10000 80060cc: 009b lsls r3, r3, #2 80060ce: 440b add r3, r1 80060d0: 605a str r2, [r3, #4] 80060d2: e019 b.n 8006108 (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), OCTOSPIM_PCR_IOLEN); } else if (cfg->IOLowPort != HAL_OSPIM_IOPORT_NONE) 80060d4: 68bb ldr r3, [r7, #8] 80060d6: 68db ldr r3, [r3, #12] 80060d8: 2b00 cmp r3, #0 80060da: d015 beq.n 8006108 { MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], 80060dc: 4a19 ldr r2, [pc, #100] ; (8006144 ) 80060de: 68bb ldr r3, [r7, #8] 80060e0: 68db ldr r3, [r3, #12] 80060e2: 3b01 subs r3, #1 80060e4: f003 0301 and.w r3, r3, #1 80060e8: 009b lsls r3, r3, #2 80060ea: 4413 add r3, r2 80060ec: 685b ldr r3, [r3, #4] 80060ee: f023 62e0 bic.w r2, r3, #117440512 ; 0x7000000 80060f2: 4914 ldr r1, [pc, #80] ; (8006144 ) 80060f4: 68bb ldr r3, [r7, #8] 80060f6: 68db ldr r3, [r3, #12] 80060f8: 3b01 subs r3, #1 80060fa: f003 0301 and.w r3, r3, #1 80060fe: f042 7280 orr.w r2, r2, #16777216 ; 0x1000000 8006102: 009b lsls r3, r3, #2 8006104: 440b add r3, r1 8006106: 605a str r2, [r3, #4] else { /* Nothing to do */ } if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U) 8006108: 68bb ldr r3, [r7, #8] 800610a: 691b ldr r3, [r3, #16] 800610c: f403 3380 and.w r3, r3, #65536 ; 0x10000 8006110: 2b00 cmp r3, #0 8006112: d019 beq.n 8006148 { MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], 8006114: 4a0b ldr r2, [pc, #44] ; (8006144 ) 8006116: 68bb ldr r3, [r7, #8] 8006118: 691b ldr r3, [r3, #16] 800611a: 3b01 subs r3, #1 800611c: f003 0301 and.w r3, r3, #1 8006120: 009b lsls r3, r3, #2 8006122: 4413 add r3, r2 8006124: 685b ldr r3, [r3, #4] 8006126: f423 22e0 bic.w r2, r3, #458752 ; 0x70000 800612a: 4906 ldr r1, [pc, #24] ; (8006144 ) 800612c: 68bb ldr r3, [r7, #8] 800612e: 691b ldr r3, [r3, #16] 8006130: 3b01 subs r3, #1 8006132: f003 0301 and.w r3, r3, #1 8006136: f442 3240 orr.w r2, r2, #196608 ; 0x30000 800613a: 009b lsls r3, r3, #2 800613c: 440b add r3, r1 800613e: 605a str r2, [r3, #4] 8006140: e0c6 b.n 80062d0 8006142: bf00 nop 8006144: 5200b400 .word 0x5200b400 (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0)); } else if (cfg->IOHighPort != HAL_OSPIM_IOPORT_NONE) 8006148: 68bb ldr r3, [r7, #8] 800614a: 691b ldr r3, [r3, #16] 800614c: 2b00 cmp r3, #0 800614e: f000 80bf beq.w 80062d0 { MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], 8006152: 4a6e ldr r2, [pc, #440] ; (800630c ) 8006154: 68bb ldr r3, [r7, #8] 8006156: 691b ldr r3, [r3, #16] 8006158: 3b01 subs r3, #1 800615a: f003 0301 and.w r3, r3, #1 800615e: 009b lsls r3, r3, #2 8006160: 4413 add r3, r2 8006162: 685b ldr r3, [r3, #4] 8006164: f023 62e0 bic.w r2, r3, #117440512 ; 0x7000000 8006168: 4968 ldr r1, [pc, #416] ; (800630c ) 800616a: 68bb ldr r3, [r7, #8] 800616c: 691b ldr r3, [r3, #16] 800616e: 3b01 subs r3, #1 8006170: f003 0301 and.w r3, r3, #1 8006174: f042 7240 orr.w r2, r2, #50331648 ; 0x3000000 8006178: 009b lsls r3, r3, #2 800617a: 440b add r3, r1 800617c: 605a str r2, [r3, #4] 800617e: e0a7 b.n 80062d0 /* Nothing to do */ } } else { MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), 8006180: 4a62 ldr r2, [pc, #392] ; (800630c ) 8006182: 68bb ldr r3, [r7, #8] 8006184: 681b ldr r3, [r3, #0] 8006186: 3b01 subs r3, #1 8006188: 009b lsls r3, r3, #2 800618a: 4413 add r3, r2 800618c: 685b ldr r3, [r3, #4] 800618e: f023 0203 bic.w r2, r3, #3 8006192: 6cbb ldr r3, [r7, #72] ; 0x48 8006194: 005b lsls r3, r3, #1 8006196: 431a orrs r2, r3 8006198: 495c ldr r1, [pc, #368] ; (800630c ) 800619a: 68bb ldr r3, [r7, #8] 800619c: 681b ldr r3, [r3, #0] 800619e: 3b01 subs r3, #1 80061a0: f042 0201 orr.w r2, r2, #1 80061a4: 009b lsls r3, r3, #2 80061a6: 440b add r3, r1 80061a8: 605a str r2, [r3, #4] (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos))); if (cfg->DQSPort != 0U) 80061aa: 68bb ldr r3, [r7, #8] 80061ac: 685b ldr r3, [r3, #4] 80061ae: 2b00 cmp r3, #0 80061b0: d014 beq.n 80061dc { MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), 80061b2: 4a56 ldr r2, [pc, #344] ; (800630c ) 80061b4: 68bb ldr r3, [r7, #8] 80061b6: 685b ldr r3, [r3, #4] 80061b8: 3b01 subs r3, #1 80061ba: 009b lsls r3, r3, #2 80061bc: 4413 add r3, r2 80061be: 685b ldr r3, [r3, #4] 80061c0: f023 0230 bic.w r2, r3, #48 ; 0x30 80061c4: 6cbb ldr r3, [r7, #72] ; 0x48 80061c6: 015b lsls r3, r3, #5 80061c8: 431a orrs r2, r3 80061ca: 4950 ldr r1, [pc, #320] ; (800630c ) 80061cc: 68bb ldr r3, [r7, #8] 80061ce: 685b ldr r3, [r3, #4] 80061d0: 3b01 subs r3, #1 80061d2: f042 0210 orr.w r2, r2, #16 80061d6: 009b lsls r3, r3, #2 80061d8: 440b add r3, r1 80061da: 605a str r2, [r3, #4] (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos))); } if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U) 80061dc: 68bb ldr r3, [r7, #8] 80061de: 68db ldr r3, [r3, #12] 80061e0: f403 3380 and.w r3, r3, #65536 ; 0x10000 80061e4: 2b00 cmp r3, #0 80061e6: d019 beq.n 800621c { MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], 80061e8: 4a48 ldr r2, [pc, #288] ; (800630c ) 80061ea: 68bb ldr r3, [r7, #8] 80061ec: 68db ldr r3, [r3, #12] 80061ee: 3b01 subs r3, #1 80061f0: f003 0301 and.w r3, r3, #1 80061f4: 009b lsls r3, r3, #2 80061f6: 4413 add r3, r2 80061f8: 685b ldr r3, [r3, #4] 80061fa: f423 22e0 bic.w r2, r3, #458752 ; 0x70000 80061fe: 6cbb ldr r3, [r7, #72] ; 0x48 8006200: 049b lsls r3, r3, #18 8006202: 431a orrs r2, r3 8006204: 4941 ldr r1, [pc, #260] ; (800630c ) 8006206: 68bb ldr r3, [r7, #8] 8006208: 68db ldr r3, [r3, #12] 800620a: 3b01 subs r3, #1 800620c: f003 0301 and.w r3, r3, #1 8006210: f442 3280 orr.w r2, r2, #65536 ; 0x10000 8006214: 009b lsls r3, r3, #2 8006216: 440b add r3, r1 8006218: 605a str r2, [r3, #4] 800621a: e01c b.n 8006256 (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), (OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U)))); } else if (cfg->IOLowPort != HAL_OSPIM_IOPORT_NONE) 800621c: 68bb ldr r3, [r7, #8] 800621e: 68db ldr r3, [r3, #12] 8006220: 2b00 cmp r3, #0 8006222: d018 beq.n 8006256 { MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], 8006224: 4a39 ldr r2, [pc, #228] ; (800630c ) 8006226: 68bb ldr r3, [r7, #8] 8006228: 68db ldr r3, [r3, #12] 800622a: 3b01 subs r3, #1 800622c: f003 0301 and.w r3, r3, #1 8006230: 009b lsls r3, r3, #2 8006232: 4413 add r3, r2 8006234: 685b ldr r3, [r3, #4] 8006236: f023 62e0 bic.w r2, r3, #117440512 ; 0x7000000 800623a: 6cbb ldr r3, [r7, #72] ; 0x48 800623c: 069b lsls r3, r3, #26 800623e: 431a orrs r2, r3 8006240: 4932 ldr r1, [pc, #200] ; (800630c ) 8006242: 68bb ldr r3, [r7, #8] 8006244: 68db ldr r3, [r3, #12] 8006246: 3b01 subs r3, #1 8006248: f003 0301 and.w r3, r3, #1 800624c: f042 7280 orr.w r2, r2, #16777216 ; 0x1000000 8006250: 009b lsls r3, r3, #2 8006252: 440b add r3, r1 8006254: 605a str r2, [r3, #4] else { /* Nothing to do */ } if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U) 8006256: 68bb ldr r3, [r7, #8] 8006258: 691b ldr r3, [r3, #16] 800625a: f403 3380 and.w r3, r3, #65536 ; 0x10000 800625e: 2b00 cmp r3, #0 8006260: d019 beq.n 8006296 { MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], 8006262: 4a2a ldr r2, [pc, #168] ; (800630c ) 8006264: 68bb ldr r3, [r7, #8] 8006266: 691b ldr r3, [r3, #16] 8006268: 3b01 subs r3, #1 800626a: f003 0301 and.w r3, r3, #1 800626e: 009b lsls r3, r3, #2 8006270: 4413 add r3, r2 8006272: 685b ldr r3, [r3, #4] 8006274: f423 22e0 bic.w r2, r3, #458752 ; 0x70000 8006278: 6cbb ldr r3, [r7, #72] ; 0x48 800627a: 049b lsls r3, r3, #18 800627c: 431a orrs r2, r3 800627e: 4923 ldr r1, [pc, #140] ; (800630c ) 8006280: 68bb ldr r3, [r7, #8] 8006282: 691b ldr r3, [r3, #16] 8006284: 3b01 subs r3, #1 8006286: f003 0301 and.w r3, r3, #1 800628a: f442 3240 orr.w r2, r2, #196608 ; 0x30000 800628e: 009b lsls r3, r3, #2 8006290: 440b add r3, r1 8006292: 605a str r2, [r3, #4] 8006294: e01c b.n 80062d0 (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U)))); } else if (cfg->IOHighPort != HAL_OSPIM_IOPORT_NONE) 8006296: 68bb ldr r3, [r7, #8] 8006298: 691b ldr r3, [r3, #16] 800629a: 2b00 cmp r3, #0 800629c: d018 beq.n 80062d0 { MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], 800629e: 4a1b ldr r2, [pc, #108] ; (800630c ) 80062a0: 68bb ldr r3, [r7, #8] 80062a2: 691b ldr r3, [r3, #16] 80062a4: 3b01 subs r3, #1 80062a6: f003 0301 and.w r3, r3, #1 80062aa: 009b lsls r3, r3, #2 80062ac: 4413 add r3, r2 80062ae: 685b ldr r3, [r3, #4] 80062b0: f023 62e0 bic.w r2, r3, #117440512 ; 0x7000000 80062b4: 6cbb ldr r3, [r7, #72] ; 0x48 80062b6: 069b lsls r3, r3, #26 80062b8: 431a orrs r2, r3 80062ba: 4914 ldr r1, [pc, #80] ; (800630c ) 80062bc: 68bb ldr r3, [r7, #8] 80062be: 691b ldr r3, [r3, #16] 80062c0: 3b01 subs r3, #1 80062c2: f003 0301 and.w r3, r3, #1 80062c6: f042 7240 orr.w r2, r2, #50331648 ; 0x3000000 80062ca: 009b lsls r3, r3, #2 80062cc: 440b add r3, r1 80062ce: 605a str r2, [r3, #4] /* Nothing to do */ } } /******* Re-enable both OctoSPI after configure OctoSPI IO Manager ********/ if ((ospi_enabled & 0x1U) != 0U) 80062d0: f897 3046 ldrb.w r3, [r7, #70] ; 0x46 80062d4: f003 0301 and.w r3, r3, #1 80062d8: 2b00 cmp r3, #0 80062da: d005 beq.n 80062e8 { SET_BIT(OCTOSPI1->CR, OCTOSPI_CR_EN); 80062dc: 4b0c ldr r3, [pc, #48] ; (8006310 ) 80062de: 681b ldr r3, [r3, #0] 80062e0: 4a0b ldr r2, [pc, #44] ; (8006310 ) 80062e2: f043 0301 orr.w r3, r3, #1 80062e6: 6013 str r3, [r2, #0] } if ((ospi_enabled & 0x2U) != 0U) 80062e8: f897 3046 ldrb.w r3, [r7, #70] ; 0x46 80062ec: f003 0302 and.w r3, r3, #2 80062f0: 2b00 cmp r3, #0 80062f2: d005 beq.n 8006300 { SET_BIT(OCTOSPI2->CR, OCTOSPI_CR_EN); 80062f4: 4b07 ldr r3, [pc, #28] ; (8006314 ) 80062f6: 681b ldr r3, [r3, #0] 80062f8: 4a06 ldr r2, [pc, #24] ; (8006314 ) 80062fa: f043 0301 orr.w r3, r3, #1 80062fe: 6013 str r3, [r2, #0] } } /* Return function status */ return status; 8006300: f897 304f ldrb.w r3, [r7, #79] ; 0x4f } 8006304: 4618 mov r0, r3 8006306: 3750 adds r7, #80 ; 0x50 8006308: 46bd mov sp, r7 800630a: bd80 pop {r7, pc} 800630c: 5200b400 .word 0x5200b400 8006310: 52005000 .word 0x52005000 8006314: 5200a000 .word 0x5200a000 08006318 : * @param Tickstart : Tick start value * @retval HAL status */ static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout) { 8006318: b580 push {r7, lr} 800631a: b084 sub sp, #16 800631c: af00 add r7, sp, #0 800631e: 60f8 str r0, [r7, #12] 8006320: 60b9 str r1, [r7, #8] 8006322: 603b str r3, [r7, #0] 8006324: 4613 mov r3, r2 8006326: 71fb strb r3, [r7, #7] /* Wait until flag is in expected state */ while((__HAL_OSPI_GET_FLAG(hospi, Flag)) != State) 8006328: e01a b.n 8006360 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 800632a: 69bb ldr r3, [r7, #24] 800632c: f1b3 3fff cmp.w r3, #4294967295 8006330: d016 beq.n 8006360 { if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8006332: f7fc ff59 bl 80031e8 8006336: 4602 mov r2, r0 8006338: 683b ldr r3, [r7, #0] 800633a: 1ad3 subs r3, r2, r3 800633c: 69ba ldr r2, [r7, #24] 800633e: 429a cmp r2, r3 8006340: d302 bcc.n 8006348 8006342: 69bb ldr r3, [r7, #24] 8006344: 2b00 cmp r3, #0 8006346: d10b bne.n 8006360 { hospi->State = HAL_OSPI_STATE_ERROR; 8006348: 68fb ldr r3, [r7, #12] 800634a: f44f 7200 mov.w r2, #512 ; 0x200 800634e: 655a str r2, [r3, #84] ; 0x54 hospi->ErrorCode |= HAL_OSPI_ERROR_TIMEOUT; 8006350: 68fb ldr r3, [r7, #12] 8006352: 6d9b ldr r3, [r3, #88] ; 0x58 8006354: f043 0201 orr.w r2, r3, #1 8006358: 68fb ldr r3, [r7, #12] 800635a: 659a str r2, [r3, #88] ; 0x58 return HAL_ERROR; 800635c: 2301 movs r3, #1 800635e: e00e b.n 800637e while((__HAL_OSPI_GET_FLAG(hospi, Flag)) != State) 8006360: 68fb ldr r3, [r7, #12] 8006362: 681b ldr r3, [r3, #0] 8006364: 6a1a ldr r2, [r3, #32] 8006366: 68bb ldr r3, [r7, #8] 8006368: 4013 ands r3, r2 800636a: 2b00 cmp r3, #0 800636c: bf14 ite ne 800636e: 2301 movne r3, #1 8006370: 2300 moveq r3, #0 8006372: b2db uxtb r3, r3 8006374: 461a mov r2, r3 8006376: 79fb ldrb r3, [r7, #7] 8006378: 429a cmp r2, r3 800637a: d1d6 bne.n 800632a } } } return HAL_OK; 800637c: 2300 movs r3, #0 } 800637e: 4618 mov r0, r3 8006380: 3710 adds r7, #16 8006382: 46bd mov sp, r7 8006384: bd80 pop {r7, pc} ... 08006388 : * @param instance_nb : number of the instance * @param cfg : configuration of the IO Manager for the instance * @retval HAL status */ static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *cfg) { 8006388: b480 push {r7} 800638a: b087 sub sp, #28 800638c: af00 add r7, sp, #0 800638e: 4603 mov r3, r0 8006390: 6039 str r1, [r7, #0] 8006392: 71fb strb r3, [r7, #7] HAL_StatusTypeDef status = HAL_OK; 8006394: 2300 movs r3, #0 8006396: 75fb strb r3, [r7, #23] uint32_t reg; uint32_t value = 0U; 8006398: 2300 movs r3, #0 800639a: 613b str r3, [r7, #16] uint32_t index; if ((instance_nb == 0U) || (instance_nb > OSPI_NB_INSTANCE) || (cfg == NULL)) 800639c: 79fb ldrb r3, [r7, #7] 800639e: 2b00 cmp r3, #0 80063a0: d005 beq.n 80063ae 80063a2: 79fb ldrb r3, [r7, #7] 80063a4: 2b02 cmp r3, #2 80063a6: d802 bhi.n 80063ae 80063a8: 683b ldr r3, [r7, #0] 80063aa: 2b00 cmp r3, #0 80063ac: d102 bne.n 80063b4 { /* Invalid parameter -> error returned */ status = HAL_ERROR; 80063ae: 2301 movs r3, #1 80063b0: 75fb strb r3, [r7, #23] 80063b2: e098 b.n 80064e6 } else { /* Initialize the structure */ cfg->ClkPort = 0U; 80063b4: 683b ldr r3, [r7, #0] 80063b6: 2200 movs r2, #0 80063b8: 601a str r2, [r3, #0] cfg->DQSPort = 0U; 80063ba: 683b ldr r3, [r7, #0] 80063bc: 2200 movs r2, #0 80063be: 605a str r2, [r3, #4] cfg->NCSPort = 0U; 80063c0: 683b ldr r3, [r7, #0] 80063c2: 2200 movs r2, #0 80063c4: 609a str r2, [r3, #8] cfg->IOLowPort = 0U; 80063c6: 683b ldr r3, [r7, #0] 80063c8: 2200 movs r2, #0 80063ca: 60da str r2, [r3, #12] cfg->IOHighPort = 0U; 80063cc: 683b ldr r3, [r7, #0] 80063ce: 2200 movs r2, #0 80063d0: 611a str r2, [r3, #16] if (instance_nb == 2U) 80063d2: 79fb ldrb r3, [r7, #7] 80063d4: 2b02 cmp r3, #2 80063d6: d10b bne.n 80063f0 { if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) == 0U) 80063d8: 4b46 ldr r3, [pc, #280] ; (80064f4 ) 80063da: 681b ldr r3, [r3, #0] 80063dc: f003 0301 and.w r3, r3, #1 80063e0: 2b00 cmp r3, #0 80063e2: d102 bne.n 80063ea { value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC 80063e4: 4b44 ldr r3, [pc, #272] ; (80064f8 ) 80063e6: 613b str r3, [r7, #16] 80063e8: e002 b.n 80063f0 | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1); } else { value = OCTOSPIM_PCR_NCSSRC; 80063ea: f44f 7300 mov.w r3, #512 ; 0x200 80063ee: 613b str r3, [r7, #16] } } /* Get the information about the instance */ for (index = 0U; index < OSPI_IOM_NB_PORTS; index ++) 80063f0: 2300 movs r3, #0 80063f2: 60fb str r3, [r7, #12] 80063f4: e074 b.n 80064e0 { reg = OCTOSPIM->PCR[index]; 80063f6: 4a3f ldr r2, [pc, #252] ; (80064f4 ) 80063f8: 68fb ldr r3, [r7, #12] 80063fa: 009b lsls r3, r3, #2 80063fc: 4413 add r3, r2 80063fe: 685b ldr r3, [r3, #4] 8006400: 60bb str r3, [r7, #8] if ((reg & OCTOSPIM_PCR_CLKEN) != 0U) 8006402: 68bb ldr r3, [r7, #8] 8006404: f003 0301 and.w r3, r3, #1 8006408: 2b00 cmp r3, #0 800640a: d00a beq.n 8006422 { /* The clock is enabled on this port */ if ((reg & OCTOSPIM_PCR_CLKSRC) == (value & OCTOSPIM_PCR_CLKSRC)) 800640c: 68ba ldr r2, [r7, #8] 800640e: 693b ldr r3, [r7, #16] 8006410: 4053 eors r3, r2 8006412: f003 0302 and.w r3, r3, #2 8006416: 2b00 cmp r3, #0 8006418: d103 bne.n 8006422 { /* The clock correspond to the instance passed as parameter */ cfg->ClkPort = index+1U; 800641a: 68fb ldr r3, [r7, #12] 800641c: 1c5a adds r2, r3, #1 800641e: 683b ldr r3, [r7, #0] 8006420: 601a str r2, [r3, #0] } } if ((reg & OCTOSPIM_PCR_DQSEN) != 0U) 8006422: 68bb ldr r3, [r7, #8] 8006424: f003 0310 and.w r3, r3, #16 8006428: 2b00 cmp r3, #0 800642a: d00a beq.n 8006442 { /* The DQS is enabled on this port */ if ((reg & OCTOSPIM_PCR_DQSSRC) == (value & OCTOSPIM_PCR_DQSSRC)) 800642c: 68ba ldr r2, [r7, #8] 800642e: 693b ldr r3, [r7, #16] 8006430: 4053 eors r3, r2 8006432: f003 0320 and.w r3, r3, #32 8006436: 2b00 cmp r3, #0 8006438: d103 bne.n 8006442 { /* The DQS correspond to the instance passed as parameter */ cfg->DQSPort = index+1U; 800643a: 68fb ldr r3, [r7, #12] 800643c: 1c5a adds r2, r3, #1 800643e: 683b ldr r3, [r7, #0] 8006440: 605a str r2, [r3, #4] } } if ((reg & OCTOSPIM_PCR_NCSEN) != 0U) 8006442: 68bb ldr r3, [r7, #8] 8006444: f403 7380 and.w r3, r3, #256 ; 0x100 8006448: 2b00 cmp r3, #0 800644a: d00a beq.n 8006462 { /* The nCS is enabled on this port */ if ((reg & OCTOSPIM_PCR_NCSSRC) == (value & OCTOSPIM_PCR_NCSSRC)) 800644c: 68ba ldr r2, [r7, #8] 800644e: 693b ldr r3, [r7, #16] 8006450: 4053 eors r3, r2 8006452: f403 7300 and.w r3, r3, #512 ; 0x200 8006456: 2b00 cmp r3, #0 8006458: d103 bne.n 8006462 { /* The nCS correspond to the instance passed as parameter */ cfg->NCSPort = index+1U; 800645a: 68fb ldr r3, [r7, #12] 800645c: 1c5a adds r2, r3, #1 800645e: 683b ldr r3, [r7, #0] 8006460: 609a str r2, [r3, #8] } } if ((reg & OCTOSPIM_PCR_IOLEN) != 0U) 8006462: 68bb ldr r3, [r7, #8] 8006464: f403 3380 and.w r3, r3, #65536 ; 0x10000 8006468: 2b00 cmp r3, #0 800646a: d018 beq.n 800649e { /* The IO Low is enabled on this port */ if ((reg & OCTOSPIM_PCR_IOLSRC_1) == (value & OCTOSPIM_PCR_IOLSRC_1)) 800646c: 68ba ldr r2, [r7, #8] 800646e: 693b ldr r3, [r7, #16] 8006470: 4053 eors r3, r2 8006472: f403 2380 and.w r3, r3, #262144 ; 0x40000 8006476: 2b00 cmp r3, #0 8006478: d111 bne.n 800649e { /* The IO Low correspond to the instance passed as parameter */ if ((reg & OCTOSPIM_PCR_IOLSRC_0) == 0U) 800647a: 68bb ldr r3, [r7, #8] 800647c: f403 3300 and.w r3, r3, #131072 ; 0x20000 8006480: 2b00 cmp r3, #0 8006482: d106 bne.n 8006492 { cfg->IOLowPort = (OCTOSPIM_PCR_IOLEN | (index+1U)); 8006484: 68fb ldr r3, [r7, #12] 8006486: 3301 adds r3, #1 8006488: f443 3280 orr.w r2, r3, #65536 ; 0x10000 800648c: 683b ldr r3, [r7, #0] 800648e: 60da str r2, [r3, #12] 8006490: e005 b.n 800649e } else { cfg->IOLowPort = (OCTOSPIM_PCR_IOHEN | (index+1U)); 8006492: 68fb ldr r3, [r7, #12] 8006494: 3301 adds r3, #1 8006496: f043 7280 orr.w r2, r3, #16777216 ; 0x1000000 800649a: 683b ldr r3, [r7, #0] 800649c: 60da str r2, [r3, #12] } } } if ((reg & OCTOSPIM_PCR_IOHEN) != 0U) 800649e: 68bb ldr r3, [r7, #8] 80064a0: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 80064a4: 2b00 cmp r3, #0 80064a6: d018 beq.n 80064da { /* The IO High is enabled on this port */ if ((reg & OCTOSPIM_PCR_IOHSRC_1) == (value & OCTOSPIM_PCR_IOHSRC_1)) 80064a8: 68ba ldr r2, [r7, #8] 80064aa: 693b ldr r3, [r7, #16] 80064ac: 4053 eors r3, r2 80064ae: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 80064b2: 2b00 cmp r3, #0 80064b4: d111 bne.n 80064da { /* The IO High correspond to the instance passed as parameter */ if ((reg & OCTOSPIM_PCR_IOHSRC_0) == 0U) 80064b6: 68bb ldr r3, [r7, #8] 80064b8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80064bc: 2b00 cmp r3, #0 80064be: d106 bne.n 80064ce { cfg->IOHighPort = (OCTOSPIM_PCR_IOLEN | (index+1U)); 80064c0: 68fb ldr r3, [r7, #12] 80064c2: 3301 adds r3, #1 80064c4: f443 3280 orr.w r2, r3, #65536 ; 0x10000 80064c8: 683b ldr r3, [r7, #0] 80064ca: 611a str r2, [r3, #16] 80064cc: e005 b.n 80064da } else { cfg->IOHighPort = (OCTOSPIM_PCR_IOHEN | (index+1U)); 80064ce: 68fb ldr r3, [r7, #12] 80064d0: 3301 adds r3, #1 80064d2: f043 7280 orr.w r2, r3, #16777216 ; 0x1000000 80064d6: 683b ldr r3, [r7, #0] 80064d8: 611a str r2, [r3, #16] for (index = 0U; index < OSPI_IOM_NB_PORTS; index ++) 80064da: 68fb ldr r3, [r7, #12] 80064dc: 3301 adds r3, #1 80064de: 60fb str r3, [r7, #12] 80064e0: 68fb ldr r3, [r7, #12] 80064e2: 2b01 cmp r3, #1 80064e4: d987 bls.n 80063f6 } } } /* Return function status */ return status; 80064e6: 7dfb ldrb r3, [r7, #23] } 80064e8: 4618 mov r0, r3 80064ea: 371c adds r7, #28 80064ec: 46bd mov sp, r7 80064ee: f85d 7b04 ldr.w r7, [sp], #4 80064f2: 4770 bx lr 80064f4: 5200b400 .word 0x5200b400 80064f8: 04040222 .word 0x04040222 080064fc : * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS * regulator. * @retval HAL status. */ HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource) { 80064fc: b580 push {r7, lr} 80064fe: b084 sub sp, #16 8006500: af00 add r7, sp, #0 8006502: 6078 str r0, [r7, #4] /* Check if supply source was configured */ #if defined (PWR_FLAG_SCUEN) if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U) #else if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) 8006504: 4b29 ldr r3, [pc, #164] ; (80065ac ) 8006506: 68db ldr r3, [r3, #12] 8006508: f003 0307 and.w r3, r3, #7 800650c: 2b06 cmp r3, #6 800650e: d00a beq.n 8006526 #endif /* defined (PWR_FLAG_SCUEN) */ { /* Check supply configuration */ if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) 8006510: 4b26 ldr r3, [pc, #152] ; (80065ac ) 8006512: 68db ldr r3, [r3, #12] 8006514: f003 033f and.w r3, r3, #63 ; 0x3f 8006518: 687a ldr r2, [r7, #4] 800651a: 429a cmp r2, r3 800651c: d001 beq.n 8006522 { /* Supply configuration update locked, can't apply a new supply config */ return HAL_ERROR; 800651e: 2301 movs r3, #1 8006520: e040 b.n 80065a4 else { /* Supply configuration update locked, but new supply configuration matches with old supply configuration : nothing to do */ return HAL_OK; 8006522: 2300 movs r3, #0 8006524: e03e b.n 80065a4 } } /* Set the power supply configuration */ MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource); 8006526: 4b21 ldr r3, [pc, #132] ; (80065ac ) 8006528: 68db ldr r3, [r3, #12] 800652a: f023 023f bic.w r2, r3, #63 ; 0x3f 800652e: 491f ldr r1, [pc, #124] ; (80065ac ) 8006530: 687b ldr r3, [r7, #4] 8006532: 4313 orrs r3, r2 8006534: 60cb str r3, [r1, #12] /* Get tick */ tickstart = HAL_GetTick (); 8006536: f7fc fe57 bl 80031e8 800653a: 60f8 str r0, [r7, #12] /* Wait till voltage level flag is set */ while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 800653c: e009 b.n 8006552 { if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) 800653e: f7fc fe53 bl 80031e8 8006542: 4602 mov r2, r0 8006544: 68fb ldr r3, [r7, #12] 8006546: 1ad3 subs r3, r2, r3 8006548: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 800654c: d901 bls.n 8006552 { return HAL_ERROR; 800654e: 2301 movs r3, #1 8006550: e028 b.n 80065a4 while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 8006552: 4b16 ldr r3, [pc, #88] ; (80065ac ) 8006554: 685b ldr r3, [r3, #4] 8006556: f403 5300 and.w r3, r3, #8192 ; 0x2000 800655a: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 800655e: d1ee bne.n 800653e } } #if defined (SMPS) /* When the SMPS supplies external circuits verify that SDEXTRDY flag is set */ if ((SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) || 8006560: 687b ldr r3, [r7, #4] 8006562: 2b1e cmp r3, #30 8006564: d008 beq.n 8006578 8006566: 687b ldr r3, [r7, #4] 8006568: 2b2e cmp r3, #46 ; 0x2e 800656a: d005 beq.n 8006578 (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) || 800656c: 687b ldr r3, [r7, #4] 800656e: 2b1d cmp r3, #29 8006570: d002 beq.n 8006578 (SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT) || 8006572: 687b ldr r3, [r7, #4] 8006574: 2b2d cmp r3, #45 ; 0x2d 8006576: d114 bne.n 80065a2 (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT)) { /* Get the current tick number */ tickstart = HAL_GetTick (); 8006578: f7fc fe36 bl 80031e8 800657c: 60f8 str r0, [r7, #12] /* Wait till SMPS external supply ready flag is set */ while (__HAL_PWR_GET_FLAG (PWR_FLAG_SMPSEXTRDY) == 0U) 800657e: e009 b.n 8006594 { if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) 8006580: f7fc fe32 bl 80031e8 8006584: 4602 mov r2, r0 8006586: 68fb ldr r3, [r7, #12] 8006588: 1ad3 subs r3, r2, r3 800658a: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 800658e: d901 bls.n 8006594 { return HAL_ERROR; 8006590: 2301 movs r3, #1 8006592: e007 b.n 80065a4 while (__HAL_PWR_GET_FLAG (PWR_FLAG_SMPSEXTRDY) == 0U) 8006594: 4b05 ldr r3, [pc, #20] ; (80065ac ) 8006596: 68db ldr r3, [r3, #12] 8006598: f403 3380 and.w r3, r3, #65536 ; 0x10000 800659c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80065a0: d1ee bne.n 8006580 } } } #endif /* defined (SMPS) */ return HAL_OK; 80065a2: 2300 movs r3, #0 } 80065a4: 4618 mov r0, r3 80065a6: 3710 adds r7, #16 80065a8: 46bd mov sp, r7 80065aa: bd80 pop {r7, pc} 80065ac: 58024800 .word 0x58024800 080065b0 : * supported by this function. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 80065b0: b580 push {r7, lr} 80065b2: b08c sub sp, #48 ; 0x30 80065b4: af00 add r7, sp, #0 80065b6: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t temp1_pllckcfg, temp2_pllckcfg; /* Check Null pointer */ if(RCC_OscInitStruct == NULL) 80065b8: 687b ldr r3, [r7, #4] 80065ba: 2b00 cmp r3, #0 80065bc: d101 bne.n 80065c2 { return HAL_ERROR; 80065be: 2301 movs r3, #1 80065c0: e3f3 b.n 8006daa } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 80065c2: 687b ldr r3, [r7, #4] 80065c4: 681b ldr r3, [r3, #0] 80065c6: f003 0301 and.w r3, r3, #1 80065ca: 2b00 cmp r3, #0 80065cc: f000 80b3 beq.w 8006736 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 80065d0: 4b9e ldr r3, [pc, #632] ; (800684c ) 80065d2: 691b ldr r3, [r3, #16] 80065d4: f003 0338 and.w r3, r3, #56 ; 0x38 80065d8: 62fb str r3, [r7, #44] ; 0x2c const uint32_t temp_pllckselr = RCC->PLLCKSELR; 80065da: 4b9c ldr r3, [pc, #624] ; (800684c ) 80065dc: 6a9b ldr r3, [r3, #40] ; 0x28 80065de: 62bb str r3, [r7, #40] ; 0x28 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ if((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE))) 80065e0: 6afb ldr r3, [r7, #44] ; 0x2c 80065e2: 2b10 cmp r3, #16 80065e4: d007 beq.n 80065f6 80065e6: 6afb ldr r3, [r7, #44] ; 0x2c 80065e8: 2b18 cmp r3, #24 80065ea: d112 bne.n 8006612 80065ec: 6abb ldr r3, [r7, #40] ; 0x28 80065ee: f003 0303 and.w r3, r3, #3 80065f2: 2b02 cmp r3, #2 80065f4: d10d bne.n 8006612 { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80065f6: 4b95 ldr r3, [pc, #596] ; (800684c ) 80065f8: 681b ldr r3, [r3, #0] 80065fa: f403 3300 and.w r3, r3, #131072 ; 0x20000 80065fe: 2b00 cmp r3, #0 8006600: f000 8098 beq.w 8006734 8006604: 687b ldr r3, [r7, #4] 8006606: 685b ldr r3, [r3, #4] 8006608: 2b00 cmp r3, #0 800660a: f040 8093 bne.w 8006734 { return HAL_ERROR; 800660e: 2301 movs r3, #1 8006610: e3cb b.n 8006daa } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8006612: 687b ldr r3, [r7, #4] 8006614: 685b ldr r3, [r3, #4] 8006616: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 800661a: d106 bne.n 800662a 800661c: 4b8b ldr r3, [pc, #556] ; (800684c ) 800661e: 681b ldr r3, [r3, #0] 8006620: 4a8a ldr r2, [pc, #552] ; (800684c ) 8006622: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8006626: 6013 str r3, [r2, #0] 8006628: e058 b.n 80066dc 800662a: 687b ldr r3, [r7, #4] 800662c: 685b ldr r3, [r3, #4] 800662e: 2b00 cmp r3, #0 8006630: d112 bne.n 8006658 8006632: 4b86 ldr r3, [pc, #536] ; (800684c ) 8006634: 681b ldr r3, [r3, #0] 8006636: 4a85 ldr r2, [pc, #532] ; (800684c ) 8006638: f423 3380 bic.w r3, r3, #65536 ; 0x10000 800663c: 6013 str r3, [r2, #0] 800663e: 4b83 ldr r3, [pc, #524] ; (800684c ) 8006640: 681b ldr r3, [r3, #0] 8006642: 4a82 ldr r2, [pc, #520] ; (800684c ) 8006644: f423 1380 bic.w r3, r3, #1048576 ; 0x100000 8006648: 6013 str r3, [r2, #0] 800664a: 4b80 ldr r3, [pc, #512] ; (800684c ) 800664c: 681b ldr r3, [r3, #0] 800664e: 4a7f ldr r2, [pc, #508] ; (800684c ) 8006650: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8006654: 6013 str r3, [r2, #0] 8006656: e041 b.n 80066dc 8006658: 687b ldr r3, [r7, #4] 800665a: 685b ldr r3, [r3, #4] 800665c: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8006660: d112 bne.n 8006688 8006662: 4b7a ldr r3, [pc, #488] ; (800684c ) 8006664: 681b ldr r3, [r3, #0] 8006666: 4a79 ldr r2, [pc, #484] ; (800684c ) 8006668: f443 2380 orr.w r3, r3, #262144 ; 0x40000 800666c: 6013 str r3, [r2, #0] 800666e: 4b77 ldr r3, [pc, #476] ; (800684c ) 8006670: 681b ldr r3, [r3, #0] 8006672: 4a76 ldr r2, [pc, #472] ; (800684c ) 8006674: f423 1380 bic.w r3, r3, #1048576 ; 0x100000 8006678: 6013 str r3, [r2, #0] 800667a: 4b74 ldr r3, [pc, #464] ; (800684c ) 800667c: 681b ldr r3, [r3, #0] 800667e: 4a73 ldr r2, [pc, #460] ; (800684c ) 8006680: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8006684: 6013 str r3, [r2, #0] 8006686: e029 b.n 80066dc 8006688: 687b ldr r3, [r7, #4] 800668a: 685b ldr r3, [r3, #4] 800668c: f5b3 1fa8 cmp.w r3, #1376256 ; 0x150000 8006690: d112 bne.n 80066b8 8006692: 4b6e ldr r3, [pc, #440] ; (800684c ) 8006694: 681b ldr r3, [r3, #0] 8006696: 4a6d ldr r2, [pc, #436] ; (800684c ) 8006698: f443 2380 orr.w r3, r3, #262144 ; 0x40000 800669c: 6013 str r3, [r2, #0] 800669e: 4b6b ldr r3, [pc, #428] ; (800684c ) 80066a0: 681b ldr r3, [r3, #0] 80066a2: 4a6a ldr r2, [pc, #424] ; (800684c ) 80066a4: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 80066a8: 6013 str r3, [r2, #0] 80066aa: 4b68 ldr r3, [pc, #416] ; (800684c ) 80066ac: 681b ldr r3, [r3, #0] 80066ae: 4a67 ldr r2, [pc, #412] ; (800684c ) 80066b0: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80066b4: 6013 str r3, [r2, #0] 80066b6: e011 b.n 80066dc 80066b8: 4b64 ldr r3, [pc, #400] ; (800684c ) 80066ba: 681b ldr r3, [r3, #0] 80066bc: 4a63 ldr r2, [pc, #396] ; (800684c ) 80066be: f423 3380 bic.w r3, r3, #65536 ; 0x10000 80066c2: 6013 str r3, [r2, #0] 80066c4: 4b61 ldr r3, [pc, #388] ; (800684c ) 80066c6: 681b ldr r3, [r3, #0] 80066c8: 4a60 ldr r2, [pc, #384] ; (800684c ) 80066ca: f423 2380 bic.w r3, r3, #262144 ; 0x40000 80066ce: 6013 str r3, [r2, #0] 80066d0: 4b5e ldr r3, [pc, #376] ; (800684c ) 80066d2: 681b ldr r3, [r3, #0] 80066d4: 4a5d ldr r2, [pc, #372] ; (800684c ) 80066d6: f423 1380 bic.w r3, r3, #1048576 ; 0x100000 80066da: 6013 str r3, [r2, #0] /* Check the HSE State */ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 80066dc: 687b ldr r3, [r7, #4] 80066de: 685b ldr r3, [r3, #4] 80066e0: 2b00 cmp r3, #0 80066e2: d013 beq.n 800670c { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80066e4: f7fc fd80 bl 80031e8 80066e8: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 80066ea: e008 b.n 80066fe { if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 80066ec: f7fc fd7c bl 80031e8 80066f0: 4602 mov r2, r0 80066f2: 6a7b ldr r3, [r7, #36] ; 0x24 80066f4: 1ad3 subs r3, r2, r3 80066f6: 2b64 cmp r3, #100 ; 0x64 80066f8: d901 bls.n 80066fe { return HAL_TIMEOUT; 80066fa: 2303 movs r3, #3 80066fc: e355 b.n 8006daa while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 80066fe: 4b53 ldr r3, [pc, #332] ; (800684c ) 8006700: 681b ldr r3, [r3, #0] 8006702: f403 3300 and.w r3, r3, #131072 ; 0x20000 8006706: 2b00 cmp r3, #0 8006708: d0f0 beq.n 80066ec 800670a: e014 b.n 8006736 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800670c: f7fc fd6c bl 80031e8 8006710: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 8006712: e008 b.n 8006726 { if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 8006714: f7fc fd68 bl 80031e8 8006718: 4602 mov r2, r0 800671a: 6a7b ldr r3, [r7, #36] ; 0x24 800671c: 1ad3 subs r3, r2, r3 800671e: 2b64 cmp r3, #100 ; 0x64 8006720: d901 bls.n 8006726 { return HAL_TIMEOUT; 8006722: 2303 movs r3, #3 8006724: e341 b.n 8006daa while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 8006726: 4b49 ldr r3, [pc, #292] ; (800684c ) 8006728: 681b ldr r3, [r3, #0] 800672a: f403 3300 and.w r3, r3, #131072 ; 0x20000 800672e: 2b00 cmp r3, #0 8006730: d1f0 bne.n 8006714 8006732: e000 b.n 8006736 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8006734: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8006736: 687b ldr r3, [r7, #4] 8006738: 681b ldr r3, [r3, #0] 800673a: f003 0302 and.w r3, r3, #2 800673e: 2b00 cmp r3, #0 8006740: f000 808c beq.w 800685c /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* When the HSI is used as system clock it will not be disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8006744: 4b41 ldr r3, [pc, #260] ; (800684c ) 8006746: 691b ldr r3, [r3, #16] 8006748: f003 0338 and.w r3, r3, #56 ; 0x38 800674c: 623b str r3, [r7, #32] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800674e: 4b3f ldr r3, [pc, #252] ; (800684c ) 8006750: 6a9b ldr r3, [r3, #40] ; 0x28 8006752: 61fb str r3, [r7, #28] if((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI))) 8006754: 6a3b ldr r3, [r7, #32] 8006756: 2b00 cmp r3, #0 8006758: d007 beq.n 800676a 800675a: 6a3b ldr r3, [r7, #32] 800675c: 2b18 cmp r3, #24 800675e: d137 bne.n 80067d0 8006760: 69fb ldr r3, [r7, #28] 8006762: f003 0303 and.w r3, r3, #3 8006766: 2b00 cmp r3, #0 8006768: d132 bne.n 80067d0 { /* When HSI is used as system clock it will not be disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800676a: 4b38 ldr r3, [pc, #224] ; (800684c ) 800676c: 681b ldr r3, [r3, #0] 800676e: f003 0304 and.w r3, r3, #4 8006772: 2b00 cmp r3, #0 8006774: d005 beq.n 8006782 8006776: 687b ldr r3, [r7, #4] 8006778: 68db ldr r3, [r3, #12] 800677a: 2b00 cmp r3, #0 800677c: d101 bne.n 8006782 { return HAL_ERROR; 800677e: 2301 movs r3, #1 8006780: e313 b.n 8006daa } /* Otherwise, only HSI division and calibration are allowed */ else { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 8006782: 4b32 ldr r3, [pc, #200] ; (800684c ) 8006784: 681b ldr r3, [r3, #0] 8006786: f023 0219 bic.w r2, r3, #25 800678a: 687b ldr r3, [r7, #4] 800678c: 68db ldr r3, [r3, #12] 800678e: 492f ldr r1, [pc, #188] ; (800684c ) 8006790: 4313 orrs r3, r2 8006792: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8006794: f7fc fd28 bl 80031e8 8006798: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800679a: e008 b.n 80067ae { if((uint32_t) (HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 800679c: f7fc fd24 bl 80031e8 80067a0: 4602 mov r2, r0 80067a2: 6a7b ldr r3, [r7, #36] ; 0x24 80067a4: 1ad3 subs r3, r2, r3 80067a6: 2b02 cmp r3, #2 80067a8: d901 bls.n 80067ae { return HAL_TIMEOUT; 80067aa: 2303 movs r3, #3 80067ac: e2fd b.n 8006daa while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 80067ae: 4b27 ldr r3, [pc, #156] ; (800684c ) 80067b0: 681b ldr r3, [r3, #0] 80067b2: f003 0304 and.w r3, r3, #4 80067b6: 2b00 cmp r3, #0 80067b8: d0f0 beq.n 800679c } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80067ba: 4b24 ldr r3, [pc, #144] ; (800684c ) 80067bc: 685b ldr r3, [r3, #4] 80067be: f023 42fe bic.w r2, r3, #2130706432 ; 0x7f000000 80067c2: 687b ldr r3, [r7, #4] 80067c4: 691b ldr r3, [r3, #16] 80067c6: 061b lsls r3, r3, #24 80067c8: 4920 ldr r1, [pc, #128] ; (800684c ) 80067ca: 4313 orrs r3, r2 80067cc: 604b str r3, [r1, #4] if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 80067ce: e045 b.n 800685c } else { /* Check the HSI State */ if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) 80067d0: 687b ldr r3, [r7, #4] 80067d2: 68db ldr r3, [r3, #12] 80067d4: 2b00 cmp r3, #0 80067d6: d026 beq.n 8006826 { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 80067d8: 4b1c ldr r3, [pc, #112] ; (800684c ) 80067da: 681b ldr r3, [r3, #0] 80067dc: f023 0219 bic.w r2, r3, #25 80067e0: 687b ldr r3, [r7, #4] 80067e2: 68db ldr r3, [r3, #12] 80067e4: 4919 ldr r1, [pc, #100] ; (800684c ) 80067e6: 4313 orrs r3, r2 80067e8: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80067ea: f7fc fcfd bl 80031e8 80067ee: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 80067f0: e008 b.n 8006804 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 80067f2: f7fc fcf9 bl 80031e8 80067f6: 4602 mov r2, r0 80067f8: 6a7b ldr r3, [r7, #36] ; 0x24 80067fa: 1ad3 subs r3, r2, r3 80067fc: 2b02 cmp r3, #2 80067fe: d901 bls.n 8006804 { return HAL_TIMEOUT; 8006800: 2303 movs r3, #3 8006802: e2d2 b.n 8006daa while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 8006804: 4b11 ldr r3, [pc, #68] ; (800684c ) 8006806: 681b ldr r3, [r3, #0] 8006808: f003 0304 and.w r3, r3, #4 800680c: 2b00 cmp r3, #0 800680e: d0f0 beq.n 80067f2 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8006810: 4b0e ldr r3, [pc, #56] ; (800684c ) 8006812: 685b ldr r3, [r3, #4] 8006814: f023 42fe bic.w r2, r3, #2130706432 ; 0x7f000000 8006818: 687b ldr r3, [r7, #4] 800681a: 691b ldr r3, [r3, #16] 800681c: 061b lsls r3, r3, #24 800681e: 490b ldr r1, [pc, #44] ; (800684c ) 8006820: 4313 orrs r3, r2 8006822: 604b str r3, [r1, #4] 8006824: e01a b.n 800685c } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8006826: 4b09 ldr r3, [pc, #36] ; (800684c ) 8006828: 681b ldr r3, [r3, #0] 800682a: 4a08 ldr r2, [pc, #32] ; (800684c ) 800682c: f023 0301 bic.w r3, r3, #1 8006830: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8006832: f7fc fcd9 bl 80031e8 8006836: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 8006838: e00a b.n 8006850 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 800683a: f7fc fcd5 bl 80031e8 800683e: 4602 mov r2, r0 8006840: 6a7b ldr r3, [r7, #36] ; 0x24 8006842: 1ad3 subs r3, r2, r3 8006844: 2b02 cmp r3, #2 8006846: d903 bls.n 8006850 { return HAL_TIMEOUT; 8006848: 2303 movs r3, #3 800684a: e2ae b.n 8006daa 800684c: 58024400 .word 0x58024400 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 8006850: 4b99 ldr r3, [pc, #612] ; (8006ab8 ) 8006852: 681b ldr r3, [r3, #0] 8006854: f003 0304 and.w r3, r3, #4 8006858: 2b00 cmp r3, #0 800685a: d1ee bne.n 800683a } } } } /*----------------------------- CSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) 800685c: 687b ldr r3, [r7, #4] 800685e: 681b ldr r3, [r3, #0] 8006860: f003 0310 and.w r3, r3, #16 8006864: 2b00 cmp r3, #0 8006866: d06a beq.n 800693e /* Check the parameters */ assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState)); assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue)); /* When the CSI is used as system clock it will not disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8006868: 4b93 ldr r3, [pc, #588] ; (8006ab8 ) 800686a: 691b ldr r3, [r3, #16] 800686c: f003 0338 and.w r3, r3, #56 ; 0x38 8006870: 61bb str r3, [r7, #24] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 8006872: 4b91 ldr r3, [pc, #580] ; (8006ab8 ) 8006874: 6a9b ldr r3, [r3, #40] ; 0x28 8006876: 617b str r3, [r7, #20] if((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI))) 8006878: 69bb ldr r3, [r7, #24] 800687a: 2b08 cmp r3, #8 800687c: d007 beq.n 800688e 800687e: 69bb ldr r3, [r7, #24] 8006880: 2b18 cmp r3, #24 8006882: d11b bne.n 80068bc 8006884: 697b ldr r3, [r7, #20] 8006886: f003 0303 and.w r3, r3, #3 800688a: 2b01 cmp r3, #1 800688c: d116 bne.n 80068bc { /* When CSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800688e: 4b8a ldr r3, [pc, #552] ; (8006ab8 ) 8006890: 681b ldr r3, [r3, #0] 8006892: f403 7380 and.w r3, r3, #256 ; 0x100 8006896: 2b00 cmp r3, #0 8006898: d005 beq.n 80068a6 800689a: 687b ldr r3, [r7, #4] 800689c: 69db ldr r3, [r3, #28] 800689e: 2b80 cmp r3, #128 ; 0x80 80068a0: d001 beq.n 80068a6 { return HAL_ERROR; 80068a2: 2301 movs r3, #1 80068a4: e281 b.n 8006daa } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 80068a6: 4b84 ldr r3, [pc, #528] ; (8006ab8 ) 80068a8: 68db ldr r3, [r3, #12] 80068aa: f023 527c bic.w r2, r3, #1056964608 ; 0x3f000000 80068ae: 687b ldr r3, [r7, #4] 80068b0: 6a1b ldr r3, [r3, #32] 80068b2: 061b lsls r3, r3, #24 80068b4: 4980 ldr r1, [pc, #512] ; (8006ab8 ) 80068b6: 4313 orrs r3, r2 80068b8: 60cb str r3, [r1, #12] if((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 80068ba: e040 b.n 800693e } } else { /* Check the CSI State */ if((RCC_OscInitStruct->CSIState)!= RCC_CSI_OFF) 80068bc: 687b ldr r3, [r7, #4] 80068be: 69db ldr r3, [r3, #28] 80068c0: 2b00 cmp r3, #0 80068c2: d023 beq.n 800690c { /* Enable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_ENABLE(); 80068c4: 4b7c ldr r3, [pc, #496] ; (8006ab8 ) 80068c6: 681b ldr r3, [r3, #0] 80068c8: 4a7b ldr r2, [pc, #492] ; (8006ab8 ) 80068ca: f043 0380 orr.w r3, r3, #128 ; 0x80 80068ce: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80068d0: f7fc fc8a bl 80031e8 80068d4: 6278 str r0, [r7, #36] ; 0x24 /* Wait till CSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 80068d6: e008 b.n 80068ea { if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE) 80068d8: f7fc fc86 bl 80031e8 80068dc: 4602 mov r2, r0 80068de: 6a7b ldr r3, [r7, #36] ; 0x24 80068e0: 1ad3 subs r3, r2, r3 80068e2: 2b02 cmp r3, #2 80068e4: d901 bls.n 80068ea { return HAL_TIMEOUT; 80068e6: 2303 movs r3, #3 80068e8: e25f b.n 8006daa while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 80068ea: 4b73 ldr r3, [pc, #460] ; (8006ab8 ) 80068ec: 681b ldr r3, [r3, #0] 80068ee: f403 7380 and.w r3, r3, #256 ; 0x100 80068f2: 2b00 cmp r3, #0 80068f4: d0f0 beq.n 80068d8 } } /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 80068f6: 4b70 ldr r3, [pc, #448] ; (8006ab8 ) 80068f8: 68db ldr r3, [r3, #12] 80068fa: f023 527c bic.w r2, r3, #1056964608 ; 0x3f000000 80068fe: 687b ldr r3, [r7, #4] 8006900: 6a1b ldr r3, [r3, #32] 8006902: 061b lsls r3, r3, #24 8006904: 496c ldr r1, [pc, #432] ; (8006ab8 ) 8006906: 4313 orrs r3, r2 8006908: 60cb str r3, [r1, #12] 800690a: e018 b.n 800693e } else { /* Disable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_DISABLE(); 800690c: 4b6a ldr r3, [pc, #424] ; (8006ab8 ) 800690e: 681b ldr r3, [r3, #0] 8006910: 4a69 ldr r2, [pc, #420] ; (8006ab8 ) 8006912: f023 0380 bic.w r3, r3, #128 ; 0x80 8006916: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8006918: f7fc fc66 bl 80031e8 800691c: 6278 str r0, [r7, #36] ; 0x24 /* Wait till CSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 800691e: e008 b.n 8006932 { if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE) 8006920: f7fc fc62 bl 80031e8 8006924: 4602 mov r2, r0 8006926: 6a7b ldr r3, [r7, #36] ; 0x24 8006928: 1ad3 subs r3, r2, r3 800692a: 2b02 cmp r3, #2 800692c: d901 bls.n 8006932 { return HAL_TIMEOUT; 800692e: 2303 movs r3, #3 8006930: e23b b.n 8006daa while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 8006932: 4b61 ldr r3, [pc, #388] ; (8006ab8 ) 8006934: 681b ldr r3, [r3, #0] 8006936: f403 7380 and.w r3, r3, #256 ; 0x100 800693a: 2b00 cmp r3, #0 800693c: d1f0 bne.n 8006920 } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 800693e: 687b ldr r3, [r7, #4] 8006940: 681b ldr r3, [r3, #0] 8006942: f003 0308 and.w r3, r3, #8 8006946: 2b00 cmp r3, #0 8006948: d036 beq.n 80069b8 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) 800694a: 687b ldr r3, [r7, #4] 800694c: 695b ldr r3, [r3, #20] 800694e: 2b00 cmp r3, #0 8006950: d019 beq.n 8006986 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8006952: 4b59 ldr r3, [pc, #356] ; (8006ab8 ) 8006954: 6f5b ldr r3, [r3, #116] ; 0x74 8006956: 4a58 ldr r2, [pc, #352] ; (8006ab8 ) 8006958: f043 0301 orr.w r3, r3, #1 800695c: 6753 str r3, [r2, #116] ; 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800695e: f7fc fc43 bl 80031e8 8006962: 6278 str r0, [r7, #36] ; 0x24 /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 8006964: e008 b.n 8006978 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8006966: f7fc fc3f bl 80031e8 800696a: 4602 mov r2, r0 800696c: 6a7b ldr r3, [r7, #36] ; 0x24 800696e: 1ad3 subs r3, r2, r3 8006970: 2b02 cmp r3, #2 8006972: d901 bls.n 8006978 { return HAL_TIMEOUT; 8006974: 2303 movs r3, #3 8006976: e218 b.n 8006daa while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 8006978: 4b4f ldr r3, [pc, #316] ; (8006ab8 ) 800697a: 6f5b ldr r3, [r3, #116] ; 0x74 800697c: f003 0302 and.w r3, r3, #2 8006980: 2b00 cmp r3, #0 8006982: d0f0 beq.n 8006966 8006984: e018 b.n 80069b8 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8006986: 4b4c ldr r3, [pc, #304] ; (8006ab8 ) 8006988: 6f5b ldr r3, [r3, #116] ; 0x74 800698a: 4a4b ldr r2, [pc, #300] ; (8006ab8 ) 800698c: f023 0301 bic.w r3, r3, #1 8006990: 6753 str r3, [r2, #116] ; 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8006992: f7fc fc29 bl 80031e8 8006996: 6278 str r0, [r7, #36] ; 0x24 /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 8006998: e008 b.n 80069ac { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 800699a: f7fc fc25 bl 80031e8 800699e: 4602 mov r2, r0 80069a0: 6a7b ldr r3, [r7, #36] ; 0x24 80069a2: 1ad3 subs r3, r2, r3 80069a4: 2b02 cmp r3, #2 80069a6: d901 bls.n 80069ac { return HAL_TIMEOUT; 80069a8: 2303 movs r3, #3 80069aa: e1fe b.n 8006daa while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 80069ac: 4b42 ldr r3, [pc, #264] ; (8006ab8 ) 80069ae: 6f5b ldr r3, [r3, #116] ; 0x74 80069b0: f003 0302 and.w r3, r3, #2 80069b4: 2b00 cmp r3, #0 80069b6: d1f0 bne.n 800699a } } } /*------------------------------ HSI48 Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 80069b8: 687b ldr r3, [r7, #4] 80069ba: 681b ldr r3, [r3, #0] 80069bc: f003 0320 and.w r3, r3, #32 80069c0: 2b00 cmp r3, #0 80069c2: d036 beq.n 8006a32 { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI48 State */ if((RCC_OscInitStruct->HSI48State)!= RCC_HSI48_OFF) 80069c4: 687b ldr r3, [r7, #4] 80069c6: 699b ldr r3, [r3, #24] 80069c8: 2b00 cmp r3, #0 80069ca: d019 beq.n 8006a00 { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); 80069cc: 4b3a ldr r3, [pc, #232] ; (8006ab8 ) 80069ce: 681b ldr r3, [r3, #0] 80069d0: 4a39 ldr r2, [pc, #228] ; (8006ab8 ) 80069d2: f443 5380 orr.w r3, r3, #4096 ; 0x1000 80069d6: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 80069d8: f7fc fc06 bl 80031e8 80069dc: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI48 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 80069de: e008 b.n 80069f2 { if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE) 80069e0: f7fc fc02 bl 80031e8 80069e4: 4602 mov r2, r0 80069e6: 6a7b ldr r3, [r7, #36] ; 0x24 80069e8: 1ad3 subs r3, r2, r3 80069ea: 2b02 cmp r3, #2 80069ec: d901 bls.n 80069f2 { return HAL_TIMEOUT; 80069ee: 2303 movs r3, #3 80069f0: e1db b.n 8006daa while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 80069f2: 4b31 ldr r3, [pc, #196] ; (8006ab8 ) 80069f4: 681b ldr r3, [r3, #0] 80069f6: f403 5300 and.w r3, r3, #8192 ; 0x2000 80069fa: 2b00 cmp r3, #0 80069fc: d0f0 beq.n 80069e0 80069fe: e018 b.n 8006a32 } } else { /* Disable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); 8006a00: 4b2d ldr r3, [pc, #180] ; (8006ab8 ) 8006a02: 681b ldr r3, [r3, #0] 8006a04: 4a2c ldr r2, [pc, #176] ; (8006ab8 ) 8006a06: f423 5380 bic.w r3, r3, #4096 ; 0x1000 8006a0a: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 8006a0c: f7fc fbec bl 80031e8 8006a10: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI48 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 8006a12: e008 b.n 8006a26 { if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE) 8006a14: f7fc fbe8 bl 80031e8 8006a18: 4602 mov r2, r0 8006a1a: 6a7b ldr r3, [r7, #36] ; 0x24 8006a1c: 1ad3 subs r3, r2, r3 8006a1e: 2b02 cmp r3, #2 8006a20: d901 bls.n 8006a26 { return HAL_TIMEOUT; 8006a22: 2303 movs r3, #3 8006a24: e1c1 b.n 8006daa while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 8006a26: 4b24 ldr r3, [pc, #144] ; (8006ab8 ) 8006a28: 681b ldr r3, [r3, #0] 8006a2a: f403 5300 and.w r3, r3, #8192 ; 0x2000 8006a2e: 2b00 cmp r3, #0 8006a30: d1f0 bne.n 8006a14 } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8006a32: 687b ldr r3, [r7, #4] 8006a34: 681b ldr r3, [r3, #0] 8006a36: f003 0304 and.w r3, r3, #4 8006a3a: 2b00 cmp r3, #0 8006a3c: f000 80af beq.w 8006b9e { /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; 8006a40: 4b1e ldr r3, [pc, #120] ; (8006abc ) 8006a42: 681b ldr r3, [r3, #0] 8006a44: 4a1d ldr r2, [pc, #116] ; (8006abc ) 8006a46: f443 7380 orr.w r3, r3, #256 ; 0x100 8006a4a: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8006a4c: f7fc fbcc bl 80031e8 8006a50: 6278 str r0, [r7, #36] ; 0x24 while((PWR->CR1 & PWR_CR1_DBP) == 0U) 8006a52: e008 b.n 8006a66 { if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) 8006a54: f7fc fbc8 bl 80031e8 8006a58: 4602 mov r2, r0 8006a5a: 6a7b ldr r3, [r7, #36] ; 0x24 8006a5c: 1ad3 subs r3, r2, r3 8006a5e: 2b64 cmp r3, #100 ; 0x64 8006a60: d901 bls.n 8006a66 { return HAL_TIMEOUT; 8006a62: 2303 movs r3, #3 8006a64: e1a1 b.n 8006daa while((PWR->CR1 & PWR_CR1_DBP) == 0U) 8006a66: 4b15 ldr r3, [pc, #84] ; (8006abc ) 8006a68: 681b ldr r3, [r3, #0] 8006a6a: f403 7380 and.w r3, r3, #256 ; 0x100 8006a6e: 2b00 cmp r3, #0 8006a70: d0f0 beq.n 8006a54 } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8006a72: 687b ldr r3, [r7, #4] 8006a74: 689b ldr r3, [r3, #8] 8006a76: 2b01 cmp r3, #1 8006a78: d106 bne.n 8006a88 8006a7a: 4b0f ldr r3, [pc, #60] ; (8006ab8 ) 8006a7c: 6f1b ldr r3, [r3, #112] ; 0x70 8006a7e: 4a0e ldr r2, [pc, #56] ; (8006ab8 ) 8006a80: f043 0301 orr.w r3, r3, #1 8006a84: 6713 str r3, [r2, #112] ; 0x70 8006a86: e05b b.n 8006b40 8006a88: 687b ldr r3, [r7, #4] 8006a8a: 689b ldr r3, [r3, #8] 8006a8c: 2b00 cmp r3, #0 8006a8e: d117 bne.n 8006ac0 8006a90: 4b09 ldr r3, [pc, #36] ; (8006ab8 ) 8006a92: 6f1b ldr r3, [r3, #112] ; 0x70 8006a94: 4a08 ldr r2, [pc, #32] ; (8006ab8 ) 8006a96: f023 0301 bic.w r3, r3, #1 8006a9a: 6713 str r3, [r2, #112] ; 0x70 8006a9c: 4b06 ldr r3, [pc, #24] ; (8006ab8 ) 8006a9e: 6f1b ldr r3, [r3, #112] ; 0x70 8006aa0: 4a05 ldr r2, [pc, #20] ; (8006ab8 ) 8006aa2: f023 0380 bic.w r3, r3, #128 ; 0x80 8006aa6: 6713 str r3, [r2, #112] ; 0x70 8006aa8: 4b03 ldr r3, [pc, #12] ; (8006ab8 ) 8006aaa: 6f1b ldr r3, [r3, #112] ; 0x70 8006aac: 4a02 ldr r2, [pc, #8] ; (8006ab8 ) 8006aae: f023 0304 bic.w r3, r3, #4 8006ab2: 6713 str r3, [r2, #112] ; 0x70 8006ab4: e044 b.n 8006b40 8006ab6: bf00 nop 8006ab8: 58024400 .word 0x58024400 8006abc: 58024800 .word 0x58024800 8006ac0: 687b ldr r3, [r7, #4] 8006ac2: 689b ldr r3, [r3, #8] 8006ac4: 2b05 cmp r3, #5 8006ac6: d112 bne.n 8006aee 8006ac8: 4b95 ldr r3, [pc, #596] ; (8006d20 ) 8006aca: 6f1b ldr r3, [r3, #112] ; 0x70 8006acc: 4a94 ldr r2, [pc, #592] ; (8006d20 ) 8006ace: f043 0304 orr.w r3, r3, #4 8006ad2: 6713 str r3, [r2, #112] ; 0x70 8006ad4: 4b92 ldr r3, [pc, #584] ; (8006d20 ) 8006ad6: 6f1b ldr r3, [r3, #112] ; 0x70 8006ad8: 4a91 ldr r2, [pc, #580] ; (8006d20 ) 8006ada: f023 0380 bic.w r3, r3, #128 ; 0x80 8006ade: 6713 str r3, [r2, #112] ; 0x70 8006ae0: 4b8f ldr r3, [pc, #572] ; (8006d20 ) 8006ae2: 6f1b ldr r3, [r3, #112] ; 0x70 8006ae4: 4a8e ldr r2, [pc, #568] ; (8006d20 ) 8006ae6: f043 0301 orr.w r3, r3, #1 8006aea: 6713 str r3, [r2, #112] ; 0x70 8006aec: e028 b.n 8006b40 8006aee: 687b ldr r3, [r7, #4] 8006af0: 689b ldr r3, [r3, #8] 8006af2: 2b85 cmp r3, #133 ; 0x85 8006af4: d112 bne.n 8006b1c 8006af6: 4b8a ldr r3, [pc, #552] ; (8006d20 ) 8006af8: 6f1b ldr r3, [r3, #112] ; 0x70 8006afa: 4a89 ldr r2, [pc, #548] ; (8006d20 ) 8006afc: f043 0304 orr.w r3, r3, #4 8006b00: 6713 str r3, [r2, #112] ; 0x70 8006b02: 4b87 ldr r3, [pc, #540] ; (8006d20 ) 8006b04: 6f1b ldr r3, [r3, #112] ; 0x70 8006b06: 4a86 ldr r2, [pc, #536] ; (8006d20 ) 8006b08: f043 0380 orr.w r3, r3, #128 ; 0x80 8006b0c: 6713 str r3, [r2, #112] ; 0x70 8006b0e: 4b84 ldr r3, [pc, #528] ; (8006d20 ) 8006b10: 6f1b ldr r3, [r3, #112] ; 0x70 8006b12: 4a83 ldr r2, [pc, #524] ; (8006d20 ) 8006b14: f043 0301 orr.w r3, r3, #1 8006b18: 6713 str r3, [r2, #112] ; 0x70 8006b1a: e011 b.n 8006b40 8006b1c: 4b80 ldr r3, [pc, #512] ; (8006d20 ) 8006b1e: 6f1b ldr r3, [r3, #112] ; 0x70 8006b20: 4a7f ldr r2, [pc, #508] ; (8006d20 ) 8006b22: f023 0301 bic.w r3, r3, #1 8006b26: 6713 str r3, [r2, #112] ; 0x70 8006b28: 4b7d ldr r3, [pc, #500] ; (8006d20 ) 8006b2a: 6f1b ldr r3, [r3, #112] ; 0x70 8006b2c: 4a7c ldr r2, [pc, #496] ; (8006d20 ) 8006b2e: f023 0304 bic.w r3, r3, #4 8006b32: 6713 str r3, [r2, #112] ; 0x70 8006b34: 4b7a ldr r3, [pc, #488] ; (8006d20 ) 8006b36: 6f1b ldr r3, [r3, #112] ; 0x70 8006b38: 4a79 ldr r2, [pc, #484] ; (8006d20 ) 8006b3a: f023 0380 bic.w r3, r3, #128 ; 0x80 8006b3e: 6713 str r3, [r2, #112] ; 0x70 /* Check the LSE State */ if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 8006b40: 687b ldr r3, [r7, #4] 8006b42: 689b ldr r3, [r3, #8] 8006b44: 2b00 cmp r3, #0 8006b46: d015 beq.n 8006b74 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8006b48: f7fc fb4e bl 80031e8 8006b4c: 6278 str r0, [r7, #36] ; 0x24 /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 8006b4e: e00a b.n 8006b66 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8006b50: f7fc fb4a bl 80031e8 8006b54: 4602 mov r2, r0 8006b56: 6a7b ldr r3, [r7, #36] ; 0x24 8006b58: 1ad3 subs r3, r2, r3 8006b5a: f241 3288 movw r2, #5000 ; 0x1388 8006b5e: 4293 cmp r3, r2 8006b60: d901 bls.n 8006b66 { return HAL_TIMEOUT; 8006b62: 2303 movs r3, #3 8006b64: e121 b.n 8006daa while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 8006b66: 4b6e ldr r3, [pc, #440] ; (8006d20 ) 8006b68: 6f1b ldr r3, [r3, #112] ; 0x70 8006b6a: f003 0302 and.w r3, r3, #2 8006b6e: 2b00 cmp r3, #0 8006b70: d0ee beq.n 8006b50 8006b72: e014 b.n 8006b9e } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8006b74: f7fc fb38 bl 80031e8 8006b78: 6278 str r0, [r7, #36] ; 0x24 /* Wait till LSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 8006b7a: e00a b.n 8006b92 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8006b7c: f7fc fb34 bl 80031e8 8006b80: 4602 mov r2, r0 8006b82: 6a7b ldr r3, [r7, #36] ; 0x24 8006b84: 1ad3 subs r3, r2, r3 8006b86: f241 3288 movw r2, #5000 ; 0x1388 8006b8a: 4293 cmp r3, r2 8006b8c: d901 bls.n 8006b92 { return HAL_TIMEOUT; 8006b8e: 2303 movs r3, #3 8006b90: e10b b.n 8006daa while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 8006b92: 4b63 ldr r3, [pc, #396] ; (8006d20 ) 8006b94: 6f1b ldr r3, [r3, #112] ; 0x70 8006b96: f003 0302 and.w r3, r3, #2 8006b9a: 2b00 cmp r3, #0 8006b9c: d1ee bne.n 8006b7c } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8006b9e: 687b ldr r3, [r7, #4] 8006ba0: 6a5b ldr r3, [r3, #36] ; 0x24 8006ba2: 2b00 cmp r3, #0 8006ba4: f000 8100 beq.w 8006da8 { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) 8006ba8: 4b5d ldr r3, [pc, #372] ; (8006d20 ) 8006baa: 691b ldr r3, [r3, #16] 8006bac: f003 0338 and.w r3, r3, #56 ; 0x38 8006bb0: 2b18 cmp r3, #24 8006bb2: f000 80bb beq.w 8006d2c { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8006bb6: 687b ldr r3, [r7, #4] 8006bb8: 6a5b ldr r3, [r3, #36] ; 0x24 8006bba: 2b02 cmp r3, #2 8006bbc: f040 8095 bne.w 8006cea assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8006bc0: 4b57 ldr r3, [pc, #348] ; (8006d20 ) 8006bc2: 681b ldr r3, [r3, #0] 8006bc4: 4a56 ldr r2, [pc, #344] ; (8006d20 ) 8006bc6: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 8006bca: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8006bcc: f7fc fb0c bl 80031e8 8006bd0: 6278 str r0, [r7, #36] ; 0x24 /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 8006bd2: e008 b.n 8006be6 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8006bd4: f7fc fb08 bl 80031e8 8006bd8: 4602 mov r2, r0 8006bda: 6a7b ldr r3, [r7, #36] ; 0x24 8006bdc: 1ad3 subs r3, r2, r3 8006bde: 2b02 cmp r3, #2 8006be0: d901 bls.n 8006be6 { return HAL_TIMEOUT; 8006be2: 2303 movs r3, #3 8006be4: e0e1 b.n 8006daa while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 8006be6: 4b4e ldr r3, [pc, #312] ; (8006d20 ) 8006be8: 681b ldr r3, [r3, #0] 8006bea: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8006bee: 2b00 cmp r3, #0 8006bf0: d1f0 bne.n 8006bd4 } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8006bf2: 4b4b ldr r3, [pc, #300] ; (8006d20 ) 8006bf4: 6a9a ldr r2, [r3, #40] ; 0x28 8006bf6: 4b4b ldr r3, [pc, #300] ; (8006d24 ) 8006bf8: 4013 ands r3, r2 8006bfa: 687a ldr r2, [r7, #4] 8006bfc: 6a91 ldr r1, [r2, #40] ; 0x28 8006bfe: 687a ldr r2, [r7, #4] 8006c00: 6ad2 ldr r2, [r2, #44] ; 0x2c 8006c02: 0112 lsls r2, r2, #4 8006c04: 430a orrs r2, r1 8006c06: 4946 ldr r1, [pc, #280] ; (8006d20 ) 8006c08: 4313 orrs r3, r2 8006c0a: 628b str r3, [r1, #40] ; 0x28 8006c0c: 687b ldr r3, [r7, #4] 8006c0e: 6b1b ldr r3, [r3, #48] ; 0x30 8006c10: 3b01 subs r3, #1 8006c12: f3c3 0208 ubfx r2, r3, #0, #9 8006c16: 687b ldr r3, [r7, #4] 8006c18: 6b5b ldr r3, [r3, #52] ; 0x34 8006c1a: 3b01 subs r3, #1 8006c1c: 025b lsls r3, r3, #9 8006c1e: b29b uxth r3, r3 8006c20: 431a orrs r2, r3 8006c22: 687b ldr r3, [r7, #4] 8006c24: 6b9b ldr r3, [r3, #56] ; 0x38 8006c26: 3b01 subs r3, #1 8006c28: 041b lsls r3, r3, #16 8006c2a: f403 03fe and.w r3, r3, #8323072 ; 0x7f0000 8006c2e: 431a orrs r2, r3 8006c30: 687b ldr r3, [r7, #4] 8006c32: 6bdb ldr r3, [r3, #60] ; 0x3c 8006c34: 3b01 subs r3, #1 8006c36: 061b lsls r3, r3, #24 8006c38: f003 43fe and.w r3, r3, #2130706432 ; 0x7f000000 8006c3c: 4938 ldr r1, [pc, #224] ; (8006d20 ) 8006c3e: 4313 orrs r3, r2 8006c40: 630b str r3, [r1, #48] ; 0x30 RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); /* Disable PLLFRACN . */ __HAL_RCC_PLLFRACN_DISABLE(); 8006c42: 4b37 ldr r3, [pc, #220] ; (8006d20 ) 8006c44: 6adb ldr r3, [r3, #44] ; 0x2c 8006c46: 4a36 ldr r2, [pc, #216] ; (8006d20 ) 8006c48: f023 0301 bic.w r3, r3, #1 8006c4c: 62d3 str r3, [r2, #44] ; 0x2c /* Configure PLL PLL1FRACN */ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 8006c4e: 4b34 ldr r3, [pc, #208] ; (8006d20 ) 8006c50: 6b5a ldr r2, [r3, #52] ; 0x34 8006c52: 4b35 ldr r3, [pc, #212] ; (8006d28 ) 8006c54: 4013 ands r3, r2 8006c56: 687a ldr r2, [r7, #4] 8006c58: 6c92 ldr r2, [r2, #72] ; 0x48 8006c5a: 00d2 lsls r2, r2, #3 8006c5c: 4930 ldr r1, [pc, #192] ; (8006d20 ) 8006c5e: 4313 orrs r3, r2 8006c60: 634b str r3, [r1, #52] ; 0x34 /* Select PLL1 input reference frequency range: VCI */ __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ; 8006c62: 4b2f ldr r3, [pc, #188] ; (8006d20 ) 8006c64: 6adb ldr r3, [r3, #44] ; 0x2c 8006c66: f023 020c bic.w r2, r3, #12 8006c6a: 687b ldr r3, [r7, #4] 8006c6c: 6c1b ldr r3, [r3, #64] ; 0x40 8006c6e: 492c ldr r1, [pc, #176] ; (8006d20 ) 8006c70: 4313 orrs r3, r2 8006c72: 62cb str r3, [r1, #44] ; 0x2c /* Select PLL1 output frequency range : VCO */ __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ; 8006c74: 4b2a ldr r3, [pc, #168] ; (8006d20 ) 8006c76: 6adb ldr r3, [r3, #44] ; 0x2c 8006c78: f023 0202 bic.w r2, r3, #2 8006c7c: 687b ldr r3, [r7, #4] 8006c7e: 6c5b ldr r3, [r3, #68] ; 0x44 8006c80: 4927 ldr r1, [pc, #156] ; (8006d20 ) 8006c82: 4313 orrs r3, r2 8006c84: 62cb str r3, [r1, #44] ; 0x2c /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); 8006c86: 4b26 ldr r3, [pc, #152] ; (8006d20 ) 8006c88: 6adb ldr r3, [r3, #44] ; 0x2c 8006c8a: 4a25 ldr r2, [pc, #148] ; (8006d20 ) 8006c8c: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8006c90: 62d3 str r3, [r2, #44] ; 0x2c /* Enable PLL1Q Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8006c92: 4b23 ldr r3, [pc, #140] ; (8006d20 ) 8006c94: 6adb ldr r3, [r3, #44] ; 0x2c 8006c96: 4a22 ldr r2, [pc, #136] ; (8006d20 ) 8006c98: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8006c9c: 62d3 str r3, [r2, #44] ; 0x2c /* Enable PLL1R Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); 8006c9e: 4b20 ldr r3, [pc, #128] ; (8006d20 ) 8006ca0: 6adb ldr r3, [r3, #44] ; 0x2c 8006ca2: 4a1f ldr r2, [pc, #124] ; (8006d20 ) 8006ca4: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8006ca8: 62d3 str r3, [r2, #44] ; 0x2c /* Enable PLL1FRACN . */ __HAL_RCC_PLLFRACN_ENABLE(); 8006caa: 4b1d ldr r3, [pc, #116] ; (8006d20 ) 8006cac: 6adb ldr r3, [r3, #44] ; 0x2c 8006cae: 4a1c ldr r2, [pc, #112] ; (8006d20 ) 8006cb0: f043 0301 orr.w r3, r3, #1 8006cb4: 62d3 str r3, [r2, #44] ; 0x2c /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8006cb6: 4b1a ldr r3, [pc, #104] ; (8006d20 ) 8006cb8: 681b ldr r3, [r3, #0] 8006cba: 4a19 ldr r2, [pc, #100] ; (8006d20 ) 8006cbc: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 8006cc0: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8006cc2: f7fc fa91 bl 80031e8 8006cc6: 6278 str r0, [r7, #36] ; 0x24 /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 8006cc8: e008 b.n 8006cdc { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8006cca: f7fc fa8d bl 80031e8 8006cce: 4602 mov r2, r0 8006cd0: 6a7b ldr r3, [r7, #36] ; 0x24 8006cd2: 1ad3 subs r3, r2, r3 8006cd4: 2b02 cmp r3, #2 8006cd6: d901 bls.n 8006cdc { return HAL_TIMEOUT; 8006cd8: 2303 movs r3, #3 8006cda: e066 b.n 8006daa while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 8006cdc: 4b10 ldr r3, [pc, #64] ; (8006d20 ) 8006cde: 681b ldr r3, [r3, #0] 8006ce0: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8006ce4: 2b00 cmp r3, #0 8006ce6: d0f0 beq.n 8006cca 8006ce8: e05e b.n 8006da8 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8006cea: 4b0d ldr r3, [pc, #52] ; (8006d20 ) 8006cec: 681b ldr r3, [r3, #0] 8006cee: 4a0c ldr r2, [pc, #48] ; (8006d20 ) 8006cf0: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 8006cf4: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8006cf6: f7fc fa77 bl 80031e8 8006cfa: 6278 str r0, [r7, #36] ; 0x24 /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 8006cfc: e008 b.n 8006d10 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8006cfe: f7fc fa73 bl 80031e8 8006d02: 4602 mov r2, r0 8006d04: 6a7b ldr r3, [r7, #36] ; 0x24 8006d06: 1ad3 subs r3, r2, r3 8006d08: 2b02 cmp r3, #2 8006d0a: d901 bls.n 8006d10 { return HAL_TIMEOUT; 8006d0c: 2303 movs r3, #3 8006d0e: e04c b.n 8006daa while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 8006d10: 4b03 ldr r3, [pc, #12] ; (8006d20 ) 8006d12: 681b ldr r3, [r3, #0] 8006d14: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8006d18: 2b00 cmp r3, #0 8006d1a: d1f0 bne.n 8006cfe 8006d1c: e044 b.n 8006da8 8006d1e: bf00 nop 8006d20: 58024400 .word 0x58024400 8006d24: fffffc0c .word 0xfffffc0c 8006d28: ffff0007 .word 0xffff0007 } } else { /* Do not return HAL_ERROR if request repeats the current configuration */ temp1_pllckcfg = RCC->PLLCKSELR; 8006d2c: 4b21 ldr r3, [pc, #132] ; (8006db4 ) 8006d2e: 6a9b ldr r3, [r3, #40] ; 0x28 8006d30: 613b str r3, [r7, #16] temp2_pllckcfg = RCC->PLL1DIVR; 8006d32: 4b20 ldr r3, [pc, #128] ; (8006db4 ) 8006d34: 6b1b ldr r3, [r3, #48] ; 0x30 8006d36: 60fb str r3, [r7, #12] if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 8006d38: 687b ldr r3, [r7, #4] 8006d3a: 6a5b ldr r3, [r3, #36] ; 0x24 8006d3c: 2b01 cmp r3, #1 8006d3e: d031 beq.n 8006da4 (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8006d40: 693b ldr r3, [r7, #16] 8006d42: f003 0203 and.w r2, r3, #3 8006d46: 687b ldr r3, [r7, #4] 8006d48: 6a9b ldr r3, [r3, #40] ; 0x28 if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 8006d4a: 429a cmp r2, r3 8006d4c: d12a bne.n 8006da4 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 8006d4e: 693b ldr r3, [r7, #16] 8006d50: 091b lsrs r3, r3, #4 8006d52: f003 023f and.w r2, r3, #63 ; 0x3f 8006d56: 687b ldr r3, [r7, #4] 8006d58: 6adb ldr r3, [r3, #44] ; 0x2c (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8006d5a: 429a cmp r2, r3 8006d5c: d122 bne.n 8006da4 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 8006d5e: 68fb ldr r3, [r7, #12] 8006d60: f3c3 0208 ubfx r2, r3, #0, #9 8006d64: 687b ldr r3, [r7, #4] 8006d66: 6b1b ldr r3, [r3, #48] ; 0x30 8006d68: 3b01 subs r3, #1 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 8006d6a: 429a cmp r2, r3 8006d6c: d11a bne.n 8006da4 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 8006d6e: 68fb ldr r3, [r7, #12] 8006d70: 0a5b lsrs r3, r3, #9 8006d72: f003 027f and.w r2, r3, #127 ; 0x7f 8006d76: 687b ldr r3, [r7, #4] 8006d78: 6b5b ldr r3, [r3, #52] ; 0x34 8006d7a: 3b01 subs r3, #1 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 8006d7c: 429a cmp r2, r3 8006d7e: d111 bne.n 8006da4 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 8006d80: 68fb ldr r3, [r7, #12] 8006d82: 0c1b lsrs r3, r3, #16 8006d84: f003 027f and.w r2, r3, #127 ; 0x7f 8006d88: 687b ldr r3, [r7, #4] 8006d8a: 6b9b ldr r3, [r3, #56] ; 0x38 8006d8c: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 8006d8e: 429a cmp r2, r3 8006d90: d108 bne.n 8006da4 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U))) 8006d92: 68fb ldr r3, [r7, #12] 8006d94: 0e1b lsrs r3, r3, #24 8006d96: f003 027f and.w r2, r3, #127 ; 0x7f 8006d9a: 687b ldr r3, [r7, #4] 8006d9c: 6bdb ldr r3, [r3, #60] ; 0x3c 8006d9e: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 8006da0: 429a cmp r2, r3 8006da2: d001 beq.n 8006da8 { return HAL_ERROR; 8006da4: 2301 movs r3, #1 8006da6: e000 b.n 8006daa } } } return HAL_OK; 8006da8: 2300 movs r3, #0 } 8006daa: 4618 mov r0, r3 8006dac: 3730 adds r7, #48 ; 0x30 8006dae: 46bd mov sp, r7 8006db0: bd80 pop {r7, pc} 8006db2: bf00 nop 8006db4: 58024400 .word 0x58024400 08006db8 : * D1CPRE[3:0] bits to ensure that Domain1 core clock not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8006db8: b580 push {r7, lr} 8006dba: b086 sub sp, #24 8006dbc: af00 add r7, sp, #0 8006dbe: 6078 str r0, [r7, #4] 8006dc0: 6039 str r1, [r7, #0] HAL_StatusTypeDef halstatus; uint32_t tickstart; uint32_t common_system_clock; /* Check Null pointer */ if(RCC_ClkInitStruct == NULL) 8006dc2: 687b ldr r3, [r7, #4] 8006dc4: 2b00 cmp r3, #0 8006dc6: d101 bne.n 8006dcc { return HAL_ERROR; 8006dc8: 2301 movs r3, #1 8006dca: e19c b.n 8007106 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the CPU frequency */ if(FLatency > __HAL_FLASH_GET_LATENCY()) 8006dcc: 4b8a ldr r3, [pc, #552] ; (8006ff8 ) 8006dce: 681b ldr r3, [r3, #0] 8006dd0: f003 030f and.w r3, r3, #15 8006dd4: 683a ldr r2, [r7, #0] 8006dd6: 429a cmp r2, r3 8006dd8: d910 bls.n 8006dfc { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8006dda: 4b87 ldr r3, [pc, #540] ; (8006ff8 ) 8006ddc: 681b ldr r3, [r3, #0] 8006dde: f023 020f bic.w r2, r3, #15 8006de2: 4985 ldr r1, [pc, #532] ; (8006ff8 ) 8006de4: 683b ldr r3, [r7, #0] 8006de6: 4313 orrs r3, r2 8006de8: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8006dea: 4b83 ldr r3, [pc, #524] ; (8006ff8 ) 8006dec: 681b ldr r3, [r3, #0] 8006dee: f003 030f and.w r3, r3, #15 8006df2: 683a ldr r2, [r7, #0] 8006df4: 429a cmp r2, r3 8006df6: d001 beq.n 8006dfc { return HAL_ERROR; 8006df8: 2301 movs r3, #1 8006dfa: e184 b.n 8007106 } /* Increasing the BUS frequency divider */ /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 8006dfc: 687b ldr r3, [r7, #4] 8006dfe: 681b ldr r3, [r3, #0] 8006e00: f003 0304 and.w r3, r3, #4 8006e04: 2b00 cmp r3, #0 8006e06: d010 beq.n 8006e2a { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); } #else if((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)) 8006e08: 687b ldr r3, [r7, #4] 8006e0a: 691a ldr r2, [r3, #16] 8006e0c: 4b7b ldr r3, [pc, #492] ; (8006ffc ) 8006e0e: 699b ldr r3, [r3, #24] 8006e10: f003 0370 and.w r3, r3, #112 ; 0x70 8006e14: 429a cmp r2, r3 8006e16: d908 bls.n 8006e2a { assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider); 8006e18: 4b78 ldr r3, [pc, #480] ; (8006ffc ) 8006e1a: 699b ldr r3, [r3, #24] 8006e1c: f023 0270 bic.w r2, r3, #112 ; 0x70 8006e20: 687b ldr r3, [r7, #4] 8006e22: 691b ldr r3, [r3, #16] 8006e24: 4975 ldr r1, [pc, #468] ; (8006ffc ) 8006e26: 4313 orrs r3, r2 8006e28: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8006e2a: 687b ldr r3, [r7, #4] 8006e2c: 681b ldr r3, [r3, #0] 8006e2e: f003 0308 and.w r3, r3, #8 8006e32: 2b00 cmp r3, #0 8006e34: d010 beq.n 8006e58 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); } #else if((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)) 8006e36: 687b ldr r3, [r7, #4] 8006e38: 695a ldr r2, [r3, #20] 8006e3a: 4b70 ldr r3, [pc, #448] ; (8006ffc ) 8006e3c: 69db ldr r3, [r3, #28] 8006e3e: f003 0370 and.w r3, r3, #112 ; 0x70 8006e42: 429a cmp r2, r3 8006e44: d908 bls.n 8006e58 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 8006e46: 4b6d ldr r3, [pc, #436] ; (8006ffc ) 8006e48: 69db ldr r3, [r3, #28] 8006e4a: f023 0270 bic.w r2, r3, #112 ; 0x70 8006e4e: 687b ldr r3, [r7, #4] 8006e50: 695b ldr r3, [r3, #20] 8006e52: 496a ldr r1, [pc, #424] ; (8006ffc ) 8006e54: 4313 orrs r3, r2 8006e56: 61cb str r3, [r1, #28] } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8006e58: 687b ldr r3, [r7, #4] 8006e5a: 681b ldr r3, [r3, #0] 8006e5c: f003 0310 and.w r3, r3, #16 8006e60: 2b00 cmp r3, #0 8006e62: d010 beq.n 8006e86 { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); } #else if((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)) 8006e64: 687b ldr r3, [r7, #4] 8006e66: 699a ldr r2, [r3, #24] 8006e68: 4b64 ldr r3, [pc, #400] ; (8006ffc ) 8006e6a: 69db ldr r3, [r3, #28] 8006e6c: f403 63e0 and.w r3, r3, #1792 ; 0x700 8006e70: 429a cmp r2, r3 8006e72: d908 bls.n 8006e86 { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 8006e74: 4b61 ldr r3, [pc, #388] ; (8006ffc ) 8006e76: 69db ldr r3, [r3, #28] 8006e78: f423 62e0 bic.w r2, r3, #1792 ; 0x700 8006e7c: 687b ldr r3, [r7, #4] 8006e7e: 699b ldr r3, [r3, #24] 8006e80: 495e ldr r1, [pc, #376] ; (8006ffc ) 8006e82: 4313 orrs r3, r2 8006e84: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 8006e86: 687b ldr r3, [r7, #4] 8006e88: 681b ldr r3, [r3, #0] 8006e8a: f003 0320 and.w r3, r3, #32 8006e8e: 2b00 cmp r3, #0 8006e90: d010 beq.n 8006eb4 { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) ); } #else if((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)) 8006e92: 687b ldr r3, [r7, #4] 8006e94: 69da ldr r2, [r3, #28] 8006e96: 4b59 ldr r3, [pc, #356] ; (8006ffc ) 8006e98: 6a1b ldr r3, [r3, #32] 8006e9a: f003 0370 and.w r3, r3, #112 ; 0x70 8006e9e: 429a cmp r2, r3 8006ea0: d908 bls.n 8006eb4 { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider) ); 8006ea2: 4b56 ldr r3, [pc, #344] ; (8006ffc ) 8006ea4: 6a1b ldr r3, [r3, #32] 8006ea6: f023 0270 bic.w r2, r3, #112 ; 0x70 8006eaa: 687b ldr r3, [r7, #4] 8006eac: 69db ldr r3, [r3, #28] 8006eae: 4953 ldr r1, [pc, #332] ; (8006ffc ) 8006eb0: 4313 orrs r3, r2 8006eb2: 620b str r3, [r1, #32] } #endif } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8006eb4: 687b ldr r3, [r7, #4] 8006eb6: 681b ldr r3, [r3, #0] 8006eb8: f003 0302 and.w r3, r3, #2 8006ebc: 2b00 cmp r3, #0 8006ebe: d010 beq.n 8006ee2 /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); } #else if((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)) 8006ec0: 687b ldr r3, [r7, #4] 8006ec2: 68da ldr r2, [r3, #12] 8006ec4: 4b4d ldr r3, [pc, #308] ; (8006ffc ) 8006ec6: 699b ldr r3, [r3, #24] 8006ec8: f003 030f and.w r3, r3, #15 8006ecc: 429a cmp r2, r3 8006ece: d908 bls.n 8006ee2 { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8006ed0: 4b4a ldr r3, [pc, #296] ; (8006ffc ) 8006ed2: 699b ldr r3, [r3, #24] 8006ed4: f023 020f bic.w r2, r3, #15 8006ed8: 687b ldr r3, [r7, #4] 8006eda: 68db ldr r3, [r3, #12] 8006edc: 4947 ldr r1, [pc, #284] ; (8006ffc ) 8006ede: 4313 orrs r3, r2 8006ee0: 618b str r3, [r1, #24] } #endif } /*------------------------- SYSCLK Configuration -------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8006ee2: 687b ldr r3, [r7, #4] 8006ee4: 681b ldr r3, [r3, #0] 8006ee6: f003 0301 and.w r3, r3, #1 8006eea: 2b00 cmp r3, #0 8006eec: d055 beq.n 8006f9a assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); #if defined(RCC_D1CFGR_D1CPRE) MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider); #else MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider); 8006eee: 4b43 ldr r3, [pc, #268] ; (8006ffc ) 8006ef0: 699b ldr r3, [r3, #24] 8006ef2: f423 6270 bic.w r2, r3, #3840 ; 0xf00 8006ef6: 687b ldr r3, [r7, #4] 8006ef8: 689b ldr r3, [r3, #8] 8006efa: 4940 ldr r1, [pc, #256] ; (8006ffc ) 8006efc: 4313 orrs r3, r2 8006efe: 618b str r3, [r1, #24] #endif /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8006f00: 687b ldr r3, [r7, #4] 8006f02: 685b ldr r3, [r3, #4] 8006f04: 2b02 cmp r3, #2 8006f06: d107 bne.n 8006f18 { /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 8006f08: 4b3c ldr r3, [pc, #240] ; (8006ffc ) 8006f0a: 681b ldr r3, [r3, #0] 8006f0c: f403 3300 and.w r3, r3, #131072 ; 0x20000 8006f10: 2b00 cmp r3, #0 8006f12: d121 bne.n 8006f58 { return HAL_ERROR; 8006f14: 2301 movs r3, #1 8006f16: e0f6 b.n 8007106 } } /* PLL is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8006f18: 687b ldr r3, [r7, #4] 8006f1a: 685b ldr r3, [r3, #4] 8006f1c: 2b03 cmp r3, #3 8006f1e: d107 bne.n 8006f30 { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 8006f20: 4b36 ldr r3, [pc, #216] ; (8006ffc ) 8006f22: 681b ldr r3, [r3, #0] 8006f24: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8006f28: 2b00 cmp r3, #0 8006f2a: d115 bne.n 8006f58 { return HAL_ERROR; 8006f2c: 2301 movs r3, #1 8006f2e: e0ea b.n 8007106 } } /* CSI is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) 8006f30: 687b ldr r3, [r7, #4] 8006f32: 685b ldr r3, [r3, #4] 8006f34: 2b01 cmp r3, #1 8006f36: d107 bne.n 8006f48 { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 8006f38: 4b30 ldr r3, [pc, #192] ; (8006ffc ) 8006f3a: 681b ldr r3, [r3, #0] 8006f3c: f403 7380 and.w r3, r3, #256 ; 0x100 8006f40: 2b00 cmp r3, #0 8006f42: d109 bne.n 8006f58 { return HAL_ERROR; 8006f44: 2301 movs r3, #1 8006f46: e0de b.n 8007106 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 8006f48: 4b2c ldr r3, [pc, #176] ; (8006ffc ) 8006f4a: 681b ldr r3, [r3, #0] 8006f4c: f003 0304 and.w r3, r3, #4 8006f50: 2b00 cmp r3, #0 8006f52: d101 bne.n 8006f58 { return HAL_ERROR; 8006f54: 2301 movs r3, #1 8006f56: e0d6 b.n 8007106 } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 8006f58: 4b28 ldr r3, [pc, #160] ; (8006ffc ) 8006f5a: 691b ldr r3, [r3, #16] 8006f5c: f023 0207 bic.w r2, r3, #7 8006f60: 687b ldr r3, [r7, #4] 8006f62: 685b ldr r3, [r3, #4] 8006f64: 4925 ldr r1, [pc, #148] ; (8006ffc ) 8006f66: 4313 orrs r3, r2 8006f68: 610b str r3, [r1, #16] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8006f6a: f7fc f93d bl 80031e8 8006f6e: 6178 str r0, [r7, #20] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8006f70: e00a b.n 8006f88 { if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 8006f72: f7fc f939 bl 80031e8 8006f76: 4602 mov r2, r0 8006f78: 697b ldr r3, [r7, #20] 8006f7a: 1ad3 subs r3, r2, r3 8006f7c: f241 3288 movw r2, #5000 ; 0x1388 8006f80: 4293 cmp r3, r2 8006f82: d901 bls.n 8006f88 { return HAL_TIMEOUT; 8006f84: 2303 movs r3, #3 8006f86: e0be b.n 8007106 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8006f88: 4b1c ldr r3, [pc, #112] ; (8006ffc ) 8006f8a: 691b ldr r3, [r3, #16] 8006f8c: f003 0238 and.w r2, r3, #56 ; 0x38 8006f90: 687b ldr r3, [r7, #4] 8006f92: 685b ldr r3, [r3, #4] 8006f94: 00db lsls r3, r3, #3 8006f96: 429a cmp r2, r3 8006f98: d1eb bne.n 8006f72 } /* Decreasing the BUS frequency divider */ /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8006f9a: 687b ldr r3, [r7, #4] 8006f9c: 681b ldr r3, [r3, #0] 8006f9e: f003 0302 and.w r3, r3, #2 8006fa2: 2b00 cmp r3, #0 8006fa4: d010 beq.n 8006fc8 /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); } #else if((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)) 8006fa6: 687b ldr r3, [r7, #4] 8006fa8: 68da ldr r2, [r3, #12] 8006faa: 4b14 ldr r3, [pc, #80] ; (8006ffc ) 8006fac: 699b ldr r3, [r3, #24] 8006fae: f003 030f and.w r3, r3, #15 8006fb2: 429a cmp r2, r3 8006fb4: d208 bcs.n 8006fc8 { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8006fb6: 4b11 ldr r3, [pc, #68] ; (8006ffc ) 8006fb8: 699b ldr r3, [r3, #24] 8006fba: f023 020f bic.w r2, r3, #15 8006fbe: 687b ldr r3, [r7, #4] 8006fc0: 68db ldr r3, [r3, #12] 8006fc2: 490e ldr r1, [pc, #56] ; (8006ffc ) 8006fc4: 4313 orrs r3, r2 8006fc6: 618b str r3, [r1, #24] } #endif } /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < __HAL_FLASH_GET_LATENCY()) 8006fc8: 4b0b ldr r3, [pc, #44] ; (8006ff8 ) 8006fca: 681b ldr r3, [r3, #0] 8006fcc: f003 030f and.w r3, r3, #15 8006fd0: 683a ldr r2, [r7, #0] 8006fd2: 429a cmp r2, r3 8006fd4: d214 bcs.n 8007000 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8006fd6: 4b08 ldr r3, [pc, #32] ; (8006ff8 ) 8006fd8: 681b ldr r3, [r3, #0] 8006fda: f023 020f bic.w r2, r3, #15 8006fde: 4906 ldr r1, [pc, #24] ; (8006ff8 ) 8006fe0: 683b ldr r3, [r7, #0] 8006fe2: 4313 orrs r3, r2 8006fe4: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8006fe6: 4b04 ldr r3, [pc, #16] ; (8006ff8 ) 8006fe8: 681b ldr r3, [r3, #0] 8006fea: f003 030f and.w r3, r3, #15 8006fee: 683a ldr r2, [r7, #0] 8006ff0: 429a cmp r2, r3 8006ff2: d005 beq.n 8007000 { return HAL_ERROR; 8006ff4: 2301 movs r3, #1 8006ff6: e086 b.n 8007106 8006ff8: 52002000 .word 0x52002000 8006ffc: 58024400 .word 0x58024400 } } /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 8007000: 687b ldr r3, [r7, #4] 8007002: 681b ldr r3, [r3, #0] 8007004: f003 0304 and.w r3, r3, #4 8007008: 2b00 cmp r3, #0 800700a: d010 beq.n 800702e { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); } #else if((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)) 800700c: 687b ldr r3, [r7, #4] 800700e: 691a ldr r2, [r3, #16] 8007010: 4b3f ldr r3, [pc, #252] ; (8007110 ) 8007012: 699b ldr r3, [r3, #24] 8007014: f003 0370 and.w r3, r3, #112 ; 0x70 8007018: 429a cmp r2, r3 800701a: d208 bcs.n 800702e { assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider); 800701c: 4b3c ldr r3, [pc, #240] ; (8007110 ) 800701e: 699b ldr r3, [r3, #24] 8007020: f023 0270 bic.w r2, r3, #112 ; 0x70 8007024: 687b ldr r3, [r7, #4] 8007026: 691b ldr r3, [r3, #16] 8007028: 4939 ldr r1, [pc, #228] ; (8007110 ) 800702a: 4313 orrs r3, r2 800702c: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800702e: 687b ldr r3, [r7, #4] 8007030: 681b ldr r3, [r3, #0] 8007032: f003 0308 and.w r3, r3, #8 8007036: 2b00 cmp r3, #0 8007038: d010 beq.n 800705c { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); } #else if((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)) 800703a: 687b ldr r3, [r7, #4] 800703c: 695a ldr r2, [r3, #20] 800703e: 4b34 ldr r3, [pc, #208] ; (8007110 ) 8007040: 69db ldr r3, [r3, #28] 8007042: f003 0370 and.w r3, r3, #112 ; 0x70 8007046: 429a cmp r2, r3 8007048: d208 bcs.n 800705c { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 800704a: 4b31 ldr r3, [pc, #196] ; (8007110 ) 800704c: 69db ldr r3, [r3, #28] 800704e: f023 0270 bic.w r2, r3, #112 ; 0x70 8007052: 687b ldr r3, [r7, #4] 8007054: 695b ldr r3, [r3, #20] 8007056: 492e ldr r1, [pc, #184] ; (8007110 ) 8007058: 4313 orrs r3, r2 800705a: 61cb str r3, [r1, #28] } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800705c: 687b ldr r3, [r7, #4] 800705e: 681b ldr r3, [r3, #0] 8007060: f003 0310 and.w r3, r3, #16 8007064: 2b00 cmp r3, #0 8007066: d010 beq.n 800708a { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); } #else if((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)) 8007068: 687b ldr r3, [r7, #4] 800706a: 699a ldr r2, [r3, #24] 800706c: 4b28 ldr r3, [pc, #160] ; (8007110 ) 800706e: 69db ldr r3, [r3, #28] 8007070: f403 63e0 and.w r3, r3, #1792 ; 0x700 8007074: 429a cmp r2, r3 8007076: d208 bcs.n 800708a { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 8007078: 4b25 ldr r3, [pc, #148] ; (8007110 ) 800707a: 69db ldr r3, [r3, #28] 800707c: f423 62e0 bic.w r2, r3, #1792 ; 0x700 8007080: 687b ldr r3, [r7, #4] 8007082: 699b ldr r3, [r3, #24] 8007084: 4922 ldr r1, [pc, #136] ; (8007110 ) 8007086: 4313 orrs r3, r2 8007088: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 800708a: 687b ldr r3, [r7, #4] 800708c: 681b ldr r3, [r3, #0] 800708e: f003 0320 and.w r3, r3, #32 8007092: 2b00 cmp r3, #0 8007094: d010 beq.n 80070b8 { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) ); } #else if((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)) 8007096: 687b ldr r3, [r7, #4] 8007098: 69da ldr r2, [r3, #28] 800709a: 4b1d ldr r3, [pc, #116] ; (8007110 ) 800709c: 6a1b ldr r3, [r3, #32] 800709e: f003 0370 and.w r3, r3, #112 ; 0x70 80070a2: 429a cmp r2, r3 80070a4: d208 bcs.n 80070b8 { assert_param(IS_RCC_SRDPCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider) ); 80070a6: 4b1a ldr r3, [pc, #104] ; (8007110 ) 80070a8: 6a1b ldr r3, [r3, #32] 80070aa: f023 0270 bic.w r2, r3, #112 ; 0x70 80070ae: 687b ldr r3, [r7, #4] 80070b0: 69db ldr r3, [r3, #28] 80070b2: 4917 ldr r1, [pc, #92] ; (8007110 ) 80070b4: 4313 orrs r3, r2 80070b6: 620b str r3, [r1, #32] /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); #else common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); 80070b8: f000 f834 bl 8007124 80070bc: 4602 mov r2, r0 80070be: 4b14 ldr r3, [pc, #80] ; (8007110 ) 80070c0: 699b ldr r3, [r3, #24] 80070c2: 0a1b lsrs r3, r3, #8 80070c4: f003 030f and.w r3, r3, #15 80070c8: 4912 ldr r1, [pc, #72] ; (8007114 ) 80070ca: 5ccb ldrb r3, [r1, r3] 80070cc: f003 031f and.w r3, r3, #31 80070d0: fa22 f303 lsr.w r3, r2, r3 80070d4: 613b str r3, [r7, #16] #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); #else SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); 80070d6: 4b0e ldr r3, [pc, #56] ; (8007110 ) 80070d8: 699b ldr r3, [r3, #24] 80070da: f003 030f and.w r3, r3, #15 80070de: 4a0d ldr r2, [pc, #52] ; (8007114 ) 80070e0: 5cd3 ldrb r3, [r2, r3] 80070e2: f003 031f and.w r3, r3, #31 80070e6: 693a ldr r2, [r7, #16] 80070e8: fa22 f303 lsr.w r3, r2, r3 80070ec: 4a0a ldr r2, [pc, #40] ; (8007118 ) 80070ee: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 80070f0: 4a0a ldr r2, [pc, #40] ; (800711c ) 80070f2: 693b ldr r3, [r7, #16] 80070f4: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Configure the source of time base considering new system clocks settings*/ halstatus = HAL_InitTick (uwTickPrio); 80070f6: 4b0a ldr r3, [pc, #40] ; (8007120 ) 80070f8: 681b ldr r3, [r3, #0] 80070fa: 4618 mov r0, r3 80070fc: f7fc f82a bl 8003154 8007100: 4603 mov r3, r0 8007102: 73fb strb r3, [r7, #15] return halstatus; 8007104: 7bfb ldrb r3, [r7, #15] } 8007106: 4618 mov r0, r3 8007108: 3718 adds r7, #24 800710a: 46bd mov sp, r7 800710c: bd80 pop {r7, pc} 800710e: bf00 nop 8007110: 58024400 .word 0x58024400 8007114: 0800e64c .word 0x0800e64c 8007118: 20000004 .word 0x20000004 800711c: 20000000 .word 0x20000000 8007120: 20000008 .word 0x20000008 08007124 : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8007124: b480 push {r7} 8007126: b089 sub sp, #36 ; 0x24 8007128: af00 add r7, sp, #0 float_t fracn1, pllvco; uint32_t sysclockfreq; /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 800712a: 4bb3 ldr r3, [pc, #716] ; (80073f8 ) 800712c: 691b ldr r3, [r3, #16] 800712e: f003 0338 and.w r3, r3, #56 ; 0x38 8007132: 2b18 cmp r3, #24 8007134: f200 8155 bhi.w 80073e2 8007138: a201 add r2, pc, #4 ; (adr r2, 8007140 ) 800713a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800713e: bf00 nop 8007140: 080071a5 .word 0x080071a5 8007144: 080073e3 .word 0x080073e3 8007148: 080073e3 .word 0x080073e3 800714c: 080073e3 .word 0x080073e3 8007150: 080073e3 .word 0x080073e3 8007154: 080073e3 .word 0x080073e3 8007158: 080073e3 .word 0x080073e3 800715c: 080073e3 .word 0x080073e3 8007160: 080071cb .word 0x080071cb 8007164: 080073e3 .word 0x080073e3 8007168: 080073e3 .word 0x080073e3 800716c: 080073e3 .word 0x080073e3 8007170: 080073e3 .word 0x080073e3 8007174: 080073e3 .word 0x080073e3 8007178: 080073e3 .word 0x080073e3 800717c: 080073e3 .word 0x080073e3 8007180: 080071d1 .word 0x080071d1 8007184: 080073e3 .word 0x080073e3 8007188: 080073e3 .word 0x080073e3 800718c: 080073e3 .word 0x080073e3 8007190: 080073e3 .word 0x080073e3 8007194: 080073e3 .word 0x080073e3 8007198: 080073e3 .word 0x080073e3 800719c: 080073e3 .word 0x080073e3 80071a0: 080071d7 .word 0x080071d7 { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 80071a4: 4b94 ldr r3, [pc, #592] ; (80073f8 ) 80071a6: 681b ldr r3, [r3, #0] 80071a8: f003 0320 and.w r3, r3, #32 80071ac: 2b00 cmp r3, #0 80071ae: d009 beq.n 80071c4 { sysclockfreq = (uint32_t) (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 80071b0: 4b91 ldr r3, [pc, #580] ; (80073f8 ) 80071b2: 681b ldr r3, [r3, #0] 80071b4: 08db lsrs r3, r3, #3 80071b6: f003 0303 and.w r3, r3, #3 80071ba: 4a90 ldr r2, [pc, #576] ; (80073fc ) 80071bc: fa22 f303 lsr.w r3, r2, r3 80071c0: 61bb str r3, [r7, #24] else { sysclockfreq = (uint32_t) HSI_VALUE; } break; 80071c2: e111 b.n 80073e8 sysclockfreq = (uint32_t) HSI_VALUE; 80071c4: 4b8d ldr r3, [pc, #564] ; (80073fc ) 80071c6: 61bb str r3, [r7, #24] break; 80071c8: e10e b.n 80073e8 case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ sysclockfreq = CSI_VALUE; 80071ca: 4b8d ldr r3, [pc, #564] ; (8007400 ) 80071cc: 61bb str r3, [r7, #24] break; 80071ce: e10b b.n 80073e8 case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; 80071d0: 4b8c ldr r3, [pc, #560] ; (8007404 ) 80071d2: 61bb str r3, [r7, #24] break; 80071d4: e108 b.n 80073e8 case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 80071d6: 4b88 ldr r3, [pc, #544] ; (80073f8 ) 80071d8: 6a9b ldr r3, [r3, #40] ; 0x28 80071da: f003 0303 and.w r3, r3, #3 80071de: 617b str r3, [r7, #20] pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; 80071e0: 4b85 ldr r3, [pc, #532] ; (80073f8 ) 80071e2: 6a9b ldr r3, [r3, #40] ; 0x28 80071e4: 091b lsrs r3, r3, #4 80071e6: f003 033f and.w r3, r3, #63 ; 0x3f 80071ea: 613b str r3, [r7, #16] pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos); 80071ec: 4b82 ldr r3, [pc, #520] ; (80073f8 ) 80071ee: 6adb ldr r3, [r3, #44] ; 0x2c 80071f0: f003 0301 and.w r3, r3, #1 80071f4: 60fb str r3, [r7, #12] fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); 80071f6: 4b80 ldr r3, [pc, #512] ; (80073f8 ) 80071f8: 6b5b ldr r3, [r3, #52] ; 0x34 80071fa: 08db lsrs r3, r3, #3 80071fc: f3c3 030c ubfx r3, r3, #0, #13 8007200: 68fa ldr r2, [r7, #12] 8007202: fb02 f303 mul.w r3, r2, r3 8007206: ee07 3a90 vmov s15, r3 800720a: eef8 7a67 vcvt.f32.u32 s15, s15 800720e: edc7 7a02 vstr s15, [r7, #8] if (pllm != 0U) 8007212: 693b ldr r3, [r7, #16] 8007214: 2b00 cmp r3, #0 8007216: f000 80e1 beq.w 80073dc 800721a: 697b ldr r3, [r7, #20] 800721c: 2b02 cmp r3, #2 800721e: f000 8083 beq.w 8007328 8007222: 697b ldr r3, [r7, #20] 8007224: 2b02 cmp r3, #2 8007226: f200 80a1 bhi.w 800736c 800722a: 697b ldr r3, [r7, #20] 800722c: 2b00 cmp r3, #0 800722e: d003 beq.n 8007238 8007230: 697b ldr r3, [r7, #20] 8007232: 2b01 cmp r3, #1 8007234: d056 beq.n 80072e4 8007236: e099 b.n 800736c { switch (pllsource) { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8007238: 4b6f ldr r3, [pc, #444] ; (80073f8 ) 800723a: 681b ldr r3, [r3, #0] 800723c: f003 0320 and.w r3, r3, #32 8007240: 2b00 cmp r3, #0 8007242: d02d beq.n 80072a0 { hsivalue= (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 8007244: 4b6c ldr r3, [pc, #432] ; (80073f8 ) 8007246: 681b ldr r3, [r3, #0] 8007248: 08db lsrs r3, r3, #3 800724a: f003 0303 and.w r3, r3, #3 800724e: 4a6b ldr r2, [pc, #428] ; (80073fc ) 8007250: fa22 f303 lsr.w r3, r2, r3 8007254: 607b str r3, [r7, #4] pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 8007256: 687b ldr r3, [r7, #4] 8007258: ee07 3a90 vmov s15, r3 800725c: eef8 6a67 vcvt.f32.u32 s13, s15 8007260: 693b ldr r3, [r7, #16] 8007262: ee07 3a90 vmov s15, r3 8007266: eef8 7a67 vcvt.f32.u32 s15, s15 800726a: ee86 7aa7 vdiv.f32 s14, s13, s15 800726e: 4b62 ldr r3, [pc, #392] ; (80073f8 ) 8007270: 6b1b ldr r3, [r3, #48] ; 0x30 8007272: f3c3 0308 ubfx r3, r3, #0, #9 8007276: ee07 3a90 vmov s15, r3 800727a: eef8 6a67 vcvt.f32.u32 s13, s15 800727e: ed97 6a02 vldr s12, [r7, #8] 8007282: eddf 5a61 vldr s11, [pc, #388] ; 8007408 8007286: eec6 7a25 vdiv.f32 s15, s12, s11 800728a: ee76 7aa7 vadd.f32 s15, s13, s15 800728e: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8007292: ee77 7aa6 vadd.f32 s15, s15, s13 8007296: ee67 7a27 vmul.f32 s15, s14, s15 800729a: edc7 7a07 vstr s15, [r7, #28] } else { pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); } break; 800729e: e087 b.n 80073b0 pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 80072a0: 693b ldr r3, [r7, #16] 80072a2: ee07 3a90 vmov s15, r3 80072a6: eef8 7a67 vcvt.f32.u32 s15, s15 80072aa: eddf 6a58 vldr s13, [pc, #352] ; 800740c 80072ae: ee86 7aa7 vdiv.f32 s14, s13, s15 80072b2: 4b51 ldr r3, [pc, #324] ; (80073f8 ) 80072b4: 6b1b ldr r3, [r3, #48] ; 0x30 80072b6: f3c3 0308 ubfx r3, r3, #0, #9 80072ba: ee07 3a90 vmov s15, r3 80072be: eef8 6a67 vcvt.f32.u32 s13, s15 80072c2: ed97 6a02 vldr s12, [r7, #8] 80072c6: eddf 5a50 vldr s11, [pc, #320] ; 8007408 80072ca: eec6 7a25 vdiv.f32 s15, s12, s11 80072ce: ee76 7aa7 vadd.f32 s15, s13, s15 80072d2: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 80072d6: ee77 7aa6 vadd.f32 s15, s15, s13 80072da: ee67 7a27 vmul.f32 s15, s14, s15 80072de: edc7 7a07 vstr s15, [r7, #28] break; 80072e2: e065 b.n 80073b0 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 80072e4: 693b ldr r3, [r7, #16] 80072e6: ee07 3a90 vmov s15, r3 80072ea: eef8 7a67 vcvt.f32.u32 s15, s15 80072ee: eddf 6a48 vldr s13, [pc, #288] ; 8007410 80072f2: ee86 7aa7 vdiv.f32 s14, s13, s15 80072f6: 4b40 ldr r3, [pc, #256] ; (80073f8 ) 80072f8: 6b1b ldr r3, [r3, #48] ; 0x30 80072fa: f3c3 0308 ubfx r3, r3, #0, #9 80072fe: ee07 3a90 vmov s15, r3 8007302: eef8 6a67 vcvt.f32.u32 s13, s15 8007306: ed97 6a02 vldr s12, [r7, #8] 800730a: eddf 5a3f vldr s11, [pc, #252] ; 8007408 800730e: eec6 7a25 vdiv.f32 s15, s12, s11 8007312: ee76 7aa7 vadd.f32 s15, s13, s15 8007316: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 800731a: ee77 7aa6 vadd.f32 s15, s15, s13 800731e: ee67 7a27 vmul.f32 s15, s14, s15 8007322: edc7 7a07 vstr s15, [r7, #28] break; 8007326: e043 b.n 80073b0 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 8007328: 693b ldr r3, [r7, #16] 800732a: ee07 3a90 vmov s15, r3 800732e: eef8 7a67 vcvt.f32.u32 s15, s15 8007332: eddf 6a38 vldr s13, [pc, #224] ; 8007414 8007336: ee86 7aa7 vdiv.f32 s14, s13, s15 800733a: 4b2f ldr r3, [pc, #188] ; (80073f8 ) 800733c: 6b1b ldr r3, [r3, #48] ; 0x30 800733e: f3c3 0308 ubfx r3, r3, #0, #9 8007342: ee07 3a90 vmov s15, r3 8007346: eef8 6a67 vcvt.f32.u32 s13, s15 800734a: ed97 6a02 vldr s12, [r7, #8] 800734e: eddf 5a2e vldr s11, [pc, #184] ; 8007408 8007352: eec6 7a25 vdiv.f32 s15, s12, s11 8007356: ee76 7aa7 vadd.f32 s15, s13, s15 800735a: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 800735e: ee77 7aa6 vadd.f32 s15, s15, s13 8007362: ee67 7a27 vmul.f32 s15, s14, s15 8007366: edc7 7a07 vstr s15, [r7, #28] break; 800736a: e021 b.n 80073b0 default: pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 800736c: 693b ldr r3, [r7, #16] 800736e: ee07 3a90 vmov s15, r3 8007372: eef8 7a67 vcvt.f32.u32 s15, s15 8007376: eddf 6a26 vldr s13, [pc, #152] ; 8007410 800737a: ee86 7aa7 vdiv.f32 s14, s13, s15 800737e: 4b1e ldr r3, [pc, #120] ; (80073f8 ) 8007380: 6b1b ldr r3, [r3, #48] ; 0x30 8007382: f3c3 0308 ubfx r3, r3, #0, #9 8007386: ee07 3a90 vmov s15, r3 800738a: eef8 6a67 vcvt.f32.u32 s13, s15 800738e: ed97 6a02 vldr s12, [r7, #8] 8007392: eddf 5a1d vldr s11, [pc, #116] ; 8007408 8007396: eec6 7a25 vdiv.f32 s15, s12, s11 800739a: ee76 7aa7 vadd.f32 s15, s13, s15 800739e: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 80073a2: ee77 7aa6 vadd.f32 s15, s15, s13 80073a6: ee67 7a27 vmul.f32 s15, s14, s15 80073aa: edc7 7a07 vstr s15, [r7, #28] break; 80073ae: bf00 nop } pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; 80073b0: 4b11 ldr r3, [pc, #68] ; (80073f8 ) 80073b2: 6b1b ldr r3, [r3, #48] ; 0x30 80073b4: 0a5b lsrs r3, r3, #9 80073b6: f003 037f and.w r3, r3, #127 ; 0x7f 80073ba: 3301 adds r3, #1 80073bc: 603b str r3, [r7, #0] sysclockfreq = (uint32_t)(float_t)(pllvco/(float_t)pllp); 80073be: 683b ldr r3, [r7, #0] 80073c0: ee07 3a90 vmov s15, r3 80073c4: eeb8 7a67 vcvt.f32.u32 s14, s15 80073c8: edd7 6a07 vldr s13, [r7, #28] 80073cc: eec6 7a87 vdiv.f32 s15, s13, s14 80073d0: eefc 7ae7 vcvt.u32.f32 s15, s15 80073d4: ee17 3a90 vmov r3, s15 80073d8: 61bb str r3, [r7, #24] } else { sysclockfreq = 0U; } break; 80073da: e005 b.n 80073e8 sysclockfreq = 0U; 80073dc: 2300 movs r3, #0 80073de: 61bb str r3, [r7, #24] break; 80073e0: e002 b.n 80073e8 default: sysclockfreq = CSI_VALUE; 80073e2: 4b07 ldr r3, [pc, #28] ; (8007400 ) 80073e4: 61bb str r3, [r7, #24] break; 80073e6: bf00 nop } return sysclockfreq; 80073e8: 69bb ldr r3, [r7, #24] } 80073ea: 4618 mov r0, r3 80073ec: 3724 adds r7, #36 ; 0x24 80073ee: 46bd mov sp, r7 80073f0: f85d 7b04 ldr.w r7, [sp], #4 80073f4: 4770 bx lr 80073f6: bf00 nop 80073f8: 58024400 .word 0x58024400 80073fc: 03d09000 .word 0x03d09000 8007400: 003d0900 .word 0x003d0900 8007404: 016e3600 .word 0x016e3600 8007408: 46000000 .word 0x46000000 800740c: 4c742400 .word 0x4c742400 8007410: 4a742400 .word 0x4a742400 8007414: 4bb71b00 .word 0x4bb71b00 08007418 : * @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8007418: b580 push {r7, lr} 800741a: b082 sub sp, #8 800741c: af00 add r7, sp, #0 uint32_t common_system_clock; #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); #else common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); 800741e: f7ff fe81 bl 8007124 8007422: 4602 mov r2, r0 8007424: 4b10 ldr r3, [pc, #64] ; (8007468 ) 8007426: 699b ldr r3, [r3, #24] 8007428: 0a1b lsrs r3, r3, #8 800742a: f003 030f and.w r3, r3, #15 800742e: 490f ldr r1, [pc, #60] ; (800746c ) 8007430: 5ccb ldrb r3, [r1, r3] 8007432: f003 031f and.w r3, r3, #31 8007436: fa22 f303 lsr.w r3, r2, r3 800743a: 607b str r3, [r7, #4] #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); #else SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); 800743c: 4b0a ldr r3, [pc, #40] ; (8007468 ) 800743e: 699b ldr r3, [r3, #24] 8007440: f003 030f and.w r3, r3, #15 8007444: 4a09 ldr r2, [pc, #36] ; (800746c ) 8007446: 5cd3 ldrb r3, [r2, r3] 8007448: f003 031f and.w r3, r3, #31 800744c: 687a ldr r2, [r7, #4] 800744e: fa22 f303 lsr.w r3, r2, r3 8007452: 4a07 ldr r2, [pc, #28] ; (8007470 ) 8007454: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 8007456: 4a07 ldr r2, [pc, #28] ; (8007474 ) 8007458: 687b ldr r3, [r7, #4] 800745a: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ return SystemD2Clock; 800745c: 4b04 ldr r3, [pc, #16] ; (8007470 ) 800745e: 681b ldr r3, [r3, #0] } 8007460: 4618 mov r0, r3 8007462: 3708 adds r7, #8 8007464: 46bd mov sp, r7 8007466: bd80 pop {r7, pc} 8007468: 58024400 .word 0x58024400 800746c: 0800e64c .word 0x0800e64c 8007470: 20000004 .word 0x20000004 8007474: 20000000 .word 0x20000000 08007478 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8007478: b580 push {r7, lr} 800747a: af00 add r7, sp, #0 #if defined (RCC_D2CFGR_D2PPRE1) /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)>> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU)); #else /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)>> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU)); 800747c: f7ff ffcc bl 8007418 8007480: 4602 mov r2, r0 8007482: 4b06 ldr r3, [pc, #24] ; (800749c ) 8007484: 69db ldr r3, [r3, #28] 8007486: 091b lsrs r3, r3, #4 8007488: f003 0307 and.w r3, r3, #7 800748c: 4904 ldr r1, [pc, #16] ; (80074a0 ) 800748e: 5ccb ldrb r3, [r1, r3] 8007490: f003 031f and.w r3, r3, #31 8007494: fa22 f303 lsr.w r3, r2, r3 #endif } 8007498: 4618 mov r0, r3 800749a: bd80 pop {r7, pc} 800749c: 58024400 .word 0x58024400 80074a0: 0800e64c .word 0x0800e64c 080074a4 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 80074a4: b580 push {r7, lr} 80074a6: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ #if defined(RCC_D2CFGR_D2PPRE2) return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)>> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU)); #else return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)>> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU)); 80074a8: f7ff ffb6 bl 8007418 80074ac: 4602 mov r2, r0 80074ae: 4b06 ldr r3, [pc, #24] ; (80074c8 ) 80074b0: 69db ldr r3, [r3, #28] 80074b2: 0a1b lsrs r3, r3, #8 80074b4: f003 0307 and.w r3, r3, #7 80074b8: 4904 ldr r1, [pc, #16] ; (80074cc ) 80074ba: 5ccb ldrb r3, [r1, r3] 80074bc: f003 031f and.w r3, r3, #31 80074c0: fa22 f303 lsr.w r3, r2, r3 #endif } 80074c4: 4618 mov r0, r3 80074c6: bd80 pop {r7, pc} 80074c8: 58024400 .word 0x58024400 80074cc: 0800e64c .word 0x0800e64c 080074d0 : * (*) : Available on some STM32H7 lines only. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 80074d0: b580 push {r7, lr} 80074d2: b086 sub sp, #24 80074d4: af00 add r7, sp, #0 80074d6: 6078 str r0, [r7, #4] uint32_t tmpreg; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 80074d8: 2300 movs r3, #0 80074da: 75fb strb r3, [r7, #23] HAL_StatusTypeDef status = HAL_OK; /* Final status */ 80074dc: 2300 movs r3, #0 80074de: 75bb strb r3, [r7, #22] /*---------------------------- SPDIFRX configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 80074e0: 687b ldr r3, [r7, #4] 80074e2: 681b ldr r3, [r3, #0] 80074e4: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 80074e8: 2b00 cmp r3, #0 80074ea: d03f beq.n 800756c { switch(PeriphClkInit->SpdifrxClockSelection) 80074ec: 687b ldr r3, [r7, #4] 80074ee: 6e9b ldr r3, [r3, #104] ; 0x68 80074f0: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000 80074f4: d02a beq.n 800754c 80074f6: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000 80074fa: d824 bhi.n 8007546 80074fc: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 8007500: d018 beq.n 8007534 8007502: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 8007506: d81e bhi.n 8007546 8007508: 2b00 cmp r3, #0 800750a: d003 beq.n 8007514 800750c: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 8007510: d007 beq.n 8007522 8007512: e018 b.n 8007546 { case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/ /* Enable PLL1Q Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8007514: 4ba6 ldr r3, [pc, #664] ; (80077b0 ) 8007516: 6adb ldr r3, [r3, #44] ; 0x2c 8007518: 4aa5 ldr r2, [pc, #660] ; (80077b0 ) 800751a: f443 3300 orr.w r3, r3, #131072 ; 0x20000 800751e: 62d3 str r3, [r2, #44] ; 0x2c /* SPDIFRX clock source configuration done later after clock selection check */ break; 8007520: e015 b.n 800754e case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); 8007522: 687b ldr r3, [r7, #4] 8007524: 3304 adds r3, #4 8007526: 2102 movs r1, #2 8007528: 4618 mov r0, r3 800752a: f001 ff17 bl 800935c 800752e: 4603 mov r3, r0 8007530: 75fb strb r3, [r7, #23] /* SPDIFRX clock source configuration done later after clock selection check */ break; 8007532: e00c b.n 800754e case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 8007534: 687b ldr r3, [r7, #4] 8007536: 3324 adds r3, #36 ; 0x24 8007538: 2102 movs r1, #2 800753a: 4618 mov r0, r3 800753c: f001 ffc0 bl 80094c0 8007540: 4603 mov r3, r0 8007542: 75fb strb r3, [r7, #23] /* SPDIFRX clock source configuration done later after clock selection check */ break; 8007544: e003 b.n 800754e /* Internal OSC clock is used as source of SPDIFRX clock*/ /* SPDIFRX clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8007546: 2301 movs r3, #1 8007548: 75fb strb r3, [r7, #23] break; 800754a: e000 b.n 800754e break; 800754c: bf00 nop } if(ret == HAL_OK) 800754e: 7dfb ldrb r3, [r7, #23] 8007550: 2b00 cmp r3, #0 8007552: d109 bne.n 8007568 { /* Set the source of SPDIFRX clock*/ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); 8007554: 4b96 ldr r3, [pc, #600] ; (80077b0 ) 8007556: 6d1b ldr r3, [r3, #80] ; 0x50 8007558: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 800755c: 687b ldr r3, [r7, #4] 800755e: 6e9b ldr r3, [r3, #104] ; 0x68 8007560: 4993 ldr r1, [pc, #588] ; (80077b0 ) 8007562: 4313 orrs r3, r2 8007564: 650b str r3, [r1, #80] ; 0x50 8007566: e001 b.n 800756c } else { /* set overall return value */ status = ret; 8007568: 7dfb ldrb r3, [r7, #23] 800756a: 75bb strb r3, [r7, #22] } } /*---------------------------- SAI1 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 800756c: 687b ldr r3, [r7, #4] 800756e: 681b ldr r3, [r3, #0] 8007570: f403 7380 and.w r3, r3, #256 ; 0x100 8007574: 2b00 cmp r3, #0 8007576: d03d beq.n 80075f4 { switch(PeriphClkInit->Sai1ClockSelection) 8007578: 687b ldr r3, [r7, #4] 800757a: 6d5b ldr r3, [r3, #84] ; 0x54 800757c: 2b04 cmp r3, #4 800757e: d826 bhi.n 80075ce 8007580: a201 add r2, pc, #4 ; (adr r2, 8007588 ) 8007582: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8007586: bf00 nop 8007588: 0800759d .word 0x0800759d 800758c: 080075ab .word 0x080075ab 8007590: 080075bd .word 0x080075bd 8007594: 080075d5 .word 0x080075d5 8007598: 080075d5 .word 0x080075d5 { case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800759c: 4b84 ldr r3, [pc, #528] ; (80077b0 ) 800759e: 6adb ldr r3, [r3, #44] ; 0x2c 80075a0: 4a83 ldr r2, [pc, #524] ; (80077b0 ) 80075a2: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80075a6: 62d3 str r3, [r2, #44] ; 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 80075a8: e015 b.n 80075d6 case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 80075aa: 687b ldr r3, [r7, #4] 80075ac: 3304 adds r3, #4 80075ae: 2100 movs r1, #0 80075b0: 4618 mov r0, r3 80075b2: f001 fed3 bl 800935c 80075b6: 4603 mov r3, r0 80075b8: 75fb strb r3, [r7, #23] /* SAI1 clock source configuration done later after clock selection check */ break; 80075ba: e00c b.n 80075d6 case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); 80075bc: 687b ldr r3, [r7, #4] 80075be: 3324 adds r3, #36 ; 0x24 80075c0: 2100 movs r1, #0 80075c2: 4618 mov r0, r3 80075c4: f001 ff7c bl 80094c0 80075c8: 4603 mov r3, r0 80075ca: 75fb strb r3, [r7, #23] /* SAI1 clock source configuration done later after clock selection check */ break; 80075cc: e003 b.n 80075d6 /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */ /* SAI1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80075ce: 2301 movs r3, #1 80075d0: 75fb strb r3, [r7, #23] break; 80075d2: e000 b.n 80075d6 break; 80075d4: bf00 nop } if(ret == HAL_OK) 80075d6: 7dfb ldrb r3, [r7, #23] 80075d8: 2b00 cmp r3, #0 80075da: d109 bne.n 80075f0 { /* Set the source of SAI1 clock*/ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 80075dc: 4b74 ldr r3, [pc, #464] ; (80077b0 ) 80075de: 6d1b ldr r3, [r3, #80] ; 0x50 80075e0: f023 0207 bic.w r2, r3, #7 80075e4: 687b ldr r3, [r7, #4] 80075e6: 6d5b ldr r3, [r3, #84] ; 0x54 80075e8: 4971 ldr r1, [pc, #452] ; (80077b0 ) 80075ea: 4313 orrs r3, r2 80075ec: 650b str r3, [r1, #80] ; 0x50 80075ee: e001 b.n 80075f4 } else { /* set overall return value */ status = ret; 80075f0: 7dfb ldrb r3, [r7, #23] 80075f2: 75bb strb r3, [r7, #22] #endif /* SAI3 */ #if defined(RCC_CDCCIP1R_SAI2ASEL) /*---------------------------- SAI2A configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2A) == RCC_PERIPHCLK_SAI2A) 80075f4: 687b ldr r3, [r7, #4] 80075f6: 681b ldr r3, [r3, #0] 80075f8: f403 7300 and.w r3, r3, #512 ; 0x200 80075fc: 2b00 cmp r3, #0 80075fe: d04a beq.n 8007696 { switch(PeriphClkInit->Sai2AClockSelection) 8007600: 687b ldr r3, [r7, #4] 8007602: 6d9b ldr r3, [r3, #88] ; 0x58 8007604: f5b3 7fa0 cmp.w r3, #320 ; 0x140 8007608: d031 beq.n 800766e 800760a: f5b3 7fa0 cmp.w r3, #320 ; 0x140 800760e: d82b bhi.n 8007668 8007610: f5b3 7f80 cmp.w r3, #256 ; 0x100 8007614: d02d beq.n 8007672 8007616: f5b3 7f80 cmp.w r3, #256 ; 0x100 800761a: d825 bhi.n 8007668 800761c: 2bc0 cmp r3, #192 ; 0xc0 800761e: d02a beq.n 8007676 8007620: 2bc0 cmp r3, #192 ; 0xc0 8007622: d821 bhi.n 8007668 8007624: 2b80 cmp r3, #128 ; 0x80 8007626: d016 beq.n 8007656 8007628: 2b80 cmp r3, #128 ; 0x80 800762a: d81d bhi.n 8007668 800762c: 2b00 cmp r3, #0 800762e: d002 beq.n 8007636 8007630: 2b40 cmp r3, #64 ; 0x40 8007632: d007 beq.n 8007644 8007634: e018 b.n 8007668 { case RCC_SAI2ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2A */ /* Enable SAI2A Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8007636: 4b5e ldr r3, [pc, #376] ; (80077b0 ) 8007638: 6adb ldr r3, [r3, #44] ; 0x2c 800763a: 4a5d ldr r2, [pc, #372] ; (80077b0 ) 800763c: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8007640: 62d3 str r3, [r2, #44] ; 0x2c /* SAI2A clock source configuration done later after clock selection check */ break; 8007642: e019 b.n 8007678 case RCC_SAI2ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2A */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 8007644: 687b ldr r3, [r7, #4] 8007646: 3304 adds r3, #4 8007648: 2100 movs r1, #0 800764a: 4618 mov r0, r3 800764c: f001 fe86 bl 800935c 8007650: 4603 mov r3, r0 8007652: 75fb strb r3, [r7, #23] /* SAI2A clock source configuration done later after clock selection check */ break; 8007654: e010 b.n 8007678 case RCC_SAI2ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2A */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); 8007656: 687b ldr r3, [r7, #4] 8007658: 3324 adds r3, #36 ; 0x24 800765a: 2100 movs r1, #0 800765c: 4618 mov r0, r3 800765e: f001 ff2f bl 80094c0 8007662: 4603 mov r3, r0 8007664: 75fb strb r3, [r7, #23] /* SAI2A clock source configuration done later after clock selection check */ break; 8007666: e007 b.n 8007678 /* SPDIF clock is used as source of SAI2A clock */ /* SAI2A clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8007668: 2301 movs r3, #1 800766a: 75fb strb r3, [r7, #23] break; 800766c: e004 b.n 8007678 break; 800766e: bf00 nop 8007670: e002 b.n 8007678 break; 8007672: bf00 nop 8007674: e000 b.n 8007678 break; 8007676: bf00 nop } if(ret == HAL_OK) 8007678: 7dfb ldrb r3, [r7, #23] 800767a: 2b00 cmp r3, #0 800767c: d109 bne.n 8007692 { /* Set the source of SAI2A clock*/ __HAL_RCC_SAI2A_CONFIG(PeriphClkInit->Sai2AClockSelection); 800767e: 4b4c ldr r3, [pc, #304] ; (80077b0 ) 8007680: 6d1b ldr r3, [r3, #80] ; 0x50 8007682: f423 72e0 bic.w r2, r3, #448 ; 0x1c0 8007686: 687b ldr r3, [r7, #4] 8007688: 6d9b ldr r3, [r3, #88] ; 0x58 800768a: 4949 ldr r1, [pc, #292] ; (80077b0 ) 800768c: 4313 orrs r3, r2 800768e: 650b str r3, [r1, #80] ; 0x50 8007690: e001 b.n 8007696 } else { /* set overall return value */ status = ret; 8007692: 7dfb ldrb r3, [r7, #23] 8007694: 75bb strb r3, [r7, #22] #endif /*SAI2A*/ #if defined(RCC_CDCCIP1R_SAI2BSEL) /*---------------------------- SAI2B configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2B) == RCC_PERIPHCLK_SAI2B) 8007696: 687b ldr r3, [r7, #4] 8007698: 681b ldr r3, [r3, #0] 800769a: f403 6380 and.w r3, r3, #1024 ; 0x400 800769e: 2b00 cmp r3, #0 80076a0: d04f beq.n 8007742 { switch(PeriphClkInit->Sai2BClockSelection) 80076a2: 687b ldr r3, [r7, #4] 80076a4: 6ddb ldr r3, [r3, #92] ; 0x5c 80076a6: f5b3 6f20 cmp.w r3, #2560 ; 0xa00 80076aa: d036 beq.n 800771a 80076ac: f5b3 6f20 cmp.w r3, #2560 ; 0xa00 80076b0: d830 bhi.n 8007714 80076b2: f5b3 6f00 cmp.w r3, #2048 ; 0x800 80076b6: d032 beq.n 800771e 80076b8: f5b3 6f00 cmp.w r3, #2048 ; 0x800 80076bc: d82a bhi.n 8007714 80076be: f5b3 6fc0 cmp.w r3, #1536 ; 0x600 80076c2: d02e beq.n 8007722 80076c4: f5b3 6fc0 cmp.w r3, #1536 ; 0x600 80076c8: d824 bhi.n 8007714 80076ca: f5b3 6f80 cmp.w r3, #1024 ; 0x400 80076ce: d018 beq.n 8007702 80076d0: f5b3 6f80 cmp.w r3, #1024 ; 0x400 80076d4: d81e bhi.n 8007714 80076d6: 2b00 cmp r3, #0 80076d8: d003 beq.n 80076e2 80076da: f5b3 7f00 cmp.w r3, #512 ; 0x200 80076de: d007 beq.n 80076f0 80076e0: e018 b.n 8007714 { case RCC_SAI2BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2B */ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80076e2: 4b33 ldr r3, [pc, #204] ; (80077b0 ) 80076e4: 6adb ldr r3, [r3, #44] ; 0x2c 80076e6: 4a32 ldr r2, [pc, #200] ; (80077b0 ) 80076e8: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80076ec: 62d3 str r3, [r2, #44] ; 0x2c /* SAI2B clock source configuration done later after clock selection check */ break; 80076ee: e019 b.n 8007724 case RCC_SAI2BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2B */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 80076f0: 687b ldr r3, [r7, #4] 80076f2: 3304 adds r3, #4 80076f4: 2100 movs r1, #0 80076f6: 4618 mov r0, r3 80076f8: f001 fe30 bl 800935c 80076fc: 4603 mov r3, r0 80076fe: 75fb strb r3, [r7, #23] /* SAI2B clock source configuration done later after clock selection check */ break; 8007700: e010 b.n 8007724 case RCC_SAI2BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2B */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); 8007702: 687b ldr r3, [r7, #4] 8007704: 3324 adds r3, #36 ; 0x24 8007706: 2100 movs r1, #0 8007708: 4618 mov r0, r3 800770a: f001 fed9 bl 80094c0 800770e: 4603 mov r3, r0 8007710: 75fb strb r3, [r7, #23] /* SAI2B clock source configuration done later after clock selection check */ break; 8007712: e007 b.n 8007724 /* SPDIF clock is used as source of SAI2B clock */ /* SAI2B clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8007714: 2301 movs r3, #1 8007716: 75fb strb r3, [r7, #23] break; 8007718: e004 b.n 8007724 break; 800771a: bf00 nop 800771c: e002 b.n 8007724 break; 800771e: bf00 nop 8007720: e000 b.n 8007724 break; 8007722: bf00 nop } if(ret == HAL_OK) 8007724: 7dfb ldrb r3, [r7, #23] 8007726: 2b00 cmp r3, #0 8007728: d109 bne.n 800773e { /* Set the source of SAI2B clock*/ __HAL_RCC_SAI2B_CONFIG(PeriphClkInit->Sai2BClockSelection); 800772a: 4b21 ldr r3, [pc, #132] ; (80077b0 ) 800772c: 6d1b ldr r3, [r3, #80] ; 0x50 800772e: f423 6260 bic.w r2, r3, #3584 ; 0xe00 8007732: 687b ldr r3, [r7, #4] 8007734: 6ddb ldr r3, [r3, #92] ; 0x5c 8007736: 491e ldr r1, [pc, #120] ; (80077b0 ) 8007738: 4313 orrs r3, r2 800773a: 650b str r3, [r1, #80] ; 0x50 800773c: e001 b.n 8007742 } else { /* set overall return value */ status = ret; 800773e: 7dfb ldrb r3, [r7, #23] 8007740: 75bb strb r3, [r7, #22] } #endif /*QUADSPI*/ #if defined(OCTOSPI1) || defined(OCTOSPI2) /*---------------------------- OCTOSPI configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) 8007742: 687b ldr r3, [r7, #4] 8007744: 681b ldr r3, [r3, #0] 8007746: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 800774a: 2b00 cmp r3, #0 800774c: d034 beq.n 80077b8 { switch(PeriphClkInit->OspiClockSelection) 800774e: 687b ldr r3, [r7, #4] 8007750: 6c9b ldr r3, [r3, #72] ; 0x48 8007752: 2b30 cmp r3, #48 ; 0x30 8007754: d01c beq.n 8007790 8007756: 2b30 cmp r3, #48 ; 0x30 8007758: d817 bhi.n 800778a 800775a: 2b20 cmp r3, #32 800775c: d00c beq.n 8007778 800775e: 2b20 cmp r3, #32 8007760: d813 bhi.n 800778a 8007762: 2b00 cmp r3, #0 8007764: d016 beq.n 8007794 8007766: 2b10 cmp r3, #16 8007768: d10f bne.n 800778a { case RCC_OSPICLKSOURCE_PLL: /* PLL is used as clock source for OSPI*/ /* Enable OSPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800776a: 4b11 ldr r3, [pc, #68] ; (80077b0 ) 800776c: 6adb ldr r3, [r3, #44] ; 0x2c 800776e: 4a10 ldr r2, [pc, #64] ; (80077b0 ) 8007770: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8007774: 62d3 str r3, [r2, #44] ; 0x2c /* OSPI clock source configuration done later after clock selection check */ break; 8007776: e00e b.n 8007796 case RCC_OSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for OSPI*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); 8007778: 687b ldr r3, [r7, #4] 800777a: 3304 adds r3, #4 800777c: 2102 movs r1, #2 800777e: 4618 mov r0, r3 8007780: f001 fdec bl 800935c 8007784: 4603 mov r3, r0 8007786: 75fb strb r3, [r7, #23] /* OSPI clock source configuration done later after clock selection check */ break; 8007788: e005 b.n 8007796 case RCC_OSPICLKSOURCE_HCLK: /* HCLK clock selected as OSPI kernel peripheral clock */ break; default: ret = HAL_ERROR; 800778a: 2301 movs r3, #1 800778c: 75fb strb r3, [r7, #23] break; 800778e: e002 b.n 8007796 break; 8007790: bf00 nop 8007792: e000 b.n 8007796 break; 8007794: bf00 nop } if(ret == HAL_OK) 8007796: 7dfb ldrb r3, [r7, #23] 8007798: 2b00 cmp r3, #0 800779a: d10b bne.n 80077b4 { /* Set the source of OSPI clock*/ __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection); 800779c: 4b04 ldr r3, [pc, #16] ; (80077b0 ) 800779e: 6cdb ldr r3, [r3, #76] ; 0x4c 80077a0: f023 0230 bic.w r2, r3, #48 ; 0x30 80077a4: 687b ldr r3, [r7, #4] 80077a6: 6c9b ldr r3, [r3, #72] ; 0x48 80077a8: 4901 ldr r1, [pc, #4] ; (80077b0 ) 80077aa: 4313 orrs r3, r2 80077ac: 64cb str r3, [r1, #76] ; 0x4c 80077ae: e003 b.n 80077b8 80077b0: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 80077b4: 7dfb ldrb r3, [r7, #23] 80077b6: 75bb strb r3, [r7, #22] } } #endif /*OCTOSPI*/ /*---------------------------- SPI1/2/3 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) 80077b8: 687b ldr r3, [r7, #4] 80077ba: 681b ldr r3, [r3, #0] 80077bc: f403 5380 and.w r3, r3, #4096 ; 0x1000 80077c0: 2b00 cmp r3, #0 80077c2: d047 beq.n 8007854 { switch(PeriphClkInit->Spi123ClockSelection) 80077c4: 687b ldr r3, [r7, #4] 80077c6: 6e1b ldr r3, [r3, #96] ; 0x60 80077c8: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 80077cc: d030 beq.n 8007830 80077ce: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 80077d2: d82a bhi.n 800782a 80077d4: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 80077d8: d02c beq.n 8007834 80077da: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 80077de: d824 bhi.n 800782a 80077e0: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 80077e4: d018 beq.n 8007818 80077e6: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 80077ea: d81e bhi.n 800782a 80077ec: 2b00 cmp r3, #0 80077ee: d003 beq.n 80077f8 80077f0: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 80077f4: d007 beq.n 8007806 80077f6: e018 b.n 800782a { case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */ /* Enable SPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80077f8: 4bb0 ldr r3, [pc, #704] ; (8007abc ) 80077fa: 6adb ldr r3, [r3, #44] ; 0x2c 80077fc: 4aaf ldr r2, [pc, #700] ; (8007abc ) 80077fe: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8007802: 62d3 str r3, [r2, #44] ; 0x2c /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 8007804: e017 b.n 8007836 case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 8007806: 687b ldr r3, [r7, #4] 8007808: 3304 adds r3, #4 800780a: 2100 movs r1, #0 800780c: 4618 mov r0, r3 800780e: f001 fda5 bl 800935c 8007812: 4603 mov r3, r0 8007814: 75fb strb r3, [r7, #23] /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 8007816: e00e b.n 8007836 case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); 8007818: 687b ldr r3, [r7, #4] 800781a: 3324 adds r3, #36 ; 0x24 800781c: 2100 movs r1, #0 800781e: 4618 mov r0, r3 8007820: f001 fe4e bl 80094c0 8007824: 4603 mov r3, r0 8007826: 75fb strb r3, [r7, #23] /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 8007828: e005 b.n 8007836 /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */ /* SPI1/2/3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800782a: 2301 movs r3, #1 800782c: 75fb strb r3, [r7, #23] break; 800782e: e002 b.n 8007836 break; 8007830: bf00 nop 8007832: e000 b.n 8007836 break; 8007834: bf00 nop } if(ret == HAL_OK) 8007836: 7dfb ldrb r3, [r7, #23] 8007838: 2b00 cmp r3, #0 800783a: d109 bne.n 8007850 { /* Set the source of SPI1/2/3 clock*/ __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection); 800783c: 4b9f ldr r3, [pc, #636] ; (8007abc ) 800783e: 6d1b ldr r3, [r3, #80] ; 0x50 8007840: f423 42e0 bic.w r2, r3, #28672 ; 0x7000 8007844: 687b ldr r3, [r7, #4] 8007846: 6e1b ldr r3, [r3, #96] ; 0x60 8007848: 499c ldr r1, [pc, #624] ; (8007abc ) 800784a: 4313 orrs r3, r2 800784c: 650b str r3, [r1, #80] ; 0x50 800784e: e001 b.n 8007854 } else { /* set overall return value */ status = ret; 8007850: 7dfb ldrb r3, [r7, #23] 8007852: 75bb strb r3, [r7, #22] } } /*---------------------------- SPI4/5 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) 8007854: 687b ldr r3, [r7, #4] 8007856: 681b ldr r3, [r3, #0] 8007858: f403 5300 and.w r3, r3, #8192 ; 0x2000 800785c: 2b00 cmp r3, #0 800785e: d049 beq.n 80078f4 { switch(PeriphClkInit->Spi45ClockSelection) 8007860: 687b ldr r3, [r7, #4] 8007862: 6e5b ldr r3, [r3, #100] ; 0x64 8007864: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8007868: d02e beq.n 80078c8 800786a: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 800786e: d828 bhi.n 80078c2 8007870: f5b3 2f80 cmp.w r3, #262144 ; 0x40000 8007874: d02a beq.n 80078cc 8007876: f5b3 2f80 cmp.w r3, #262144 ; 0x40000 800787a: d822 bhi.n 80078c2 800787c: f5b3 3f40 cmp.w r3, #196608 ; 0x30000 8007880: d026 beq.n 80078d0 8007882: f5b3 3f40 cmp.w r3, #196608 ; 0x30000 8007886: d81c bhi.n 80078c2 8007888: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 800788c: d010 beq.n 80078b0 800788e: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 8007892: d816 bhi.n 80078c2 8007894: 2b00 cmp r3, #0 8007896: d01d beq.n 80078d4 8007898: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 800789c: d111 bne.n 80078c2 /* SPI4/5 clock source configuration done later after clock selection check */ break; case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 800789e: 687b ldr r3, [r7, #4] 80078a0: 3304 adds r3, #4 80078a2: 2101 movs r1, #1 80078a4: 4618 mov r0, r3 80078a6: f001 fd59 bl 800935c 80078aa: 4603 mov r3, r0 80078ac: 75fb strb r3, [r7, #23] /* SPI4/5 clock source configuration done later after clock selection check */ break; 80078ae: e012 b.n 80078d6 case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 80078b0: 687b ldr r3, [r7, #4] 80078b2: 3324 adds r3, #36 ; 0x24 80078b4: 2101 movs r1, #1 80078b6: 4618 mov r0, r3 80078b8: f001 fe02 bl 80094c0 80078bc: 4603 mov r3, r0 80078be: 75fb strb r3, [r7, #23] /* SPI4/5 clock source configuration done later after clock selection check */ break; 80078c0: e009 b.n 80078d6 /* HSE, oscillator is used as source of SPI4/5 clock */ /* SPI4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80078c2: 2301 movs r3, #1 80078c4: 75fb strb r3, [r7, #23] break; 80078c6: e006 b.n 80078d6 break; 80078c8: bf00 nop 80078ca: e004 b.n 80078d6 break; 80078cc: bf00 nop 80078ce: e002 b.n 80078d6 break; 80078d0: bf00 nop 80078d2: e000 b.n 80078d6 break; 80078d4: bf00 nop } if(ret == HAL_OK) 80078d6: 7dfb ldrb r3, [r7, #23] 80078d8: 2b00 cmp r3, #0 80078da: d109 bne.n 80078f0 { /* Set the source of SPI4/5 clock*/ __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection); 80078dc: 4b77 ldr r3, [pc, #476] ; (8007abc ) 80078de: 6d1b ldr r3, [r3, #80] ; 0x50 80078e0: f423 22e0 bic.w r2, r3, #458752 ; 0x70000 80078e4: 687b ldr r3, [r7, #4] 80078e6: 6e5b ldr r3, [r3, #100] ; 0x64 80078e8: 4974 ldr r1, [pc, #464] ; (8007abc ) 80078ea: 4313 orrs r3, r2 80078ec: 650b str r3, [r1, #80] ; 0x50 80078ee: e001 b.n 80078f4 } else { /* set overall return value */ status = ret; 80078f0: 7dfb ldrb r3, [r7, #23] 80078f2: 75bb strb r3, [r7, #22] } } /*---------------------------- SPI6 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) 80078f4: 687b ldr r3, [r7, #4] 80078f6: 681b ldr r3, [r3, #0] 80078f8: f403 4380 and.w r3, r3, #16384 ; 0x4000 80078fc: 2b00 cmp r3, #0 80078fe: d053 beq.n 80079a8 { switch(PeriphClkInit->Spi6ClockSelection) 8007900: 687b ldr r3, [r7, #4] 8007902: f8d3 30ac ldr.w r3, [r3, #172] ; 0xac 8007906: f1b3 4fc0 cmp.w r3, #1610612736 ; 0x60000000 800790a: d034 beq.n 8007976 800790c: f1b3 4fc0 cmp.w r3, #1610612736 ; 0x60000000 8007910: d82e bhi.n 8007970 8007912: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 8007916: d030 beq.n 800797a 8007918: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 800791c: d828 bhi.n 8007970 800791e: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8007922: d02c beq.n 800797e 8007924: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8007928: d822 bhi.n 8007970 800792a: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 800792e: d028 beq.n 8007982 8007930: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 8007934: d81c bhi.n 8007970 8007936: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 800793a: d010 beq.n 800795e 800793c: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8007940: d816 bhi.n 8007970 8007942: 2b00 cmp r3, #0 8007944: d01f beq.n 8007986 8007946: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 800794a: d111 bne.n 8007970 /* SPI6 clock source configuration done later after clock selection check */ break; case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 800794c: 687b ldr r3, [r7, #4] 800794e: 3304 adds r3, #4 8007950: 2101 movs r1, #1 8007952: 4618 mov r0, r3 8007954: f001 fd02 bl 800935c 8007958: 4603 mov r3, r0 800795a: 75fb strb r3, [r7, #23] /* SPI6 clock source configuration done later after clock selection check */ break; 800795c: e014 b.n 8007988 case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 800795e: 687b ldr r3, [r7, #4] 8007960: 3324 adds r3, #36 ; 0x24 8007962: 2101 movs r1, #1 8007964: 4618 mov r0, r3 8007966: f001 fdab bl 80094c0 800796a: 4603 mov r3, r0 800796c: 75fb strb r3, [r7, #23] /* SPI6 clock source configuration done later after clock selection check */ break; 800796e: e00b b.n 8007988 /* SPI6 clock source configuration done later after clock selection check */ break; #endif default: ret = HAL_ERROR; 8007970: 2301 movs r3, #1 8007972: 75fb strb r3, [r7, #23] break; 8007974: e008 b.n 8007988 break; 8007976: bf00 nop 8007978: e006 b.n 8007988 break; 800797a: bf00 nop 800797c: e004 b.n 8007988 break; 800797e: bf00 nop 8007980: e002 b.n 8007988 break; 8007982: bf00 nop 8007984: e000 b.n 8007988 break; 8007986: bf00 nop } if(ret == HAL_OK) 8007988: 7dfb ldrb r3, [r7, #23] 800798a: 2b00 cmp r3, #0 800798c: d10a bne.n 80079a4 { /* Set the source of SPI6 clock*/ __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection); 800798e: 4b4b ldr r3, [pc, #300] ; (8007abc ) 8007990: 6d9b ldr r3, [r3, #88] ; 0x58 8007992: f023 42e0 bic.w r2, r3, #1879048192 ; 0x70000000 8007996: 687b ldr r3, [r7, #4] 8007998: f8d3 30ac ldr.w r3, [r3, #172] ; 0xac 800799c: 4947 ldr r1, [pc, #284] ; (8007abc ) 800799e: 4313 orrs r3, r2 80079a0: 658b str r3, [r1, #88] ; 0x58 80079a2: e001 b.n 80079a8 } else { /* set overall return value */ status = ret; 80079a4: 7dfb ldrb r3, [r7, #23] 80079a6: 75bb strb r3, [r7, #22] } #endif /*DSI*/ #if defined(FDCAN1) || defined(FDCAN2) /*---------------------------- FDCAN configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) 80079a8: 687b ldr r3, [r7, #4] 80079aa: 681b ldr r3, [r3, #0] 80079ac: f403 4300 and.w r3, r3, #32768 ; 0x8000 80079b0: 2b00 cmp r3, #0 80079b2: d02f beq.n 8007a14 { switch(PeriphClkInit->FdcanClockSelection) 80079b4: 687b ldr r3, [r7, #4] 80079b6: 6f5b ldr r3, [r3, #116] ; 0x74 80079b8: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 80079bc: d00e beq.n 80079dc 80079be: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 80079c2: d814 bhi.n 80079ee 80079c4: 2b00 cmp r3, #0 80079c6: d015 beq.n 80079f4 80079c8: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 80079cc: d10f bne.n 80079ee { case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/ /* Enable FDCAN Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80079ce: 4b3b ldr r3, [pc, #236] ; (8007abc ) 80079d0: 6adb ldr r3, [r3, #44] ; 0x2c 80079d2: 4a3a ldr r2, [pc, #232] ; (8007abc ) 80079d4: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80079d8: 62d3 str r3, [r2, #44] ; 0x2c /* FDCAN clock source configuration done later after clock selection check */ break; 80079da: e00c b.n 80079f6 case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 80079dc: 687b ldr r3, [r7, #4] 80079de: 3304 adds r3, #4 80079e0: 2101 movs r1, #1 80079e2: 4618 mov r0, r3 80079e4: f001 fcba bl 800935c 80079e8: 4603 mov r3, r0 80079ea: 75fb strb r3, [r7, #23] /* FDCAN clock source configuration done later after clock selection check */ break; 80079ec: e003 b.n 80079f6 /* HSE is used as clock source for FDCAN*/ /* FDCAN clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80079ee: 2301 movs r3, #1 80079f0: 75fb strb r3, [r7, #23] break; 80079f2: e000 b.n 80079f6 break; 80079f4: bf00 nop } if(ret == HAL_OK) 80079f6: 7dfb ldrb r3, [r7, #23] 80079f8: 2b00 cmp r3, #0 80079fa: d109 bne.n 8007a10 { /* Set the source of FDCAN clock*/ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); 80079fc: 4b2f ldr r3, [pc, #188] ; (8007abc ) 80079fe: 6d1b ldr r3, [r3, #80] ; 0x50 8007a00: f023 5240 bic.w r2, r3, #805306368 ; 0x30000000 8007a04: 687b ldr r3, [r7, #4] 8007a06: 6f5b ldr r3, [r3, #116] ; 0x74 8007a08: 492c ldr r1, [pc, #176] ; (8007abc ) 8007a0a: 4313 orrs r3, r2 8007a0c: 650b str r3, [r1, #80] ; 0x50 8007a0e: e001 b.n 8007a14 } else { /* set overall return value */ status = ret; 8007a10: 7dfb ldrb r3, [r7, #23] 8007a12: 75bb strb r3, [r7, #22] } } #endif /*FDCAN1 || FDCAN2*/ /*---------------------------- FMC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) 8007a14: 687b ldr r3, [r7, #4] 8007a16: 681b ldr r3, [r3, #0] 8007a18: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 8007a1c: 2b00 cmp r3, #0 8007a1e: d032 beq.n 8007a86 { switch(PeriphClkInit->FmcClockSelection) 8007a20: 687b ldr r3, [r7, #4] 8007a22: 6c5b ldr r3, [r3, #68] ; 0x44 8007a24: 2b03 cmp r3, #3 8007a26: d81b bhi.n 8007a60 8007a28: a201 add r2, pc, #4 ; (adr r2, 8007a30 ) 8007a2a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8007a2e: bf00 nop 8007a30: 08007a67 .word 0x08007a67 8007a34: 08007a41 .word 0x08007a41 8007a38: 08007a4f .word 0x08007a4f 8007a3c: 08007a67 .word 0x08007a67 { case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/ /* Enable FMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8007a40: 4b1e ldr r3, [pc, #120] ; (8007abc ) 8007a42: 6adb ldr r3, [r3, #44] ; 0x2c 8007a44: 4a1d ldr r2, [pc, #116] ; (8007abc ) 8007a46: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8007a4a: 62d3 str r3, [r2, #44] ; 0x2c /* FMC clock source configuration done later after clock selection check */ break; 8007a4c: e00c b.n 8007a68 case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); 8007a4e: 687b ldr r3, [r7, #4] 8007a50: 3304 adds r3, #4 8007a52: 2102 movs r1, #2 8007a54: 4618 mov r0, r3 8007a56: f001 fc81 bl 800935c 8007a5a: 4603 mov r3, r0 8007a5c: 75fb strb r3, [r7, #23] /* FMC clock source configuration done later after clock selection check */ break; 8007a5e: e003 b.n 8007a68 case RCC_FMCCLKSOURCE_HCLK: /* D1/CD HCLK clock selected as FMC kernel peripheral clock */ break; default: ret = HAL_ERROR; 8007a60: 2301 movs r3, #1 8007a62: 75fb strb r3, [r7, #23] break; 8007a64: e000 b.n 8007a68 break; 8007a66: bf00 nop } if(ret == HAL_OK) 8007a68: 7dfb ldrb r3, [r7, #23] 8007a6a: 2b00 cmp r3, #0 8007a6c: d109 bne.n 8007a82 { /* Set the source of FMC clock*/ __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection); 8007a6e: 4b13 ldr r3, [pc, #76] ; (8007abc ) 8007a70: 6cdb ldr r3, [r3, #76] ; 0x4c 8007a72: f023 0203 bic.w r2, r3, #3 8007a76: 687b ldr r3, [r7, #4] 8007a78: 6c5b ldr r3, [r3, #68] ; 0x44 8007a7a: 4910 ldr r1, [pc, #64] ; (8007abc ) 8007a7c: 4313 orrs r3, r2 8007a7e: 64cb str r3, [r1, #76] ; 0x4c 8007a80: e001 b.n 8007a86 } else { /* set overall return value */ status = ret; 8007a82: 7dfb ldrb r3, [r7, #23] 8007a84: 75bb strb r3, [r7, #22] } } /*---------------------------- RTC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 8007a86: 687b ldr r3, [r7, #4] 8007a88: 681b ldr r3, [r3, #0] 8007a8a: f403 0380 and.w r3, r3, #4194304 ; 0x400000 8007a8e: 2b00 cmp r3, #0 8007a90: f000 808a beq.w 8007ba8 { /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 8007a94: 4b0a ldr r3, [pc, #40] ; (8007ac0 ) 8007a96: 681b ldr r3, [r3, #0] 8007a98: 4a09 ldr r2, [pc, #36] ; (8007ac0 ) 8007a9a: f443 7380 orr.w r3, r3, #256 ; 0x100 8007a9e: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8007aa0: f7fb fba2 bl 80031e8 8007aa4: 6138 str r0, [r7, #16] while((PWR->CR1 & PWR_CR1_DBP) == 0U) 8007aa6: e00d b.n 8007ac4 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8007aa8: f7fb fb9e bl 80031e8 8007aac: 4602 mov r2, r0 8007aae: 693b ldr r3, [r7, #16] 8007ab0: 1ad3 subs r3, r2, r3 8007ab2: 2b64 cmp r3, #100 ; 0x64 8007ab4: d906 bls.n 8007ac4 { ret = HAL_TIMEOUT; 8007ab6: 2303 movs r3, #3 8007ab8: 75fb strb r3, [r7, #23] break; 8007aba: e009 b.n 8007ad0 8007abc: 58024400 .word 0x58024400 8007ac0: 58024800 .word 0x58024800 while((PWR->CR1 & PWR_CR1_DBP) == 0U) 8007ac4: 4bba ldr r3, [pc, #744] ; (8007db0 ) 8007ac6: 681b ldr r3, [r3, #0] 8007ac8: f403 7380 and.w r3, r3, #256 ; 0x100 8007acc: 2b00 cmp r3, #0 8007ace: d0eb beq.n 8007aa8 } } if(ret == HAL_OK) 8007ad0: 7dfb ldrb r3, [r7, #23] 8007ad2: 2b00 cmp r3, #0 8007ad4: d166 bne.n 8007ba4 { /* Reset the Backup domain only if the RTC Clock source selection is modified */ if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) 8007ad6: 4bb7 ldr r3, [pc, #732] ; (8007db4 ) 8007ad8: 6f1a ldr r2, [r3, #112] ; 0x70 8007ada: 687b ldr r3, [r7, #4] 8007adc: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 8007ae0: 4053 eors r3, r2 8007ae2: f403 7340 and.w r3, r3, #768 ; 0x300 8007ae6: 2b00 cmp r3, #0 8007ae8: d013 beq.n 8007b12 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 8007aea: 4bb2 ldr r3, [pc, #712] ; (8007db4 ) 8007aec: 6f1b ldr r3, [r3, #112] ; 0x70 8007aee: f423 7340 bic.w r3, r3, #768 ; 0x300 8007af2: 60fb str r3, [r7, #12] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8007af4: 4baf ldr r3, [pc, #700] ; (8007db4 ) 8007af6: 6f1b ldr r3, [r3, #112] ; 0x70 8007af8: 4aae ldr r2, [pc, #696] ; (8007db4 ) 8007afa: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8007afe: 6713 str r3, [r2, #112] ; 0x70 __HAL_RCC_BACKUPRESET_RELEASE(); 8007b00: 4bac ldr r3, [pc, #688] ; (8007db4 ) 8007b02: 6f1b ldr r3, [r3, #112] ; 0x70 8007b04: 4aab ldr r2, [pc, #684] ; (8007db4 ) 8007b06: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8007b0a: 6713 str r3, [r2, #112] ; 0x70 /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg; 8007b0c: 4aa9 ldr r2, [pc, #676] ; (8007db4 ) 8007b0e: 68fb ldr r3, [r7, #12] 8007b10: 6713 str r3, [r2, #112] ; 0x70 } /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */ if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) 8007b12: 687b ldr r3, [r7, #4] 8007b14: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 8007b18: f5b3 7f80 cmp.w r3, #256 ; 0x100 8007b1c: d115 bne.n 8007b4a { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8007b1e: f7fb fb63 bl 80031e8 8007b22: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 8007b24: e00b b.n 8007b3e { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8007b26: f7fb fb5f bl 80031e8 8007b2a: 4602 mov r2, r0 8007b2c: 693b ldr r3, [r7, #16] 8007b2e: 1ad3 subs r3, r2, r3 8007b30: f241 3288 movw r2, #5000 ; 0x1388 8007b34: 4293 cmp r3, r2 8007b36: d902 bls.n 8007b3e { ret = HAL_TIMEOUT; 8007b38: 2303 movs r3, #3 8007b3a: 75fb strb r3, [r7, #23] break; 8007b3c: e005 b.n 8007b4a while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 8007b3e: 4b9d ldr r3, [pc, #628] ; (8007db4 ) 8007b40: 6f1b ldr r3, [r3, #112] ; 0x70 8007b42: f003 0302 and.w r3, r3, #2 8007b46: 2b00 cmp r3, #0 8007b48: d0ed beq.n 8007b26 } } } if(ret == HAL_OK) 8007b4a: 7dfb ldrb r3, [r7, #23] 8007b4c: 2b00 cmp r3, #0 8007b4e: d126 bne.n 8007b9e { __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8007b50: 687b ldr r3, [r7, #4] 8007b52: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 8007b56: f403 7340 and.w r3, r3, #768 ; 0x300 8007b5a: f5b3 7f40 cmp.w r3, #768 ; 0x300 8007b5e: d10d bne.n 8007b7c 8007b60: 4b94 ldr r3, [pc, #592] ; (8007db4 ) 8007b62: 691b ldr r3, [r3, #16] 8007b64: f423 527c bic.w r2, r3, #16128 ; 0x3f00 8007b68: 687b ldr r3, [r7, #4] 8007b6a: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 8007b6e: 0919 lsrs r1, r3, #4 8007b70: 4b91 ldr r3, [pc, #580] ; (8007db8 ) 8007b72: 400b ands r3, r1 8007b74: 498f ldr r1, [pc, #572] ; (8007db4 ) 8007b76: 4313 orrs r3, r2 8007b78: 610b str r3, [r1, #16] 8007b7a: e005 b.n 8007b88 8007b7c: 4b8d ldr r3, [pc, #564] ; (8007db4 ) 8007b7e: 691b ldr r3, [r3, #16] 8007b80: 4a8c ldr r2, [pc, #560] ; (8007db4 ) 8007b82: f423 537c bic.w r3, r3, #16128 ; 0x3f00 8007b86: 6113 str r3, [r2, #16] 8007b88: 4b8a ldr r3, [pc, #552] ; (8007db4 ) 8007b8a: 6f1a ldr r2, [r3, #112] ; 0x70 8007b8c: 687b ldr r3, [r7, #4] 8007b8e: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 8007b92: f3c3 030b ubfx r3, r3, #0, #12 8007b96: 4987 ldr r1, [pc, #540] ; (8007db4 ) 8007b98: 4313 orrs r3, r2 8007b9a: 670b str r3, [r1, #112] ; 0x70 8007b9c: e004 b.n 8007ba8 } else { /* set overall return value */ status = ret; 8007b9e: 7dfb ldrb r3, [r7, #23] 8007ba0: 75bb strb r3, [r7, #22] 8007ba2: e001 b.n 8007ba8 } } else { /* set overall return value */ status = ret; 8007ba4: 7dfb ldrb r3, [r7, #23] 8007ba6: 75bb strb r3, [r7, #22] } } /*-------------------------- USART1/6 configuration --------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) 8007ba8: 687b ldr r3, [r7, #4] 8007baa: 681b ldr r3, [r3, #0] 8007bac: f003 0301 and.w r3, r3, #1 8007bb0: 2b00 cmp r3, #0 8007bb2: d07f beq.n 8007cb4 { switch(PeriphClkInit->Usart16ClockSelection) 8007bb4: 687b ldr r3, [r7, #4] 8007bb6: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 8007bba: 2b28 cmp r3, #40 ; 0x28 8007bbc: d866 bhi.n 8007c8c 8007bbe: a201 add r2, pc, #4 ; (adr r2, 8007bc4 ) 8007bc0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8007bc4: 08007c93 .word 0x08007c93 8007bc8: 08007c8d .word 0x08007c8d 8007bcc: 08007c8d .word 0x08007c8d 8007bd0: 08007c8d .word 0x08007c8d 8007bd4: 08007c8d .word 0x08007c8d 8007bd8: 08007c8d .word 0x08007c8d 8007bdc: 08007c8d .word 0x08007c8d 8007be0: 08007c8d .word 0x08007c8d 8007be4: 08007c69 .word 0x08007c69 8007be8: 08007c8d .word 0x08007c8d 8007bec: 08007c8d .word 0x08007c8d 8007bf0: 08007c8d .word 0x08007c8d 8007bf4: 08007c8d .word 0x08007c8d 8007bf8: 08007c8d .word 0x08007c8d 8007bfc: 08007c8d .word 0x08007c8d 8007c00: 08007c8d .word 0x08007c8d 8007c04: 08007c7b .word 0x08007c7b 8007c08: 08007c8d .word 0x08007c8d 8007c0c: 08007c8d .word 0x08007c8d 8007c10: 08007c8d .word 0x08007c8d 8007c14: 08007c8d .word 0x08007c8d 8007c18: 08007c8d .word 0x08007c8d 8007c1c: 08007c8d .word 0x08007c8d 8007c20: 08007c8d .word 0x08007c8d 8007c24: 08007c93 .word 0x08007c93 8007c28: 08007c8d .word 0x08007c8d 8007c2c: 08007c8d .word 0x08007c8d 8007c30: 08007c8d .word 0x08007c8d 8007c34: 08007c8d .word 0x08007c8d 8007c38: 08007c8d .word 0x08007c8d 8007c3c: 08007c8d .word 0x08007c8d 8007c40: 08007c8d .word 0x08007c8d 8007c44: 08007c93 .word 0x08007c93 8007c48: 08007c8d .word 0x08007c8d 8007c4c: 08007c8d .word 0x08007c8d 8007c50: 08007c8d .word 0x08007c8d 8007c54: 08007c8d .word 0x08007c8d 8007c58: 08007c8d .word 0x08007c8d 8007c5c: 08007c8d .word 0x08007c8d 8007c60: 08007c8d .word 0x08007c8d 8007c64: 08007c93 .word 0x08007c93 case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */ /* USART1/6 clock source configuration done later after clock selection check */ break; case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 8007c68: 687b ldr r3, [r7, #4] 8007c6a: 3304 adds r3, #4 8007c6c: 2101 movs r1, #1 8007c6e: 4618 mov r0, r3 8007c70: f001 fb74 bl 800935c 8007c74: 4603 mov r3, r0 8007c76: 75fb strb r3, [r7, #23] /* USART1/6 clock source configuration done later after clock selection check */ break; 8007c78: e00c b.n 8007c94 case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 8007c7a: 687b ldr r3, [r7, #4] 8007c7c: 3324 adds r3, #36 ; 0x24 8007c7e: 2101 movs r1, #1 8007c80: 4618 mov r0, r3 8007c82: f001 fc1d bl 80094c0 8007c86: 4603 mov r3, r0 8007c88: 75fb strb r3, [r7, #23] /* USART1/6 clock source configuration done later after clock selection check */ break; 8007c8a: e003 b.n 8007c94 /* LSE, oscillator is used as source of USART1/6 clock */ /* USART1/6 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8007c8c: 2301 movs r3, #1 8007c8e: 75fb strb r3, [r7, #23] break; 8007c90: e000 b.n 8007c94 break; 8007c92: bf00 nop } if(ret == HAL_OK) 8007c94: 7dfb ldrb r3, [r7, #23] 8007c96: 2b00 cmp r3, #0 8007c98: d10a bne.n 8007cb0 { /* Set the source of USART1/6 clock */ __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection); 8007c9a: 4b46 ldr r3, [pc, #280] ; (8007db4 ) 8007c9c: 6d5b ldr r3, [r3, #84] ; 0x54 8007c9e: f023 0238 bic.w r2, r3, #56 ; 0x38 8007ca2: 687b ldr r3, [r7, #4] 8007ca4: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 8007ca8: 4942 ldr r1, [pc, #264] ; (8007db4 ) 8007caa: 4313 orrs r3, r2 8007cac: 654b str r3, [r1, #84] ; 0x54 8007cae: e001 b.n 8007cb4 } else { /* set overall return value */ status = ret; 8007cb0: 7dfb ldrb r3, [r7, #23] 8007cb2: 75bb strb r3, [r7, #22] } } /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) 8007cb4: 687b ldr r3, [r7, #4] 8007cb6: 681b ldr r3, [r3, #0] 8007cb8: f003 0302 and.w r3, r3, #2 8007cbc: 2b00 cmp r3, #0 8007cbe: d038 beq.n 8007d32 { switch(PeriphClkInit->Usart234578ClockSelection) 8007cc0: 687b ldr r3, [r7, #4] 8007cc2: 6fdb ldr r3, [r3, #124] ; 0x7c 8007cc4: 2b05 cmp r3, #5 8007cc6: d821 bhi.n 8007d0c 8007cc8: a201 add r2, pc, #4 ; (adr r2, 8007cd0 ) 8007cca: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8007cce: bf00 nop 8007cd0: 08007d13 .word 0x08007d13 8007cd4: 08007ce9 .word 0x08007ce9 8007cd8: 08007cfb .word 0x08007cfb 8007cdc: 08007d13 .word 0x08007d13 8007ce0: 08007d13 .word 0x08007d13 8007ce4: 08007d13 .word 0x08007d13 case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 8007ce8: 687b ldr r3, [r7, #4] 8007cea: 3304 adds r3, #4 8007cec: 2101 movs r1, #1 8007cee: 4618 mov r0, r3 8007cf0: f001 fb34 bl 800935c 8007cf4: 4603 mov r3, r0 8007cf6: 75fb strb r3, [r7, #23] /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 8007cf8: e00c b.n 8007d14 case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 8007cfa: 687b ldr r3, [r7, #4] 8007cfc: 3324 adds r3, #36 ; 0x24 8007cfe: 2101 movs r1, #1 8007d00: 4618 mov r0, r3 8007d02: f001 fbdd bl 80094c0 8007d06: 4603 mov r3, r0 8007d08: 75fb strb r3, [r7, #23] /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 8007d0a: e003 b.n 8007d14 /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8007d0c: 2301 movs r3, #1 8007d0e: 75fb strb r3, [r7, #23] break; 8007d10: e000 b.n 8007d14 break; 8007d12: bf00 nop } if(ret == HAL_OK) 8007d14: 7dfb ldrb r3, [r7, #23] 8007d16: 2b00 cmp r3, #0 8007d18: d109 bne.n 8007d2e { /* Set the source of USART2/3/4/5/7/8 clock */ __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection); 8007d1a: 4b26 ldr r3, [pc, #152] ; (8007db4 ) 8007d1c: 6d5b ldr r3, [r3, #84] ; 0x54 8007d1e: f023 0207 bic.w r2, r3, #7 8007d22: 687b ldr r3, [r7, #4] 8007d24: 6fdb ldr r3, [r3, #124] ; 0x7c 8007d26: 4923 ldr r1, [pc, #140] ; (8007db4 ) 8007d28: 4313 orrs r3, r2 8007d2a: 654b str r3, [r1, #84] ; 0x54 8007d2c: e001 b.n 8007d32 } else { /* set overall return value */ status = ret; 8007d2e: 7dfb ldrb r3, [r7, #23] 8007d30: 75bb strb r3, [r7, #22] } } /*-------------------------- LPUART1 Configuration -------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 8007d32: 687b ldr r3, [r7, #4] 8007d34: 681b ldr r3, [r3, #0] 8007d36: f003 0304 and.w r3, r3, #4 8007d3a: 2b00 cmp r3, #0 8007d3c: d040 beq.n 8007dc0 { switch(PeriphClkInit->Lpuart1ClockSelection) 8007d3e: 687b ldr r3, [r7, #4] 8007d40: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98 8007d44: 2b05 cmp r3, #5 8007d46: d821 bhi.n 8007d8c 8007d48: a201 add r2, pc, #4 ; (adr r2, 8007d50 ) 8007d4a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8007d4e: bf00 nop 8007d50: 08007d93 .word 0x08007d93 8007d54: 08007d69 .word 0x08007d69 8007d58: 08007d7b .word 0x08007d7b 8007d5c: 08007d93 .word 0x08007d93 8007d60: 08007d93 .word 0x08007d93 8007d64: 08007d93 .word 0x08007d93 case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */ /* LPUART1 clock source configuration done later after clock selection check */ break; case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 8007d68: 687b ldr r3, [r7, #4] 8007d6a: 3304 adds r3, #4 8007d6c: 2101 movs r1, #1 8007d6e: 4618 mov r0, r3 8007d70: f001 faf4 bl 800935c 8007d74: 4603 mov r3, r0 8007d76: 75fb strb r3, [r7, #23] /* LPUART1 clock source configuration done later after clock selection check */ break; 8007d78: e00c b.n 8007d94 case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 8007d7a: 687b ldr r3, [r7, #4] 8007d7c: 3324 adds r3, #36 ; 0x24 8007d7e: 2101 movs r1, #1 8007d80: 4618 mov r0, r3 8007d82: f001 fb9d bl 80094c0 8007d86: 4603 mov r3, r0 8007d88: 75fb strb r3, [r7, #23] /* LPUART1 clock source configuration done later after clock selection check */ break; 8007d8a: e003 b.n 8007d94 /* LSE, oscillator is used as source of LPUART1 clock */ /* LPUART1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8007d8c: 2301 movs r3, #1 8007d8e: 75fb strb r3, [r7, #23] break; 8007d90: e000 b.n 8007d94 break; 8007d92: bf00 nop } if(ret == HAL_OK) 8007d94: 7dfb ldrb r3, [r7, #23] 8007d96: 2b00 cmp r3, #0 8007d98: d110 bne.n 8007dbc { /* Set the source of LPUART1 clock */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 8007d9a: 4b06 ldr r3, [pc, #24] ; (8007db4 ) 8007d9c: 6d9b ldr r3, [r3, #88] ; 0x58 8007d9e: f023 0207 bic.w r2, r3, #7 8007da2: 687b ldr r3, [r7, #4] 8007da4: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98 8007da8: 4902 ldr r1, [pc, #8] ; (8007db4 ) 8007daa: 4313 orrs r3, r2 8007dac: 658b str r3, [r1, #88] ; 0x58 8007dae: e007 b.n 8007dc0 8007db0: 58024800 .word 0x58024800 8007db4: 58024400 .word 0x58024400 8007db8: 00ffffcf .word 0x00ffffcf } else { /* set overall return value */ status = ret; 8007dbc: 7dfb ldrb r3, [r7, #23] 8007dbe: 75bb strb r3, [r7, #22] } } /*---------------------------- LPTIM1 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) 8007dc0: 687b ldr r3, [r7, #4] 8007dc2: 681b ldr r3, [r3, #0] 8007dc4: f003 0320 and.w r3, r3, #32 8007dc8: 2b00 cmp r3, #0 8007dca: d04b beq.n 8007e64 { switch(PeriphClkInit->Lptim1ClockSelection) 8007dcc: 687b ldr r3, [r7, #4] 8007dce: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 8007dd2: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 8007dd6: d02e beq.n 8007e36 8007dd8: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 8007ddc: d828 bhi.n 8007e30 8007dde: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8007de2: d02a beq.n 8007e3a 8007de4: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8007de8: d822 bhi.n 8007e30 8007dea: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 8007dee: d026 beq.n 8007e3e 8007df0: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 8007df4: d81c bhi.n 8007e30 8007df6: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8007dfa: d010 beq.n 8007e1e 8007dfc: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8007e00: d816 bhi.n 8007e30 8007e02: 2b00 cmp r3, #0 8007e04: d01d beq.n 8007e42 8007e06: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 8007e0a: d111 bne.n 8007e30 /* LPTIM1 clock source configuration done later after clock selection check */ break; case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 8007e0c: 687b ldr r3, [r7, #4] 8007e0e: 3304 adds r3, #4 8007e10: 2100 movs r1, #0 8007e12: 4618 mov r0, r3 8007e14: f001 faa2 bl 800935c 8007e18: 4603 mov r3, r0 8007e1a: 75fb strb r3, [r7, #23] /* LPTIM1 clock source configuration done later after clock selection check */ break; 8007e1c: e012 b.n 8007e44 case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 8007e1e: 687b ldr r3, [r7, #4] 8007e20: 3324 adds r3, #36 ; 0x24 8007e22: 2102 movs r1, #2 8007e24: 4618 mov r0, r3 8007e26: f001 fb4b bl 80094c0 8007e2a: 4603 mov r3, r0 8007e2c: 75fb strb r3, [r7, #23] /* LPTIM1 clock source configuration done later after clock selection check */ break; 8007e2e: e009 b.n 8007e44 /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */ /* LPTIM1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8007e30: 2301 movs r3, #1 8007e32: 75fb strb r3, [r7, #23] break; 8007e34: e006 b.n 8007e44 break; 8007e36: bf00 nop 8007e38: e004 b.n 8007e44 break; 8007e3a: bf00 nop 8007e3c: e002 b.n 8007e44 break; 8007e3e: bf00 nop 8007e40: e000 b.n 8007e44 break; 8007e42: bf00 nop } if(ret == HAL_OK) 8007e44: 7dfb ldrb r3, [r7, #23] 8007e46: 2b00 cmp r3, #0 8007e48: d10a bne.n 8007e60 { /* Set the source of LPTIM1 clock*/ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 8007e4a: 4bb3 ldr r3, [pc, #716] ; (8008118 ) 8007e4c: 6d5b ldr r3, [r3, #84] ; 0x54 8007e4e: f023 42e0 bic.w r2, r3, #1879048192 ; 0x70000000 8007e52: 687b ldr r3, [r7, #4] 8007e54: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 8007e58: 49af ldr r1, [pc, #700] ; (8008118 ) 8007e5a: 4313 orrs r3, r2 8007e5c: 654b str r3, [r1, #84] ; 0x54 8007e5e: e001 b.n 8007e64 } else { /* set overall return value */ status = ret; 8007e60: 7dfb ldrb r3, [r7, #23] 8007e62: 75bb strb r3, [r7, #22] } } /*---------------------------- LPTIM2 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) 8007e64: 687b ldr r3, [r7, #4] 8007e66: 681b ldr r3, [r3, #0] 8007e68: f003 0340 and.w r3, r3, #64 ; 0x40 8007e6c: 2b00 cmp r3, #0 8007e6e: d04b beq.n 8007f08 { switch(PeriphClkInit->Lptim2ClockSelection) 8007e70: 687b ldr r3, [r7, #4] 8007e72: f8d3 30a0 ldr.w r3, [r3, #160] ; 0xa0 8007e76: f5b3 5fa0 cmp.w r3, #5120 ; 0x1400 8007e7a: d02e beq.n 8007eda 8007e7c: f5b3 5fa0 cmp.w r3, #5120 ; 0x1400 8007e80: d828 bhi.n 8007ed4 8007e82: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8007e86: d02a beq.n 8007ede 8007e88: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8007e8c: d822 bhi.n 8007ed4 8007e8e: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 8007e92: d026 beq.n 8007ee2 8007e94: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 8007e98: d81c bhi.n 8007ed4 8007e9a: f5b3 6f00 cmp.w r3, #2048 ; 0x800 8007e9e: d010 beq.n 8007ec2 8007ea0: f5b3 6f00 cmp.w r3, #2048 ; 0x800 8007ea4: d816 bhi.n 8007ed4 8007ea6: 2b00 cmp r3, #0 8007ea8: d01d beq.n 8007ee6 8007eaa: f5b3 6f80 cmp.w r3, #1024 ; 0x400 8007eae: d111 bne.n 8007ed4 /* LPTIM2 clock source configuration done later after clock selection check */ break; case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 8007eb0: 687b ldr r3, [r7, #4] 8007eb2: 3304 adds r3, #4 8007eb4: 2100 movs r1, #0 8007eb6: 4618 mov r0, r3 8007eb8: f001 fa50 bl 800935c 8007ebc: 4603 mov r3, r0 8007ebe: 75fb strb r3, [r7, #23] /* LPTIM2 clock source configuration done later after clock selection check */ break; 8007ec0: e012 b.n 8007ee8 case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 8007ec2: 687b ldr r3, [r7, #4] 8007ec4: 3324 adds r3, #36 ; 0x24 8007ec6: 2102 movs r1, #2 8007ec8: 4618 mov r0, r3 8007eca: f001 faf9 bl 80094c0 8007ece: 4603 mov r3, r0 8007ed0: 75fb strb r3, [r7, #23] /* LPTIM2 clock source configuration done later after clock selection check */ break; 8007ed2: e009 b.n 8007ee8 /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */ /* LPTIM2 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8007ed4: 2301 movs r3, #1 8007ed6: 75fb strb r3, [r7, #23] break; 8007ed8: e006 b.n 8007ee8 break; 8007eda: bf00 nop 8007edc: e004 b.n 8007ee8 break; 8007ede: bf00 nop 8007ee0: e002 b.n 8007ee8 break; 8007ee2: bf00 nop 8007ee4: e000 b.n 8007ee8 break; 8007ee6: bf00 nop } if(ret == HAL_OK) 8007ee8: 7dfb ldrb r3, [r7, #23] 8007eea: 2b00 cmp r3, #0 8007eec: d10a bne.n 8007f04 { /* Set the source of LPTIM2 clock*/ __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); 8007eee: 4b8a ldr r3, [pc, #552] ; (8008118 ) 8007ef0: 6d9b ldr r3, [r3, #88] ; 0x58 8007ef2: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00 8007ef6: 687b ldr r3, [r7, #4] 8007ef8: f8d3 30a0 ldr.w r3, [r3, #160] ; 0xa0 8007efc: 4986 ldr r1, [pc, #536] ; (8008118 ) 8007efe: 4313 orrs r3, r2 8007f00: 658b str r3, [r1, #88] ; 0x58 8007f02: e001 b.n 8007f08 } else { /* set overall return value */ status = ret; 8007f04: 7dfb ldrb r3, [r7, #23] 8007f06: 75bb strb r3, [r7, #22] } } /*---------------------------- LPTIM345 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345) 8007f08: 687b ldr r3, [r7, #4] 8007f0a: 681b ldr r3, [r3, #0] 8007f0c: f003 0380 and.w r3, r3, #128 ; 0x80 8007f10: 2b00 cmp r3, #0 8007f12: d04b beq.n 8007fac { switch(PeriphClkInit->Lptim345ClockSelection) 8007f14: 687b ldr r3, [r7, #4] 8007f16: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4 8007f1a: f5b3 4f20 cmp.w r3, #40960 ; 0xa000 8007f1e: d02e beq.n 8007f7e 8007f20: f5b3 4f20 cmp.w r3, #40960 ; 0xa000 8007f24: d828 bhi.n 8007f78 8007f26: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 8007f2a: d02a beq.n 8007f82 8007f2c: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 8007f30: d822 bhi.n 8007f78 8007f32: f5b3 4fc0 cmp.w r3, #24576 ; 0x6000 8007f36: d026 beq.n 8007f86 8007f38: f5b3 4fc0 cmp.w r3, #24576 ; 0x6000 8007f3c: d81c bhi.n 8007f78 8007f3e: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 8007f42: d010 beq.n 8007f66 8007f44: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 8007f48: d816 bhi.n 8007f78 8007f4a: 2b00 cmp r3, #0 8007f4c: d01d beq.n 8007f8a 8007f4e: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 8007f52: d111 bne.n 8007f78 case RCC_LPTIM345CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 8007f54: 687b ldr r3, [r7, #4] 8007f56: 3304 adds r3, #4 8007f58: 2100 movs r1, #0 8007f5a: 4618 mov r0, r3 8007f5c: f001 f9fe bl 800935c 8007f60: 4603 mov r3, r0 8007f62: 75fb strb r3, [r7, #23] /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 8007f64: e012 b.n 8007f8c case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 8007f66: 687b ldr r3, [r7, #4] 8007f68: 3324 adds r3, #36 ; 0x24 8007f6a: 2102 movs r1, #2 8007f6c: 4618 mov r0, r3 8007f6e: f001 faa7 bl 80094c0 8007f72: 4603 mov r3, r0 8007f74: 75fb strb r3, [r7, #23] /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 8007f76: e009 b.n 8007f8c /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8007f78: 2301 movs r3, #1 8007f7a: 75fb strb r3, [r7, #23] break; 8007f7c: e006 b.n 8007f8c break; 8007f7e: bf00 nop 8007f80: e004 b.n 8007f8c break; 8007f82: bf00 nop 8007f84: e002 b.n 8007f8c break; 8007f86: bf00 nop 8007f88: e000 b.n 8007f8c break; 8007f8a: bf00 nop } if(ret == HAL_OK) 8007f8c: 7dfb ldrb r3, [r7, #23] 8007f8e: 2b00 cmp r3, #0 8007f90: d10a bne.n 8007fa8 { /* Set the source of LPTIM3/4/5 clock */ __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection); 8007f92: 4b61 ldr r3, [pc, #388] ; (8008118 ) 8007f94: 6d9b ldr r3, [r3, #88] ; 0x58 8007f96: f423 4260 bic.w r2, r3, #57344 ; 0xe000 8007f9a: 687b ldr r3, [r7, #4] 8007f9c: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4 8007fa0: 495d ldr r1, [pc, #372] ; (8008118 ) 8007fa2: 4313 orrs r3, r2 8007fa4: 658b str r3, [r1, #88] ; 0x58 8007fa6: e001 b.n 8007fac } else { /* set overall return value */ status = ret; 8007fa8: 7dfb ldrb r3, [r7, #23] 8007faa: 75bb strb r3, [r7, #22] __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection); } #else if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123) 8007fac: 687b ldr r3, [r7, #4] 8007fae: 681b ldr r3, [r3, #0] 8007fb0: f003 0308 and.w r3, r3, #8 8007fb4: 2b00 cmp r3, #0 8007fb6: d01a beq.n 8007fee { /* Check the parameters */ assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection)); if ((PeriphClkInit->I2c123ClockSelection )== RCC_I2C123CLKSOURCE_PLL3 ) 8007fb8: 687b ldr r3, [r7, #4] 8007fba: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8007fbe: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8007fc2: d10a bne.n 8007fda { if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK) 8007fc4: 687b ldr r3, [r7, #4] 8007fc6: 3324 adds r3, #36 ; 0x24 8007fc8: 2102 movs r1, #2 8007fca: 4618 mov r0, r3 8007fcc: f001 fa78 bl 80094c0 8007fd0: 4603 mov r3, r0 8007fd2: 2b00 cmp r3, #0 8007fd4: d001 beq.n 8007fda { status = HAL_ERROR; 8007fd6: 2301 movs r3, #1 8007fd8: 75bb strb r3, [r7, #22] } } __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection); 8007fda: 4b4f ldr r3, [pc, #316] ; (8008118 ) 8007fdc: 6d5b ldr r3, [r3, #84] ; 0x54 8007fde: f423 5240 bic.w r2, r3, #12288 ; 0x3000 8007fe2: 687b ldr r3, [r7, #4] 8007fe4: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8007fe8: 494b ldr r1, [pc, #300] ; (8008118 ) 8007fea: 4313 orrs r3, r2 8007fec: 654b str r3, [r1, #84] ; 0x54 } #endif /* I2C5 */ /*------------------------------ I2C4 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) 8007fee: 687b ldr r3, [r7, #4] 8007ff0: 681b ldr r3, [r3, #0] 8007ff2: f003 0310 and.w r3, r3, #16 8007ff6: 2b00 cmp r3, #0 8007ff8: d01a beq.n 8008030 { /* Check the parameters */ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3 ) 8007ffa: 687b ldr r3, [r7, #4] 8007ffc: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 8008000: f5b3 7f80 cmp.w r3, #256 ; 0x100 8008004: d10a bne.n 800801c { if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK) 8008006: 687b ldr r3, [r7, #4] 8008008: 3324 adds r3, #36 ; 0x24 800800a: 2102 movs r1, #2 800800c: 4618 mov r0, r3 800800e: f001 fa57 bl 80094c0 8008012: 4603 mov r3, r0 8008014: 2b00 cmp r3, #0 8008016: d001 beq.n 800801c { status = HAL_ERROR; 8008018: 2301 movs r3, #1 800801a: 75bb strb r3, [r7, #22] } } __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); 800801c: 4b3e ldr r3, [pc, #248] ; (8008118 ) 800801e: 6d9b ldr r3, [r3, #88] ; 0x58 8008020: f423 7240 bic.w r2, r3, #768 ; 0x300 8008024: 687b ldr r3, [r7, #4] 8008026: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 800802a: 493b ldr r1, [pc, #236] ; (8008118 ) 800802c: 4313 orrs r3, r2 800802e: 658b str r3, [r1, #88] ; 0x58 } /*---------------------------- ADC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 8008030: 687b ldr r3, [r7, #4] 8008032: 681b ldr r3, [r3, #0] 8008034: f403 2300 and.w r3, r3, #524288 ; 0x80000 8008038: 2b00 cmp r3, #0 800803a: d034 beq.n 80080a6 { switch(PeriphClkInit->AdcClockSelection) 800803c: 687b ldr r3, [r7, #4] 800803e: f8d3 30a8 ldr.w r3, [r3, #168] ; 0xa8 8008042: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 8008046: d01d beq.n 8008084 8008048: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 800804c: d817 bhi.n 800807e 800804e: 2b00 cmp r3, #0 8008050: d003 beq.n 800805a 8008052: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8008056: d009 beq.n 800806c 8008058: e011 b.n 800807e { case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 800805a: 687b ldr r3, [r7, #4] 800805c: 3304 adds r3, #4 800805e: 2100 movs r1, #0 8008060: 4618 mov r0, r3 8008062: f001 f97b bl 800935c 8008066: 4603 mov r3, r0 8008068: 75fb strb r3, [r7, #23] /* ADC clock source configuration done later after clock selection check */ break; 800806a: e00c b.n 8008086 case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 800806c: 687b ldr r3, [r7, #4] 800806e: 3324 adds r3, #36 ; 0x24 8008070: 2102 movs r1, #2 8008072: 4618 mov r0, r3 8008074: f001 fa24 bl 80094c0 8008078: 4603 mov r3, r0 800807a: 75fb strb r3, [r7, #23] /* ADC clock source configuration done later after clock selection check */ break; 800807c: e003 b.n 8008086 /* HSI, HSE, or CSI oscillator is used as source of ADC clock */ /* ADC clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800807e: 2301 movs r3, #1 8008080: 75fb strb r3, [r7, #23] break; 8008082: e000 b.n 8008086 break; 8008084: bf00 nop } if(ret == HAL_OK) 8008086: 7dfb ldrb r3, [r7, #23] 8008088: 2b00 cmp r3, #0 800808a: d10a bne.n 80080a2 { /* Set the source of ADC clock*/ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 800808c: 4b22 ldr r3, [pc, #136] ; (8008118 ) 800808e: 6d9b ldr r3, [r3, #88] ; 0x58 8008090: f423 3240 bic.w r2, r3, #196608 ; 0x30000 8008094: 687b ldr r3, [r7, #4] 8008096: f8d3 30a8 ldr.w r3, [r3, #168] ; 0xa8 800809a: 491f ldr r1, [pc, #124] ; (8008118 ) 800809c: 4313 orrs r3, r2 800809e: 658b str r3, [r1, #88] ; 0x58 80080a0: e001 b.n 80080a6 } else { /* set overall return value */ status = ret; 80080a2: 7dfb ldrb r3, [r7, #23] 80080a4: 75bb strb r3, [r7, #22] } } /*------------------------------ USB Configuration -------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 80080a6: 687b ldr r3, [r7, #4] 80080a8: 681b ldr r3, [r3, #0] 80080aa: f403 2380 and.w r3, r3, #262144 ; 0x40000 80080ae: 2b00 cmp r3, #0 80080b0: d036 beq.n 8008120 { switch(PeriphClkInit->UsbClockSelection) 80080b2: 687b ldr r3, [r7, #4] 80080b4: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 80080b8: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000 80080bc: d01c beq.n 80080f8 80080be: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000 80080c2: d816 bhi.n 80080f2 80080c4: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 80080c8: d003 beq.n 80080d2 80080ca: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 80080ce: d007 beq.n 80080e0 80080d0: e00f b.n 80080f2 { case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/ /* Enable USB Clock output generated form System USB . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80080d2: 4b11 ldr r3, [pc, #68] ; (8008118 ) 80080d4: 6adb ldr r3, [r3, #44] ; 0x2c 80080d6: 4a10 ldr r2, [pc, #64] ; (8008118 ) 80080d8: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80080dc: 62d3 str r3, [r2, #44] ; 0x2c /* USB clock source configuration done later after clock selection check */ break; 80080de: e00c b.n 80080fa case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 80080e0: 687b ldr r3, [r7, #4] 80080e2: 3324 adds r3, #36 ; 0x24 80080e4: 2101 movs r1, #1 80080e6: 4618 mov r0, r3 80080e8: f001 f9ea bl 80094c0 80080ec: 4603 mov r3, r0 80080ee: 75fb strb r3, [r7, #23] /* USB clock source configuration done later after clock selection check */ break; 80080f0: e003 b.n 80080fa /* HSI48 oscillator is used as source of USB clock */ /* USB clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80080f2: 2301 movs r3, #1 80080f4: 75fb strb r3, [r7, #23] break; 80080f6: e000 b.n 80080fa break; 80080f8: bf00 nop } if(ret == HAL_OK) 80080fa: 7dfb ldrb r3, [r7, #23] 80080fc: 2b00 cmp r3, #0 80080fe: d10d bne.n 800811c { /* Set the source of USB clock*/ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 8008100: 4b05 ldr r3, [pc, #20] ; (8008118 ) 8008102: 6d5b ldr r3, [r3, #84] ; 0x54 8008104: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 8008108: 687b ldr r3, [r7, #4] 800810a: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 800810e: 4902 ldr r1, [pc, #8] ; (8008118 ) 8008110: 4313 orrs r3, r2 8008112: 654b str r3, [r1, #84] ; 0x54 8008114: e004 b.n 8008120 8008116: bf00 nop 8008118: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 800811c: 7dfb ldrb r3, [r7, #23] 800811e: 75bb strb r3, [r7, #22] } } /*------------------------------------- SDMMC Configuration ------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC) 8008120: 687b ldr r3, [r7, #4] 8008122: 681b ldr r3, [r3, #0] 8008124: f403 3380 and.w r3, r3, #65536 ; 0x10000 8008128: 2b00 cmp r3, #0 800812a: d029 beq.n 8008180 { /* Check the parameters */ assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection)); switch(PeriphClkInit->SdmmcClockSelection) 800812c: 687b ldr r3, [r7, #4] 800812e: 6cdb ldr r3, [r3, #76] ; 0x4c 8008130: 2b00 cmp r3, #0 8008132: d003 beq.n 800813c 8008134: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8008138: d007 beq.n 800814a 800813a: e00f b.n 800815c { case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/ /* Enable SDMMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800813c: 4b69 ldr r3, [pc, #420] ; (80082e4 ) 800813e: 6adb ldr r3, [r3, #44] ; 0x2c 8008140: 4a68 ldr r2, [pc, #416] ; (80082e4 ) 8008142: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8008146: 62d3 str r3, [r2, #44] ; 0x2c /* SDMMC clock source configuration done later after clock selection check */ break; 8008148: e00b b.n 8008162 case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); 800814a: 687b ldr r3, [r7, #4] 800814c: 3304 adds r3, #4 800814e: 2102 movs r1, #2 8008150: 4618 mov r0, r3 8008152: f001 f903 bl 800935c 8008156: 4603 mov r3, r0 8008158: 75fb strb r3, [r7, #23] /* SDMMC clock source configuration done later after clock selection check */ break; 800815a: e002 b.n 8008162 default: ret = HAL_ERROR; 800815c: 2301 movs r3, #1 800815e: 75fb strb r3, [r7, #23] break; 8008160: bf00 nop } if(ret == HAL_OK) 8008162: 7dfb ldrb r3, [r7, #23] 8008164: 2b00 cmp r3, #0 8008166: d109 bne.n 800817c { /* Set the source of SDMMC clock*/ __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection); 8008168: 4b5e ldr r3, [pc, #376] ; (80082e4 ) 800816a: 6cdb ldr r3, [r3, #76] ; 0x4c 800816c: f423 3280 bic.w r2, r3, #65536 ; 0x10000 8008170: 687b ldr r3, [r7, #4] 8008172: 6cdb ldr r3, [r3, #76] ; 0x4c 8008174: 495b ldr r1, [pc, #364] ; (80082e4 ) 8008176: 4313 orrs r3, r2 8008178: 64cb str r3, [r1, #76] ; 0x4c 800817a: e001 b.n 8008180 } else { /* set overall return value */ status = ret; 800817c: 7dfb ldrb r3, [r7, #23] 800817e: 75bb strb r3, [r7, #22] } } #if defined(LTDC) /*-------------------------------------- LTDC Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) 8008180: 687b ldr r3, [r7, #4] 8008182: 681b ldr r3, [r3, #0] 8008184: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 8008188: 2b00 cmp r3, #0 800818a: d00a beq.n 80081a2 { if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!=HAL_OK) 800818c: 687b ldr r3, [r7, #4] 800818e: 3324 adds r3, #36 ; 0x24 8008190: 2102 movs r1, #2 8008192: 4618 mov r0, r3 8008194: f001 f994 bl 80094c0 8008198: 4603 mov r3, r0 800819a: 2b00 cmp r3, #0 800819c: d001 beq.n 80081a2 { status=HAL_ERROR; 800819e: 2301 movs r3, #1 80081a0: 75bb strb r3, [r7, #22] } } #endif /* LTDC */ /*------------------------------ RNG Configuration -------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) 80081a2: 687b ldr r3, [r7, #4] 80081a4: 681b ldr r3, [r3, #0] 80081a6: f403 3300 and.w r3, r3, #131072 ; 0x20000 80081aa: 2b00 cmp r3, #0 80081ac: d032 beq.n 8008214 { switch(PeriphClkInit->RngClockSelection) 80081ae: 687b ldr r3, [r7, #4] 80081b0: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 80081b4: f5b3 7f40 cmp.w r3, #768 ; 0x300 80081b8: d017 beq.n 80081ea 80081ba: f5b3 7f40 cmp.w r3, #768 ; 0x300 80081be: d811 bhi.n 80081e4 80081c0: f5b3 7f00 cmp.w r3, #512 ; 0x200 80081c4: d013 beq.n 80081ee 80081c6: f5b3 7f00 cmp.w r3, #512 ; 0x200 80081ca: d80b bhi.n 80081e4 80081cc: 2b00 cmp r3, #0 80081ce: d010 beq.n 80081f2 80081d0: f5b3 7f80 cmp.w r3, #256 ; 0x100 80081d4: d106 bne.n 80081e4 { case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/ /* Enable RNG Clock output generated form System RNG . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80081d6: 4b43 ldr r3, [pc, #268] ; (80082e4 ) 80081d8: 6adb ldr r3, [r3, #44] ; 0x2c 80081da: 4a42 ldr r2, [pc, #264] ; (80082e4 ) 80081dc: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80081e0: 62d3 str r3, [r2, #44] ; 0x2c /* RNG clock source configuration done later after clock selection check */ break; 80081e2: e007 b.n 80081f4 /* HSI48 oscillator is used as source of RNG clock */ /* RNG clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80081e4: 2301 movs r3, #1 80081e6: 75fb strb r3, [r7, #23] break; 80081e8: e004 b.n 80081f4 break; 80081ea: bf00 nop 80081ec: e002 b.n 80081f4 break; 80081ee: bf00 nop 80081f0: e000 b.n 80081f4 break; 80081f2: bf00 nop } if(ret == HAL_OK) 80081f4: 7dfb ldrb r3, [r7, #23] 80081f6: 2b00 cmp r3, #0 80081f8: d10a bne.n 8008210 { /* Set the source of RNG clock*/ __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 80081fa: 4b3a ldr r3, [pc, #232] ; (80082e4 ) 80081fc: 6d5b ldr r3, [r3, #84] ; 0x54 80081fe: f423 7240 bic.w r2, r3, #768 ; 0x300 8008202: 687b ldr r3, [r7, #4] 8008204: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 8008208: 4936 ldr r1, [pc, #216] ; (80082e4 ) 800820a: 4313 orrs r3, r2 800820c: 654b str r3, [r1, #84] ; 0x54 800820e: e001 b.n 8008214 } else { /* set overall return value */ status = ret; 8008210: 7dfb ldrb r3, [r7, #23] 8008212: 75bb strb r3, [r7, #22] } } /*------------------------------ SWPMI1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) 8008214: 687b ldr r3, [r7, #4] 8008216: 681b ldr r3, [r3, #0] 8008218: f403 1380 and.w r3, r3, #1048576 ; 0x100000 800821c: 2b00 cmp r3, #0 800821e: d008 beq.n 8008232 { /* Check the parameters */ assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); /* Configure the SWPMI1 interface clock source */ __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); 8008220: 4b30 ldr r3, [pc, #192] ; (80082e4 ) 8008222: 6d1b ldr r3, [r3, #80] ; 0x50 8008224: f023 4200 bic.w r2, r3, #2147483648 ; 0x80000000 8008228: 687b ldr r3, [r7, #4] 800822a: 6f9b ldr r3, [r3, #120] ; 0x78 800822c: 492d ldr r1, [pc, #180] ; (80082e4 ) 800822e: 4313 orrs r3, r2 8008230: 650b str r3, [r1, #80] ; 0x50 /* Configure the HRTIM1 clock source */ __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); } #endif /*HRTIM1*/ /*------------------------------ DFSDM1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) 8008232: 687b ldr r3, [r7, #4] 8008234: 681b ldr r3, [r3, #0] 8008236: f403 1300 and.w r3, r3, #2097152 ; 0x200000 800823a: 2b00 cmp r3, #0 800823c: d008 beq.n 8008250 { /* Check the parameters */ assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); /* Configure the DFSDM1 interface clock source */ __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); 800823e: 4b29 ldr r3, [pc, #164] ; (80082e4 ) 8008240: 6d1b ldr r3, [r3, #80] ; 0x50 8008242: f023 7280 bic.w r2, r3, #16777216 ; 0x1000000 8008246: 687b ldr r3, [r7, #4] 8008248: 6edb ldr r3, [r3, #108] ; 0x6c 800824a: 4926 ldr r1, [pc, #152] ; (80082e4 ) 800824c: 4313 orrs r3, r2 800824e: 650b str r3, [r1, #80] ; 0x50 } #if defined(DFSDM2_BASE) /*------------------------------ DFSDM2 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2) 8008250: 687b ldr r3, [r7, #4] 8008252: 681b ldr r3, [r3, #0] 8008254: f403 6300 and.w r3, r3, #2048 ; 0x800 8008258: 2b00 cmp r3, #0 800825a: d008 beq.n 800826e { /* Check the parameters */ assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection)); /* Configure the DFSDM2 interface clock source */ __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); 800825c: 4b21 ldr r3, [pc, #132] ; (80082e4 ) 800825e: 6d9b ldr r3, [r3, #88] ; 0x58 8008260: f023 6200 bic.w r2, r3, #134217728 ; 0x8000000 8008264: 687b ldr r3, [r7, #4] 8008266: 6f1b ldr r3, [r3, #112] ; 0x70 8008268: 491e ldr r1, [pc, #120] ; (80082e4 ) 800826a: 4313 orrs r3, r2 800826c: 658b str r3, [r1, #88] ; 0x58 } #endif /* DFSDM2 */ /*------------------------------------ TIM configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) 800826e: 687b ldr r3, [r7, #4] 8008270: 681b ldr r3, [r3, #0] 8008272: f003 4380 and.w r3, r3, #1073741824 ; 0x40000000 8008276: 2b00 cmp r3, #0 8008278: d00d beq.n 8008296 { /* Check the parameters */ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 800827a: 4b1a ldr r3, [pc, #104] ; (80082e4 ) 800827c: 691b ldr r3, [r3, #16] 800827e: 4a19 ldr r2, [pc, #100] ; (80082e4 ) 8008280: f423 4300 bic.w r3, r3, #32768 ; 0x8000 8008284: 6113 str r3, [r2, #16] 8008286: 4b17 ldr r3, [pc, #92] ; (80082e4 ) 8008288: 691a ldr r2, [r3, #16] 800828a: 687b ldr r3, [r7, #4] 800828c: f8d3 30b4 ldr.w r3, [r3, #180] ; 0xb4 8008290: 4914 ldr r1, [pc, #80] ; (80082e4 ) 8008292: 4313 orrs r3, r2 8008294: 610b str r3, [r1, #16] } /*------------------------------------ CKPER configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) 8008296: 687b ldr r3, [r7, #4] 8008298: 681b ldr r3, [r3, #0] 800829a: 2b00 cmp r3, #0 800829c: da08 bge.n 80082b0 { /* Check the parameters */ assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection)); /* Configure the CKPER clock source */ __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); 800829e: 4b11 ldr r3, [pc, #68] ; (80082e4 ) 80082a0: 6cdb ldr r3, [r3, #76] ; 0x4c 80082a2: f023 5240 bic.w r2, r3, #805306368 ; 0x30000000 80082a6: 687b ldr r3, [r7, #4] 80082a8: 6d1b ldr r3, [r3, #80] ; 0x50 80082aa: 490e ldr r1, [pc, #56] ; (80082e4 ) 80082ac: 4313 orrs r3, r2 80082ae: 64cb str r3, [r1, #76] ; 0x4c } /*------------------------------ CEC Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 80082b0: 687b ldr r3, [r7, #4] 80082b2: 681b ldr r3, [r3, #0] 80082b4: f403 0300 and.w r3, r3, #8388608 ; 0x800000 80082b8: 2b00 cmp r3, #0 80082ba: d009 beq.n 80082d0 { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC interface clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 80082bc: 4b09 ldr r3, [pc, #36] ; (80082e4 ) 80082be: 6d5b ldr r3, [r3, #84] ; 0x54 80082c0: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 80082c4: 687b ldr r3, [r7, #4] 80082c6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 80082ca: 4906 ldr r1, [pc, #24] ; (80082e4 ) 80082cc: 4313 orrs r3, r2 80082ce: 654b str r3, [r1, #84] ; 0x54 } if (status == HAL_OK) 80082d0: 7dbb ldrb r3, [r7, #22] 80082d2: 2b00 cmp r3, #0 80082d4: d101 bne.n 80082da { return HAL_OK; 80082d6: 2300 movs r3, #0 80082d8: e000 b.n 80082dc } return HAL_ERROR; 80082da: 2301 movs r3, #1 } 80082dc: 4618 mov r0, r3 80082de: 3718 adds r7, #24 80082e0: 46bd mov sp, r7 80082e2: bd80 pop {r7, pc} 80082e4: 58024400 .word 0x58024400 080082e8 : * @retval Frequency in KHz * * (*) : Available on some STM32H7 lines only. */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { 80082e8: b580 push {r7, lr} 80082ea: b090 sub sp, #64 ; 0x40 80082ec: af00 add r7, sp, #0 80082ee: 6078 str r0, [r7, #4] /* This variable is used to store the SAI and CKP clock source */ uint32_t saiclocksource; uint32_t ckpclocksource; uint32_t srcclk; if (PeriphClk == RCC_PERIPHCLK_SAI1) 80082f0: 687b ldr r3, [r7, #4] 80082f2: f5b3 7f80 cmp.w r3, #256 ; 0x100 80082f6: f040 8089 bne.w 800840c { saiclocksource= __HAL_RCC_GET_SAI1_SOURCE(); 80082fa: 4ba8 ldr r3, [pc, #672] ; (800859c ) 80082fc: 6d1b ldr r3, [r3, #80] ; 0x50 80082fe: f003 0307 and.w r3, r3, #7 8008302: 633b str r3, [r7, #48] ; 0x30 8008304: 6b3b ldr r3, [r7, #48] ; 0x30 8008306: 2b04 cmp r3, #4 8008308: d87d bhi.n 8008406 800830a: a201 add r2, pc, #4 ; (adr r2, 8008310 ) 800830c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8008310: 08008325 .word 0x08008325 8008314: 08008349 .word 0x08008349 8008318: 0800836d .word 0x0800836d 800831c: 08008401 .word 0x08008401 8008320: 08008391 .word 0x08008391 switch (saiclocksource) { case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 8008324: 4b9d ldr r3, [pc, #628] ; (800859c ) 8008326: 681b ldr r3, [r3, #0] 8008328: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 800832c: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 8008330: d107 bne.n 8008342 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 8008332: f107 0324 add.w r3, r7, #36 ; 0x24 8008336: 4618 mov r0, r3 8008338: f000 febe bl 80090b8 frequency = pll1_clocks.PLL1_Q_Frequency; 800833c: 6abb ldr r3, [r7, #40] ; 0x28 800833e: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8008340: e3f5 b.n 8008b2e frequency = 0; 8008342: 2300 movs r3, #0 8008344: 63fb str r3, [r7, #60] ; 0x3c break; 8008346: e3f2 b.n 8008b2e } case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 8008348: 4b94 ldr r3, [pc, #592] ; (800859c ) 800834a: 681b ldr r3, [r3, #0] 800834c: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8008350: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 8008354: d107 bne.n 8008366 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8008356: f107 0318 add.w r3, r7, #24 800835a: 4618 mov r0, r3 800835c: f000 fc04 bl 8008b68 frequency = pll2_clocks.PLL2_P_Frequency; 8008360: 69bb ldr r3, [r7, #24] 8008362: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8008364: e3e3 b.n 8008b2e frequency = 0; 8008366: 2300 movs r3, #0 8008368: 63fb str r3, [r7, #60] ; 0x3c break; 800836a: e3e0 b.n 8008b2e } case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800836c: 4b8b ldr r3, [pc, #556] ; (800859c ) 800836e: 681b ldr r3, [r3, #0] 8008370: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 8008374: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8008378: d107 bne.n 800838a { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800837a: f107 030c add.w r3, r7, #12 800837e: 4618 mov r0, r3 8008380: f000 fd46 bl 8008e10 frequency = pll3_clocks.PLL3_P_Frequency; 8008384: 68fb ldr r3, [r7, #12] 8008386: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8008388: e3d1 b.n 8008b2e frequency = 0; 800838a: 2300 movs r3, #0 800838c: 63fb str r3, [r7, #60] ; 0x3c break; 800838e: e3ce b.n 8008b2e } case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/ { ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); 8008390: 4b82 ldr r3, [pc, #520] ; (800859c ) 8008392: 6cdb ldr r3, [r3, #76] ; 0x4c 8008394: f003 5340 and.w r3, r3, #805306368 ; 0x30000000 8008398: 637b str r3, [r7, #52] ; 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800839a: 4b80 ldr r3, [pc, #512] ; (800859c ) 800839c: 681b ldr r3, [r3, #0] 800839e: f003 0304 and.w r3, r3, #4 80083a2: 2b04 cmp r3, #4 80083a4: d10c bne.n 80083c0 80083a6: 6b7b ldr r3, [r7, #52] ; 0x34 80083a8: 2b00 cmp r3, #0 80083aa: d109 bne.n 80083c0 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 80083ac: 4b7b ldr r3, [pc, #492] ; (800859c ) 80083ae: 681b ldr r3, [r3, #0] 80083b0: 08db lsrs r3, r3, #3 80083b2: f003 0303 and.w r3, r3, #3 80083b6: 4a7a ldr r2, [pc, #488] ; (80085a0 ) 80083b8: fa22 f303 lsr.w r3, r2, r3 80083bc: 63fb str r3, [r7, #60] ; 0x3c 80083be: e01e b.n 80083fe } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 80083c0: 4b76 ldr r3, [pc, #472] ; (800859c ) 80083c2: 681b ldr r3, [r3, #0] 80083c4: f403 7380 and.w r3, r3, #256 ; 0x100 80083c8: f5b3 7f80 cmp.w r3, #256 ; 0x100 80083cc: d106 bne.n 80083dc 80083ce: 6b7b ldr r3, [r7, #52] ; 0x34 80083d0: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 80083d4: d102 bne.n 80083dc { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 80083d6: 4b73 ldr r3, [pc, #460] ; (80085a4 ) 80083d8: 63fb str r3, [r7, #60] ; 0x3c 80083da: e010 b.n 80083fe } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 80083dc: 4b6f ldr r3, [pc, #444] ; (800859c ) 80083de: 681b ldr r3, [r3, #0] 80083e0: f403 3300 and.w r3, r3, #131072 ; 0x20000 80083e4: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 80083e8: d106 bne.n 80083f8 80083ea: 6b7b ldr r3, [r7, #52] ; 0x34 80083ec: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 80083f0: d102 bne.n 80083f8 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 80083f2: 4b6d ldr r3, [pc, #436] ; (80085a8 ) 80083f4: 63fb str r3, [r7, #60] ; 0x3c 80083f6: e002 b.n 80083fe } else { /* In Case the CKPER is disabled*/ frequency = 0; 80083f8: 2300 movs r3, #0 80083fa: 63fb str r3, [r7, #60] ; 0x3c } break; 80083fc: e397 b.n 8008b2e 80083fe: e396 b.n 8008b2e } case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */ { frequency = EXTERNAL_CLOCK_VALUE; 8008400: 4b6a ldr r3, [pc, #424] ; (80085ac ) 8008402: 63fb str r3, [r7, #60] ; 0x3c break; 8008404: e393 b.n 8008b2e } default : { frequency = 0; 8008406: 2300 movs r3, #0 8008408: 63fb str r3, [r7, #60] ; 0x3c break; 800840a: e390 b.n 8008b2e } #endif /* SAI3 */ #if defined(RCC_CDCCIP1R_SAI2ASEL) else if (PeriphClk == RCC_PERIPHCLK_SAI2A) 800840c: 687b ldr r3, [r7, #4] 800840e: f5b3 7f00 cmp.w r3, #512 ; 0x200 8008412: f040 8095 bne.w 8008540 { saiclocksource= __HAL_RCC_GET_SAI2A_SOURCE(); 8008416: 4b61 ldr r3, [pc, #388] ; (800859c ) 8008418: 6d1b ldr r3, [r3, #80] ; 0x50 800841a: f403 73e0 and.w r3, r3, #448 ; 0x1c0 800841e: 633b str r3, [r7, #48] ; 0x30 switch (saiclocksource) 8008420: 6b3b ldr r3, [r7, #48] ; 0x30 8008422: f5b3 7f80 cmp.w r3, #256 ; 0x100 8008426: d04d beq.n 80084c4 8008428: 6b3b ldr r3, [r7, #48] ; 0x30 800842a: f5b3 7f80 cmp.w r3, #256 ; 0x100 800842e: f200 8084 bhi.w 800853a 8008432: 6b3b ldr r3, [r7, #48] ; 0x30 8008434: 2bc0 cmp r3, #192 ; 0xc0 8008436: d07d beq.n 8008534 8008438: 6b3b ldr r3, [r7, #48] ; 0x30 800843a: 2bc0 cmp r3, #192 ; 0xc0 800843c: d87d bhi.n 800853a 800843e: 6b3b ldr r3, [r7, #48] ; 0x30 8008440: 2b80 cmp r3, #128 ; 0x80 8008442: d02d beq.n 80084a0 8008444: 6b3b ldr r3, [r7, #48] ; 0x30 8008446: 2b80 cmp r3, #128 ; 0x80 8008448: d877 bhi.n 800853a 800844a: 6b3b ldr r3, [r7, #48] ; 0x30 800844c: 2b00 cmp r3, #0 800844e: d003 beq.n 8008458 8008450: 6b3b ldr r3, [r7, #48] ; 0x30 8008452: 2b40 cmp r3, #64 ; 0x40 8008454: d012 beq.n 800847c 8008456: e070 b.n 800853a { case RCC_SAI2ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI2A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 8008458: 4b50 ldr r3, [pc, #320] ; (800859c ) 800845a: 681b ldr r3, [r3, #0] 800845c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8008460: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 8008464: d107 bne.n 8008476 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 8008466: f107 0324 add.w r3, r7, #36 ; 0x24 800846a: 4618 mov r0, r3 800846c: f000 fe24 bl 80090b8 frequency = pll1_clocks.PLL1_Q_Frequency; 8008470: 6abb ldr r3, [r7, #40] ; 0x28 8008472: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8008474: e35b b.n 8008b2e frequency = 0; 8008476: 2300 movs r3, #0 8008478: 63fb str r3, [r7, #60] ; 0x3c break; 800847a: e358 b.n 8008b2e } case RCC_SAI2ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800847c: 4b47 ldr r3, [pc, #284] ; (800859c ) 800847e: 681b ldr r3, [r3, #0] 8008480: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8008484: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 8008488: d107 bne.n 800849a { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800848a: f107 0318 add.w r3, r7, #24 800848e: 4618 mov r0, r3 8008490: f000 fb6a bl 8008b68 frequency = pll2_clocks.PLL2_P_Frequency; 8008494: 69bb ldr r3, [r7, #24] 8008496: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8008498: e349 b.n 8008b2e frequency = 0; 800849a: 2300 movs r3, #0 800849c: 63fb str r3, [r7, #60] ; 0x3c break; 800849e: e346 b.n 8008b2e } case RCC_SAI2ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 80084a0: 4b3e ldr r3, [pc, #248] ; (800859c ) 80084a2: 681b ldr r3, [r3, #0] 80084a4: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 80084a8: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 80084ac: d107 bne.n 80084be { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 80084ae: f107 030c add.w r3, r7, #12 80084b2: 4618 mov r0, r3 80084b4: f000 fcac bl 8008e10 frequency = pll3_clocks.PLL3_P_Frequency; 80084b8: 68fb ldr r3, [r7, #12] 80084ba: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 80084bc: e337 b.n 8008b2e frequency = 0; 80084be: 2300 movs r3, #0 80084c0: 63fb str r3, [r7, #60] ; 0x3c break; 80084c2: e334 b.n 8008b2e } case RCC_SAI2ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI2A */ { ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); 80084c4: 4b35 ldr r3, [pc, #212] ; (800859c ) 80084c6: 6cdb ldr r3, [r3, #76] ; 0x4c 80084c8: f003 5340 and.w r3, r3, #805306368 ; 0x30000000 80084cc: 637b str r3, [r7, #52] ; 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 80084ce: 4b33 ldr r3, [pc, #204] ; (800859c ) 80084d0: 681b ldr r3, [r3, #0] 80084d2: f003 0304 and.w r3, r3, #4 80084d6: 2b04 cmp r3, #4 80084d8: d10c bne.n 80084f4 80084da: 6b7b ldr r3, [r7, #52] ; 0x34 80084dc: 2b00 cmp r3, #0 80084de: d109 bne.n 80084f4 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 80084e0: 4b2e ldr r3, [pc, #184] ; (800859c ) 80084e2: 681b ldr r3, [r3, #0] 80084e4: 08db lsrs r3, r3, #3 80084e6: f003 0303 and.w r3, r3, #3 80084ea: 4a2d ldr r2, [pc, #180] ; (80085a0 ) 80084ec: fa22 f303 lsr.w r3, r2, r3 80084f0: 63fb str r3, [r7, #60] ; 0x3c 80084f2: e01e b.n 8008532 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 80084f4: 4b29 ldr r3, [pc, #164] ; (800859c ) 80084f6: 681b ldr r3, [r3, #0] 80084f8: f403 7380 and.w r3, r3, #256 ; 0x100 80084fc: f5b3 7f80 cmp.w r3, #256 ; 0x100 8008500: d106 bne.n 8008510 8008502: 6b7b ldr r3, [r7, #52] ; 0x34 8008504: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 8008508: d102 bne.n 8008510 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800850a: 4b26 ldr r3, [pc, #152] ; (80085a4 ) 800850c: 63fb str r3, [r7, #60] ; 0x3c 800850e: e010 b.n 8008532 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 8008510: 4b22 ldr r3, [pc, #136] ; (800859c ) 8008512: 681b ldr r3, [r3, #0] 8008514: f403 3300 and.w r3, r3, #131072 ; 0x20000 8008518: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 800851c: d106 bne.n 800852c 800851e: 6b7b ldr r3, [r7, #52] ; 0x34 8008520: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8008524: d102 bne.n 800852c { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 8008526: 4b20 ldr r3, [pc, #128] ; (80085a8 ) 8008528: 63fb str r3, [r7, #60] ; 0x3c 800852a: e002 b.n 8008532 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800852c: 2300 movs r3, #0 800852e: 63fb str r3, [r7, #60] ; 0x3c } break; 8008530: e2fd b.n 8008b2e 8008532: e2fc b.n 8008b2e } case (RCC_SAI2ACLKSOURCE_PIN): /* External clock is the clock source for SAI2A */ { frequency = EXTERNAL_CLOCK_VALUE; 8008534: 4b1d ldr r3, [pc, #116] ; (80085ac ) 8008536: 63fb str r3, [r7, #60] ; 0x3c break; 8008538: e2f9 b.n 8008b2e } default : { frequency = 0; 800853a: 2300 movs r3, #0 800853c: 63fb str r3, [r7, #60] ; 0x3c break; 800853e: e2f6 b.n 8008b2e } #endif #if defined(RCC_CDCCIP1R_SAI2BSEL_0) else if (PeriphClk == RCC_PERIPHCLK_SAI2B) 8008540: 687b ldr r3, [r7, #4] 8008542: f5b3 6f80 cmp.w r3, #1024 ; 0x400 8008546: f040 80a7 bne.w 8008698 { saiclocksource= __HAL_RCC_GET_SAI2B_SOURCE(); 800854a: 4b14 ldr r3, [pc, #80] ; (800859c ) 800854c: 6d1b ldr r3, [r3, #80] ; 0x50 800854e: f403 6360 and.w r3, r3, #3584 ; 0xe00 8008552: 633b str r3, [r7, #48] ; 0x30 switch (saiclocksource) 8008554: 6b3b ldr r3, [r7, #48] ; 0x30 8008556: f5b3 6f00 cmp.w r3, #2048 ; 0x800 800855a: d05f beq.n 800861c 800855c: 6b3b ldr r3, [r7, #48] ; 0x30 800855e: f5b3 6f00 cmp.w r3, #2048 ; 0x800 8008562: f200 8096 bhi.w 8008692 8008566: 6b3b ldr r3, [r7, #48] ; 0x30 8008568: f5b3 6fc0 cmp.w r3, #1536 ; 0x600 800856c: f000 808e beq.w 800868c 8008570: 6b3b ldr r3, [r7, #48] ; 0x30 8008572: f5b3 6fc0 cmp.w r3, #1536 ; 0x600 8008576: f200 808c bhi.w 8008692 800857a: 6b3b ldr r3, [r7, #48] ; 0x30 800857c: f5b3 6f80 cmp.w r3, #1024 ; 0x400 8008580: d03a beq.n 80085f8 8008582: 6b3b ldr r3, [r7, #48] ; 0x30 8008584: f5b3 6f80 cmp.w r3, #1024 ; 0x400 8008588: f200 8083 bhi.w 8008692 800858c: 6b3b ldr r3, [r7, #48] ; 0x30 800858e: 2b00 cmp r3, #0 8008590: d00e beq.n 80085b0 8008592: 6b3b ldr r3, [r7, #48] ; 0x30 8008594: f5b3 7f00 cmp.w r3, #512 ; 0x200 8008598: d01c beq.n 80085d4 800859a: e07a b.n 8008692 800859c: 58024400 .word 0x58024400 80085a0: 03d09000 .word 0x03d09000 80085a4: 003d0900 .word 0x003d0900 80085a8: 016e3600 .word 0x016e3600 80085ac: 00bb8000 .word 0x00bb8000 { case RCC_SAI2BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI2B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 80085b0: 4ba8 ldr r3, [pc, #672] ; (8008854 ) 80085b2: 681b ldr r3, [r3, #0] 80085b4: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80085b8: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 80085bc: d107 bne.n 80085ce { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 80085be: f107 0324 add.w r3, r7, #36 ; 0x24 80085c2: 4618 mov r0, r3 80085c4: f000 fd78 bl 80090b8 frequency = pll1_clocks.PLL1_Q_Frequency; 80085c8: 6abb ldr r3, [r7, #40] ; 0x28 80085ca: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 80085cc: e2af b.n 8008b2e frequency = 0; 80085ce: 2300 movs r3, #0 80085d0: 63fb str r3, [r7, #60] ; 0x3c break; 80085d2: e2ac b.n 8008b2e } case RCC_SAI2BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 80085d4: 4b9f ldr r3, [pc, #636] ; (8008854 ) 80085d6: 681b ldr r3, [r3, #0] 80085d8: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 80085dc: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 80085e0: d107 bne.n 80085f2 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 80085e2: f107 0318 add.w r3, r7, #24 80085e6: 4618 mov r0, r3 80085e8: f000 fabe bl 8008b68 frequency = pll2_clocks.PLL2_P_Frequency; 80085ec: 69bb ldr r3, [r7, #24] 80085ee: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 80085f0: e29d b.n 8008b2e frequency = 0; 80085f2: 2300 movs r3, #0 80085f4: 63fb str r3, [r7, #60] ; 0x3c break; 80085f6: e29a b.n 8008b2e } case RCC_SAI2BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 80085f8: 4b96 ldr r3, [pc, #600] ; (8008854 ) 80085fa: 681b ldr r3, [r3, #0] 80085fc: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 8008600: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8008604: d107 bne.n 8008616 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8008606: f107 030c add.w r3, r7, #12 800860a: 4618 mov r0, r3 800860c: f000 fc00 bl 8008e10 frequency = pll3_clocks.PLL3_P_Frequency; 8008610: 68fb ldr r3, [r7, #12] 8008612: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8008614: e28b b.n 8008b2e frequency = 0; 8008616: 2300 movs r3, #0 8008618: 63fb str r3, [r7, #60] ; 0x3c break; 800861a: e288 b.n 8008b2e } case RCC_SAI2BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI2B*/ { ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); 800861c: 4b8d ldr r3, [pc, #564] ; (8008854 ) 800861e: 6cdb ldr r3, [r3, #76] ; 0x4c 8008620: f003 5340 and.w r3, r3, #805306368 ; 0x30000000 8008624: 637b str r3, [r7, #52] ; 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 8008626: 4b8b ldr r3, [pc, #556] ; (8008854 ) 8008628: 681b ldr r3, [r3, #0] 800862a: f003 0304 and.w r3, r3, #4 800862e: 2b04 cmp r3, #4 8008630: d10c bne.n 800864c 8008632: 6b7b ldr r3, [r7, #52] ; 0x34 8008634: 2b00 cmp r3, #0 8008636: d109 bne.n 800864c { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 8008638: 4b86 ldr r3, [pc, #536] ; (8008854 ) 800863a: 681b ldr r3, [r3, #0] 800863c: 08db lsrs r3, r3, #3 800863e: f003 0303 and.w r3, r3, #3 8008642: 4a85 ldr r2, [pc, #532] ; (8008858 ) 8008644: fa22 f303 lsr.w r3, r2, r3 8008648: 63fb str r3, [r7, #60] ; 0x3c 800864a: e01e b.n 800868a } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800864c: 4b81 ldr r3, [pc, #516] ; (8008854 ) 800864e: 681b ldr r3, [r3, #0] 8008650: f403 7380 and.w r3, r3, #256 ; 0x100 8008654: f5b3 7f80 cmp.w r3, #256 ; 0x100 8008658: d106 bne.n 8008668 800865a: 6b7b ldr r3, [r7, #52] ; 0x34 800865c: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 8008660: d102 bne.n 8008668 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 8008662: 4b7e ldr r3, [pc, #504] ; (800885c ) 8008664: 63fb str r3, [r7, #60] ; 0x3c 8008666: e010 b.n 800868a } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 8008668: 4b7a ldr r3, [pc, #488] ; (8008854 ) 800866a: 681b ldr r3, [r3, #0] 800866c: f403 3300 and.w r3, r3, #131072 ; 0x20000 8008670: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 8008674: d106 bne.n 8008684 8008676: 6b7b ldr r3, [r7, #52] ; 0x34 8008678: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 800867c: d102 bne.n 8008684 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800867e: 4b78 ldr r3, [pc, #480] ; (8008860 ) 8008680: 63fb str r3, [r7, #60] ; 0x3c 8008682: e002 b.n 800868a } else { /* In Case the CKPER is disabled*/ frequency = 0; 8008684: 2300 movs r3, #0 8008686: 63fb str r3, [r7, #60] ; 0x3c } break; 8008688: e251 b.n 8008b2e 800868a: e250 b.n 8008b2e } case (RCC_SAI2BCLKSOURCE_PIN): /* External clock is the clock source for SAI2B */ { frequency = EXTERNAL_CLOCK_VALUE; 800868c: 4b75 ldr r3, [pc, #468] ; (8008864 ) 800868e: 63fb str r3, [r7, #60] ; 0x3c break; 8008690: e24d b.n 8008b2e } default : { frequency = 0; 8008692: 2300 movs r3, #0 8008694: 63fb str r3, [r7, #60] ; 0x3c break; 8008696: e24a b.n 8008b2e break; } } } #endif /*SAI4*/ else if (PeriphClk == RCC_PERIPHCLK_SPI123) 8008698: 687b ldr r3, [r7, #4] 800869a: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 800869e: f040 809c bne.w 80087da { /* Get SPI1/2/3 clock source */ srcclk= __HAL_RCC_GET_SPI123_SOURCE(); 80086a2: 4b6c ldr r3, [pc, #432] ; (8008854 ) 80086a4: 6d1b ldr r3, [r3, #80] ; 0x50 80086a6: f403 43e0 and.w r3, r3, #28672 ; 0x7000 80086aa: 63bb str r3, [r7, #56] ; 0x38 switch (srcclk) 80086ac: 6bbb ldr r3, [r7, #56] ; 0x38 80086ae: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 80086b2: d054 beq.n 800875e 80086b4: 6bbb ldr r3, [r7, #56] ; 0x38 80086b6: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 80086ba: f200 808b bhi.w 80087d4 80086be: 6bbb ldr r3, [r7, #56] ; 0x38 80086c0: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 80086c4: f000 8083 beq.w 80087ce 80086c8: 6bbb ldr r3, [r7, #56] ; 0x38 80086ca: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 80086ce: f200 8081 bhi.w 80087d4 80086d2: 6bbb ldr r3, [r7, #56] ; 0x38 80086d4: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 80086d8: d02f beq.n 800873a 80086da: 6bbb ldr r3, [r7, #56] ; 0x38 80086dc: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 80086e0: d878 bhi.n 80087d4 80086e2: 6bbb ldr r3, [r7, #56] ; 0x38 80086e4: 2b00 cmp r3, #0 80086e6: d004 beq.n 80086f2 80086e8: 6bbb ldr r3, [r7, #56] ; 0x38 80086ea: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 80086ee: d012 beq.n 8008716 80086f0: e070 b.n 80087d4 { case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 80086f2: 4b58 ldr r3, [pc, #352] ; (8008854 ) 80086f4: 681b ldr r3, [r3, #0] 80086f6: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80086fa: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 80086fe: d107 bne.n 8008710 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 8008700: f107 0324 add.w r3, r7, #36 ; 0x24 8008704: 4618 mov r0, r3 8008706: f000 fcd7 bl 80090b8 frequency = pll1_clocks.PLL1_Q_Frequency; 800870a: 6abb ldr r3, [r7, #40] ; 0x28 800870c: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 800870e: e20e b.n 8008b2e frequency = 0; 8008710: 2300 movs r3, #0 8008712: 63fb str r3, [r7, #60] ; 0x3c break; 8008714: e20b b.n 8008b2e } case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 8008716: 4b4f ldr r3, [pc, #316] ; (8008854 ) 8008718: 681b ldr r3, [r3, #0] 800871a: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 800871e: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 8008722: d107 bne.n 8008734 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8008724: f107 0318 add.w r3, r7, #24 8008728: 4618 mov r0, r3 800872a: f000 fa1d bl 8008b68 frequency = pll2_clocks.PLL2_P_Frequency; 800872e: 69bb ldr r3, [r7, #24] 8008730: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8008732: e1fc b.n 8008b2e frequency = 0; 8008734: 2300 movs r3, #0 8008736: 63fb str r3, [r7, #60] ; 0x3c break; 8008738: e1f9 b.n 8008b2e } case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800873a: 4b46 ldr r3, [pc, #280] ; (8008854 ) 800873c: 681b ldr r3, [r3, #0] 800873e: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 8008742: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8008746: d107 bne.n 8008758 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8008748: f107 030c add.w r3, r7, #12 800874c: 4618 mov r0, r3 800874e: f000 fb5f bl 8008e10 frequency = pll3_clocks.PLL3_P_Frequency; 8008752: 68fb ldr r3, [r7, #12] 8008754: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8008756: e1ea b.n 8008b2e frequency = 0; 8008758: 2300 movs r3, #0 800875a: 63fb str r3, [r7, #60] ; 0x3c break; 800875c: e1e7 b.n 8008b2e } case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for SPI123 */ { ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); 800875e: 4b3d ldr r3, [pc, #244] ; (8008854 ) 8008760: 6cdb ldr r3, [r3, #76] ; 0x4c 8008762: f003 5340 and.w r3, r3, #805306368 ; 0x30000000 8008766: 637b str r3, [r7, #52] ; 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 8008768: 4b3a ldr r3, [pc, #232] ; (8008854 ) 800876a: 681b ldr r3, [r3, #0] 800876c: f003 0304 and.w r3, r3, #4 8008770: 2b04 cmp r3, #4 8008772: d10c bne.n 800878e 8008774: 6b7b ldr r3, [r7, #52] ; 0x34 8008776: 2b00 cmp r3, #0 8008778: d109 bne.n 800878e { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 800877a: 4b36 ldr r3, [pc, #216] ; (8008854 ) 800877c: 681b ldr r3, [r3, #0] 800877e: 08db lsrs r3, r3, #3 8008780: f003 0303 and.w r3, r3, #3 8008784: 4a34 ldr r2, [pc, #208] ; (8008858 ) 8008786: fa22 f303 lsr.w r3, r2, r3 800878a: 63fb str r3, [r7, #60] ; 0x3c 800878c: e01e b.n 80087cc } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800878e: 4b31 ldr r3, [pc, #196] ; (8008854 ) 8008790: 681b ldr r3, [r3, #0] 8008792: f403 7380 and.w r3, r3, #256 ; 0x100 8008796: f5b3 7f80 cmp.w r3, #256 ; 0x100 800879a: d106 bne.n 80087aa 800879c: 6b7b ldr r3, [r7, #52] ; 0x34 800879e: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 80087a2: d102 bne.n 80087aa { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 80087a4: 4b2d ldr r3, [pc, #180] ; (800885c ) 80087a6: 63fb str r3, [r7, #60] ; 0x3c 80087a8: e010 b.n 80087cc } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 80087aa: 4b2a ldr r3, [pc, #168] ; (8008854 ) 80087ac: 681b ldr r3, [r3, #0] 80087ae: f403 3300 and.w r3, r3, #131072 ; 0x20000 80087b2: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 80087b6: d106 bne.n 80087c6 80087b8: 6b7b ldr r3, [r7, #52] ; 0x34 80087ba: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 80087be: d102 bne.n 80087c6 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 80087c0: 4b27 ldr r3, [pc, #156] ; (8008860 ) 80087c2: 63fb str r3, [r7, #60] ; 0x3c 80087c4: e002 b.n 80087cc } else { /* In Case the CKPER is disabled*/ frequency = 0; 80087c6: 2300 movs r3, #0 80087c8: 63fb str r3, [r7, #60] ; 0x3c } break; 80087ca: e1b0 b.n 8008b2e 80087cc: e1af b.n 8008b2e } case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */ { frequency = EXTERNAL_CLOCK_VALUE; 80087ce: 4b25 ldr r3, [pc, #148] ; (8008864 ) 80087d0: 63fb str r3, [r7, #60] ; 0x3c break; 80087d2: e1ac b.n 8008b2e } default : { frequency = 0; 80087d4: 2300 movs r3, #0 80087d6: 63fb str r3, [r7, #60] ; 0x3c break; 80087d8: e1a9 b.n 8008b2e } } } else if (PeriphClk == RCC_PERIPHCLK_ADC) 80087da: 687b ldr r3, [r7, #4] 80087dc: f5b3 2f00 cmp.w r3, #524288 ; 0x80000 80087e0: d17d bne.n 80088de { /* Get ADC clock source */ srcclk= __HAL_RCC_GET_ADC_SOURCE(); 80087e2: 4b1c ldr r3, [pc, #112] ; (8008854 ) 80087e4: 6d9b ldr r3, [r3, #88] ; 0x58 80087e6: f403 3340 and.w r3, r3, #196608 ; 0x30000 80087ea: 63bb str r3, [r7, #56] ; 0x38 switch (srcclk) 80087ec: 6bbb ldr r3, [r7, #56] ; 0x38 80087ee: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 80087f2: d039 beq.n 8008868 80087f4: 6bbb ldr r3, [r7, #56] ; 0x38 80087f6: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 80087fa: d86d bhi.n 80088d8 80087fc: 6bbb ldr r3, [r7, #56] ; 0x38 80087fe: 2b00 cmp r3, #0 8008800: d004 beq.n 800880c 8008802: 6bbb ldr r3, [r7, #56] ; 0x38 8008804: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8008808: d012 beq.n 8008830 800880a: e065 b.n 80088d8 { case RCC_ADCCLKSOURCE_PLL2: { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800880c: 4b11 ldr r3, [pc, #68] ; (8008854 ) 800880e: 681b ldr r3, [r3, #0] 8008810: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8008814: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 8008818: d107 bne.n 800882a { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800881a: f107 0318 add.w r3, r7, #24 800881e: 4618 mov r0, r3 8008820: f000 f9a2 bl 8008b68 frequency = pll2_clocks.PLL2_P_Frequency; 8008824: 69bb ldr r3, [r7, #24] 8008826: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8008828: e181 b.n 8008b2e frequency = 0; 800882a: 2300 movs r3, #0 800882c: 63fb str r3, [r7, #60] ; 0x3c break; 800882e: e17e b.n 8008b2e } case RCC_ADCCLKSOURCE_PLL3: { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 8008830: 4b08 ldr r3, [pc, #32] ; (8008854 ) 8008832: 681b ldr r3, [r3, #0] 8008834: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 8008838: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 800883c: d107 bne.n 800884e { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800883e: f107 030c add.w r3, r7, #12 8008842: 4618 mov r0, r3 8008844: f000 fae4 bl 8008e10 frequency = pll3_clocks.PLL3_R_Frequency; 8008848: 697b ldr r3, [r7, #20] 800884a: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 800884c: e16f b.n 8008b2e frequency = 0; 800884e: 2300 movs r3, #0 8008850: 63fb str r3, [r7, #60] ; 0x3c break; 8008852: e16c b.n 8008b2e 8008854: 58024400 .word 0x58024400 8008858: 03d09000 .word 0x03d09000 800885c: 003d0900 .word 0x003d0900 8008860: 016e3600 .word 0x016e3600 8008864: 00bb8000 .word 0x00bb8000 } case RCC_ADCCLKSOURCE_CLKP: { ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); 8008868: 4ba0 ldr r3, [pc, #640] ; (8008aec ) 800886a: 6cdb ldr r3, [r3, #76] ; 0x4c 800886c: f003 5340 and.w r3, r3, #805306368 ; 0x30000000 8008870: 637b str r3, [r7, #52] ; 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 8008872: 4b9e ldr r3, [pc, #632] ; (8008aec ) 8008874: 681b ldr r3, [r3, #0] 8008876: f003 0304 and.w r3, r3, #4 800887a: 2b04 cmp r3, #4 800887c: d10c bne.n 8008898 800887e: 6b7b ldr r3, [r7, #52] ; 0x34 8008880: 2b00 cmp r3, #0 8008882: d109 bne.n 8008898 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 8008884: 4b99 ldr r3, [pc, #612] ; (8008aec ) 8008886: 681b ldr r3, [r3, #0] 8008888: 08db lsrs r3, r3, #3 800888a: f003 0303 and.w r3, r3, #3 800888e: 4a98 ldr r2, [pc, #608] ; (8008af0 ) 8008890: fa22 f303 lsr.w r3, r2, r3 8008894: 63fb str r3, [r7, #60] ; 0x3c 8008896: e01e b.n 80088d6 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 8008898: 4b94 ldr r3, [pc, #592] ; (8008aec ) 800889a: 681b ldr r3, [r3, #0] 800889c: f403 7380 and.w r3, r3, #256 ; 0x100 80088a0: f5b3 7f80 cmp.w r3, #256 ; 0x100 80088a4: d106 bne.n 80088b4 80088a6: 6b7b ldr r3, [r7, #52] ; 0x34 80088a8: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 80088ac: d102 bne.n 80088b4 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 80088ae: 4b91 ldr r3, [pc, #580] ; (8008af4 ) 80088b0: 63fb str r3, [r7, #60] ; 0x3c 80088b2: e010 b.n 80088d6 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 80088b4: 4b8d ldr r3, [pc, #564] ; (8008aec ) 80088b6: 681b ldr r3, [r3, #0] 80088b8: f403 3300 and.w r3, r3, #131072 ; 0x20000 80088bc: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 80088c0: d106 bne.n 80088d0 80088c2: 6b7b ldr r3, [r7, #52] ; 0x34 80088c4: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 80088c8: d102 bne.n 80088d0 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 80088ca: 4b8b ldr r3, [pc, #556] ; (8008af8 ) 80088cc: 63fb str r3, [r7, #60] ; 0x3c 80088ce: e002 b.n 80088d6 } else { /* In Case the CKPER is disabled*/ frequency = 0; 80088d0: 2300 movs r3, #0 80088d2: 63fb str r3, [r7, #60] ; 0x3c } break; 80088d4: e12b b.n 8008b2e 80088d6: e12a b.n 8008b2e } default : { frequency = 0; 80088d8: 2300 movs r3, #0 80088da: 63fb str r3, [r7, #60] ; 0x3c break; 80088dc: e127 b.n 8008b2e } } } else if (PeriphClk == RCC_PERIPHCLK_SDMMC) 80088de: 687b ldr r3, [r7, #4] 80088e0: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80088e4: d133 bne.n 800894e { /* Get SDMMC clock source */ srcclk= __HAL_RCC_GET_SDMMC_SOURCE(); 80088e6: 4b81 ldr r3, [pc, #516] ; (8008aec ) 80088e8: 6cdb ldr r3, [r3, #76] ; 0x4c 80088ea: f403 3380 and.w r3, r3, #65536 ; 0x10000 80088ee: 63bb str r3, [r7, #56] ; 0x38 switch (srcclk) 80088f0: 6bbb ldr r3, [r7, #56] ; 0x38 80088f2: 2b00 cmp r3, #0 80088f4: d004 beq.n 8008900 80088f6: 6bbb ldr r3, [r7, #56] ; 0x38 80088f8: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80088fc: d012 beq.n 8008924 80088fe: e023 b.n 8008948 { case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 8008900: 4b7a ldr r3, [pc, #488] ; (8008aec ) 8008902: 681b ldr r3, [r3, #0] 8008904: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8008908: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 800890c: d107 bne.n 800891e { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800890e: f107 0324 add.w r3, r7, #36 ; 0x24 8008912: 4618 mov r0, r3 8008914: f000 fbd0 bl 80090b8 frequency = pll1_clocks.PLL1_Q_Frequency; 8008918: 6abb ldr r3, [r7, #40] ; 0x28 800891a: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 800891c: e107 b.n 8008b2e frequency = 0; 800891e: 2300 movs r3, #0 8008920: 63fb str r3, [r7, #60] ; 0x3c break; 8008922: e104 b.n 8008b2e } case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 8008924: 4b71 ldr r3, [pc, #452] ; (8008aec ) 8008926: 681b ldr r3, [r3, #0] 8008928: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 800892c: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 8008930: d107 bne.n 8008942 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8008932: f107 0318 add.w r3, r7, #24 8008936: 4618 mov r0, r3 8008938: f000 f916 bl 8008b68 frequency = pll2_clocks.PLL2_R_Frequency; 800893c: 6a3b ldr r3, [r7, #32] 800893e: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8008940: e0f5 b.n 8008b2e frequency = 0; 8008942: 2300 movs r3, #0 8008944: 63fb str r3, [r7, #60] ; 0x3c break; 8008946: e0f2 b.n 8008b2e } default : { frequency = 0; 8008948: 2300 movs r3, #0 800894a: 63fb str r3, [r7, #60] ; 0x3c break; 800894c: e0ef b.n 8008b2e } } } else if (PeriphClk == RCC_PERIPHCLK_SPI6) 800894e: 687b ldr r3, [r7, #4] 8008950: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 8008954: f040 8091 bne.w 8008a7a { /* Get SPI6 clock source */ srcclk= __HAL_RCC_GET_SPI6_SOURCE(); 8008958: 4b64 ldr r3, [pc, #400] ; (8008aec ) 800895a: 6d9b ldr r3, [r3, #88] ; 0x58 800895c: f003 43e0 and.w r3, r3, #1879048192 ; 0x70000000 8008960: 63bb str r3, [r7, #56] ; 0x38 switch (srcclk) 8008962: 6bbb ldr r3, [r7, #56] ; 0x38 8008964: f1b3 4fc0 cmp.w r3, #1610612736 ; 0x60000000 8008968: f000 8081 beq.w 8008a6e 800896c: 6bbb ldr r3, [r7, #56] ; 0x38 800896e: f1b3 4fc0 cmp.w r3, #1610612736 ; 0x60000000 8008972: d87f bhi.n 8008a74 8008974: 6bbb ldr r3, [r7, #56] ; 0x38 8008976: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 800897a: d06b beq.n 8008a54 800897c: 6bbb ldr r3, [r7, #56] ; 0x38 800897e: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 8008982: d877 bhi.n 8008a74 8008984: 6bbb ldr r3, [r7, #56] ; 0x38 8008986: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 800898a: d056 beq.n 8008a3a 800898c: 6bbb ldr r3, [r7, #56] ; 0x38 800898e: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8008992: d86f bhi.n 8008a74 8008994: 6bbb ldr r3, [r7, #56] ; 0x38 8008996: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 800899a: d03b beq.n 8008a14 800899c: 6bbb ldr r3, [r7, #56] ; 0x38 800899e: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 80089a2: d867 bhi.n 8008a74 80089a4: 6bbb ldr r3, [r7, #56] ; 0x38 80089a6: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 80089aa: d021 beq.n 80089f0 80089ac: 6bbb ldr r3, [r7, #56] ; 0x38 80089ae: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 80089b2: d85f bhi.n 8008a74 80089b4: 6bbb ldr r3, [r7, #56] ; 0x38 80089b6: 2b00 cmp r3, #0 80089b8: d004 beq.n 80089c4 80089ba: 6bbb ldr r3, [r7, #56] ; 0x38 80089bc: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 80089c0: d004 beq.n 80089cc 80089c2: e057 b.n 8008a74 { case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */ { frequency = HAL_RCCEx_GetD3PCLK1Freq(); 80089c4: f000 f8ba bl 8008b3c 80089c8: 63f8 str r0, [r7, #60] ; 0x3c break; 80089ca: e0b0 b.n 8008b2e } case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 80089cc: 4b47 ldr r3, [pc, #284] ; (8008aec ) 80089ce: 681b ldr r3, [r3, #0] 80089d0: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 80089d4: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 80089d8: d107 bne.n 80089ea { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 80089da: f107 0318 add.w r3, r7, #24 80089de: 4618 mov r0, r3 80089e0: f000 f8c2 bl 8008b68 frequency = pll2_clocks.PLL2_Q_Frequency; 80089e4: 69fb ldr r3, [r7, #28] 80089e6: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 80089e8: e0a1 b.n 8008b2e frequency = 0; 80089ea: 2300 movs r3, #0 80089ec: 63fb str r3, [r7, #60] ; 0x3c break; 80089ee: e09e b.n 8008b2e } case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 80089f0: 4b3e ldr r3, [pc, #248] ; (8008aec ) 80089f2: 681b ldr r3, [r3, #0] 80089f4: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 80089f8: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 80089fc: d107 bne.n 8008a0e { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 80089fe: f107 030c add.w r3, r7, #12 8008a02: 4618 mov r0, r3 8008a04: f000 fa04 bl 8008e10 frequency = pll3_clocks.PLL3_Q_Frequency; 8008a08: 693b ldr r3, [r7, #16] 8008a0a: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8008a0c: e08f b.n 8008b2e frequency = 0; 8008a0e: 2300 movs r3, #0 8008a10: 63fb str r3, [r7, #60] ; 0x3c break; 8008a12: e08c b.n 8008b2e } case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 8008a14: 4b35 ldr r3, [pc, #212] ; (8008aec ) 8008a16: 681b ldr r3, [r3, #0] 8008a18: f003 0304 and.w r3, r3, #4 8008a1c: 2b04 cmp r3, #4 8008a1e: d109 bne.n 8008a34 { frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 8008a20: 4b32 ldr r3, [pc, #200] ; (8008aec ) 8008a22: 681b ldr r3, [r3, #0] 8008a24: 08db lsrs r3, r3, #3 8008a26: f003 0303 and.w r3, r3, #3 8008a2a: 4a31 ldr r2, [pc, #196] ; (8008af0 ) 8008a2c: fa22 f303 lsr.w r3, r2, r3 8008a30: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8008a32: e07c b.n 8008b2e frequency = 0; 8008a34: 2300 movs r3, #0 8008a36: 63fb str r3, [r7, #60] ; 0x3c break; 8008a38: e079 b.n 8008b2e } case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) 8008a3a: 4b2c ldr r3, [pc, #176] ; (8008aec ) 8008a3c: 681b ldr r3, [r3, #0] 8008a3e: f403 7380 and.w r3, r3, #256 ; 0x100 8008a42: f5b3 7f80 cmp.w r3, #256 ; 0x100 8008a46: d102 bne.n 8008a4e { frequency = CSI_VALUE; 8008a48: 4b2a ldr r3, [pc, #168] ; (8008af4 ) 8008a4a: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8008a4c: e06f b.n 8008b2e frequency = 0; 8008a4e: 2300 movs r3, #0 8008a50: 63fb str r3, [r7, #60] ; 0x3c break; 8008a52: e06c b.n 8008b2e } case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 8008a54: 4b25 ldr r3, [pc, #148] ; (8008aec ) 8008a56: 681b ldr r3, [r3, #0] 8008a58: f403 3300 and.w r3, r3, #131072 ; 0x20000 8008a5c: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 8008a60: d102 bne.n 8008a68 { frequency = HSE_VALUE; 8008a62: 4b25 ldr r3, [pc, #148] ; (8008af8 ) 8008a64: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8008a66: e062 b.n 8008b2e frequency = 0; 8008a68: 2300 movs r3, #0 8008a6a: 63fb str r3, [r7, #60] ; 0x3c break; 8008a6c: e05f b.n 8008b2e } #if defined(RCC_SPI6CLKSOURCE_PIN) case RCC_SPI6CLKSOURCE_PIN: /* External clock is the clock source for SPI6 */ { frequency = EXTERNAL_CLOCK_VALUE; 8008a6e: 4b23 ldr r3, [pc, #140] ; (8008afc ) 8008a70: 63fb str r3, [r7, #60] ; 0x3c break; 8008a72: e05c b.n 8008b2e } #endif /* RCC_SPI6CLKSOURCE_PIN */ default : { frequency = 0; 8008a74: 2300 movs r3, #0 8008a76: 63fb str r3, [r7, #60] ; 0x3c break; 8008a78: e059 b.n 8008b2e } } } else if (PeriphClk == RCC_PERIPHCLK_FDCAN) 8008a7a: 687b ldr r3, [r7, #4] 8008a7c: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 8008a80: d153 bne.n 8008b2a { /* Get FDCAN clock source */ srcclk= __HAL_RCC_GET_FDCAN_SOURCE(); 8008a82: 4b1a ldr r3, [pc, #104] ; (8008aec ) 8008a84: 6d1b ldr r3, [r3, #80] ; 0x50 8008a86: f003 5340 and.w r3, r3, #805306368 ; 0x30000000 8008a8a: 63bb str r3, [r7, #56] ; 0x38 switch (srcclk) 8008a8c: 6bbb ldr r3, [r7, #56] ; 0x38 8008a8e: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8008a92: d035 beq.n 8008b00 8008a94: 6bbb ldr r3, [r7, #56] ; 0x38 8008a96: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8008a9a: d843 bhi.n 8008b24 8008a9c: 6bbb ldr r3, [r7, #56] ; 0x38 8008a9e: 2b00 cmp r3, #0 8008aa0: d004 beq.n 8008aac 8008aa2: 6bbb ldr r3, [r7, #56] ; 0x38 8008aa4: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 8008aa8: d00d beq.n 8008ac6 8008aaa: e03b b.n 8008b24 { case RCC_FDCANCLKSOURCE_HSE: /* HSE is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 8008aac: 4b0f ldr r3, [pc, #60] ; (8008aec ) 8008aae: 681b ldr r3, [r3, #0] 8008ab0: f403 3300 and.w r3, r3, #131072 ; 0x20000 8008ab4: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 8008ab8: d102 bne.n 8008ac0 { frequency = HSE_VALUE; 8008aba: 4b0f ldr r3, [pc, #60] ; (8008af8 ) 8008abc: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8008abe: e036 b.n 8008b2e frequency = 0; 8008ac0: 2300 movs r3, #0 8008ac2: 63fb str r3, [r7, #60] ; 0x3c break; 8008ac4: e033 b.n 8008b2e } case RCC_FDCANCLKSOURCE_PLL: /* PLL is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 8008ac6: 4b09 ldr r3, [pc, #36] ; (8008aec ) 8008ac8: 681b ldr r3, [r3, #0] 8008aca: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8008ace: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 8008ad2: d107 bne.n 8008ae4 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 8008ad4: f107 0324 add.w r3, r7, #36 ; 0x24 8008ad8: 4618 mov r0, r3 8008ada: f000 faed bl 80090b8 frequency = pll1_clocks.PLL1_Q_Frequency; 8008ade: 6abb ldr r3, [r7, #40] ; 0x28 8008ae0: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8008ae2: e024 b.n 8008b2e frequency = 0; 8008ae4: 2300 movs r3, #0 8008ae6: 63fb str r3, [r7, #60] ; 0x3c break; 8008ae8: e021 b.n 8008b2e 8008aea: bf00 nop 8008aec: 58024400 .word 0x58024400 8008af0: 03d09000 .word 0x03d09000 8008af4: 003d0900 .word 0x003d0900 8008af8: 016e3600 .word 0x016e3600 8008afc: 00bb8000 .word 0x00bb8000 } case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 8008b00: 4b0d ldr r3, [pc, #52] ; (8008b38 ) 8008b02: 681b ldr r3, [r3, #0] 8008b04: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8008b08: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 8008b0c: d107 bne.n 8008b1e { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8008b0e: f107 0318 add.w r3, r7, #24 8008b12: 4618 mov r0, r3 8008b14: f000 f828 bl 8008b68 frequency = pll2_clocks.PLL2_Q_Frequency; 8008b18: 69fb ldr r3, [r7, #28] 8008b1a: 63fb str r3, [r7, #60] ; 0x3c } else { frequency = 0; } break; 8008b1c: e007 b.n 8008b2e frequency = 0; 8008b1e: 2300 movs r3, #0 8008b20: 63fb str r3, [r7, #60] ; 0x3c break; 8008b22: e004 b.n 8008b2e } default : { frequency = 0; 8008b24: 2300 movs r3, #0 8008b26: 63fb str r3, [r7, #60] ; 0x3c break; 8008b28: e001 b.n 8008b2e } } } else { frequency = 0; 8008b2a: 2300 movs r3, #0 8008b2c: 63fb str r3, [r7, #60] ; 0x3c } return frequency; 8008b2e: 6bfb ldr r3, [r7, #60] ; 0x3c } 8008b30: 4618 mov r0, r3 8008b32: 3740 adds r7, #64 ; 0x40 8008b34: 46bd mov sp, r7 8008b36: bd80 pop {r7, pc} 8008b38: 58024400 .word 0x58024400 08008b3c : * @note Each time D3PCLK1 changes, this function must be called to update the * right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval D3PCLK1 frequency */ uint32_t HAL_RCCEx_GetD3PCLK1Freq(void) { 8008b3c: b580 push {r7, lr} 8008b3e: af00 add r7, sp, #0 #if defined(RCC_D3CFGR_D3PPRE) /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE)>> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU)); #else /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)>> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU)); 8008b40: f7fe fc6a bl 8007418 8008b44: 4602 mov r2, r0 8008b46: 4b06 ldr r3, [pc, #24] ; (8008b60 ) 8008b48: 6a1b ldr r3, [r3, #32] 8008b4a: 091b lsrs r3, r3, #4 8008b4c: f003 0307 and.w r3, r3, #7 8008b50: 4904 ldr r1, [pc, #16] ; (8008b64 ) 8008b52: 5ccb ldrb r3, [r1, r3] 8008b54: f003 031f and.w r3, r3, #31 8008b58: fa22 f303 lsr.w r3, r2, r3 #endif } 8008b5c: 4618 mov r0, r3 8008b5e: bd80 pop {r7, pc} 8008b60: 58024400 .word 0x58024400 8008b64: 0800e64c .word 0x0800e64c 08008b68 : * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL2_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks) { 8008b68: b480 push {r7} 8008b6a: b089 sub sp, #36 ; 0x24 8008b6c: af00 add r7, sp, #0 8008b6e: 6078 str r0, [r7, #4] float_t fracn2, pll2vco; /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N PLL2xCLK = PLL2_VCO / PLL2x */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 8008b70: 4ba1 ldr r3, [pc, #644] ; (8008df8 ) 8008b72: 6a9b ldr r3, [r3, #40] ; 0x28 8008b74: f003 0303 and.w r3, r3, #3 8008b78: 61bb str r3, [r7, #24] pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> 12); 8008b7a: 4b9f ldr r3, [pc, #636] ; (8008df8 ) 8008b7c: 6a9b ldr r3, [r3, #40] ; 0x28 8008b7e: 0b1b lsrs r3, r3, #12 8008b80: f003 033f and.w r3, r3, #63 ; 0x3f 8008b84: 617b str r3, [r7, #20] pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos; 8008b86: 4b9c ldr r3, [pc, #624] ; (8008df8 ) 8008b88: 6adb ldr r3, [r3, #44] ; 0x2c 8008b8a: 091b lsrs r3, r3, #4 8008b8c: f003 0301 and.w r3, r3, #1 8008b90: 613b str r3, [r7, #16] fracn2 =(float_t)(uint32_t)(pll2fracen* ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2)>> 3)); 8008b92: 4b99 ldr r3, [pc, #612] ; (8008df8 ) 8008b94: 6bdb ldr r3, [r3, #60] ; 0x3c 8008b96: 08db lsrs r3, r3, #3 8008b98: f3c3 030c ubfx r3, r3, #0, #13 8008b9c: 693a ldr r2, [r7, #16] 8008b9e: fb02 f303 mul.w r3, r2, r3 8008ba2: ee07 3a90 vmov s15, r3 8008ba6: eef8 7a67 vcvt.f32.u32 s15, s15 8008baa: edc7 7a03 vstr s15, [r7, #12] if (pll2m != 0U) 8008bae: 697b ldr r3, [r7, #20] 8008bb0: 2b00 cmp r3, #0 8008bb2: f000 8111 beq.w 8008dd8 { switch (pllsource) 8008bb6: 69bb ldr r3, [r7, #24] 8008bb8: 2b02 cmp r3, #2 8008bba: f000 8083 beq.w 8008cc4 8008bbe: 69bb ldr r3, [r7, #24] 8008bc0: 2b02 cmp r3, #2 8008bc2: f200 80a1 bhi.w 8008d08 8008bc6: 69bb ldr r3, [r7, #24] 8008bc8: 2b00 cmp r3, #0 8008bca: d003 beq.n 8008bd4 8008bcc: 69bb ldr r3, [r7, #24] 8008bce: 2b01 cmp r3, #1 8008bd0: d056 beq.n 8008c80 8008bd2: e099 b.n 8008d08 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8008bd4: 4b88 ldr r3, [pc, #544] ; (8008df8 ) 8008bd6: 681b ldr r3, [r3, #0] 8008bd8: f003 0320 and.w r3, r3, #32 8008bdc: 2b00 cmp r3, #0 8008bde: d02d beq.n 8008c3c { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 8008be0: 4b85 ldr r3, [pc, #532] ; (8008df8 ) 8008be2: 681b ldr r3, [r3, #0] 8008be4: 08db lsrs r3, r3, #3 8008be6: f003 0303 and.w r3, r3, #3 8008bea: 4a84 ldr r2, [pc, #528] ; (8008dfc ) 8008bec: fa22 f303 lsr.w r3, r2, r3 8008bf0: 60bb str r3, [r7, #8] pll2vco = ( (float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 ); 8008bf2: 68bb ldr r3, [r7, #8] 8008bf4: ee07 3a90 vmov s15, r3 8008bf8: eef8 6a67 vcvt.f32.u32 s13, s15 8008bfc: 697b ldr r3, [r7, #20] 8008bfe: ee07 3a90 vmov s15, r3 8008c02: eef8 7a67 vcvt.f32.u32 s15, s15 8008c06: ee86 7aa7 vdiv.f32 s14, s13, s15 8008c0a: 4b7b ldr r3, [pc, #492] ; (8008df8 ) 8008c0c: 6b9b ldr r3, [r3, #56] ; 0x38 8008c0e: f3c3 0308 ubfx r3, r3, #0, #9 8008c12: ee07 3a90 vmov s15, r3 8008c16: eef8 6a67 vcvt.f32.u32 s13, s15 8008c1a: ed97 6a03 vldr s12, [r7, #12] 8008c1e: eddf 5a78 vldr s11, [pc, #480] ; 8008e00 8008c22: eec6 7a25 vdiv.f32 s15, s12, s11 8008c26: ee76 7aa7 vadd.f32 s15, s13, s15 8008c2a: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8008c2e: ee77 7aa6 vadd.f32 s15, s15, s13 8008c32: ee67 7a27 vmul.f32 s15, s14, s15 8008c36: edc7 7a07 vstr s15, [r7, #28] } else { pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 ); } break; 8008c3a: e087 b.n 8008d4c pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 ); 8008c3c: 697b ldr r3, [r7, #20] 8008c3e: ee07 3a90 vmov s15, r3 8008c42: eef8 7a67 vcvt.f32.u32 s15, s15 8008c46: eddf 6a6f vldr s13, [pc, #444] ; 8008e04 8008c4a: ee86 7aa7 vdiv.f32 s14, s13, s15 8008c4e: 4b6a ldr r3, [pc, #424] ; (8008df8 ) 8008c50: 6b9b ldr r3, [r3, #56] ; 0x38 8008c52: f3c3 0308 ubfx r3, r3, #0, #9 8008c56: ee07 3a90 vmov s15, r3 8008c5a: eef8 6a67 vcvt.f32.u32 s13, s15 8008c5e: ed97 6a03 vldr s12, [r7, #12] 8008c62: eddf 5a67 vldr s11, [pc, #412] ; 8008e00 8008c66: eec6 7a25 vdiv.f32 s15, s12, s11 8008c6a: ee76 7aa7 vadd.f32 s15, s13, s15 8008c6e: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8008c72: ee77 7aa6 vadd.f32 s15, s15, s13 8008c76: ee67 7a27 vmul.f32 s15, s14, s15 8008c7a: edc7 7a07 vstr s15, [r7, #28] break; 8008c7e: e065 b.n 8008d4c case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 ); 8008c80: 697b ldr r3, [r7, #20] 8008c82: ee07 3a90 vmov s15, r3 8008c86: eef8 7a67 vcvt.f32.u32 s15, s15 8008c8a: eddf 6a5f vldr s13, [pc, #380] ; 8008e08 8008c8e: ee86 7aa7 vdiv.f32 s14, s13, s15 8008c92: 4b59 ldr r3, [pc, #356] ; (8008df8 ) 8008c94: 6b9b ldr r3, [r3, #56] ; 0x38 8008c96: f3c3 0308 ubfx r3, r3, #0, #9 8008c9a: ee07 3a90 vmov s15, r3 8008c9e: eef8 6a67 vcvt.f32.u32 s13, s15 8008ca2: ed97 6a03 vldr s12, [r7, #12] 8008ca6: eddf 5a56 vldr s11, [pc, #344] ; 8008e00 8008caa: eec6 7a25 vdiv.f32 s15, s12, s11 8008cae: ee76 7aa7 vadd.f32 s15, s13, s15 8008cb2: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8008cb6: ee77 7aa6 vadd.f32 s15, s15, s13 8008cba: ee67 7a27 vmul.f32 s15, s14, s15 8008cbe: edc7 7a07 vstr s15, [r7, #28] break; 8008cc2: e043 b.n 8008d4c case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 ); 8008cc4: 697b ldr r3, [r7, #20] 8008cc6: ee07 3a90 vmov s15, r3 8008cca: eef8 7a67 vcvt.f32.u32 s15, s15 8008cce: eddf 6a4f vldr s13, [pc, #316] ; 8008e0c 8008cd2: ee86 7aa7 vdiv.f32 s14, s13, s15 8008cd6: 4b48 ldr r3, [pc, #288] ; (8008df8 ) 8008cd8: 6b9b ldr r3, [r3, #56] ; 0x38 8008cda: f3c3 0308 ubfx r3, r3, #0, #9 8008cde: ee07 3a90 vmov s15, r3 8008ce2: eef8 6a67 vcvt.f32.u32 s13, s15 8008ce6: ed97 6a03 vldr s12, [r7, #12] 8008cea: eddf 5a45 vldr s11, [pc, #276] ; 8008e00 8008cee: eec6 7a25 vdiv.f32 s15, s12, s11 8008cf2: ee76 7aa7 vadd.f32 s15, s13, s15 8008cf6: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8008cfa: ee77 7aa6 vadd.f32 s15, s15, s13 8008cfe: ee67 7a27 vmul.f32 s15, s14, s15 8008d02: edc7 7a07 vstr s15, [r7, #28] break; 8008d06: e021 b.n 8008d4c default: pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 ); 8008d08: 697b ldr r3, [r7, #20] 8008d0a: ee07 3a90 vmov s15, r3 8008d0e: eef8 7a67 vcvt.f32.u32 s15, s15 8008d12: eddf 6a3d vldr s13, [pc, #244] ; 8008e08 8008d16: ee86 7aa7 vdiv.f32 s14, s13, s15 8008d1a: 4b37 ldr r3, [pc, #220] ; (8008df8 ) 8008d1c: 6b9b ldr r3, [r3, #56] ; 0x38 8008d1e: f3c3 0308 ubfx r3, r3, #0, #9 8008d22: ee07 3a90 vmov s15, r3 8008d26: eef8 6a67 vcvt.f32.u32 s13, s15 8008d2a: ed97 6a03 vldr s12, [r7, #12] 8008d2e: eddf 5a34 vldr s11, [pc, #208] ; 8008e00 8008d32: eec6 7a25 vdiv.f32 s15, s12, s11 8008d36: ee76 7aa7 vadd.f32 s15, s13, s15 8008d3a: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8008d3e: ee77 7aa6 vadd.f32 s15, s15, s13 8008d42: ee67 7a27 vmul.f32 s15, s14, s15 8008d46: edc7 7a07 vstr s15, [r7, #28] break; 8008d4a: bf00 nop } PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >>9) + (float_t)1 )) ; 8008d4c: 4b2a ldr r3, [pc, #168] ; (8008df8 ) 8008d4e: 6b9b ldr r3, [r3, #56] ; 0x38 8008d50: 0a5b lsrs r3, r3, #9 8008d52: f003 037f and.w r3, r3, #127 ; 0x7f 8008d56: ee07 3a90 vmov s15, r3 8008d5a: eef8 7a67 vcvt.f32.u32 s15, s15 8008d5e: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 8008d62: ee37 7a87 vadd.f32 s14, s15, s14 8008d66: edd7 6a07 vldr s13, [r7, #28] 8008d6a: eec6 7a87 vdiv.f32 s15, s13, s14 8008d6e: eefc 7ae7 vcvt.u32.f32 s15, s15 8008d72: ee17 2a90 vmov r2, s15 8008d76: 687b ldr r3, [r7, #4] 8008d78: 601a str r2, [r3, #0] PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >>16) + (float_t)1 )) ; 8008d7a: 4b1f ldr r3, [pc, #124] ; (8008df8 ) 8008d7c: 6b9b ldr r3, [r3, #56] ; 0x38 8008d7e: 0c1b lsrs r3, r3, #16 8008d80: f003 037f and.w r3, r3, #127 ; 0x7f 8008d84: ee07 3a90 vmov s15, r3 8008d88: eef8 7a67 vcvt.f32.u32 s15, s15 8008d8c: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 8008d90: ee37 7a87 vadd.f32 s14, s15, s14 8008d94: edd7 6a07 vldr s13, [r7, #28] 8008d98: eec6 7a87 vdiv.f32 s15, s13, s14 8008d9c: eefc 7ae7 vcvt.u32.f32 s15, s15 8008da0: ee17 2a90 vmov r2, s15 8008da4: 687b ldr r3, [r7, #4] 8008da6: 605a str r2, [r3, #4] PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >>24) + (float_t)1 )) ; 8008da8: 4b13 ldr r3, [pc, #76] ; (8008df8 ) 8008daa: 6b9b ldr r3, [r3, #56] ; 0x38 8008dac: 0e1b lsrs r3, r3, #24 8008dae: f003 037f and.w r3, r3, #127 ; 0x7f 8008db2: ee07 3a90 vmov s15, r3 8008db6: eef8 7a67 vcvt.f32.u32 s15, s15 8008dba: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 8008dbe: ee37 7a87 vadd.f32 s14, s15, s14 8008dc2: edd7 6a07 vldr s13, [r7, #28] 8008dc6: eec6 7a87 vdiv.f32 s15, s13, s14 8008dca: eefc 7ae7 vcvt.u32.f32 s15, s15 8008dce: ee17 2a90 vmov r2, s15 8008dd2: 687b ldr r3, [r7, #4] 8008dd4: 609a str r2, [r3, #8] { PLL2_Clocks->PLL2_P_Frequency = 0U; PLL2_Clocks->PLL2_Q_Frequency = 0U; PLL2_Clocks->PLL2_R_Frequency = 0U; } } 8008dd6: e008 b.n 8008dea PLL2_Clocks->PLL2_P_Frequency = 0U; 8008dd8: 687b ldr r3, [r7, #4] 8008dda: 2200 movs r2, #0 8008ddc: 601a str r2, [r3, #0] PLL2_Clocks->PLL2_Q_Frequency = 0U; 8008dde: 687b ldr r3, [r7, #4] 8008de0: 2200 movs r2, #0 8008de2: 605a str r2, [r3, #4] PLL2_Clocks->PLL2_R_Frequency = 0U; 8008de4: 687b ldr r3, [r7, #4] 8008de6: 2200 movs r2, #0 8008de8: 609a str r2, [r3, #8] } 8008dea: bf00 nop 8008dec: 3724 adds r7, #36 ; 0x24 8008dee: 46bd mov sp, r7 8008df0: f85d 7b04 ldr.w r7, [sp], #4 8008df4: 4770 bx lr 8008df6: bf00 nop 8008df8: 58024400 .word 0x58024400 8008dfc: 03d09000 .word 0x03d09000 8008e00: 46000000 .word 0x46000000 8008e04: 4c742400 .word 0x4c742400 8008e08: 4a742400 .word 0x4a742400 8008e0c: 4bb71b00 .word 0x4bb71b00 08008e10 : * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL3_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks) { 8008e10: b480 push {r7} 8008e12: b089 sub sp, #36 ; 0x24 8008e14: af00 add r7, sp, #0 8008e16: 6078 str r0, [r7, #4] float_t fracn3, pll3vco; /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N PLL3xCLK = PLL3_VCO / PLLxR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 8008e18: 4ba1 ldr r3, [pc, #644] ; (80090a0 ) 8008e1a: 6a9b ldr r3, [r3, #40] ; 0x28 8008e1c: f003 0303 and.w r3, r3, #3 8008e20: 61bb str r3, [r7, #24] pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> 20) ; 8008e22: 4b9f ldr r3, [pc, #636] ; (80090a0 ) 8008e24: 6a9b ldr r3, [r3, #40] ; 0x28 8008e26: 0d1b lsrs r3, r3, #20 8008e28: f003 033f and.w r3, r3, #63 ; 0x3f 8008e2c: 617b str r3, [r7, #20] pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos; 8008e2e: 4b9c ldr r3, [pc, #624] ; (80090a0 ) 8008e30: 6adb ldr r3, [r3, #44] ; 0x2c 8008e32: 0a1b lsrs r3, r3, #8 8008e34: f003 0301 and.w r3, r3, #1 8008e38: 613b str r3, [r7, #16] fracn3 = (float_t)(uint32_t)(pll3fracen* ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3)>> 3)); 8008e3a: 4b99 ldr r3, [pc, #612] ; (80090a0 ) 8008e3c: 6c5b ldr r3, [r3, #68] ; 0x44 8008e3e: 08db lsrs r3, r3, #3 8008e40: f3c3 030c ubfx r3, r3, #0, #13 8008e44: 693a ldr r2, [r7, #16] 8008e46: fb02 f303 mul.w r3, r2, r3 8008e4a: ee07 3a90 vmov s15, r3 8008e4e: eef8 7a67 vcvt.f32.u32 s15, s15 8008e52: edc7 7a03 vstr s15, [r7, #12] if (pll3m != 0U) 8008e56: 697b ldr r3, [r7, #20] 8008e58: 2b00 cmp r3, #0 8008e5a: f000 8111 beq.w 8009080 { switch (pllsource) 8008e5e: 69bb ldr r3, [r7, #24] 8008e60: 2b02 cmp r3, #2 8008e62: f000 8083 beq.w 8008f6c 8008e66: 69bb ldr r3, [r7, #24] 8008e68: 2b02 cmp r3, #2 8008e6a: f200 80a1 bhi.w 8008fb0 8008e6e: 69bb ldr r3, [r7, #24] 8008e70: 2b00 cmp r3, #0 8008e72: d003 beq.n 8008e7c 8008e74: 69bb ldr r3, [r7, #24] 8008e76: 2b01 cmp r3, #1 8008e78: d056 beq.n 8008f28 8008e7a: e099 b.n 8008fb0 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8008e7c: 4b88 ldr r3, [pc, #544] ; (80090a0 ) 8008e7e: 681b ldr r3, [r3, #0] 8008e80: f003 0320 and.w r3, r3, #32 8008e84: 2b00 cmp r3, #0 8008e86: d02d beq.n 8008ee4 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 8008e88: 4b85 ldr r3, [pc, #532] ; (80090a0 ) 8008e8a: 681b ldr r3, [r3, #0] 8008e8c: 08db lsrs r3, r3, #3 8008e8e: f003 0303 and.w r3, r3, #3 8008e92: 4a84 ldr r2, [pc, #528] ; (80090a4 ) 8008e94: fa22 f303 lsr.w r3, r2, r3 8008e98: 60bb str r3, [r7, #8] pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 ); 8008e9a: 68bb ldr r3, [r7, #8] 8008e9c: ee07 3a90 vmov s15, r3 8008ea0: eef8 6a67 vcvt.f32.u32 s13, s15 8008ea4: 697b ldr r3, [r7, #20] 8008ea6: ee07 3a90 vmov s15, r3 8008eaa: eef8 7a67 vcvt.f32.u32 s15, s15 8008eae: ee86 7aa7 vdiv.f32 s14, s13, s15 8008eb2: 4b7b ldr r3, [pc, #492] ; (80090a0 ) 8008eb4: 6c1b ldr r3, [r3, #64] ; 0x40 8008eb6: f3c3 0308 ubfx r3, r3, #0, #9 8008eba: ee07 3a90 vmov s15, r3 8008ebe: eef8 6a67 vcvt.f32.u32 s13, s15 8008ec2: ed97 6a03 vldr s12, [r7, #12] 8008ec6: eddf 5a78 vldr s11, [pc, #480] ; 80090a8 8008eca: eec6 7a25 vdiv.f32 s15, s12, s11 8008ece: ee76 7aa7 vadd.f32 s15, s13, s15 8008ed2: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8008ed6: ee77 7aa6 vadd.f32 s15, s15, s13 8008eda: ee67 7a27 vmul.f32 s15, s14, s15 8008ede: edc7 7a07 vstr s15, [r7, #28] } else { pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 ); } break; 8008ee2: e087 b.n 8008ff4 pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 ); 8008ee4: 697b ldr r3, [r7, #20] 8008ee6: ee07 3a90 vmov s15, r3 8008eea: eef8 7a67 vcvt.f32.u32 s15, s15 8008eee: eddf 6a6f vldr s13, [pc, #444] ; 80090ac 8008ef2: ee86 7aa7 vdiv.f32 s14, s13, s15 8008ef6: 4b6a ldr r3, [pc, #424] ; (80090a0 ) 8008ef8: 6c1b ldr r3, [r3, #64] ; 0x40 8008efa: f3c3 0308 ubfx r3, r3, #0, #9 8008efe: ee07 3a90 vmov s15, r3 8008f02: eef8 6a67 vcvt.f32.u32 s13, s15 8008f06: ed97 6a03 vldr s12, [r7, #12] 8008f0a: eddf 5a67 vldr s11, [pc, #412] ; 80090a8 8008f0e: eec6 7a25 vdiv.f32 s15, s12, s11 8008f12: ee76 7aa7 vadd.f32 s15, s13, s15 8008f16: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8008f1a: ee77 7aa6 vadd.f32 s15, s15, s13 8008f1e: ee67 7a27 vmul.f32 s15, s14, s15 8008f22: edc7 7a07 vstr s15, [r7, #28] break; 8008f26: e065 b.n 8008ff4 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 ); 8008f28: 697b ldr r3, [r7, #20] 8008f2a: ee07 3a90 vmov s15, r3 8008f2e: eef8 7a67 vcvt.f32.u32 s15, s15 8008f32: eddf 6a5f vldr s13, [pc, #380] ; 80090b0 8008f36: ee86 7aa7 vdiv.f32 s14, s13, s15 8008f3a: 4b59 ldr r3, [pc, #356] ; (80090a0 ) 8008f3c: 6c1b ldr r3, [r3, #64] ; 0x40 8008f3e: f3c3 0308 ubfx r3, r3, #0, #9 8008f42: ee07 3a90 vmov s15, r3 8008f46: eef8 6a67 vcvt.f32.u32 s13, s15 8008f4a: ed97 6a03 vldr s12, [r7, #12] 8008f4e: eddf 5a56 vldr s11, [pc, #344] ; 80090a8 8008f52: eec6 7a25 vdiv.f32 s15, s12, s11 8008f56: ee76 7aa7 vadd.f32 s15, s13, s15 8008f5a: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8008f5e: ee77 7aa6 vadd.f32 s15, s15, s13 8008f62: ee67 7a27 vmul.f32 s15, s14, s15 8008f66: edc7 7a07 vstr s15, [r7, #28] break; 8008f6a: e043 b.n 8008ff4 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 ); 8008f6c: 697b ldr r3, [r7, #20] 8008f6e: ee07 3a90 vmov s15, r3 8008f72: eef8 7a67 vcvt.f32.u32 s15, s15 8008f76: eddf 6a4f vldr s13, [pc, #316] ; 80090b4 8008f7a: ee86 7aa7 vdiv.f32 s14, s13, s15 8008f7e: 4b48 ldr r3, [pc, #288] ; (80090a0 ) 8008f80: 6c1b ldr r3, [r3, #64] ; 0x40 8008f82: f3c3 0308 ubfx r3, r3, #0, #9 8008f86: ee07 3a90 vmov s15, r3 8008f8a: eef8 6a67 vcvt.f32.u32 s13, s15 8008f8e: ed97 6a03 vldr s12, [r7, #12] 8008f92: eddf 5a45 vldr s11, [pc, #276] ; 80090a8 8008f96: eec6 7a25 vdiv.f32 s15, s12, s11 8008f9a: ee76 7aa7 vadd.f32 s15, s13, s15 8008f9e: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8008fa2: ee77 7aa6 vadd.f32 s15, s15, s13 8008fa6: ee67 7a27 vmul.f32 s15, s14, s15 8008faa: edc7 7a07 vstr s15, [r7, #28] break; 8008fae: e021 b.n 8008ff4 default: pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 ); 8008fb0: 697b ldr r3, [r7, #20] 8008fb2: ee07 3a90 vmov s15, r3 8008fb6: eef8 7a67 vcvt.f32.u32 s15, s15 8008fba: eddf 6a3d vldr s13, [pc, #244] ; 80090b0 8008fbe: ee86 7aa7 vdiv.f32 s14, s13, s15 8008fc2: 4b37 ldr r3, [pc, #220] ; (80090a0 ) 8008fc4: 6c1b ldr r3, [r3, #64] ; 0x40 8008fc6: f3c3 0308 ubfx r3, r3, #0, #9 8008fca: ee07 3a90 vmov s15, r3 8008fce: eef8 6a67 vcvt.f32.u32 s13, s15 8008fd2: ed97 6a03 vldr s12, [r7, #12] 8008fd6: eddf 5a34 vldr s11, [pc, #208] ; 80090a8 8008fda: eec6 7a25 vdiv.f32 s15, s12, s11 8008fde: ee76 7aa7 vadd.f32 s15, s13, s15 8008fe2: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8008fe6: ee77 7aa6 vadd.f32 s15, s15, s13 8008fea: ee67 7a27 vmul.f32 s15, s14, s15 8008fee: edc7 7a07 vstr s15, [r7, #28] break; 8008ff2: bf00 nop } PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >>9) + (float_t)1 )) ; 8008ff4: 4b2a ldr r3, [pc, #168] ; (80090a0 ) 8008ff6: 6c1b ldr r3, [r3, #64] ; 0x40 8008ff8: 0a5b lsrs r3, r3, #9 8008ffa: f003 037f and.w r3, r3, #127 ; 0x7f 8008ffe: ee07 3a90 vmov s15, r3 8009002: eef8 7a67 vcvt.f32.u32 s15, s15 8009006: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 800900a: ee37 7a87 vadd.f32 s14, s15, s14 800900e: edd7 6a07 vldr s13, [r7, #28] 8009012: eec6 7a87 vdiv.f32 s15, s13, s14 8009016: eefc 7ae7 vcvt.u32.f32 s15, s15 800901a: ee17 2a90 vmov r2, s15 800901e: 687b ldr r3, [r7, #4] 8009020: 601a str r2, [r3, #0] PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >>16) + (float_t)1 )) ; 8009022: 4b1f ldr r3, [pc, #124] ; (80090a0 ) 8009024: 6c1b ldr r3, [r3, #64] ; 0x40 8009026: 0c1b lsrs r3, r3, #16 8009028: f003 037f and.w r3, r3, #127 ; 0x7f 800902c: ee07 3a90 vmov s15, r3 8009030: eef8 7a67 vcvt.f32.u32 s15, s15 8009034: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 8009038: ee37 7a87 vadd.f32 s14, s15, s14 800903c: edd7 6a07 vldr s13, [r7, #28] 8009040: eec6 7a87 vdiv.f32 s15, s13, s14 8009044: eefc 7ae7 vcvt.u32.f32 s15, s15 8009048: ee17 2a90 vmov r2, s15 800904c: 687b ldr r3, [r7, #4] 800904e: 605a str r2, [r3, #4] PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >>24) + (float_t)1 )) ; 8009050: 4b13 ldr r3, [pc, #76] ; (80090a0 ) 8009052: 6c1b ldr r3, [r3, #64] ; 0x40 8009054: 0e1b lsrs r3, r3, #24 8009056: f003 037f and.w r3, r3, #127 ; 0x7f 800905a: ee07 3a90 vmov s15, r3 800905e: eef8 7a67 vcvt.f32.u32 s15, s15 8009062: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 8009066: ee37 7a87 vadd.f32 s14, s15, s14 800906a: edd7 6a07 vldr s13, [r7, #28] 800906e: eec6 7a87 vdiv.f32 s15, s13, s14 8009072: eefc 7ae7 vcvt.u32.f32 s15, s15 8009076: ee17 2a90 vmov r2, s15 800907a: 687b ldr r3, [r7, #4] 800907c: 609a str r2, [r3, #8] PLL3_Clocks->PLL3_P_Frequency = 0U; PLL3_Clocks->PLL3_Q_Frequency = 0U; PLL3_Clocks->PLL3_R_Frequency = 0U; } } 800907e: e008 b.n 8009092 PLL3_Clocks->PLL3_P_Frequency = 0U; 8009080: 687b ldr r3, [r7, #4] 8009082: 2200 movs r2, #0 8009084: 601a str r2, [r3, #0] PLL3_Clocks->PLL3_Q_Frequency = 0U; 8009086: 687b ldr r3, [r7, #4] 8009088: 2200 movs r2, #0 800908a: 605a str r2, [r3, #4] PLL3_Clocks->PLL3_R_Frequency = 0U; 800908c: 687b ldr r3, [r7, #4] 800908e: 2200 movs r2, #0 8009090: 609a str r2, [r3, #8] } 8009092: bf00 nop 8009094: 3724 adds r7, #36 ; 0x24 8009096: 46bd mov sp, r7 8009098: f85d 7b04 ldr.w r7, [sp], #4 800909c: 4770 bx lr 800909e: bf00 nop 80090a0: 58024400 .word 0x58024400 80090a4: 03d09000 .word 0x03d09000 80090a8: 46000000 .word 0x46000000 80090ac: 4c742400 .word 0x4c742400 80090b0: 4a742400 .word 0x4a742400 80090b4: 4bb71b00 .word 0x4bb71b00 080090b8 : * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL1_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks) { 80090b8: b480 push {r7} 80090ba: b089 sub sp, #36 ; 0x24 80090bc: af00 add r7, sp, #0 80090be: 6078 str r0, [r7, #4] uint32_t pllsource, pll1m, pll1fracen, hsivalue; float_t fracn1, pll1vco; pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 80090c0: 4ba0 ldr r3, [pc, #640] ; (8009344 ) 80090c2: 6a9b ldr r3, [r3, #40] ; 0x28 80090c4: f003 0303 and.w r3, r3, #3 80090c8: 61bb str r3, [r7, #24] pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4); 80090ca: 4b9e ldr r3, [pc, #632] ; (8009344 ) 80090cc: 6a9b ldr r3, [r3, #40] ; 0x28 80090ce: 091b lsrs r3, r3, #4 80090d0: f003 033f and.w r3, r3, #63 ; 0x3f 80090d4: 617b str r3, [r7, #20] pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN; 80090d6: 4b9b ldr r3, [pc, #620] ; (8009344 ) 80090d8: 6adb ldr r3, [r3, #44] ; 0x2c 80090da: f003 0301 and.w r3, r3, #1 80090de: 613b str r3, [r7, #16] fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); 80090e0: 4b98 ldr r3, [pc, #608] ; (8009344 ) 80090e2: 6b5b ldr r3, [r3, #52] ; 0x34 80090e4: 08db lsrs r3, r3, #3 80090e6: f3c3 030c ubfx r3, r3, #0, #13 80090ea: 693a ldr r2, [r7, #16] 80090ec: fb02 f303 mul.w r3, r2, r3 80090f0: ee07 3a90 vmov s15, r3 80090f4: eef8 7a67 vcvt.f32.u32 s15, s15 80090f8: edc7 7a03 vstr s15, [r7, #12] if (pll1m != 0U) 80090fc: 697b ldr r3, [r7, #20] 80090fe: 2b00 cmp r3, #0 8009100: f000 8111 beq.w 8009326 { switch (pllsource) 8009104: 69bb ldr r3, [r7, #24] 8009106: 2b02 cmp r3, #2 8009108: f000 8083 beq.w 8009212 800910c: 69bb ldr r3, [r7, #24] 800910e: 2b02 cmp r3, #2 8009110: f200 80a1 bhi.w 8009256 8009114: 69bb ldr r3, [r7, #24] 8009116: 2b00 cmp r3, #0 8009118: d003 beq.n 8009122 800911a: 69bb ldr r3, [r7, #24] 800911c: 2b01 cmp r3, #1 800911e: d056 beq.n 80091ce 8009120: e099 b.n 8009256 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8009122: 4b88 ldr r3, [pc, #544] ; (8009344 ) 8009124: 681b ldr r3, [r3, #0] 8009126: f003 0320 and.w r3, r3, #32 800912a: 2b00 cmp r3, #0 800912c: d02d beq.n 800918a { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 800912e: 4b85 ldr r3, [pc, #532] ; (8009344 ) 8009130: 681b ldr r3, [r3, #0] 8009132: 08db lsrs r3, r3, #3 8009134: f003 0303 and.w r3, r3, #3 8009138: 4a83 ldr r2, [pc, #524] ; (8009348 ) 800913a: fa22 f303 lsr.w r3, r2, r3 800913e: 60bb str r3, [r7, #8] pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 8009140: 68bb ldr r3, [r7, #8] 8009142: ee07 3a90 vmov s15, r3 8009146: eef8 6a67 vcvt.f32.u32 s13, s15 800914a: 697b ldr r3, [r7, #20] 800914c: ee07 3a90 vmov s15, r3 8009150: eef8 7a67 vcvt.f32.u32 s15, s15 8009154: ee86 7aa7 vdiv.f32 s14, s13, s15 8009158: 4b7a ldr r3, [pc, #488] ; (8009344 ) 800915a: 6b1b ldr r3, [r3, #48] ; 0x30 800915c: f3c3 0308 ubfx r3, r3, #0, #9 8009160: ee07 3a90 vmov s15, r3 8009164: eef8 6a67 vcvt.f32.u32 s13, s15 8009168: ed97 6a03 vldr s12, [r7, #12] 800916c: eddf 5a77 vldr s11, [pc, #476] ; 800934c 8009170: eec6 7a25 vdiv.f32 s15, s12, s11 8009174: ee76 7aa7 vadd.f32 s15, s13, s15 8009178: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 800917c: ee77 7aa6 vadd.f32 s15, s15, s13 8009180: ee67 7a27 vmul.f32 s15, s14, s15 8009184: edc7 7a07 vstr s15, [r7, #28] } else { pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); } break; 8009188: e087 b.n 800929a pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 800918a: 697b ldr r3, [r7, #20] 800918c: ee07 3a90 vmov s15, r3 8009190: eef8 7a67 vcvt.f32.u32 s15, s15 8009194: eddf 6a6e vldr s13, [pc, #440] ; 8009350 8009198: ee86 7aa7 vdiv.f32 s14, s13, s15 800919c: 4b69 ldr r3, [pc, #420] ; (8009344 ) 800919e: 6b1b ldr r3, [r3, #48] ; 0x30 80091a0: f3c3 0308 ubfx r3, r3, #0, #9 80091a4: ee07 3a90 vmov s15, r3 80091a8: eef8 6a67 vcvt.f32.u32 s13, s15 80091ac: ed97 6a03 vldr s12, [r7, #12] 80091b0: eddf 5a66 vldr s11, [pc, #408] ; 800934c 80091b4: eec6 7a25 vdiv.f32 s15, s12, s11 80091b8: ee76 7aa7 vadd.f32 s15, s13, s15 80091bc: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 80091c0: ee77 7aa6 vadd.f32 s15, s15, s13 80091c4: ee67 7a27 vmul.f32 s15, s14, s15 80091c8: edc7 7a07 vstr s15, [r7, #28] break; 80091cc: e065 b.n 800929a case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 80091ce: 697b ldr r3, [r7, #20] 80091d0: ee07 3a90 vmov s15, r3 80091d4: eef8 7a67 vcvt.f32.u32 s15, s15 80091d8: eddf 6a5e vldr s13, [pc, #376] ; 8009354 80091dc: ee86 7aa7 vdiv.f32 s14, s13, s15 80091e0: 4b58 ldr r3, [pc, #352] ; (8009344 ) 80091e2: 6b1b ldr r3, [r3, #48] ; 0x30 80091e4: f3c3 0308 ubfx r3, r3, #0, #9 80091e8: ee07 3a90 vmov s15, r3 80091ec: eef8 6a67 vcvt.f32.u32 s13, s15 80091f0: ed97 6a03 vldr s12, [r7, #12] 80091f4: eddf 5a55 vldr s11, [pc, #340] ; 800934c 80091f8: eec6 7a25 vdiv.f32 s15, s12, s11 80091fc: ee76 7aa7 vadd.f32 s15, s13, s15 8009200: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8009204: ee77 7aa6 vadd.f32 s15, s15, s13 8009208: ee67 7a27 vmul.f32 s15, s14, s15 800920c: edc7 7a07 vstr s15, [r7, #28] break; 8009210: e043 b.n 800929a case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 8009212: 697b ldr r3, [r7, #20] 8009214: ee07 3a90 vmov s15, r3 8009218: eef8 7a67 vcvt.f32.u32 s15, s15 800921c: eddf 6a4e vldr s13, [pc, #312] ; 8009358 8009220: ee86 7aa7 vdiv.f32 s14, s13, s15 8009224: 4b47 ldr r3, [pc, #284] ; (8009344 ) 8009226: 6b1b ldr r3, [r3, #48] ; 0x30 8009228: f3c3 0308 ubfx r3, r3, #0, #9 800922c: ee07 3a90 vmov s15, r3 8009230: eef8 6a67 vcvt.f32.u32 s13, s15 8009234: ed97 6a03 vldr s12, [r7, #12] 8009238: eddf 5a44 vldr s11, [pc, #272] ; 800934c 800923c: eec6 7a25 vdiv.f32 s15, s12, s11 8009240: ee76 7aa7 vadd.f32 s15, s13, s15 8009244: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8009248: ee77 7aa6 vadd.f32 s15, s15, s13 800924c: ee67 7a27 vmul.f32 s15, s14, s15 8009250: edc7 7a07 vstr s15, [r7, #28] break; 8009254: e021 b.n 800929a default: pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 8009256: 697b ldr r3, [r7, #20] 8009258: ee07 3a90 vmov s15, r3 800925c: eef8 7a67 vcvt.f32.u32 s15, s15 8009260: eddf 6a3b vldr s13, [pc, #236] ; 8009350 8009264: ee86 7aa7 vdiv.f32 s14, s13, s15 8009268: 4b36 ldr r3, [pc, #216] ; (8009344 ) 800926a: 6b1b ldr r3, [r3, #48] ; 0x30 800926c: f3c3 0308 ubfx r3, r3, #0, #9 8009270: ee07 3a90 vmov s15, r3 8009274: eef8 6a67 vcvt.f32.u32 s13, s15 8009278: ed97 6a03 vldr s12, [r7, #12] 800927c: eddf 5a33 vldr s11, [pc, #204] ; 800934c 8009280: eec6 7a25 vdiv.f32 s15, s12, s11 8009284: ee76 7aa7 vadd.f32 s15, s13, s15 8009288: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 800928c: ee77 7aa6 vadd.f32 s15, s15, s13 8009290: ee67 7a27 vmul.f32 s15, s14, s15 8009294: edc7 7a07 vstr s15, [r7, #28] break; 8009298: bf00 nop } PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + (float_t)1 )) ; 800929a: 4b2a ldr r3, [pc, #168] ; (8009344 ) 800929c: 6b1b ldr r3, [r3, #48] ; 0x30 800929e: 0a5b lsrs r3, r3, #9 80092a0: f003 037f and.w r3, r3, #127 ; 0x7f 80092a4: ee07 3a90 vmov s15, r3 80092a8: eef8 7a67 vcvt.f32.u32 s15, s15 80092ac: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 80092b0: ee37 7a87 vadd.f32 s14, s15, s14 80092b4: edd7 6a07 vldr s13, [r7, #28] 80092b8: eec6 7a87 vdiv.f32 s15, s13, s14 80092bc: eefc 7ae7 vcvt.u32.f32 s15, s15 80092c0: ee17 2a90 vmov r2, s15 80092c4: 687b ldr r3, [r7, #4] 80092c6: 601a str r2, [r3, #0] PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >>16) + (float_t)1 )) ; 80092c8: 4b1e ldr r3, [pc, #120] ; (8009344 ) 80092ca: 6b1b ldr r3, [r3, #48] ; 0x30 80092cc: 0c1b lsrs r3, r3, #16 80092ce: f003 037f and.w r3, r3, #127 ; 0x7f 80092d2: ee07 3a90 vmov s15, r3 80092d6: eef8 7a67 vcvt.f32.u32 s15, s15 80092da: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 80092de: ee37 7a87 vadd.f32 s14, s15, s14 80092e2: edd7 6a07 vldr s13, [r7, #28] 80092e6: eec6 7a87 vdiv.f32 s15, s13, s14 80092ea: eefc 7ae7 vcvt.u32.f32 s15, s15 80092ee: ee17 2a90 vmov r2, s15 80092f2: 687b ldr r3, [r7, #4] 80092f4: 605a str r2, [r3, #4] PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >>24) + (float_t)1 )) ; 80092f6: 4b13 ldr r3, [pc, #76] ; (8009344 ) 80092f8: 6b1b ldr r3, [r3, #48] ; 0x30 80092fa: 0e1b lsrs r3, r3, #24 80092fc: f003 037f and.w r3, r3, #127 ; 0x7f 8009300: ee07 3a90 vmov s15, r3 8009304: eef8 7a67 vcvt.f32.u32 s15, s15 8009308: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 800930c: ee37 7a87 vadd.f32 s14, s15, s14 8009310: edd7 6a07 vldr s13, [r7, #28] 8009314: eec6 7a87 vdiv.f32 s15, s13, s14 8009318: eefc 7ae7 vcvt.u32.f32 s15, s15 800931c: ee17 2a90 vmov r2, s15 8009320: 687b ldr r3, [r7, #4] 8009322: 609a str r2, [r3, #8] PLL1_Clocks->PLL1_P_Frequency = 0U; PLL1_Clocks->PLL1_Q_Frequency = 0U; PLL1_Clocks->PLL1_R_Frequency = 0U; } } 8009324: e008 b.n 8009338 PLL1_Clocks->PLL1_P_Frequency = 0U; 8009326: 687b ldr r3, [r7, #4] 8009328: 2200 movs r2, #0 800932a: 601a str r2, [r3, #0] PLL1_Clocks->PLL1_Q_Frequency = 0U; 800932c: 687b ldr r3, [r7, #4] 800932e: 2200 movs r2, #0 8009330: 605a str r2, [r3, #4] PLL1_Clocks->PLL1_R_Frequency = 0U; 8009332: 687b ldr r3, [r7, #4] 8009334: 2200 movs r2, #0 8009336: 609a str r2, [r3, #8] } 8009338: bf00 nop 800933a: 3724 adds r7, #36 ; 0x24 800933c: 46bd mov sp, r7 800933e: f85d 7b04 ldr.w r7, [sp], #4 8009342: 4770 bx lr 8009344: 58024400 .word 0x58024400 8009348: 03d09000 .word 0x03d09000 800934c: 46000000 .word 0x46000000 8009350: 4c742400 .word 0x4c742400 8009354: 4a742400 .word 0x4a742400 8009358: 4bb71b00 .word 0x4bb71b00 0800935c : * @note PLL2 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider) { 800935c: b580 push {r7, lr} 800935e: b084 sub sp, #16 8009360: af00 add r7, sp, #0 8009362: 6078 str r0, [r7, #4] 8009364: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 8009366: 2300 movs r3, #0 8009368: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE)); assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN)); /* Check that PLL2 OSC clock source is already set */ if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 800936a: 4b53 ldr r3, [pc, #332] ; (80094b8 ) 800936c: 6a9b ldr r3, [r3, #40] ; 0x28 800936e: f003 0303 and.w r3, r3, #3 8009372: 2b03 cmp r3, #3 8009374: d101 bne.n 800937a { return HAL_ERROR; 8009376: 2301 movs r3, #1 8009378: e099 b.n 80094ae else { /* Disable PLL2. */ __HAL_RCC_PLL2_DISABLE(); 800937a: 4b4f ldr r3, [pc, #316] ; (80094b8 ) 800937c: 681b ldr r3, [r3, #0] 800937e: 4a4e ldr r2, [pc, #312] ; (80094b8 ) 8009380: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000 8009384: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8009386: f7f9 ff2f bl 80031e8 800938a: 60b8 str r0, [r7, #8] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 800938c: e008 b.n 80093a0 { if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE) 800938e: f7f9 ff2b bl 80031e8 8009392: 4602 mov r2, r0 8009394: 68bb ldr r3, [r7, #8] 8009396: 1ad3 subs r3, r2, r3 8009398: 2b02 cmp r3, #2 800939a: d901 bls.n 80093a0 { return HAL_TIMEOUT; 800939c: 2303 movs r3, #3 800939e: e086 b.n 80094ae while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 80093a0: 4b45 ldr r3, [pc, #276] ; (80094b8 ) 80093a2: 681b ldr r3, [r3, #0] 80093a4: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 80093a8: 2b00 cmp r3, #0 80093aa: d1f0 bne.n 800938e } } /* Configure PLL2 multiplication and division factors. */ __HAL_RCC_PLL2_CONFIG(pll2->PLL2M, 80093ac: 4b42 ldr r3, [pc, #264] ; (80094b8 ) 80093ae: 6a9b ldr r3, [r3, #40] ; 0x28 80093b0: f423 327c bic.w r2, r3, #258048 ; 0x3f000 80093b4: 687b ldr r3, [r7, #4] 80093b6: 681b ldr r3, [r3, #0] 80093b8: 031b lsls r3, r3, #12 80093ba: 493f ldr r1, [pc, #252] ; (80094b8 ) 80093bc: 4313 orrs r3, r2 80093be: 628b str r3, [r1, #40] ; 0x28 80093c0: 687b ldr r3, [r7, #4] 80093c2: 685b ldr r3, [r3, #4] 80093c4: 3b01 subs r3, #1 80093c6: f3c3 0208 ubfx r2, r3, #0, #9 80093ca: 687b ldr r3, [r7, #4] 80093cc: 689b ldr r3, [r3, #8] 80093ce: 3b01 subs r3, #1 80093d0: 025b lsls r3, r3, #9 80093d2: b29b uxth r3, r3 80093d4: 431a orrs r2, r3 80093d6: 687b ldr r3, [r7, #4] 80093d8: 68db ldr r3, [r3, #12] 80093da: 3b01 subs r3, #1 80093dc: 041b lsls r3, r3, #16 80093de: f403 03fe and.w r3, r3, #8323072 ; 0x7f0000 80093e2: 431a orrs r2, r3 80093e4: 687b ldr r3, [r7, #4] 80093e6: 691b ldr r3, [r3, #16] 80093e8: 3b01 subs r3, #1 80093ea: 061b lsls r3, r3, #24 80093ec: f003 43fe and.w r3, r3, #2130706432 ; 0x7f000000 80093f0: 4931 ldr r1, [pc, #196] ; (80094b8 ) 80093f2: 4313 orrs r3, r2 80093f4: 638b str r3, [r1, #56] ; 0x38 pll2->PLL2P, pll2->PLL2Q, pll2->PLL2R); /* Select PLL2 input reference frequency range: VCI */ __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ; 80093f6: 4b30 ldr r3, [pc, #192] ; (80094b8 ) 80093f8: 6adb ldr r3, [r3, #44] ; 0x2c 80093fa: f023 02c0 bic.w r2, r3, #192 ; 0xc0 80093fe: 687b ldr r3, [r7, #4] 8009400: 695b ldr r3, [r3, #20] 8009402: 492d ldr r1, [pc, #180] ; (80094b8 ) 8009404: 4313 orrs r3, r2 8009406: 62cb str r3, [r1, #44] ; 0x2c /* Select PLL2 output frequency range : VCO */ __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ; 8009408: 4b2b ldr r3, [pc, #172] ; (80094b8 ) 800940a: 6adb ldr r3, [r3, #44] ; 0x2c 800940c: f023 0220 bic.w r2, r3, #32 8009410: 687b ldr r3, [r7, #4] 8009412: 699b ldr r3, [r3, #24] 8009414: 4928 ldr r1, [pc, #160] ; (80094b8 ) 8009416: 4313 orrs r3, r2 8009418: 62cb str r3, [r1, #44] ; 0x2c /* Disable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_DISABLE(); 800941a: 4b27 ldr r3, [pc, #156] ; (80094b8 ) 800941c: 6adb ldr r3, [r3, #44] ; 0x2c 800941e: 4a26 ldr r2, [pc, #152] ; (80094b8 ) 8009420: f023 0310 bic.w r3, r3, #16 8009424: 62d3 str r3, [r2, #44] ; 0x2c /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN); 8009426: 4b24 ldr r3, [pc, #144] ; (80094b8 ) 8009428: 6bda ldr r2, [r3, #60] ; 0x3c 800942a: 4b24 ldr r3, [pc, #144] ; (80094bc ) 800942c: 4013 ands r3, r2 800942e: 687a ldr r2, [r7, #4] 8009430: 69d2 ldr r2, [r2, #28] 8009432: 00d2 lsls r2, r2, #3 8009434: 4920 ldr r1, [pc, #128] ; (80094b8 ) 8009436: 4313 orrs r3, r2 8009438: 63cb str r3, [r1, #60] ; 0x3c /* Enable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_ENABLE(); 800943a: 4b1f ldr r3, [pc, #124] ; (80094b8 ) 800943c: 6adb ldr r3, [r3, #44] ; 0x2c 800943e: 4a1e ldr r2, [pc, #120] ; (80094b8 ) 8009440: f043 0310 orr.w r3, r3, #16 8009444: 62d3 str r3, [r2, #44] ; 0x2c /* Enable the PLL2 clock output */ if(Divider == DIVIDER_P_UPDATE) 8009446: 683b ldr r3, [r7, #0] 8009448: 2b00 cmp r3, #0 800944a: d106 bne.n 800945a { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP); 800944c: 4b1a ldr r3, [pc, #104] ; (80094b8 ) 800944e: 6adb ldr r3, [r3, #44] ; 0x2c 8009450: 4a19 ldr r2, [pc, #100] ; (80094b8 ) 8009452: f443 2300 orr.w r3, r3, #524288 ; 0x80000 8009456: 62d3 str r3, [r2, #44] ; 0x2c 8009458: e00f b.n 800947a } else if(Divider == DIVIDER_Q_UPDATE) 800945a: 683b ldr r3, [r7, #0] 800945c: 2b01 cmp r3, #1 800945e: d106 bne.n 800946e { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ); 8009460: 4b15 ldr r3, [pc, #84] ; (80094b8 ) 8009462: 6adb ldr r3, [r3, #44] ; 0x2c 8009464: 4a14 ldr r2, [pc, #80] ; (80094b8 ) 8009466: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 800946a: 62d3 str r3, [r2, #44] ; 0x2c 800946c: e005 b.n 800947a } else { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR); 800946e: 4b12 ldr r3, [pc, #72] ; (80094b8 ) 8009470: 6adb ldr r3, [r3, #44] ; 0x2c 8009472: 4a11 ldr r2, [pc, #68] ; (80094b8 ) 8009474: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 8009478: 62d3 str r3, [r2, #44] ; 0x2c } /* Enable PLL2. */ __HAL_RCC_PLL2_ENABLE(); 800947a: 4b0f ldr r3, [pc, #60] ; (80094b8 ) 800947c: 681b ldr r3, [r3, #0] 800947e: 4a0e ldr r2, [pc, #56] ; (80094b8 ) 8009480: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 8009484: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8009486: f7f9 feaf bl 80031e8 800948a: 60b8 str r0, [r7, #8] /* Wait till PLL2 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 800948c: e008 b.n 80094a0 { if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE) 800948e: f7f9 feab bl 80031e8 8009492: 4602 mov r2, r0 8009494: 68bb ldr r3, [r7, #8] 8009496: 1ad3 subs r3, r2, r3 8009498: 2b02 cmp r3, #2 800949a: d901 bls.n 80094a0 { return HAL_TIMEOUT; 800949c: 2303 movs r3, #3 800949e: e006 b.n 80094ae while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 80094a0: 4b05 ldr r3, [pc, #20] ; (80094b8 ) 80094a2: 681b ldr r3, [r3, #0] 80094a4: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 80094a8: 2b00 cmp r3, #0 80094aa: d0f0 beq.n 800948e } } return status; 80094ac: 7bfb ldrb r3, [r7, #15] } 80094ae: 4618 mov r0, r3 80094b0: 3710 adds r7, #16 80094b2: 46bd mov sp, r7 80094b4: bd80 pop {r7, pc} 80094b6: bf00 nop 80094b8: 58024400 .word 0x58024400 80094bc: ffff0007 .word 0xffff0007 080094c0 : * @note PLL3 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider) { 80094c0: b580 push {r7, lr} 80094c2: b084 sub sp, #16 80094c4: af00 add r7, sp, #0 80094c6: 6078 str r0, [r7, #4] 80094c8: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 80094ca: 2300 movs r3, #0 80094cc: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE)); assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN)); /* Check that PLL3 OSC clock source is already set */ if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 80094ce: 4b53 ldr r3, [pc, #332] ; (800961c ) 80094d0: 6a9b ldr r3, [r3, #40] ; 0x28 80094d2: f003 0303 and.w r3, r3, #3 80094d6: 2b03 cmp r3, #3 80094d8: d101 bne.n 80094de { return HAL_ERROR; 80094da: 2301 movs r3, #1 80094dc: e099 b.n 8009612 else { /* Disable PLL3. */ __HAL_RCC_PLL3_DISABLE(); 80094de: 4b4f ldr r3, [pc, #316] ; (800961c ) 80094e0: 681b ldr r3, [r3, #0] 80094e2: 4a4e ldr r2, [pc, #312] ; (800961c ) 80094e4: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 80094e8: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80094ea: f7f9 fe7d bl 80031e8 80094ee: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 80094f0: e008 b.n 8009504 { if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE) 80094f2: f7f9 fe79 bl 80031e8 80094f6: 4602 mov r2, r0 80094f8: 68bb ldr r3, [r7, #8] 80094fa: 1ad3 subs r3, r2, r3 80094fc: 2b02 cmp r3, #2 80094fe: d901 bls.n 8009504 { return HAL_TIMEOUT; 8009500: 2303 movs r3, #3 8009502: e086 b.n 8009612 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 8009504: 4b45 ldr r3, [pc, #276] ; (800961c ) 8009506: 681b ldr r3, [r3, #0] 8009508: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 800950c: 2b00 cmp r3, #0 800950e: d1f0 bne.n 80094f2 } } /* Configure the PLL3 multiplication and division factors. */ __HAL_RCC_PLL3_CONFIG(pll3->PLL3M, 8009510: 4b42 ldr r3, [pc, #264] ; (800961c ) 8009512: 6a9b ldr r3, [r3, #40] ; 0x28 8009514: f023 727c bic.w r2, r3, #66060288 ; 0x3f00000 8009518: 687b ldr r3, [r7, #4] 800951a: 681b ldr r3, [r3, #0] 800951c: 051b lsls r3, r3, #20 800951e: 493f ldr r1, [pc, #252] ; (800961c ) 8009520: 4313 orrs r3, r2 8009522: 628b str r3, [r1, #40] ; 0x28 8009524: 687b ldr r3, [r7, #4] 8009526: 685b ldr r3, [r3, #4] 8009528: 3b01 subs r3, #1 800952a: f3c3 0208 ubfx r2, r3, #0, #9 800952e: 687b ldr r3, [r7, #4] 8009530: 689b ldr r3, [r3, #8] 8009532: 3b01 subs r3, #1 8009534: 025b lsls r3, r3, #9 8009536: b29b uxth r3, r3 8009538: 431a orrs r2, r3 800953a: 687b ldr r3, [r7, #4] 800953c: 68db ldr r3, [r3, #12] 800953e: 3b01 subs r3, #1 8009540: 041b lsls r3, r3, #16 8009542: f403 03fe and.w r3, r3, #8323072 ; 0x7f0000 8009546: 431a orrs r2, r3 8009548: 687b ldr r3, [r7, #4] 800954a: 691b ldr r3, [r3, #16] 800954c: 3b01 subs r3, #1 800954e: 061b lsls r3, r3, #24 8009550: f003 43fe and.w r3, r3, #2130706432 ; 0x7f000000 8009554: 4931 ldr r1, [pc, #196] ; (800961c ) 8009556: 4313 orrs r3, r2 8009558: 640b str r3, [r1, #64] ; 0x40 pll3->PLL3P, pll3->PLL3Q, pll3->PLL3R); /* Select PLL3 input reference frequency range: VCI */ __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ; 800955a: 4b30 ldr r3, [pc, #192] ; (800961c ) 800955c: 6adb ldr r3, [r3, #44] ; 0x2c 800955e: f423 6240 bic.w r2, r3, #3072 ; 0xc00 8009562: 687b ldr r3, [r7, #4] 8009564: 695b ldr r3, [r3, #20] 8009566: 492d ldr r1, [pc, #180] ; (800961c ) 8009568: 4313 orrs r3, r2 800956a: 62cb str r3, [r1, #44] ; 0x2c /* Select PLL3 output frequency range : VCO */ __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ; 800956c: 4b2b ldr r3, [pc, #172] ; (800961c ) 800956e: 6adb ldr r3, [r3, #44] ; 0x2c 8009570: f423 7200 bic.w r2, r3, #512 ; 0x200 8009574: 687b ldr r3, [r7, #4] 8009576: 699b ldr r3, [r3, #24] 8009578: 4928 ldr r1, [pc, #160] ; (800961c ) 800957a: 4313 orrs r3, r2 800957c: 62cb str r3, [r1, #44] ; 0x2c /* Disable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_DISABLE(); 800957e: 4b27 ldr r3, [pc, #156] ; (800961c ) 8009580: 6adb ldr r3, [r3, #44] ; 0x2c 8009582: 4a26 ldr r2, [pc, #152] ; (800961c ) 8009584: f423 7380 bic.w r3, r3, #256 ; 0x100 8009588: 62d3 str r3, [r2, #44] ; 0x2c /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN); 800958a: 4b24 ldr r3, [pc, #144] ; (800961c ) 800958c: 6c5a ldr r2, [r3, #68] ; 0x44 800958e: 4b24 ldr r3, [pc, #144] ; (8009620 ) 8009590: 4013 ands r3, r2 8009592: 687a ldr r2, [r7, #4] 8009594: 69d2 ldr r2, [r2, #28] 8009596: 00d2 lsls r2, r2, #3 8009598: 4920 ldr r1, [pc, #128] ; (800961c ) 800959a: 4313 orrs r3, r2 800959c: 644b str r3, [r1, #68] ; 0x44 /* Enable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_ENABLE(); 800959e: 4b1f ldr r3, [pc, #124] ; (800961c ) 80095a0: 6adb ldr r3, [r3, #44] ; 0x2c 80095a2: 4a1e ldr r2, [pc, #120] ; (800961c ) 80095a4: f443 7380 orr.w r3, r3, #256 ; 0x100 80095a8: 62d3 str r3, [r2, #44] ; 0x2c /* Enable the PLL3 clock output */ if(Divider == DIVIDER_P_UPDATE) 80095aa: 683b ldr r3, [r7, #0] 80095ac: 2b00 cmp r3, #0 80095ae: d106 bne.n 80095be { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP); 80095b0: 4b1a ldr r3, [pc, #104] ; (800961c ) 80095b2: 6adb ldr r3, [r3, #44] ; 0x2c 80095b4: 4a19 ldr r2, [pc, #100] ; (800961c ) 80095b6: f443 0380 orr.w r3, r3, #4194304 ; 0x400000 80095ba: 62d3 str r3, [r2, #44] ; 0x2c 80095bc: e00f b.n 80095de } else if(Divider == DIVIDER_Q_UPDATE) 80095be: 683b ldr r3, [r7, #0] 80095c0: 2b01 cmp r3, #1 80095c2: d106 bne.n 80095d2 { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ); 80095c4: 4b15 ldr r3, [pc, #84] ; (800961c ) 80095c6: 6adb ldr r3, [r3, #44] ; 0x2c 80095c8: 4a14 ldr r2, [pc, #80] ; (800961c ) 80095ca: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 80095ce: 62d3 str r3, [r2, #44] ; 0x2c 80095d0: e005 b.n 80095de } else { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR); 80095d2: 4b12 ldr r3, [pc, #72] ; (800961c ) 80095d4: 6adb ldr r3, [r3, #44] ; 0x2c 80095d6: 4a11 ldr r2, [pc, #68] ; (800961c ) 80095d8: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 80095dc: 62d3 str r3, [r2, #44] ; 0x2c } /* Enable PLL3. */ __HAL_RCC_PLL3_ENABLE(); 80095de: 4b0f ldr r3, [pc, #60] ; (800961c ) 80095e0: 681b ldr r3, [r3, #0] 80095e2: 4a0e ldr r2, [pc, #56] ; (800961c ) 80095e4: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80095e8: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80095ea: f7f9 fdfd bl 80031e8 80095ee: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 80095f0: e008 b.n 8009604 { if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE) 80095f2: f7f9 fdf9 bl 80031e8 80095f6: 4602 mov r2, r0 80095f8: 68bb ldr r3, [r7, #8] 80095fa: 1ad3 subs r3, r2, r3 80095fc: 2b02 cmp r3, #2 80095fe: d901 bls.n 8009604 { return HAL_TIMEOUT; 8009600: 2303 movs r3, #3 8009602: e006 b.n 8009612 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 8009604: 4b05 ldr r3, [pc, #20] ; (800961c ) 8009606: 681b ldr r3, [r3, #0] 8009608: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 800960c: 2b00 cmp r3, #0 800960e: d0f0 beq.n 80095f2 } } return status; 8009610: 7bfb ldrb r3, [r7, #15] } 8009612: 4618 mov r0, r3 8009614: 3710 adds r7, #16 8009616: 46bd mov sp, r7 8009618: bd80 pop {r7, pc} 800961a: bf00 nop 800961c: 58024400 .word 0x58024400 8009620: ffff0007 .word 0xffff0007 08009624 : * @brief Initialize the RTC peripheral * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) { 8009624: b580 push {r7, lr} 8009626: b084 sub sp, #16 8009628: af00 add r7, sp, #0 800962a: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_ERROR; 800962c: 2301 movs r3, #1 800962e: 73fb strb r3, [r7, #15] /* Check RTC handler */ if(hrtc != NULL) 8009630: 687b ldr r3, [r7, #4] 8009632: 2b00 cmp r3, #0 8009634: d06a beq.n 800970c { hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; } } #else /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ if(hrtc->State == HAL_RTC_STATE_RESET) 8009636: 687b ldr r3, [r7, #4] 8009638: f893 3025 ldrb.w r3, [r3, #37] ; 0x25 800963c: b2db uxtb r3, r3 800963e: 2b00 cmp r3, #0 8009640: d106 bne.n 8009650 { /* Allocate lock resource and initialize it */ hrtc->Lock = HAL_UNLOCKED; 8009642: 687b ldr r3, [r7, #4] 8009644: 2200 movs r2, #0 8009646: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Initialize RTC MSP */ HAL_RTC_MspInit(hrtc); 800964a: 6878 ldr r0, [r7, #4] 800964c: f7f9 faaa bl 8002ba4 } #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; 8009650: 687b ldr r3, [r7, #4] 8009652: 2202 movs r2, #2 8009654: f883 2025 strb.w r2, [r3, #37] ; 0x25 /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 8009658: 687b ldr r3, [r7, #4] 800965a: 681b ldr r3, [r3, #0] 800965c: 22ca movs r2, #202 ; 0xca 800965e: 625a str r2, [r3, #36] ; 0x24 8009660: 687b ldr r3, [r7, #4] 8009662: 681b ldr r3, [r3, #0] 8009664: 2253 movs r2, #83 ; 0x53 8009666: 625a str r2, [r3, #36] ; 0x24 /* Enter Initialization mode */ status = RTC_EnterInitMode(hrtc); 8009668: 6878 ldr r0, [r7, #4] 800966a: f000 f9a3 bl 80099b4 800966e: 4603 mov r3, r0 8009670: 73fb strb r3, [r7, #15] if (status == HAL_OK) 8009672: 7bfb ldrb r3, [r7, #15] 8009674: 2b00 cmp r3, #0 8009676: d13e bne.n 80096f6 { #if defined(RTC_CR_TAMPOE) /* Clear RTC_CR FMT, OSEL, POL and TAMPOE Bits */ hrtc->Instance->CR &= ~(RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE); 8009678: 687b ldr r3, [r7, #4] 800967a: 681b ldr r3, [r3, #0] 800967c: 6999 ldr r1, [r3, #24] 800967e: 687b ldr r3, [r7, #4] 8009680: 681a ldr r2, [r3, #0] 8009682: 4b25 ldr r3, [pc, #148] ; (8009718 ) 8009684: 400b ands r3, r1 8009686: 6193 str r3, [r2, #24] /* Clear RTC_CR FMT, OSEL and POL Bits */ hrtc->Instance->CR &= ~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL); #endif /* RTC_CR_TAMPOE */ /* Set RTC_CR register */ hrtc->Instance->CR |= (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); 8009688: 687b ldr r3, [r7, #4] 800968a: 681b ldr r3, [r3, #0] 800968c: 6999 ldr r1, [r3, #24] 800968e: 687b ldr r3, [r7, #4] 8009690: 685a ldr r2, [r3, #4] 8009692: 687b ldr r3, [r7, #4] 8009694: 691b ldr r3, [r3, #16] 8009696: 431a orrs r2, r3 8009698: 687b ldr r3, [r7, #4] 800969a: 699b ldr r3, [r3, #24] 800969c: 431a orrs r2, r3 800969e: 687b ldr r3, [r7, #4] 80096a0: 681b ldr r3, [r3, #0] 80096a2: 430a orrs r2, r1 80096a4: 619a str r2, [r3, #24] /* Configure the RTC PRER */ hrtc->Instance->PRER = (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos) | (hrtc->Init.SynchPrediv << RTC_PRER_PREDIV_S_Pos); 80096a6: 687b ldr r3, [r7, #4] 80096a8: 689b ldr r3, [r3, #8] 80096aa: 0419 lsls r1, r3, #16 80096ac: 687b ldr r3, [r7, #4] 80096ae: 68da ldr r2, [r3, #12] 80096b0: 687b ldr r3, [r7, #4] 80096b2: 681b ldr r3, [r3, #0] 80096b4: 430a orrs r2, r1 80096b6: 611a str r2, [r3, #16] /* Exit Initialization mode */ status = RTC_ExitInitMode(hrtc); 80096b8: 6878 ldr r0, [r7, #4] 80096ba: f000 f9b1 bl 8009a20 80096be: 4603 mov r3, r0 80096c0: 73fb strb r3, [r7, #15] if(status == HAL_OK) 80096c2: 7bfb ldrb r3, [r7, #15] 80096c4: 2b00 cmp r3, #0 80096c6: d116 bne.n 80096f6 { #if defined(RTC_CR_TAMPALRM_PU) && defined(RTC_CR_TAMPALRM_TYPE) && defined(RTC_CR_OUT2EN) hrtc->Instance->CR &= ~(RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN); 80096c8: 687b ldr r3, [r7, #4] 80096ca: 681b ldr r3, [r3, #0] 80096cc: 699a ldr r2, [r3, #24] 80096ce: 687b ldr r3, [r7, #4] 80096d0: 681b ldr r3, [r3, #0] 80096d2: f022 4260 bic.w r2, r2, #3758096384 ; 0xe0000000 80096d6: 619a str r2, [r3, #24] hrtc->Instance->CR |= (hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); 80096d8: 687b ldr r3, [r7, #4] 80096da: 681b ldr r3, [r3, #0] 80096dc: 6999 ldr r1, [r3, #24] 80096de: 687b ldr r3, [r7, #4] 80096e0: 6a1a ldr r2, [r3, #32] 80096e2: 687b ldr r3, [r7, #4] 80096e4: 69db ldr r3, [r3, #28] 80096e6: 431a orrs r2, r3 80096e8: 687b ldr r3, [r7, #4] 80096ea: 695b ldr r3, [r3, #20] 80096ec: 431a orrs r2, r3 80096ee: 687b ldr r3, [r7, #4] 80096f0: 681b ldr r3, [r3, #0] 80096f2: 430a orrs r2, r1 80096f4: 619a str r2, [r3, #24] hrtc->Instance->OR |= (hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); #endif /* ALARMOUTTYPE && RTC_OR_OUT_RMP */ } } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 80096f6: 687b ldr r3, [r7, #4] 80096f8: 681b ldr r3, [r3, #0] 80096fa: 22ff movs r2, #255 ; 0xff 80096fc: 625a str r2, [r3, #36] ; 0x24 if (status == HAL_OK) 80096fe: 7bfb ldrb r3, [r7, #15] 8009700: 2b00 cmp r3, #0 8009702: d103 bne.n 800970c { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_READY; 8009704: 687b ldr r3, [r7, #4] 8009706: 2201 movs r2, #1 8009708: f883 2025 strb.w r2, [r3, #37] ; 0x25 } } /* return status */ return status; 800970c: 7bfb ldrb r3, [r7, #15] } 800970e: 4618 mov r0, r3 8009710: 3710 adds r7, #16 8009712: 46bd mov sp, r7 8009714: bd80 pop {r7, pc} 8009716: bf00 nop 8009718: fb8fffbf .word 0xfb8fffbf 0800971c : * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) { 800971c: b590 push {r4, r7, lr} 800971e: b087 sub sp, #28 8009720: af00 add r7, sp, #0 8009722: 60f8 str r0, [r7, #12] 8009724: 60b9 str r1, [r7, #8] 8009726: 607a str r2, [r7, #4] assert_param(IS_RTC_FORMAT(Format)); assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving)); assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation)); /* Process Locked */ __HAL_LOCK(hrtc); 8009728: 68fb ldr r3, [r7, #12] 800972a: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 800972e: 2b01 cmp r3, #1 8009730: d101 bne.n 8009736 8009732: 2302 movs r3, #2 8009734: e089 b.n 800984a 8009736: 68fb ldr r3, [r7, #12] 8009738: 2201 movs r2, #1 800973a: f883 2024 strb.w r2, [r3, #36] ; 0x24 hrtc->State = HAL_RTC_STATE_BUSY; 800973e: 68fb ldr r3, [r7, #12] 8009740: 2202 movs r2, #2 8009742: f883 2025 strb.w r2, [r3, #37] ; 0x25 /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 8009746: 68fb ldr r3, [r7, #12] 8009748: 681b ldr r3, [r3, #0] 800974a: 22ca movs r2, #202 ; 0xca 800974c: 625a str r2, [r3, #36] ; 0x24 800974e: 68fb ldr r3, [r7, #12] 8009750: 681b ldr r3, [r3, #0] 8009752: 2253 movs r2, #83 ; 0x53 8009754: 625a str r2, [r3, #36] ; 0x24 /* Enter Initialization mode */ status = RTC_EnterInitMode(hrtc); 8009756: 68f8 ldr r0, [r7, #12] 8009758: f000 f92c bl 80099b4 800975c: 4603 mov r3, r0 800975e: 74fb strb r3, [r7, #19] if (status == HAL_OK) 8009760: 7cfb ldrb r3, [r7, #19] 8009762: 2b00 cmp r3, #0 8009764: d161 bne.n 800982a { if(Format == RTC_FORMAT_BIN) 8009766: 687b ldr r3, [r7, #4] 8009768: 2b00 cmp r3, #0 800976a: d126 bne.n 80097ba { if((hrtc->Instance->CR & RTC_CR_FMT) != 0U) 800976c: 68fb ldr r3, [r7, #12] 800976e: 681b ldr r3, [r3, #0] 8009770: 699b ldr r3, [r3, #24] 8009772: f003 0340 and.w r3, r3, #64 ; 0x40 8009776: 2b00 cmp r3, #0 8009778: d102 bne.n 8009780 assert_param(IS_RTC_HOUR12(sTime->Hours)); assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); } else { sTime->TimeFormat = 0x00U; 800977a: 68bb ldr r3, [r7, #8] 800977c: 2200 movs r2, #0 800977e: 70da strb r2, [r3, #3] assert_param(IS_RTC_HOUR24(sTime->Hours)); } assert_param(IS_RTC_MINUTES(sTime->Minutes)); assert_param(IS_RTC_SECONDS(sTime->Seconds)); tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \ 8009780: 68bb ldr r3, [r7, #8] 8009782: 781b ldrb r3, [r3, #0] 8009784: 4618 mov r0, r3 8009786: f000 f989 bl 8009a9c 800978a: 4603 mov r3, r0 800978c: 041c lsls r4, r3, #16 ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << RTC_TR_MNU_Pos) | \ 800978e: 68bb ldr r3, [r7, #8] 8009790: 785b ldrb r3, [r3, #1] 8009792: 4618 mov r0, r3 8009794: f000 f982 bl 8009a9c 8009798: 4603 mov r3, r0 800979a: 021b lsls r3, r3, #8 tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \ 800979c: 431c orrs r4, r3 ((uint32_t)RTC_ByteToBcd2(sTime->Seconds) << RTC_TR_SU_Pos) | \ 800979e: 68bb ldr r3, [r7, #8] 80097a0: 789b ldrb r3, [r3, #2] 80097a2: 4618 mov r0, r3 80097a4: f000 f97a bl 8009a9c 80097a8: 4603 mov r3, r0 ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << RTC_TR_MNU_Pos) | \ 80097aa: ea44 0203 orr.w r2, r4, r3 (((uint32_t)sTime->TimeFormat) << RTC_TR_PM_Pos)); 80097ae: 68bb ldr r3, [r7, #8] 80097b0: 78db ldrb r3, [r3, #3] 80097b2: 059b lsls r3, r3, #22 tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \ 80097b4: 4313 orrs r3, r2 80097b6: 617b str r3, [r7, #20] 80097b8: e018 b.n 80097ec } else { if((hrtc->Instance->CR & RTC_CR_FMT) != 0U) 80097ba: 68fb ldr r3, [r7, #12] 80097bc: 681b ldr r3, [r3, #0] 80097be: 699b ldr r3, [r3, #24] 80097c0: f003 0340 and.w r3, r3, #64 ; 0x40 80097c4: 2b00 cmp r3, #0 80097c6: d102 bne.n 80097ce assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours))); assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); } else { sTime->TimeFormat = 0x00U; 80097c8: 68bb ldr r3, [r7, #8] 80097ca: 2200 movs r2, #0 80097cc: 70da strb r2, [r3, #3] assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); } assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \ 80097ce: 68bb ldr r3, [r7, #8] 80097d0: 781b ldrb r3, [r3, #0] 80097d2: 041a lsls r2, r3, #16 ((uint32_t)(sTime->Minutes) << RTC_TR_MNU_Pos) | \ 80097d4: 68bb ldr r3, [r7, #8] 80097d6: 785b ldrb r3, [r3, #1] 80097d8: 021b lsls r3, r3, #8 tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \ 80097da: 4313 orrs r3, r2 ((uint32_t)(sTime->Seconds) << RTC_TR_SU_Pos) | \ 80097dc: 68ba ldr r2, [r7, #8] 80097de: 7892 ldrb r2, [r2, #2] ((uint32_t)(sTime->Minutes) << RTC_TR_MNU_Pos) | \ 80097e0: 431a orrs r2, r3 ((uint32_t)(sTime->TimeFormat) << RTC_TR_PM_Pos)); 80097e2: 68bb ldr r3, [r7, #8] 80097e4: 78db ldrb r3, [r3, #3] 80097e6: 059b lsls r3, r3, #22 tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \ 80097e8: 4313 orrs r3, r2 80097ea: 617b str r3, [r7, #20] } /* Set the RTC_TR register */ hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); 80097ec: 68fb ldr r3, [r7, #12] 80097ee: 681a ldr r2, [r3, #0] 80097f0: 6979 ldr r1, [r7, #20] 80097f2: 4b18 ldr r3, [pc, #96] ; (8009854 ) 80097f4: 400b ands r3, r1 80097f6: 6013 str r3, [r2, #0] /* Clear the bits to be configured */ hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BKP); 80097f8: 68fb ldr r3, [r7, #12] 80097fa: 681b ldr r3, [r3, #0] 80097fc: 699a ldr r2, [r3, #24] 80097fe: 68fb ldr r3, [r7, #12] 8009800: 681b ldr r3, [r3, #0] 8009802: f422 2280 bic.w r2, r2, #262144 ; 0x40000 8009806: 619a str r2, [r3, #24] /* Configure the RTC_CR register */ hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); 8009808: 68fb ldr r3, [r7, #12] 800980a: 681b ldr r3, [r3, #0] 800980c: 6999 ldr r1, [r3, #24] 800980e: 68bb ldr r3, [r7, #8] 8009810: 68da ldr r2, [r3, #12] 8009812: 68bb ldr r3, [r7, #8] 8009814: 691b ldr r3, [r3, #16] 8009816: 431a orrs r2, r3 8009818: 68fb ldr r3, [r7, #12] 800981a: 681b ldr r3, [r3, #0] 800981c: 430a orrs r2, r1 800981e: 619a str r2, [r3, #24] /* Exit Initialization mode */ status = RTC_ExitInitMode(hrtc); 8009820: 68f8 ldr r0, [r7, #12] 8009822: f000 f8fd bl 8009a20 8009826: 4603 mov r3, r0 8009828: 74fb strb r3, [r7, #19] } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 800982a: 68fb ldr r3, [r7, #12] 800982c: 681b ldr r3, [r3, #0] 800982e: 22ff movs r2, #255 ; 0xff 8009830: 625a str r2, [r3, #36] ; 0x24 if (status == HAL_OK) 8009832: 7cfb ldrb r3, [r7, #19] 8009834: 2b00 cmp r3, #0 8009836: d103 bne.n 8009840 { hrtc->State = HAL_RTC_STATE_READY; 8009838: 68fb ldr r3, [r7, #12] 800983a: 2201 movs r2, #1 800983c: f883 2025 strb.w r2, [r3, #37] ; 0x25 } /* Process Unlocked */ __HAL_UNLOCK(hrtc); 8009840: 68fb ldr r3, [r7, #12] 8009842: 2200 movs r2, #0 8009844: f883 2024 strb.w r2, [r3, #36] ; 0x24 return status; 8009848: 7cfb ldrb r3, [r7, #19] } 800984a: 4618 mov r0, r3 800984c: 371c adds r7, #28 800984e: 46bd mov sp, r7 8009850: bd90 pop {r4, r7, pc} 8009852: bf00 nop 8009854: 007f7f7f .word 0x007f7f7f 08009858 : * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) { 8009858: b590 push {r4, r7, lr} 800985a: b087 sub sp, #28 800985c: af00 add r7, sp, #0 800985e: 60f8 str r0, [r7, #12] 8009860: 60b9 str r1, [r7, #8] 8009862: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); /* Process Locked */ __HAL_LOCK(hrtc); 8009864: 68fb ldr r3, [r7, #12] 8009866: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 800986a: 2b01 cmp r3, #1 800986c: d101 bne.n 8009872 800986e: 2302 movs r3, #2 8009870: e073 b.n 800995a 8009872: 68fb ldr r3, [r7, #12] 8009874: 2201 movs r2, #1 8009876: f883 2024 strb.w r2, [r3, #36] ; 0x24 hrtc->State = HAL_RTC_STATE_BUSY; 800987a: 68fb ldr r3, [r7, #12] 800987c: 2202 movs r2, #2 800987e: f883 2025 strb.w r2, [r3, #37] ; 0x25 if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) 8009882: 687b ldr r3, [r7, #4] 8009884: 2b00 cmp r3, #0 8009886: d10e bne.n 80098a6 8009888: 68bb ldr r3, [r7, #8] 800988a: 785b ldrb r3, [r3, #1] 800988c: f003 0310 and.w r3, r3, #16 8009890: 2b00 cmp r3, #0 8009892: d008 beq.n 80098a6 { sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU); 8009894: 68bb ldr r3, [r7, #8] 8009896: 785b ldrb r3, [r3, #1] 8009898: f023 0310 bic.w r3, r3, #16 800989c: b2db uxtb r3, r3 800989e: 330a adds r3, #10 80098a0: b2da uxtb r2, r3 80098a2: 68bb ldr r3, [r7, #8] 80098a4: 705a strb r2, [r3, #1] } assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); if(Format == RTC_FORMAT_BIN) 80098a6: 687b ldr r3, [r7, #4] 80098a8: 2b00 cmp r3, #0 80098aa: d11c bne.n 80098e6 { assert_param(IS_RTC_YEAR(sDate->Year)); assert_param(IS_RTC_MONTH(sDate->Month)); assert_param(IS_RTC_DATE(sDate->Date)); datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << RTC_DR_YU_Pos) | \ 80098ac: 68bb ldr r3, [r7, #8] 80098ae: 78db ldrb r3, [r3, #3] 80098b0: 4618 mov r0, r3 80098b2: f000 f8f3 bl 8009a9c 80098b6: 4603 mov r3, r0 80098b8: 041c lsls r4, r3, #16 ((uint32_t)RTC_ByteToBcd2(sDate->Month) << RTC_DR_MU_Pos) | \ 80098ba: 68bb ldr r3, [r7, #8] 80098bc: 785b ldrb r3, [r3, #1] 80098be: 4618 mov r0, r3 80098c0: f000 f8ec bl 8009a9c 80098c4: 4603 mov r3, r0 80098c6: 021b lsls r3, r3, #8 datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << RTC_DR_YU_Pos) | \ 80098c8: 431c orrs r4, r3 ((uint32_t)RTC_ByteToBcd2(sDate->Date) << RTC_DR_DU_Pos) | \ 80098ca: 68bb ldr r3, [r7, #8] 80098cc: 789b ldrb r3, [r3, #2] 80098ce: 4618 mov r0, r3 80098d0: f000 f8e4 bl 8009a9c 80098d4: 4603 mov r3, r0 ((uint32_t)RTC_ByteToBcd2(sDate->Month) << RTC_DR_MU_Pos) | \ 80098d6: ea44 0203 orr.w r2, r4, r3 ((uint32_t)sDate->WeekDay << RTC_DR_WDU_Pos)); 80098da: 68bb ldr r3, [r7, #8] 80098dc: 781b ldrb r3, [r3, #0] 80098de: 035b lsls r3, r3, #13 datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << RTC_DR_YU_Pos) | \ 80098e0: 4313 orrs r3, r2 80098e2: 617b str r3, [r7, #20] 80098e4: e00e b.n 8009904 { assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month))); assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date))); datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \ 80098e6: 68bb ldr r3, [r7, #8] 80098e8: 78db ldrb r3, [r3, #3] 80098ea: 041a lsls r2, r3, #16 (((uint32_t)sDate->Month) << RTC_DR_MU_Pos) | \ 80098ec: 68bb ldr r3, [r7, #8] 80098ee: 785b ldrb r3, [r3, #1] 80098f0: 021b lsls r3, r3, #8 datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \ 80098f2: 4313 orrs r3, r2 (((uint32_t)sDate->Date) << RTC_DR_DU_Pos) | \ 80098f4: 68ba ldr r2, [r7, #8] 80098f6: 7892 ldrb r2, [r2, #2] (((uint32_t)sDate->Month) << RTC_DR_MU_Pos) | \ 80098f8: 431a orrs r2, r3 (((uint32_t)sDate->WeekDay) << RTC_DR_WDU_Pos)); 80098fa: 68bb ldr r3, [r7, #8] 80098fc: 781b ldrb r3, [r3, #0] 80098fe: 035b lsls r3, r3, #13 datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \ 8009900: 4313 orrs r3, r2 8009902: 617b str r3, [r7, #20] } /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 8009904: 68fb ldr r3, [r7, #12] 8009906: 681b ldr r3, [r3, #0] 8009908: 22ca movs r2, #202 ; 0xca 800990a: 625a str r2, [r3, #36] ; 0x24 800990c: 68fb ldr r3, [r7, #12] 800990e: 681b ldr r3, [r3, #0] 8009910: 2253 movs r2, #83 ; 0x53 8009912: 625a str r2, [r3, #36] ; 0x24 /* Enter Initialization mode */ status = RTC_EnterInitMode(hrtc); 8009914: 68f8 ldr r0, [r7, #12] 8009916: f000 f84d bl 80099b4 800991a: 4603 mov r3, r0 800991c: 74fb strb r3, [r7, #19] if (status == HAL_OK) 800991e: 7cfb ldrb r3, [r7, #19] 8009920: 2b00 cmp r3, #0 8009922: d10a bne.n 800993a { /* Set the RTC_DR register */ hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK); 8009924: 68fb ldr r3, [r7, #12] 8009926: 681a ldr r2, [r3, #0] 8009928: 6979 ldr r1, [r7, #20] 800992a: 4b0e ldr r3, [pc, #56] ; (8009964 ) 800992c: 400b ands r3, r1 800992e: 6053 str r3, [r2, #4] /* Exit Initialization mode */ status = RTC_ExitInitMode(hrtc); 8009930: 68f8 ldr r0, [r7, #12] 8009932: f000 f875 bl 8009a20 8009936: 4603 mov r3, r0 8009938: 74fb strb r3, [r7, #19] } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 800993a: 68fb ldr r3, [r7, #12] 800993c: 681b ldr r3, [r3, #0] 800993e: 22ff movs r2, #255 ; 0xff 8009940: 625a str r2, [r3, #36] ; 0x24 if (status == HAL_OK) 8009942: 7cfb ldrb r3, [r7, #19] 8009944: 2b00 cmp r3, #0 8009946: d103 bne.n 8009950 { hrtc->State = HAL_RTC_STATE_READY; 8009948: 68fb ldr r3, [r7, #12] 800994a: 2201 movs r2, #1 800994c: f883 2025 strb.w r2, [r3, #37] ; 0x25 } /* Process Unlocked */ __HAL_UNLOCK(hrtc); 8009950: 68fb ldr r3, [r7, #12] 8009952: 2200 movs r2, #0 8009954: f883 2024 strb.w r2, [r3, #36] ; 0x24 return status; 8009958: 7cfb ldrb r3, [r7, #19] } 800995a: 4618 mov r0, r3 800995c: 371c adds r7, #28 800995e: 46bd mov sp, r7 8009960: bd90 pop {r4, r7, pc} 8009962: bf00 nop 8009964: 00ffff3f .word 0x00ffff3f 08009968 : * correctly copied into the RTC_TR and RTC_DR shadow registers. * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) { 8009968: b580 push {r7, lr} 800996a: b084 sub sp, #16 800996c: af00 add r7, sp, #0 800996e: 6078 str r0, [r7, #4] uint32_t tickstart; /* Clear RSF flag */ #if defined(RTC_ICSR_RSF) hrtc->Instance->ICSR &= (uint32_t)RTC_RSF_MASK; 8009970: 687b ldr r3, [r7, #4] 8009972: 681b ldr r3, [r3, #0] 8009974: 68da ldr r2, [r3, #12] 8009976: 687b ldr r3, [r7, #4] 8009978: 681b ldr r3, [r3, #0] 800997a: f022 02a0 bic.w r2, r2, #160 ; 0xa0 800997e: 60da str r2, [r3, #12] #endif /* RTC_ICSR_RSF */ #if defined(RTC_ISR_RSF) hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; #endif /* RTC_ISR_RSF */ tickstart = HAL_GetTick(); 8009980: f7f9 fc32 bl 80031e8 8009984: 60f8 str r0, [r7, #12] /* Wait the registers to be synchronised */ #if defined(RTC_ICSR_RSF) while ((hrtc->Instance->ICSR & RTC_ICSR_RSF) == 0U) 8009986: e009 b.n 800999c #endif /* RTC_ICSR_RSF */ #if defined(RTC_ISR_RSF) while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U) #endif /* RTC_ISR_RSF */ { if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 8009988: f7f9 fc2e bl 80031e8 800998c: 4602 mov r2, r0 800998e: 68fb ldr r3, [r7, #12] 8009990: 1ad3 subs r3, r2, r3 8009992: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 8009996: d901 bls.n 800999c { return HAL_TIMEOUT; 8009998: 2303 movs r3, #3 800999a: e007 b.n 80099ac while ((hrtc->Instance->ICSR & RTC_ICSR_RSF) == 0U) 800999c: 687b ldr r3, [r7, #4] 800999e: 681b ldr r3, [r3, #0] 80099a0: 68db ldr r3, [r3, #12] 80099a2: f003 0320 and.w r3, r3, #32 80099a6: 2b00 cmp r3, #0 80099a8: d0ee beq.n 8009988 } } return HAL_OK; 80099aa: 2300 movs r3, #0 } 80099ac: 4618 mov r0, r3 80099ae: 3710 adds r7, #16 80099b0: 46bd mov sp, r7 80099b2: bd80 pop {r7, pc} 080099b4 : * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) { 80099b4: b580 push {r7, lr} 80099b6: b084 sub sp, #16 80099b8: af00 add r7, sp, #0 80099ba: 6078 str r0, [r7, #4] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 80099bc: 2300 movs r3, #0 80099be: 73fb strb r3, [r7, #15] /* Check if the Initialization mode is set */ #if defined(RTC_ICSR_INITF) if((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U) 80099c0: 687b ldr r3, [r7, #4] 80099c2: 681b ldr r3, [r3, #0] 80099c4: 68db ldr r3, [r3, #12] 80099c6: f003 0340 and.w r3, r3, #64 ; 0x40 80099ca: 2b00 cmp r3, #0 80099cc: d123 bne.n 8009a16 { /* Set the Initialization mode */ SET_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT); 80099ce: 687b ldr r3, [r7, #4] 80099d0: 681b ldr r3, [r3, #0] 80099d2: 68da ldr r2, [r3, #12] 80099d4: 687b ldr r3, [r7, #4] 80099d6: 681b ldr r3, [r3, #0] 80099d8: f042 0280 orr.w r2, r2, #128 ; 0x80 80099dc: 60da str r2, [r3, #12] tickstart = HAL_GetTick(); 80099de: f7f9 fc03 bl 80031e8 80099e2: 60b8 str r0, [r7, #8] /* Wait till RTC is in INIT state and if Time out is reached exit */ while (((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U) && (status != HAL_TIMEOUT)) 80099e4: e00d b.n 8009a02 { if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 80099e6: f7f9 fbff bl 80031e8 80099ea: 4602 mov r2, r0 80099ec: 68bb ldr r3, [r7, #8] 80099ee: 1ad3 subs r3, r2, r3 80099f0: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 80099f4: d905 bls.n 8009a02 { status = HAL_TIMEOUT; 80099f6: 2303 movs r3, #3 80099f8: 73fb strb r3, [r7, #15] hrtc->State = HAL_RTC_STATE_TIMEOUT; 80099fa: 687b ldr r3, [r7, #4] 80099fc: 2203 movs r2, #3 80099fe: f883 2025 strb.w r2, [r3, #37] ; 0x25 while (((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U) && (status != HAL_TIMEOUT)) 8009a02: 687b ldr r3, [r7, #4] 8009a04: 681b ldr r3, [r3, #0] 8009a06: 68db ldr r3, [r3, #12] 8009a08: f003 0340 and.w r3, r3, #64 ; 0x40 8009a0c: 2b00 cmp r3, #0 8009a0e: d102 bne.n 8009a16 8009a10: 7bfb ldrb r3, [r7, #15] 8009a12: 2b03 cmp r3, #3 8009a14: d1e7 bne.n 80099e6 } } } #endif /* RTC_ISR_INITF */ return status; 8009a16: 7bfb ldrb r3, [r7, #15] } 8009a18: 4618 mov r0, r3 8009a1a: 3710 adds r7, #16 8009a1c: 46bd mov sp, r7 8009a1e: bd80 pop {r7, pc} 08009a20 : * @brief Exit the RTC Initialization mode. * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) { 8009a20: b580 push {r7, lr} 8009a22: b084 sub sp, #16 8009a24: af00 add r7, sp, #0 8009a26: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8009a28: 2300 movs r3, #0 8009a2a: 73fb strb r3, [r7, #15] /* Check if the Initialization mode is set */ #if defined(RTC_ICSR_INITF) /* Exit Initialization mode */ CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT); 8009a2c: 4b1a ldr r3, [pc, #104] ; (8009a98 ) 8009a2e: 68db ldr r3, [r3, #12] 8009a30: 4a19 ldr r2, [pc, #100] ; (8009a98 ) 8009a32: f023 0380 bic.w r3, r3, #128 ; 0x80 8009a36: 60d3 str r3, [r2, #12] /* Exit Initialization mode */ CLEAR_BIT(RTC->ISR, RTC_ISR_INITF); #endif /* RTC_ISR_INITF */ /* If CR_BYPSHAD bit = 0, wait for synchro */ if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U) 8009a38: 4b17 ldr r3, [pc, #92] ; (8009a98 ) 8009a3a: 699b ldr r3, [r3, #24] 8009a3c: f003 0320 and.w r3, r3, #32 8009a40: 2b00 cmp r3, #0 8009a42: d10c bne.n 8009a5e { if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) 8009a44: 6878 ldr r0, [r7, #4] 8009a46: f7ff ff8f bl 8009968 8009a4a: 4603 mov r3, r0 8009a4c: 2b00 cmp r3, #0 8009a4e: d01e beq.n 8009a8e { hrtc->State = HAL_RTC_STATE_TIMEOUT; 8009a50: 687b ldr r3, [r7, #4] 8009a52: 2203 movs r2, #3 8009a54: f883 2025 strb.w r2, [r3, #37] ; 0x25 status = HAL_TIMEOUT; 8009a58: 2303 movs r3, #3 8009a5a: 73fb strb r3, [r7, #15] 8009a5c: e017 b.n 8009a8e } } else { /* Clear BYPSHAD bit */ CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD); 8009a5e: 4b0e ldr r3, [pc, #56] ; (8009a98 ) 8009a60: 699b ldr r3, [r3, #24] 8009a62: 4a0d ldr r2, [pc, #52] ; (8009a98 ) 8009a64: f023 0320 bic.w r3, r3, #32 8009a68: 6193 str r3, [r2, #24] if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) 8009a6a: 6878 ldr r0, [r7, #4] 8009a6c: f7ff ff7c bl 8009968 8009a70: 4603 mov r3, r0 8009a72: 2b00 cmp r3, #0 8009a74: d005 beq.n 8009a82 { hrtc->State = HAL_RTC_STATE_TIMEOUT; 8009a76: 687b ldr r3, [r7, #4] 8009a78: 2203 movs r2, #3 8009a7a: f883 2025 strb.w r2, [r3, #37] ; 0x25 status = HAL_TIMEOUT; 8009a7e: 2303 movs r3, #3 8009a80: 73fb strb r3, [r7, #15] } /* Restore BYPSHAD bit */ SET_BIT(RTC->CR, RTC_CR_BYPSHAD); 8009a82: 4b05 ldr r3, [pc, #20] ; (8009a98 ) 8009a84: 699b ldr r3, [r3, #24] 8009a86: 4a04 ldr r2, [pc, #16] ; (8009a98 ) 8009a88: f043 0320 orr.w r3, r3, #32 8009a8c: 6193 str r3, [r2, #24] } return status; 8009a8e: 7bfb ldrb r3, [r7, #15] } 8009a90: 4618 mov r0, r3 8009a92: 3710 adds r7, #16 8009a94: 46bd mov sp, r7 8009a96: bd80 pop {r7, pc} 8009a98: 58004000 .word 0x58004000 08009a9c : * @brief Convert a 2 digit decimal to BCD format. * @param Value Byte to be converted * @retval Converted byte */ uint8_t RTC_ByteToBcd2(uint8_t Value) { 8009a9c: b480 push {r7} 8009a9e: b085 sub sp, #20 8009aa0: af00 add r7, sp, #0 8009aa2: 4603 mov r3, r0 8009aa4: 71fb strb r3, [r7, #7] uint32_t bcdhigh = 0U; 8009aa6: 2300 movs r3, #0 8009aa8: 60fb str r3, [r7, #12] uint8_t bcdlow = Value; 8009aaa: 79fb ldrb r3, [r7, #7] 8009aac: 72fb strb r3, [r7, #11] while (bcdlow >= 10U) 8009aae: e005 b.n 8009abc { bcdhigh++; 8009ab0: 68fb ldr r3, [r7, #12] 8009ab2: 3301 adds r3, #1 8009ab4: 60fb str r3, [r7, #12] bcdlow -= 10U; 8009ab6: 7afb ldrb r3, [r7, #11] 8009ab8: 3b0a subs r3, #10 8009aba: 72fb strb r3, [r7, #11] while (bcdlow >= 10U) 8009abc: 7afb ldrb r3, [r7, #11] 8009abe: 2b09 cmp r3, #9 8009ac0: d8f6 bhi.n 8009ab0 } return ((uint8_t)(bcdhigh << 4U) | bcdlow); 8009ac2: 68fb ldr r3, [r7, #12] 8009ac4: b2db uxtb r3, r3 8009ac6: 011b lsls r3, r3, #4 8009ac8: b2da uxtb r2, r3 8009aca: 7afb ldrb r3, [r7, #11] 8009acc: 4313 orrs r3, r2 8009ace: b2db uxtb r3, r3 } 8009ad0: 4618 mov r0, r3 8009ad2: 3714 adds r7, #20 8009ad4: 46bd mov sp, r7 8009ad6: f85d 7b04 ldr.w r7, [sp], #4 8009ada: 4770 bx lr 08009adc : SD_HandleTypeDef and create the associated handle. * @param hsd: Pointer to the SD handle * @retval HAL status */ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) { 8009adc: b580 push {r7, lr} 8009ade: b08a sub sp, #40 ; 0x28 8009ae0: af00 add r7, sp, #0 8009ae2: 6078 str r0, [r7, #4] uint32_t speedgrade; uint32_t unitsize; uint32_t tickstart; /* Check the SD handle allocation */ if (hsd == NULL) 8009ae4: 687b ldr r3, [r7, #4] 8009ae6: 2b00 cmp r3, #0 8009ae8: d101 bne.n 8009aee { return HAL_ERROR; 8009aea: 2301 movs r3, #1 8009aec: e075 b.n 8009bda assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave)); assert_param(IS_SDMMC_BUS_WIDE(hsd->Init.BusWide)); assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl)); assert_param(IS_SDMMC_CLKDIV(hsd->Init.ClockDiv)); if (hsd->State == HAL_SD_STATE_RESET) 8009aee: 687b ldr r3, [r7, #4] 8009af0: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 8009af4: b2db uxtb r3, r3 8009af6: 2b00 cmp r3, #0 8009af8: d105 bne.n 8009b06 { /* Allocate lock resource and initialize it */ hsd->Lock = HAL_UNLOCKED; 8009afa: 687b ldr r3, [r7, #4] 8009afc: 2200 movs r2, #0 8009afe: 761a strb r2, [r3, #24] /* Init the low level hardware */ hsd->MspInitCallback(hsd); #else /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_SD_MspInit(hsd); 8009b00: 6878 ldr r0, [r7, #4] 8009b02: f7f9 f87f bl 8002c04 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } hsd->State = HAL_SD_STATE_PROGRAMMING; 8009b06: 687b ldr r3, [r7, #4] 8009b08: 2204 movs r2, #4 8009b0a: f883 2030 strb.w r2, [r3, #48] ; 0x30 /* Initialize the Card parameters */ if (HAL_SD_InitCard(hsd) != HAL_OK) 8009b0e: 6878 ldr r0, [r7, #4] 8009b10: f000 f868 bl 8009be4 8009b14: 4603 mov r3, r0 8009b16: 2b00 cmp r3, #0 8009b18: d001 beq.n 8009b1e { return HAL_ERROR; 8009b1a: 2301 movs r3, #1 8009b1c: e05d b.n 8009bda } if (HAL_SD_GetCardStatus(hsd, &CardStatus) != HAL_OK) 8009b1e: f107 0308 add.w r3, r7, #8 8009b22: 4619 mov r1, r3 8009b24: 6878 ldr r0, [r7, #4] 8009b26: f000 fdaf bl 800a688 8009b2a: 4603 mov r3, r0 8009b2c: 2b00 cmp r3, #0 8009b2e: d001 beq.n 8009b34 { return HAL_ERROR; 8009b30: 2301 movs r3, #1 8009b32: e052 b.n 8009bda } /* Get Initial Card Speed from Card Status*/ speedgrade = CardStatus.UhsSpeedGrade; 8009b34: 7e3b ldrb r3, [r7, #24] 8009b36: b2db uxtb r3, r3 8009b38: 627b str r3, [r7, #36] ; 0x24 unitsize = CardStatus.UhsAllocationUnitSize; 8009b3a: 7e7b ldrb r3, [r7, #25] 8009b3c: b2db uxtb r3, r3 8009b3e: 623b str r3, [r7, #32] if ((hsd->SdCard.CardType == CARD_SDHC_SDXC) && ((speedgrade != 0U) || (unitsize != 0U))) 8009b40: 687b ldr r3, [r7, #4] 8009b42: 6b9b ldr r3, [r3, #56] ; 0x38 8009b44: 2b01 cmp r3, #1 8009b46: d10a bne.n 8009b5e 8009b48: 6a7b ldr r3, [r7, #36] ; 0x24 8009b4a: 2b00 cmp r3, #0 8009b4c: d102 bne.n 8009b54 8009b4e: 6a3b ldr r3, [r7, #32] 8009b50: 2b00 cmp r3, #0 8009b52: d004 beq.n 8009b5e { hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED; 8009b54: 687b ldr r3, [r7, #4] 8009b56: f44f 7200 mov.w r2, #512 ; 0x200 8009b5a: 659a str r2, [r3, #88] ; 0x58 8009b5c: e00b b.n 8009b76 } else { if (hsd->SdCard.CardType == CARD_SDHC_SDXC) 8009b5e: 687b ldr r3, [r7, #4] 8009b60: 6b9b ldr r3, [r3, #56] ; 0x38 8009b62: 2b01 cmp r3, #1 8009b64: d104 bne.n 8009b70 { hsd->SdCard.CardSpeed = CARD_HIGH_SPEED; 8009b66: 687b ldr r3, [r7, #4] 8009b68: f44f 7280 mov.w r2, #256 ; 0x100 8009b6c: 659a str r2, [r3, #88] ; 0x58 8009b6e: e002 b.n 8009b76 } else { hsd->SdCard.CardSpeed = CARD_NORMAL_SPEED; 8009b70: 687b ldr r3, [r7, #4] 8009b72: 2200 movs r2, #0 8009b74: 659a str r2, [r3, #88] ; 0x58 } } /* Configure the bus wide */ if (HAL_SD_ConfigWideBusOperation(hsd, hsd->Init.BusWide) != HAL_OK) 8009b76: 687b ldr r3, [r7, #4] 8009b78: 68db ldr r3, [r3, #12] 8009b7a: 4619 mov r1, r3 8009b7c: 6878 ldr r0, [r7, #4] 8009b7e: f000 fe6d bl 800a85c 8009b82: 4603 mov r3, r0 8009b84: 2b00 cmp r3, #0 8009b86: d001 beq.n 8009b8c { return HAL_ERROR; 8009b88: 2301 movs r3, #1 8009b8a: e026 b.n 8009bda } /* Verify that SD card is ready to use after Initialization */ tickstart = HAL_GetTick(); 8009b8c: f7f9 fb2c bl 80031e8 8009b90: 61f8 str r0, [r7, #28] while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER)) 8009b92: e011 b.n 8009bb8 { if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) 8009b94: f7f9 fb28 bl 80031e8 8009b98: 4602 mov r2, r0 8009b9a: 69fb ldr r3, [r7, #28] 8009b9c: 1ad3 subs r3, r2, r3 8009b9e: f1b3 3fff cmp.w r3, #4294967295 8009ba2: d109 bne.n 8009bb8 { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; 8009ba4: 687b ldr r3, [r7, #4] 8009ba6: f04f 4200 mov.w r2, #2147483648 ; 0x80000000 8009baa: 635a str r2, [r3, #52] ; 0x34 hsd->State = HAL_SD_STATE_READY; 8009bac: 687b ldr r3, [r7, #4] 8009bae: 2201 movs r2, #1 8009bb0: f883 2030 strb.w r2, [r3, #48] ; 0x30 return HAL_TIMEOUT; 8009bb4: 2303 movs r3, #3 8009bb6: e010 b.n 8009bda while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER)) 8009bb8: 6878 ldr r0, [r7, #4] 8009bba: f000 ff61 bl 800aa80 8009bbe: 4603 mov r3, r0 8009bc0: 2b04 cmp r3, #4 8009bc2: d1e7 bne.n 8009b94 } } /* Initialize the error code */ hsd->ErrorCode = HAL_SD_ERROR_NONE; 8009bc4: 687b ldr r3, [r7, #4] 8009bc6: 2200 movs r2, #0 8009bc8: 635a str r2, [r3, #52] ; 0x34 /* Initialize the SD operation */ hsd->Context = SD_CONTEXT_NONE; 8009bca: 687b ldr r3, [r7, #4] 8009bcc: 2200 movs r2, #0 8009bce: 62da str r2, [r3, #44] ; 0x2c /* Initialize the SD state */ hsd->State = HAL_SD_STATE_READY; 8009bd0: 687b ldr r3, [r7, #4] 8009bd2: 2201 movs r2, #1 8009bd4: f883 2030 strb.w r2, [r3, #48] ; 0x30 return HAL_OK; 8009bd8: 2300 movs r3, #0 } 8009bda: 4618 mov r0, r3 8009bdc: 3728 adds r7, #40 ; 0x28 8009bde: 46bd mov sp, r7 8009be0: bd80 pop {r7, pc} ... 08009be4 : * @note This function initializes the SD card. It could be used when a card re-initialization is needed. * @retval HAL status */ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) { 8009be4: b590 push {r4, r7, lr} 8009be6: b08d sub sp, #52 ; 0x34 8009be8: af02 add r7, sp, #8 8009bea: 6078 str r0, [r7, #4] uint32_t errorstate; SD_InitTypeDef Init; uint32_t sdmmc_clk = 0U; 8009bec: 2300 movs r3, #0 8009bee: 627b str r3, [r7, #36] ; 0x24 /* Default SDMMC peripheral configuration for SD card initialization */ Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; 8009bf0: 2300 movs r3, #0 8009bf2: 60fb str r3, [r7, #12] Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; 8009bf4: 2300 movs r3, #0 8009bf6: 613b str r3, [r7, #16] Init.BusWide = SDMMC_BUS_WIDE_1B; 8009bf8: 2300 movs r3, #0 8009bfa: 617b str r3, [r7, #20] Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; 8009bfc: 2300 movs r3, #0 8009bfe: 61bb str r3, [r7, #24] /* Init Clock should be less or equal to 400Khz*/ sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC); 8009c00: f44f 3080 mov.w r0, #65536 ; 0x10000 8009c04: f7fe fb70 bl 80082e8 8009c08: 6278 str r0, [r7, #36] ; 0x24 if (sdmmc_clk == 0U) 8009c0a: 6a7b ldr r3, [r7, #36] ; 0x24 8009c0c: 2b00 cmp r3, #0 8009c0e: d109 bne.n 8009c24 { hsd->State = HAL_SD_STATE_READY; 8009c10: 687b ldr r3, [r7, #4] 8009c12: 2201 movs r2, #1 8009c14: f883 2030 strb.w r2, [r3, #48] ; 0x30 hsd->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER; 8009c18: 687b ldr r3, [r7, #4] 8009c1a: f04f 6200 mov.w r2, #134217728 ; 0x8000000 8009c1e: 635a str r2, [r3, #52] ; 0x34 return HAL_ERROR; 8009c20: 2301 movs r3, #1 8009c22: e06a b.n 8009cfa } Init.ClockDiv = sdmmc_clk / (2U * SD_INIT_FREQ); 8009c24: 6a7b ldr r3, [r7, #36] ; 0x24 8009c26: 0a1b lsrs r3, r3, #8 8009c28: 4a36 ldr r2, [pc, #216] ; (8009d04 ) 8009c2a: fba2 2303 umull r2, r3, r2, r3 8009c2e: 091b lsrs r3, r3, #4 8009c30: 61fb str r3, [r7, #28] /* Set Transceiver polarity */ hsd->Instance->POWER |= SDMMC_POWER_DIRPOL; #endif /* USE_SD_TRANSCEIVER */ /* Initialize SDMMC peripheral interface with default configuration */ (void)SDMMC_Init(hsd->Instance, Init); 8009c32: 687b ldr r3, [r7, #4] 8009c34: 681c ldr r4, [r3, #0] 8009c36: 466a mov r2, sp 8009c38: f107 0318 add.w r3, r7, #24 8009c3c: e893 0003 ldmia.w r3, {r0, r1} 8009c40: e882 0003 stmia.w r2, {r0, r1} 8009c44: f107 030c add.w r3, r7, #12 8009c48: cb0e ldmia r3, {r1, r2, r3} 8009c4a: 4620 mov r0, r4 8009c4c: f003 fd02 bl 800d654 /* Set Power State to ON */ (void)SDMMC_PowerState_ON(hsd->Instance); 8009c50: 687b ldr r3, [r7, #4] 8009c52: 681b ldr r3, [r3, #0] 8009c54: 4618 mov r0, r3 8009c56: f003 fd45 bl 800d6e4 /* wait 74 Cycles: required power up waiting time before starting the SD initialization sequence */ sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv); 8009c5a: 69fb ldr r3, [r7, #28] 8009c5c: 005b lsls r3, r3, #1 8009c5e: 6a7a ldr r2, [r7, #36] ; 0x24 8009c60: fbb2 f3f3 udiv r3, r2, r3 8009c64: 627b str r3, [r7, #36] ; 0x24 HAL_Delay(1U + (74U * 1000U / (sdmmc_clk))); 8009c66: 4a28 ldr r2, [pc, #160] ; (8009d08 ) 8009c68: 6a7b ldr r3, [r7, #36] ; 0x24 8009c6a: fbb2 f3f3 udiv r3, r2, r3 8009c6e: 3301 adds r3, #1 8009c70: 4618 mov r0, r3 8009c72: f7f9 fac5 bl 8003200 /* Identify card operating voltage */ errorstate = SD_PowerON(hsd); 8009c76: 6878 ldr r0, [r7, #4] 8009c78: f000 fff0 bl 800ac5c 8009c7c: 6238 str r0, [r7, #32] if (errorstate != HAL_SD_ERROR_NONE) 8009c7e: 6a3b ldr r3, [r7, #32] 8009c80: 2b00 cmp r3, #0 8009c82: d00b beq.n 8009c9c { hsd->State = HAL_SD_STATE_READY; 8009c84: 687b ldr r3, [r7, #4] 8009c86: 2201 movs r2, #1 8009c88: f883 2030 strb.w r2, [r3, #48] ; 0x30 hsd->ErrorCode |= errorstate; 8009c8c: 687b ldr r3, [r7, #4] 8009c8e: 6b5a ldr r2, [r3, #52] ; 0x34 8009c90: 6a3b ldr r3, [r7, #32] 8009c92: 431a orrs r2, r3 8009c94: 687b ldr r3, [r7, #4] 8009c96: 635a str r2, [r3, #52] ; 0x34 return HAL_ERROR; 8009c98: 2301 movs r3, #1 8009c9a: e02e b.n 8009cfa } /* Card initialization */ errorstate = SD_InitCard(hsd); 8009c9c: 6878 ldr r0, [r7, #4] 8009c9e: f000 ff0f bl 800aac0 8009ca2: 6238 str r0, [r7, #32] if (errorstate != HAL_SD_ERROR_NONE) 8009ca4: 6a3b ldr r3, [r7, #32] 8009ca6: 2b00 cmp r3, #0 8009ca8: d00b beq.n 8009cc2 { hsd->State = HAL_SD_STATE_READY; 8009caa: 687b ldr r3, [r7, #4] 8009cac: 2201 movs r2, #1 8009cae: f883 2030 strb.w r2, [r3, #48] ; 0x30 hsd->ErrorCode |= errorstate; 8009cb2: 687b ldr r3, [r7, #4] 8009cb4: 6b5a ldr r2, [r3, #52] ; 0x34 8009cb6: 6a3b ldr r3, [r7, #32] 8009cb8: 431a orrs r2, r3 8009cba: 687b ldr r3, [r7, #4] 8009cbc: 635a str r2, [r3, #52] ; 0x34 return HAL_ERROR; 8009cbe: 2301 movs r3, #1 8009cc0: e01b b.n 8009cfa } /* Set Block Size for Card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); 8009cc2: 687b ldr r3, [r7, #4] 8009cc4: 681b ldr r3, [r3, #0] 8009cc6: f44f 7100 mov.w r1, #512 ; 0x200 8009cca: 4618 mov r0, r3 8009ccc: f003 fda0 bl 800d810 8009cd0: 6238 str r0, [r7, #32] if (errorstate != HAL_SD_ERROR_NONE) 8009cd2: 6a3b ldr r3, [r7, #32] 8009cd4: 2b00 cmp r3, #0 8009cd6: d00f beq.n 8009cf8 { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 8009cd8: 687b ldr r3, [r7, #4] 8009cda: 681b ldr r3, [r3, #0] 8009cdc: 4a0b ldr r2, [pc, #44] ; (8009d0c ) 8009cde: 639a str r2, [r3, #56] ; 0x38 hsd->ErrorCode |= errorstate; 8009ce0: 687b ldr r3, [r7, #4] 8009ce2: 6b5a ldr r2, [r3, #52] ; 0x34 8009ce4: 6a3b ldr r3, [r7, #32] 8009ce6: 431a orrs r2, r3 8009ce8: 687b ldr r3, [r7, #4] 8009cea: 635a str r2, [r3, #52] ; 0x34 hsd->State = HAL_SD_STATE_READY; 8009cec: 687b ldr r3, [r7, #4] 8009cee: 2201 movs r2, #1 8009cf0: f883 2030 strb.w r2, [r3, #48] ; 0x30 return HAL_ERROR; 8009cf4: 2301 movs r3, #1 8009cf6: e000 b.n 8009cfa } return HAL_OK; 8009cf8: 2300 movs r3, #0 } 8009cfa: 4618 mov r0, r3 8009cfc: 372c adds r7, #44 ; 0x2c 8009cfe: 46bd mov sp, r7 8009d00: bd90 pop {r4, r7, pc} 8009d02: bf00 nop 8009d04: 014f8b59 .word 0x014f8b59 8009d08: 00012110 .word 0x00012110 8009d0c: 1fe00fff .word 0x1fe00fff 08009d10 : * @param Timeout: Specify timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) { 8009d10: b580 push {r7, lr} 8009d12: b092 sub sp, #72 ; 0x48 8009d14: af00 add r7, sp, #0 8009d16: 60f8 str r0, [r7, #12] 8009d18: 60b9 str r1, [r7, #8] 8009d1a: 607a str r2, [r7, #4] 8009d1c: 603b str r3, [r7, #0] SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); 8009d1e: f7f9 fa63 bl 80031e8 8009d22: 6338 str r0, [r7, #48] ; 0x30 uint32_t count; uint32_t data; uint32_t dataremaining; uint32_t add = BlockAdd; 8009d24: 687b ldr r3, [r7, #4] 8009d26: 63bb str r3, [r7, #56] ; 0x38 uint8_t *tempbuff = pData; 8009d28: 68bb ldr r3, [r7, #8] 8009d2a: 637b str r3, [r7, #52] ; 0x34 if (NULL == pData) 8009d2c: 68bb ldr r3, [r7, #8] 8009d2e: 2b00 cmp r3, #0 8009d30: d107 bne.n 8009d42 { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; 8009d32: 68fb ldr r3, [r7, #12] 8009d34: 6b5b ldr r3, [r3, #52] ; 0x34 8009d36: f043 6200 orr.w r2, r3, #134217728 ; 0x8000000 8009d3a: 68fb ldr r3, [r7, #12] 8009d3c: 635a str r2, [r3, #52] ; 0x34 return HAL_ERROR; 8009d3e: 2301 movs r3, #1 8009d40: e167 b.n 800a012 } if (hsd->State == HAL_SD_STATE_READY) 8009d42: 68fb ldr r3, [r7, #12] 8009d44: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 8009d48: b2db uxtb r3, r3 8009d4a: 2b01 cmp r3, #1 8009d4c: f040 815a bne.w 800a004 { hsd->ErrorCode = HAL_SD_ERROR_NONE; 8009d50: 68fb ldr r3, [r7, #12] 8009d52: 2200 movs r2, #0 8009d54: 635a str r2, [r3, #52] ; 0x34 if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) 8009d56: 6bba ldr r2, [r7, #56] ; 0x38 8009d58: 683b ldr r3, [r7, #0] 8009d5a: 441a add r2, r3 8009d5c: 68fb ldr r3, [r7, #12] 8009d5e: 6d1b ldr r3, [r3, #80] ; 0x50 8009d60: 429a cmp r2, r3 8009d62: d907 bls.n 8009d74 { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; 8009d64: 68fb ldr r3, [r7, #12] 8009d66: 6b5b ldr r3, [r3, #52] ; 0x34 8009d68: f043 7200 orr.w r2, r3, #33554432 ; 0x2000000 8009d6c: 68fb ldr r3, [r7, #12] 8009d6e: 635a str r2, [r3, #52] ; 0x34 return HAL_ERROR; 8009d70: 2301 movs r3, #1 8009d72: e14e b.n 800a012 } hsd->State = HAL_SD_STATE_BUSY; 8009d74: 68fb ldr r3, [r7, #12] 8009d76: 2203 movs r2, #3 8009d78: f883 2030 strb.w r2, [r3, #48] ; 0x30 /* Initialize data control register */ hsd->Instance->DCTRL = 0U; 8009d7c: 68fb ldr r3, [r7, #12] 8009d7e: 681b ldr r3, [r3, #0] 8009d80: 2200 movs r2, #0 8009d82: 62da str r2, [r3, #44] ; 0x2c if (hsd->SdCard.CardType != CARD_SDHC_SDXC) 8009d84: 68fb ldr r3, [r7, #12] 8009d86: 6b9b ldr r3, [r3, #56] ; 0x38 8009d88: 2b01 cmp r3, #1 8009d8a: d002 beq.n 8009d92 { add *= 512U; 8009d8c: 6bbb ldr r3, [r7, #56] ; 0x38 8009d8e: 025b lsls r3, r3, #9 8009d90: 63bb str r3, [r7, #56] ; 0x38 } /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; 8009d92: f04f 33ff mov.w r3, #4294967295 8009d96: 617b str r3, [r7, #20] config.DataLength = NumberOfBlocks * BLOCKSIZE; 8009d98: 683b ldr r3, [r7, #0] 8009d9a: 025b lsls r3, r3, #9 8009d9c: 61bb str r3, [r7, #24] config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; 8009d9e: 2390 movs r3, #144 ; 0x90 8009da0: 61fb str r3, [r7, #28] config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; 8009da2: 2302 movs r3, #2 8009da4: 623b str r3, [r7, #32] config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; 8009da6: 2300 movs r3, #0 8009da8: 627b str r3, [r7, #36] ; 0x24 config.DPSM = SDMMC_DPSM_DISABLE; 8009daa: 2300 movs r3, #0 8009dac: 62bb str r3, [r7, #40] ; 0x28 (void)SDMMC_ConfigData(hsd->Instance, &config); 8009dae: 68fb ldr r3, [r7, #12] 8009db0: 681b ldr r3, [r3, #0] 8009db2: f107 0214 add.w r2, r7, #20 8009db6: 4611 mov r1, r2 8009db8: 4618 mov r0, r3 8009dba: f003 fcfd bl 800d7b8 __SDMMC_CMDTRANS_ENABLE(hsd->Instance); 8009dbe: 68fb ldr r3, [r7, #12] 8009dc0: 681b ldr r3, [r3, #0] 8009dc2: 68da ldr r2, [r3, #12] 8009dc4: 68fb ldr r3, [r7, #12] 8009dc6: 681b ldr r3, [r3, #0] 8009dc8: f042 0240 orr.w r2, r2, #64 ; 0x40 8009dcc: 60da str r2, [r3, #12] /* Read block(s) in polling mode */ if (NumberOfBlocks > 1U) 8009dce: 683b ldr r3, [r7, #0] 8009dd0: 2b01 cmp r3, #1 8009dd2: d90a bls.n 8009dea { hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK; 8009dd4: 68fb ldr r3, [r7, #12] 8009dd6: 2202 movs r2, #2 8009dd8: 62da str r2, [r3, #44] ; 0x2c /* Read Multi Block command */ errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); 8009dda: 68fb ldr r3, [r7, #12] 8009ddc: 681b ldr r3, [r3, #0] 8009dde: 6bb9 ldr r1, [r7, #56] ; 0x38 8009de0: 4618 mov r0, r3 8009de2: f003 fd5b bl 800d89c 8009de6: 6478 str r0, [r7, #68] ; 0x44 8009de8: e009 b.n 8009dfe } else { hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK; 8009dea: 68fb ldr r3, [r7, #12] 8009dec: 2201 movs r2, #1 8009dee: 62da str r2, [r3, #44] ; 0x2c /* Read Single Block command */ errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); 8009df0: 68fb ldr r3, [r7, #12] 8009df2: 681b ldr r3, [r3, #0] 8009df4: 6bb9 ldr r1, [r7, #56] ; 0x38 8009df6: 4618 mov r0, r3 8009df8: f003 fd2d bl 800d856 8009dfc: 6478 str r0, [r7, #68] ; 0x44 } if (errorstate != HAL_SD_ERROR_NONE) 8009dfe: 6c7b ldr r3, [r7, #68] ; 0x44 8009e00: 2b00 cmp r3, #0 8009e02: d012 beq.n 8009e2a { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 8009e04: 68fb ldr r3, [r7, #12] 8009e06: 681b ldr r3, [r3, #0] 8009e08: 4a84 ldr r2, [pc, #528] ; (800a01c ) 8009e0a: 639a str r2, [r3, #56] ; 0x38 hsd->ErrorCode |= errorstate; 8009e0c: 68fb ldr r3, [r7, #12] 8009e0e: 6b5a ldr r2, [r3, #52] ; 0x34 8009e10: 6c7b ldr r3, [r7, #68] ; 0x44 8009e12: 431a orrs r2, r3 8009e14: 68fb ldr r3, [r7, #12] 8009e16: 635a str r2, [r3, #52] ; 0x34 hsd->State = HAL_SD_STATE_READY; 8009e18: 68fb ldr r3, [r7, #12] 8009e1a: 2201 movs r2, #1 8009e1c: f883 2030 strb.w r2, [r3, #48] ; 0x30 hsd->Context = SD_CONTEXT_NONE; 8009e20: 68fb ldr r3, [r7, #12] 8009e22: 2200 movs r2, #0 8009e24: 62da str r2, [r3, #44] ; 0x2c return HAL_ERROR; 8009e26: 2301 movs r3, #1 8009e28: e0f3 b.n 800a012 } /* Poll on SDMMC flags */ dataremaining = config.DataLength; 8009e2a: 69bb ldr r3, [r7, #24] 8009e2c: 63fb str r3, [r7, #60] ; 0x3c while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) 8009e2e: e058 b.n 8009ee2 { if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U)) 8009e30: 68fb ldr r3, [r7, #12] 8009e32: 681b ldr r3, [r3, #0] 8009e34: 6b5b ldr r3, [r3, #52] ; 0x34 8009e36: f403 4300 and.w r3, r3, #32768 ; 0x8000 8009e3a: 2b00 cmp r3, #0 8009e3c: d033 beq.n 8009ea6 8009e3e: 6bfb ldr r3, [r7, #60] ; 0x3c 8009e40: 2b1f cmp r3, #31 8009e42: d930 bls.n 8009ea6 { /* Read data from SDMMC Rx FIFO */ for (count = 0U; count < 8U; count++) 8009e44: 2300 movs r3, #0 8009e46: 643b str r3, [r7, #64] ; 0x40 8009e48: e027 b.n 8009e9a { data = SDMMC_ReadFIFO(hsd->Instance); 8009e4a: 68fb ldr r3, [r7, #12] 8009e4c: 681b ldr r3, [r3, #0] 8009e4e: 4618 mov r0, r3 8009e50: f003 fc2a bl 800d6a8 8009e54: 62f8 str r0, [r7, #44] ; 0x2c *tempbuff = (uint8_t)(data & 0xFFU); 8009e56: 6afb ldr r3, [r7, #44] ; 0x2c 8009e58: b2da uxtb r2, r3 8009e5a: 6b7b ldr r3, [r7, #52] ; 0x34 8009e5c: 701a strb r2, [r3, #0] tempbuff++; 8009e5e: 6b7b ldr r3, [r7, #52] ; 0x34 8009e60: 3301 adds r3, #1 8009e62: 637b str r3, [r7, #52] ; 0x34 *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); 8009e64: 6afb ldr r3, [r7, #44] ; 0x2c 8009e66: 0a1b lsrs r3, r3, #8 8009e68: b2da uxtb r2, r3 8009e6a: 6b7b ldr r3, [r7, #52] ; 0x34 8009e6c: 701a strb r2, [r3, #0] tempbuff++; 8009e6e: 6b7b ldr r3, [r7, #52] ; 0x34 8009e70: 3301 adds r3, #1 8009e72: 637b str r3, [r7, #52] ; 0x34 *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); 8009e74: 6afb ldr r3, [r7, #44] ; 0x2c 8009e76: 0c1b lsrs r3, r3, #16 8009e78: b2da uxtb r2, r3 8009e7a: 6b7b ldr r3, [r7, #52] ; 0x34 8009e7c: 701a strb r2, [r3, #0] tempbuff++; 8009e7e: 6b7b ldr r3, [r7, #52] ; 0x34 8009e80: 3301 adds r3, #1 8009e82: 637b str r3, [r7, #52] ; 0x34 *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); 8009e84: 6afb ldr r3, [r7, #44] ; 0x2c 8009e86: 0e1b lsrs r3, r3, #24 8009e88: b2da uxtb r2, r3 8009e8a: 6b7b ldr r3, [r7, #52] ; 0x34 8009e8c: 701a strb r2, [r3, #0] tempbuff++; 8009e8e: 6b7b ldr r3, [r7, #52] ; 0x34 8009e90: 3301 adds r3, #1 8009e92: 637b str r3, [r7, #52] ; 0x34 for (count = 0U; count < 8U; count++) 8009e94: 6c3b ldr r3, [r7, #64] ; 0x40 8009e96: 3301 adds r3, #1 8009e98: 643b str r3, [r7, #64] ; 0x40 8009e9a: 6c3b ldr r3, [r7, #64] ; 0x40 8009e9c: 2b07 cmp r3, #7 8009e9e: d9d4 bls.n 8009e4a } dataremaining -= 32U; 8009ea0: 6bfb ldr r3, [r7, #60] ; 0x3c 8009ea2: 3b20 subs r3, #32 8009ea4: 63fb str r3, [r7, #60] ; 0x3c } if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) 8009ea6: f7f9 f99f bl 80031e8 8009eaa: 4602 mov r2, r0 8009eac: 6b3b ldr r3, [r7, #48] ; 0x30 8009eae: 1ad3 subs r3, r2, r3 8009eb0: 6d3a ldr r2, [r7, #80] ; 0x50 8009eb2: 429a cmp r2, r3 8009eb4: d902 bls.n 8009ebc 8009eb6: 6d3b ldr r3, [r7, #80] ; 0x50 8009eb8: 2b00 cmp r3, #0 8009eba: d112 bne.n 8009ee2 { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 8009ebc: 68fb ldr r3, [r7, #12] 8009ebe: 681b ldr r3, [r3, #0] 8009ec0: 4a56 ldr r2, [pc, #344] ; (800a01c ) 8009ec2: 639a str r2, [r3, #56] ; 0x38 hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT; 8009ec4: 68fb ldr r3, [r7, #12] 8009ec6: 6b5b ldr r3, [r3, #52] ; 0x34 8009ec8: f043 4200 orr.w r2, r3, #2147483648 ; 0x80000000 8009ecc: 68fb ldr r3, [r7, #12] 8009ece: 635a str r2, [r3, #52] ; 0x34 hsd->State = HAL_SD_STATE_READY; 8009ed0: 68fb ldr r3, [r7, #12] 8009ed2: 2201 movs r2, #1 8009ed4: f883 2030 strb.w r2, [r3, #48] ; 0x30 hsd->Context = SD_CONTEXT_NONE; 8009ed8: 68fb ldr r3, [r7, #12] 8009eda: 2200 movs r2, #0 8009edc: 62da str r2, [r3, #44] ; 0x2c return HAL_TIMEOUT; 8009ede: 2303 movs r3, #3 8009ee0: e097 b.n 800a012 while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) 8009ee2: 68fb ldr r3, [r7, #12] 8009ee4: 681b ldr r3, [r3, #0] 8009ee6: 6b5b ldr r3, [r3, #52] ; 0x34 8009ee8: f403 7395 and.w r3, r3, #298 ; 0x12a 8009eec: 2b00 cmp r3, #0 8009eee: d09f beq.n 8009e30 } } __SDMMC_CMDTRANS_DISABLE(hsd->Instance); 8009ef0: 68fb ldr r3, [r7, #12] 8009ef2: 681b ldr r3, [r3, #0] 8009ef4: 68da ldr r2, [r3, #12] 8009ef6: 68fb ldr r3, [r7, #12] 8009ef8: 681b ldr r3, [r3, #0] 8009efa: f022 0240 bic.w r2, r2, #64 ; 0x40 8009efe: 60da str r2, [r3, #12] /* Send stop transmission command in case of multiblock read */ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) 8009f00: 68fb ldr r3, [r7, #12] 8009f02: 681b ldr r3, [r3, #0] 8009f04: 6b5b ldr r3, [r3, #52] ; 0x34 8009f06: f403 7380 and.w r3, r3, #256 ; 0x100 8009f0a: 2b00 cmp r3, #0 8009f0c: d022 beq.n 8009f54 8009f0e: 683b ldr r3, [r7, #0] 8009f10: 2b01 cmp r3, #1 8009f12: d91f bls.n 8009f54 { if (hsd->SdCard.CardType != CARD_SECURED) 8009f14: 68fb ldr r3, [r7, #12] 8009f16: 6b9b ldr r3, [r3, #56] ; 0x38 8009f18: 2b03 cmp r3, #3 8009f1a: d01b beq.n 8009f54 { /* Send stop transmission command */ errorstate = SDMMC_CmdStopTransfer(hsd->Instance); 8009f1c: 68fb ldr r3, [r7, #12] 8009f1e: 681b ldr r3, [r3, #0] 8009f20: 4618 mov r0, r3 8009f22: f003 fd25 bl 800d970 8009f26: 6478 str r0, [r7, #68] ; 0x44 if (errorstate != HAL_SD_ERROR_NONE) 8009f28: 6c7b ldr r3, [r7, #68] ; 0x44 8009f2a: 2b00 cmp r3, #0 8009f2c: d012 beq.n 8009f54 { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 8009f2e: 68fb ldr r3, [r7, #12] 8009f30: 681b ldr r3, [r3, #0] 8009f32: 4a3a ldr r2, [pc, #232] ; (800a01c ) 8009f34: 639a str r2, [r3, #56] ; 0x38 hsd->ErrorCode |= errorstate; 8009f36: 68fb ldr r3, [r7, #12] 8009f38: 6b5a ldr r2, [r3, #52] ; 0x34 8009f3a: 6c7b ldr r3, [r7, #68] ; 0x44 8009f3c: 431a orrs r2, r3 8009f3e: 68fb ldr r3, [r7, #12] 8009f40: 635a str r2, [r3, #52] ; 0x34 hsd->State = HAL_SD_STATE_READY; 8009f42: 68fb ldr r3, [r7, #12] 8009f44: 2201 movs r2, #1 8009f46: f883 2030 strb.w r2, [r3, #48] ; 0x30 hsd->Context = SD_CONTEXT_NONE; 8009f4a: 68fb ldr r3, [r7, #12] 8009f4c: 2200 movs r2, #0 8009f4e: 62da str r2, [r3, #44] ; 0x2c return HAL_ERROR; 8009f50: 2301 movs r3, #1 8009f52: e05e b.n 800a012 } } } /* Get error state */ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) 8009f54: 68fb ldr r3, [r7, #12] 8009f56: 681b ldr r3, [r3, #0] 8009f58: 6b5b ldr r3, [r3, #52] ; 0x34 8009f5a: f003 0308 and.w r3, r3, #8 8009f5e: 2b00 cmp r3, #0 8009f60: d012 beq.n 8009f88 { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 8009f62: 68fb ldr r3, [r7, #12] 8009f64: 681b ldr r3, [r3, #0] 8009f66: 4a2d ldr r2, [pc, #180] ; (800a01c ) 8009f68: 639a str r2, [r3, #56] ; 0x38 hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; 8009f6a: 68fb ldr r3, [r7, #12] 8009f6c: 6b5b ldr r3, [r3, #52] ; 0x34 8009f6e: f043 0208 orr.w r2, r3, #8 8009f72: 68fb ldr r3, [r7, #12] 8009f74: 635a str r2, [r3, #52] ; 0x34 hsd->State = HAL_SD_STATE_READY; 8009f76: 68fb ldr r3, [r7, #12] 8009f78: 2201 movs r2, #1 8009f7a: f883 2030 strb.w r2, [r3, #48] ; 0x30 hsd->Context = SD_CONTEXT_NONE; 8009f7e: 68fb ldr r3, [r7, #12] 8009f80: 2200 movs r2, #0 8009f82: 62da str r2, [r3, #44] ; 0x2c return HAL_ERROR; 8009f84: 2301 movs r3, #1 8009f86: e044 b.n 800a012 } else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) 8009f88: 68fb ldr r3, [r7, #12] 8009f8a: 681b ldr r3, [r3, #0] 8009f8c: 6b5b ldr r3, [r3, #52] ; 0x34 8009f8e: f003 0302 and.w r3, r3, #2 8009f92: 2b00 cmp r3, #0 8009f94: d012 beq.n 8009fbc { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 8009f96: 68fb ldr r3, [r7, #12] 8009f98: 681b ldr r3, [r3, #0] 8009f9a: 4a20 ldr r2, [pc, #128] ; (800a01c ) 8009f9c: 639a str r2, [r3, #56] ; 0x38 hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; 8009f9e: 68fb ldr r3, [r7, #12] 8009fa0: 6b5b ldr r3, [r3, #52] ; 0x34 8009fa2: f043 0202 orr.w r2, r3, #2 8009fa6: 68fb ldr r3, [r7, #12] 8009fa8: 635a str r2, [r3, #52] ; 0x34 hsd->State = HAL_SD_STATE_READY; 8009faa: 68fb ldr r3, [r7, #12] 8009fac: 2201 movs r2, #1 8009fae: f883 2030 strb.w r2, [r3, #48] ; 0x30 hsd->Context = SD_CONTEXT_NONE; 8009fb2: 68fb ldr r3, [r7, #12] 8009fb4: 2200 movs r2, #0 8009fb6: 62da str r2, [r3, #44] ; 0x2c return HAL_ERROR; 8009fb8: 2301 movs r3, #1 8009fba: e02a b.n 800a012 } else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) 8009fbc: 68fb ldr r3, [r7, #12] 8009fbe: 681b ldr r3, [r3, #0] 8009fc0: 6b5b ldr r3, [r3, #52] ; 0x34 8009fc2: f003 0320 and.w r3, r3, #32 8009fc6: 2b00 cmp r3, #0 8009fc8: d012 beq.n 8009ff0 { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 8009fca: 68fb ldr r3, [r7, #12] 8009fcc: 681b ldr r3, [r3, #0] 8009fce: 4a13 ldr r2, [pc, #76] ; (800a01c ) 8009fd0: 639a str r2, [r3, #56] ; 0x38 hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN; 8009fd2: 68fb ldr r3, [r7, #12] 8009fd4: 6b5b ldr r3, [r3, #52] ; 0x34 8009fd6: f043 0220 orr.w r2, r3, #32 8009fda: 68fb ldr r3, [r7, #12] 8009fdc: 635a str r2, [r3, #52] ; 0x34 hsd->State = HAL_SD_STATE_READY; 8009fde: 68fb ldr r3, [r7, #12] 8009fe0: 2201 movs r2, #1 8009fe2: f883 2030 strb.w r2, [r3, #48] ; 0x30 hsd->Context = SD_CONTEXT_NONE; 8009fe6: 68fb ldr r3, [r7, #12] 8009fe8: 2200 movs r2, #0 8009fea: 62da str r2, [r3, #44] ; 0x2c return HAL_ERROR; 8009fec: 2301 movs r3, #1 8009fee: e010 b.n 800a012 { /* Nothing to do */ } /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); 8009ff0: 68fb ldr r3, [r7, #12] 8009ff2: 681b ldr r3, [r3, #0] 8009ff4: 4a0a ldr r2, [pc, #40] ; (800a020 ) 8009ff6: 639a str r2, [r3, #56] ; 0x38 hsd->State = HAL_SD_STATE_READY; 8009ff8: 68fb ldr r3, [r7, #12] 8009ffa: 2201 movs r2, #1 8009ffc: f883 2030 strb.w r2, [r3, #48] ; 0x30 return HAL_OK; 800a000: 2300 movs r3, #0 800a002: e006 b.n 800a012 } else { hsd->ErrorCode |= HAL_SD_ERROR_BUSY; 800a004: 68fb ldr r3, [r7, #12] 800a006: 6b5b ldr r3, [r3, #52] ; 0x34 800a008: f043 5200 orr.w r2, r3, #536870912 ; 0x20000000 800a00c: 68fb ldr r3, [r7, #12] 800a00e: 635a str r2, [r3, #52] ; 0x34 return HAL_ERROR; 800a010: 2301 movs r3, #1 } } 800a012: 4618 mov r0, r3 800a014: 3748 adds r7, #72 ; 0x48 800a016: 46bd mov sp, r7 800a018: bd80 pop {r7, pc} 800a01a: bf00 nop 800a01c: 1fe00fff .word 0x1fe00fff 800a020: 18000f3a .word 0x18000f3a 0800a024 : * @param Timeout: Specify timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) { 800a024: b580 push {r7, lr} 800a026: b092 sub sp, #72 ; 0x48 800a028: af00 add r7, sp, #0 800a02a: 60f8 str r0, [r7, #12] 800a02c: 60b9 str r1, [r7, #8] 800a02e: 607a str r2, [r7, #4] 800a030: 603b str r3, [r7, #0] SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); 800a032: f7f9 f8d9 bl 80031e8 800a036: 6338 str r0, [r7, #48] ; 0x30 uint32_t count; uint32_t data; uint32_t dataremaining; uint32_t add = BlockAdd; 800a038: 687b ldr r3, [r7, #4] 800a03a: 63bb str r3, [r7, #56] ; 0x38 uint8_t *tempbuff = pData; 800a03c: 68bb ldr r3, [r7, #8] 800a03e: 637b str r3, [r7, #52] ; 0x34 if (NULL == pData) 800a040: 68bb ldr r3, [r7, #8] 800a042: 2b00 cmp r3, #0 800a044: d107 bne.n 800a056 { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; 800a046: 68fb ldr r3, [r7, #12] 800a048: 6b5b ldr r3, [r3, #52] ; 0x34 800a04a: f043 6200 orr.w r2, r3, #134217728 ; 0x8000000 800a04e: 68fb ldr r3, [r7, #12] 800a050: 635a str r2, [r3, #52] ; 0x34 return HAL_ERROR; 800a052: 2301 movs r3, #1 800a054: e16b b.n 800a32e } if (hsd->State == HAL_SD_STATE_READY) 800a056: 68fb ldr r3, [r7, #12] 800a058: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 800a05c: b2db uxtb r3, r3 800a05e: 2b01 cmp r3, #1 800a060: f040 815e bne.w 800a320 { hsd->ErrorCode = HAL_SD_ERROR_NONE; 800a064: 68fb ldr r3, [r7, #12] 800a066: 2200 movs r2, #0 800a068: 635a str r2, [r3, #52] ; 0x34 if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) 800a06a: 6bba ldr r2, [r7, #56] ; 0x38 800a06c: 683b ldr r3, [r7, #0] 800a06e: 441a add r2, r3 800a070: 68fb ldr r3, [r7, #12] 800a072: 6d1b ldr r3, [r3, #80] ; 0x50 800a074: 429a cmp r2, r3 800a076: d907 bls.n 800a088 { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; 800a078: 68fb ldr r3, [r7, #12] 800a07a: 6b5b ldr r3, [r3, #52] ; 0x34 800a07c: f043 7200 orr.w r2, r3, #33554432 ; 0x2000000 800a080: 68fb ldr r3, [r7, #12] 800a082: 635a str r2, [r3, #52] ; 0x34 return HAL_ERROR; 800a084: 2301 movs r3, #1 800a086: e152 b.n 800a32e } hsd->State = HAL_SD_STATE_BUSY; 800a088: 68fb ldr r3, [r7, #12] 800a08a: 2203 movs r2, #3 800a08c: f883 2030 strb.w r2, [r3, #48] ; 0x30 /* Initialize data control register */ hsd->Instance->DCTRL = 0U; 800a090: 68fb ldr r3, [r7, #12] 800a092: 681b ldr r3, [r3, #0] 800a094: 2200 movs r2, #0 800a096: 62da str r2, [r3, #44] ; 0x2c if (hsd->SdCard.CardType != CARD_SDHC_SDXC) 800a098: 68fb ldr r3, [r7, #12] 800a09a: 6b9b ldr r3, [r3, #56] ; 0x38 800a09c: 2b01 cmp r3, #1 800a09e: d002 beq.n 800a0a6 { add *= 512U; 800a0a0: 6bbb ldr r3, [r7, #56] ; 0x38 800a0a2: 025b lsls r3, r3, #9 800a0a4: 63bb str r3, [r7, #56] ; 0x38 } /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; 800a0a6: f04f 33ff mov.w r3, #4294967295 800a0aa: 61bb str r3, [r7, #24] config.DataLength = NumberOfBlocks * BLOCKSIZE; 800a0ac: 683b ldr r3, [r7, #0] 800a0ae: 025b lsls r3, r3, #9 800a0b0: 61fb str r3, [r7, #28] config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; 800a0b2: 2390 movs r3, #144 ; 0x90 800a0b4: 623b str r3, [r7, #32] config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; 800a0b6: 2300 movs r3, #0 800a0b8: 627b str r3, [r7, #36] ; 0x24 config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; 800a0ba: 2300 movs r3, #0 800a0bc: 62bb str r3, [r7, #40] ; 0x28 config.DPSM = SDMMC_DPSM_DISABLE; 800a0be: 2300 movs r3, #0 800a0c0: 62fb str r3, [r7, #44] ; 0x2c (void)SDMMC_ConfigData(hsd->Instance, &config); 800a0c2: 68fb ldr r3, [r7, #12] 800a0c4: 681b ldr r3, [r3, #0] 800a0c6: f107 0218 add.w r2, r7, #24 800a0ca: 4611 mov r1, r2 800a0cc: 4618 mov r0, r3 800a0ce: f003 fb73 bl 800d7b8 __SDMMC_CMDTRANS_ENABLE(hsd->Instance); 800a0d2: 68fb ldr r3, [r7, #12] 800a0d4: 681b ldr r3, [r3, #0] 800a0d6: 68da ldr r2, [r3, #12] 800a0d8: 68fb ldr r3, [r7, #12] 800a0da: 681b ldr r3, [r3, #0] 800a0dc: f042 0240 orr.w r2, r2, #64 ; 0x40 800a0e0: 60da str r2, [r3, #12] /* Write Blocks in Polling mode */ if (NumberOfBlocks > 1U) 800a0e2: 683b ldr r3, [r7, #0] 800a0e4: 2b01 cmp r3, #1 800a0e6: d90a bls.n 800a0fe { hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK; 800a0e8: 68fb ldr r3, [r7, #12] 800a0ea: 2220 movs r2, #32 800a0ec: 62da str r2, [r3, #44] ; 0x2c /* Write Multi Block command */ errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); 800a0ee: 68fb ldr r3, [r7, #12] 800a0f0: 681b ldr r3, [r3, #0] 800a0f2: 6bb9 ldr r1, [r7, #56] ; 0x38 800a0f4: 4618 mov r0, r3 800a0f6: f003 fc17 bl 800d928 800a0fa: 6478 str r0, [r7, #68] ; 0x44 800a0fc: e009 b.n 800a112 } else { hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK; 800a0fe: 68fb ldr r3, [r7, #12] 800a100: 2210 movs r2, #16 800a102: 62da str r2, [r3, #44] ; 0x2c /* Write Single Block command */ errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); 800a104: 68fb ldr r3, [r7, #12] 800a106: 681b ldr r3, [r3, #0] 800a108: 6bb9 ldr r1, [r7, #56] ; 0x38 800a10a: 4618 mov r0, r3 800a10c: f003 fbe9 bl 800d8e2 800a110: 6478 str r0, [r7, #68] ; 0x44 } if (errorstate != HAL_SD_ERROR_NONE) 800a112: 6c7b ldr r3, [r7, #68] ; 0x44 800a114: 2b00 cmp r3, #0 800a116: d012 beq.n 800a13e { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 800a118: 68fb ldr r3, [r7, #12] 800a11a: 681b ldr r3, [r3, #0] 800a11c: 4a86 ldr r2, [pc, #536] ; (800a338 ) 800a11e: 639a str r2, [r3, #56] ; 0x38 hsd->ErrorCode |= errorstate; 800a120: 68fb ldr r3, [r7, #12] 800a122: 6b5a ldr r2, [r3, #52] ; 0x34 800a124: 6c7b ldr r3, [r7, #68] ; 0x44 800a126: 431a orrs r2, r3 800a128: 68fb ldr r3, [r7, #12] 800a12a: 635a str r2, [r3, #52] ; 0x34 hsd->State = HAL_SD_STATE_READY; 800a12c: 68fb ldr r3, [r7, #12] 800a12e: 2201 movs r2, #1 800a130: f883 2030 strb.w r2, [r3, #48] ; 0x30 hsd->Context = SD_CONTEXT_NONE; 800a134: 68fb ldr r3, [r7, #12] 800a136: 2200 movs r2, #0 800a138: 62da str r2, [r3, #44] ; 0x2c return HAL_ERROR; 800a13a: 2301 movs r3, #1 800a13c: e0f7 b.n 800a32e } /* Write block(s) in polling mode */ dataremaining = config.DataLength; 800a13e: 69fb ldr r3, [r7, #28] 800a140: 63fb str r3, [r7, #60] ; 0x3c while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | 800a142: e05c b.n 800a1fe SDMMC_FLAG_DATAEND)) { if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U)) 800a144: 68fb ldr r3, [r7, #12] 800a146: 681b ldr r3, [r3, #0] 800a148: 6b5b ldr r3, [r3, #52] ; 0x34 800a14a: f403 4380 and.w r3, r3, #16384 ; 0x4000 800a14e: 2b00 cmp r3, #0 800a150: d037 beq.n 800a1c2 800a152: 6bfb ldr r3, [r7, #60] ; 0x3c 800a154: 2b1f cmp r3, #31 800a156: d934 bls.n 800a1c2 { /* Write data to SDMMC Tx FIFO */ for (count = 0U; count < 8U; count++) 800a158: 2300 movs r3, #0 800a15a: 643b str r3, [r7, #64] ; 0x40 800a15c: e02b b.n 800a1b6 { data = (uint32_t)(*tempbuff); 800a15e: 6b7b ldr r3, [r7, #52] ; 0x34 800a160: 781b ldrb r3, [r3, #0] 800a162: 617b str r3, [r7, #20] tempbuff++; 800a164: 6b7b ldr r3, [r7, #52] ; 0x34 800a166: 3301 adds r3, #1 800a168: 637b str r3, [r7, #52] ; 0x34 data |= ((uint32_t)(*tempbuff) << 8U); 800a16a: 6b7b ldr r3, [r7, #52] ; 0x34 800a16c: 781b ldrb r3, [r3, #0] 800a16e: 021a lsls r2, r3, #8 800a170: 697b ldr r3, [r7, #20] 800a172: 4313 orrs r3, r2 800a174: 617b str r3, [r7, #20] tempbuff++; 800a176: 6b7b ldr r3, [r7, #52] ; 0x34 800a178: 3301 adds r3, #1 800a17a: 637b str r3, [r7, #52] ; 0x34 data |= ((uint32_t)(*tempbuff) << 16U); 800a17c: 6b7b ldr r3, [r7, #52] ; 0x34 800a17e: 781b ldrb r3, [r3, #0] 800a180: 041a lsls r2, r3, #16 800a182: 697b ldr r3, [r7, #20] 800a184: 4313 orrs r3, r2 800a186: 617b str r3, [r7, #20] tempbuff++; 800a188: 6b7b ldr r3, [r7, #52] ; 0x34 800a18a: 3301 adds r3, #1 800a18c: 637b str r3, [r7, #52] ; 0x34 data |= ((uint32_t)(*tempbuff) << 24U); 800a18e: 6b7b ldr r3, [r7, #52] ; 0x34 800a190: 781b ldrb r3, [r3, #0] 800a192: 061a lsls r2, r3, #24 800a194: 697b ldr r3, [r7, #20] 800a196: 4313 orrs r3, r2 800a198: 617b str r3, [r7, #20] tempbuff++; 800a19a: 6b7b ldr r3, [r7, #52] ; 0x34 800a19c: 3301 adds r3, #1 800a19e: 637b str r3, [r7, #52] ; 0x34 (void)SDMMC_WriteFIFO(hsd->Instance, &data); 800a1a0: 68fb ldr r3, [r7, #12] 800a1a2: 681b ldr r3, [r3, #0] 800a1a4: f107 0214 add.w r2, r7, #20 800a1a8: 4611 mov r1, r2 800a1aa: 4618 mov r0, r3 800a1ac: f003 fa89 bl 800d6c2 for (count = 0U; count < 8U; count++) 800a1b0: 6c3b ldr r3, [r7, #64] ; 0x40 800a1b2: 3301 adds r3, #1 800a1b4: 643b str r3, [r7, #64] ; 0x40 800a1b6: 6c3b ldr r3, [r7, #64] ; 0x40 800a1b8: 2b07 cmp r3, #7 800a1ba: d9d0 bls.n 800a15e } dataremaining -= 32U; 800a1bc: 6bfb ldr r3, [r7, #60] ; 0x3c 800a1be: 3b20 subs r3, #32 800a1c0: 63fb str r3, [r7, #60] ; 0x3c } if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) 800a1c2: f7f9 f811 bl 80031e8 800a1c6: 4602 mov r2, r0 800a1c8: 6b3b ldr r3, [r7, #48] ; 0x30 800a1ca: 1ad3 subs r3, r2, r3 800a1cc: 6d3a ldr r2, [r7, #80] ; 0x50 800a1ce: 429a cmp r2, r3 800a1d0: d902 bls.n 800a1d8 800a1d2: 6d3b ldr r3, [r7, #80] ; 0x50 800a1d4: 2b00 cmp r3, #0 800a1d6: d112 bne.n 800a1fe { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 800a1d8: 68fb ldr r3, [r7, #12] 800a1da: 681b ldr r3, [r3, #0] 800a1dc: 4a56 ldr r2, [pc, #344] ; (800a338 ) 800a1de: 639a str r2, [r3, #56] ; 0x38 hsd->ErrorCode |= errorstate; 800a1e0: 68fb ldr r3, [r7, #12] 800a1e2: 6b5a ldr r2, [r3, #52] ; 0x34 800a1e4: 6c7b ldr r3, [r7, #68] ; 0x44 800a1e6: 431a orrs r2, r3 800a1e8: 68fb ldr r3, [r7, #12] 800a1ea: 635a str r2, [r3, #52] ; 0x34 hsd->State = HAL_SD_STATE_READY; 800a1ec: 68fb ldr r3, [r7, #12] 800a1ee: 2201 movs r2, #1 800a1f0: f883 2030 strb.w r2, [r3, #48] ; 0x30 hsd->Context = SD_CONTEXT_NONE; 800a1f4: 68fb ldr r3, [r7, #12] 800a1f6: 2200 movs r2, #0 800a1f8: 62da str r2, [r3, #44] ; 0x2c return HAL_TIMEOUT; 800a1fa: 2303 movs r3, #3 800a1fc: e097 b.n 800a32e while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | 800a1fe: 68fb ldr r3, [r7, #12] 800a200: 681b ldr r3, [r3, #0] 800a202: 6b5b ldr r3, [r3, #52] ; 0x34 800a204: f403 738d and.w r3, r3, #282 ; 0x11a 800a208: 2b00 cmp r3, #0 800a20a: d09b beq.n 800a144 } } __SDMMC_CMDTRANS_DISABLE(hsd->Instance); 800a20c: 68fb ldr r3, [r7, #12] 800a20e: 681b ldr r3, [r3, #0] 800a210: 68da ldr r2, [r3, #12] 800a212: 68fb ldr r3, [r7, #12] 800a214: 681b ldr r3, [r3, #0] 800a216: f022 0240 bic.w r2, r2, #64 ; 0x40 800a21a: 60da str r2, [r3, #12] /* Send stop transmission command in case of multiblock write */ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) 800a21c: 68fb ldr r3, [r7, #12] 800a21e: 681b ldr r3, [r3, #0] 800a220: 6b5b ldr r3, [r3, #52] ; 0x34 800a222: f403 7380 and.w r3, r3, #256 ; 0x100 800a226: 2b00 cmp r3, #0 800a228: d022 beq.n 800a270 800a22a: 683b ldr r3, [r7, #0] 800a22c: 2b01 cmp r3, #1 800a22e: d91f bls.n 800a270 { if (hsd->SdCard.CardType != CARD_SECURED) 800a230: 68fb ldr r3, [r7, #12] 800a232: 6b9b ldr r3, [r3, #56] ; 0x38 800a234: 2b03 cmp r3, #3 800a236: d01b beq.n 800a270 { /* Send stop transmission command */ errorstate = SDMMC_CmdStopTransfer(hsd->Instance); 800a238: 68fb ldr r3, [r7, #12] 800a23a: 681b ldr r3, [r3, #0] 800a23c: 4618 mov r0, r3 800a23e: f003 fb97 bl 800d970 800a242: 6478 str r0, [r7, #68] ; 0x44 if (errorstate != HAL_SD_ERROR_NONE) 800a244: 6c7b ldr r3, [r7, #68] ; 0x44 800a246: 2b00 cmp r3, #0 800a248: d012 beq.n 800a270 { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 800a24a: 68fb ldr r3, [r7, #12] 800a24c: 681b ldr r3, [r3, #0] 800a24e: 4a3a ldr r2, [pc, #232] ; (800a338 ) 800a250: 639a str r2, [r3, #56] ; 0x38 hsd->ErrorCode |= errorstate; 800a252: 68fb ldr r3, [r7, #12] 800a254: 6b5a ldr r2, [r3, #52] ; 0x34 800a256: 6c7b ldr r3, [r7, #68] ; 0x44 800a258: 431a orrs r2, r3 800a25a: 68fb ldr r3, [r7, #12] 800a25c: 635a str r2, [r3, #52] ; 0x34 hsd->State = HAL_SD_STATE_READY; 800a25e: 68fb ldr r3, [r7, #12] 800a260: 2201 movs r2, #1 800a262: f883 2030 strb.w r2, [r3, #48] ; 0x30 hsd->Context = SD_CONTEXT_NONE; 800a266: 68fb ldr r3, [r7, #12] 800a268: 2200 movs r2, #0 800a26a: 62da str r2, [r3, #44] ; 0x2c return HAL_ERROR; 800a26c: 2301 movs r3, #1 800a26e: e05e b.n 800a32e } } } /* Get error state */ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) 800a270: 68fb ldr r3, [r7, #12] 800a272: 681b ldr r3, [r3, #0] 800a274: 6b5b ldr r3, [r3, #52] ; 0x34 800a276: f003 0308 and.w r3, r3, #8 800a27a: 2b00 cmp r3, #0 800a27c: d012 beq.n 800a2a4 { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 800a27e: 68fb ldr r3, [r7, #12] 800a280: 681b ldr r3, [r3, #0] 800a282: 4a2d ldr r2, [pc, #180] ; (800a338 ) 800a284: 639a str r2, [r3, #56] ; 0x38 hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; 800a286: 68fb ldr r3, [r7, #12] 800a288: 6b5b ldr r3, [r3, #52] ; 0x34 800a28a: f043 0208 orr.w r2, r3, #8 800a28e: 68fb ldr r3, [r7, #12] 800a290: 635a str r2, [r3, #52] ; 0x34 hsd->State = HAL_SD_STATE_READY; 800a292: 68fb ldr r3, [r7, #12] 800a294: 2201 movs r2, #1 800a296: f883 2030 strb.w r2, [r3, #48] ; 0x30 hsd->Context = SD_CONTEXT_NONE; 800a29a: 68fb ldr r3, [r7, #12] 800a29c: 2200 movs r2, #0 800a29e: 62da str r2, [r3, #44] ; 0x2c return HAL_ERROR; 800a2a0: 2301 movs r3, #1 800a2a2: e044 b.n 800a32e } else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) 800a2a4: 68fb ldr r3, [r7, #12] 800a2a6: 681b ldr r3, [r3, #0] 800a2a8: 6b5b ldr r3, [r3, #52] ; 0x34 800a2aa: f003 0302 and.w r3, r3, #2 800a2ae: 2b00 cmp r3, #0 800a2b0: d012 beq.n 800a2d8 { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 800a2b2: 68fb ldr r3, [r7, #12] 800a2b4: 681b ldr r3, [r3, #0] 800a2b6: 4a20 ldr r2, [pc, #128] ; (800a338 ) 800a2b8: 639a str r2, [r3, #56] ; 0x38 hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; 800a2ba: 68fb ldr r3, [r7, #12] 800a2bc: 6b5b ldr r3, [r3, #52] ; 0x34 800a2be: f043 0202 orr.w r2, r3, #2 800a2c2: 68fb ldr r3, [r7, #12] 800a2c4: 635a str r2, [r3, #52] ; 0x34 hsd->State = HAL_SD_STATE_READY; 800a2c6: 68fb ldr r3, [r7, #12] 800a2c8: 2201 movs r2, #1 800a2ca: f883 2030 strb.w r2, [r3, #48] ; 0x30 hsd->Context = SD_CONTEXT_NONE; 800a2ce: 68fb ldr r3, [r7, #12] 800a2d0: 2200 movs r2, #0 800a2d2: 62da str r2, [r3, #44] ; 0x2c return HAL_ERROR; 800a2d4: 2301 movs r3, #1 800a2d6: e02a b.n 800a32e } else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR)) 800a2d8: 68fb ldr r3, [r7, #12] 800a2da: 681b ldr r3, [r3, #0] 800a2dc: 6b5b ldr r3, [r3, #52] ; 0x34 800a2de: f003 0310 and.w r3, r3, #16 800a2e2: 2b00 cmp r3, #0 800a2e4: d012 beq.n 800a30c { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 800a2e6: 68fb ldr r3, [r7, #12] 800a2e8: 681b ldr r3, [r3, #0] 800a2ea: 4a13 ldr r2, [pc, #76] ; (800a338 ) 800a2ec: 639a str r2, [r3, #56] ; 0x38 hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; 800a2ee: 68fb ldr r3, [r7, #12] 800a2f0: 6b5b ldr r3, [r3, #52] ; 0x34 800a2f2: f043 0210 orr.w r2, r3, #16 800a2f6: 68fb ldr r3, [r7, #12] 800a2f8: 635a str r2, [r3, #52] ; 0x34 hsd->State = HAL_SD_STATE_READY; 800a2fa: 68fb ldr r3, [r7, #12] 800a2fc: 2201 movs r2, #1 800a2fe: f883 2030 strb.w r2, [r3, #48] ; 0x30 hsd->Context = SD_CONTEXT_NONE; 800a302: 68fb ldr r3, [r7, #12] 800a304: 2200 movs r2, #0 800a306: 62da str r2, [r3, #44] ; 0x2c return HAL_ERROR; 800a308: 2301 movs r3, #1 800a30a: e010 b.n 800a32e { /* Nothing to do */ } /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); 800a30c: 68fb ldr r3, [r7, #12] 800a30e: 681b ldr r3, [r3, #0] 800a310: 4a0a ldr r2, [pc, #40] ; (800a33c ) 800a312: 639a str r2, [r3, #56] ; 0x38 hsd->State = HAL_SD_STATE_READY; 800a314: 68fb ldr r3, [r7, #12] 800a316: 2201 movs r2, #1 800a318: f883 2030 strb.w r2, [r3, #48] ; 0x30 return HAL_OK; 800a31c: 2300 movs r3, #0 800a31e: e006 b.n 800a32e } else { hsd->ErrorCode |= HAL_SD_ERROR_BUSY; 800a320: 68fb ldr r3, [r7, #12] 800a322: 6b5b ldr r3, [r3, #52] ; 0x34 800a324: f043 5200 orr.w r2, r3, #536870912 ; 0x20000000 800a328: 68fb ldr r3, [r7, #12] 800a32a: 635a str r2, [r3, #52] ; 0x34 return HAL_ERROR; 800a32c: 2301 movs r3, #1 } } 800a32e: 4618 mov r0, r3 800a330: 3748 adds r7, #72 ; 0x48 800a332: 46bd mov sp, r7 800a334: bd80 pop {r7, pc} 800a336: bf00 nop 800a338: 1fe00fff .word 0x1fe00fff 800a33c: 18000f3a .word 0x18000f3a 0800a340 : * @param pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that * contains all CSD register parameters * @retval HAL status */ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD) { 800a340: b480 push {r7} 800a342: b083 sub sp, #12 800a344: af00 add r7, sp, #0 800a346: 6078 str r0, [r7, #4] 800a348: 6039 str r1, [r7, #0] pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U); 800a34a: 687b ldr r3, [r7, #4] 800a34c: 6ddb ldr r3, [r3, #92] ; 0x5c 800a34e: 0f9b lsrs r3, r3, #30 800a350: b2da uxtb r2, r3 800a352: 683b ldr r3, [r7, #0] 800a354: 701a strb r2, [r3, #0] pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U); 800a356: 687b ldr r3, [r7, #4] 800a358: 6ddb ldr r3, [r3, #92] ; 0x5c 800a35a: 0e9b lsrs r3, r3, #26 800a35c: b2db uxtb r3, r3 800a35e: f003 030f and.w r3, r3, #15 800a362: b2da uxtb r2, r3 800a364: 683b ldr r3, [r7, #0] 800a366: 705a strb r2, [r3, #1] pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U); 800a368: 687b ldr r3, [r7, #4] 800a36a: 6ddb ldr r3, [r3, #92] ; 0x5c 800a36c: 0e1b lsrs r3, r3, #24 800a36e: b2db uxtb r3, r3 800a370: f003 0303 and.w r3, r3, #3 800a374: b2da uxtb r2, r3 800a376: 683b ldr r3, [r7, #0] 800a378: 709a strb r2, [r3, #2] pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U); 800a37a: 687b ldr r3, [r7, #4] 800a37c: 6ddb ldr r3, [r3, #92] ; 0x5c 800a37e: 0c1b lsrs r3, r3, #16 800a380: b2da uxtb r2, r3 800a382: 683b ldr r3, [r7, #0] 800a384: 70da strb r2, [r3, #3] pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U); 800a386: 687b ldr r3, [r7, #4] 800a388: 6ddb ldr r3, [r3, #92] ; 0x5c 800a38a: 0a1b lsrs r3, r3, #8 800a38c: b2da uxtb r2, r3 800a38e: 683b ldr r3, [r7, #0] 800a390: 711a strb r2, [r3, #4] pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU); 800a392: 687b ldr r3, [r7, #4] 800a394: 6ddb ldr r3, [r3, #92] ; 0x5c 800a396: b2da uxtb r2, r3 800a398: 683b ldr r3, [r7, #0] 800a39a: 715a strb r2, [r3, #5] pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U); 800a39c: 687b ldr r3, [r7, #4] 800a39e: 6e1b ldr r3, [r3, #96] ; 0x60 800a3a0: 0d1b lsrs r3, r3, #20 800a3a2: b29a uxth r2, r3 800a3a4: 683b ldr r3, [r7, #0] 800a3a6: 80da strh r2, [r3, #6] pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U); 800a3a8: 687b ldr r3, [r7, #4] 800a3aa: 6e1b ldr r3, [r3, #96] ; 0x60 800a3ac: 0c1b lsrs r3, r3, #16 800a3ae: b2db uxtb r3, r3 800a3b0: f003 030f and.w r3, r3, #15 800a3b4: b2da uxtb r2, r3 800a3b6: 683b ldr r3, [r7, #0] 800a3b8: 721a strb r2, [r3, #8] pCSD->PartBlockRead = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U); 800a3ba: 687b ldr r3, [r7, #4] 800a3bc: 6e1b ldr r3, [r3, #96] ; 0x60 800a3be: 0bdb lsrs r3, r3, #15 800a3c0: b2db uxtb r3, r3 800a3c2: f003 0301 and.w r3, r3, #1 800a3c6: b2da uxtb r2, r3 800a3c8: 683b ldr r3, [r7, #0] 800a3ca: 725a strb r2, [r3, #9] pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U); 800a3cc: 687b ldr r3, [r7, #4] 800a3ce: 6e1b ldr r3, [r3, #96] ; 0x60 800a3d0: 0b9b lsrs r3, r3, #14 800a3d2: b2db uxtb r3, r3 800a3d4: f003 0301 and.w r3, r3, #1 800a3d8: b2da uxtb r2, r3 800a3da: 683b ldr r3, [r7, #0] 800a3dc: 729a strb r2, [r3, #10] pCSD->RdBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00002000U) >> 13U); 800a3de: 687b ldr r3, [r7, #4] 800a3e0: 6e1b ldr r3, [r3, #96] ; 0x60 800a3e2: 0b5b lsrs r3, r3, #13 800a3e4: b2db uxtb r3, r3 800a3e6: f003 0301 and.w r3, r3, #1 800a3ea: b2da uxtb r2, r3 800a3ec: 683b ldr r3, [r7, #0] 800a3ee: 72da strb r2, [r3, #11] pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U); 800a3f0: 687b ldr r3, [r7, #4] 800a3f2: 6e1b ldr r3, [r3, #96] ; 0x60 800a3f4: 0b1b lsrs r3, r3, #12 800a3f6: b2db uxtb r3, r3 800a3f8: f003 0301 and.w r3, r3, #1 800a3fc: b2da uxtb r2, r3 800a3fe: 683b ldr r3, [r7, #0] 800a400: 731a strb r2, [r3, #12] pCSD->Reserved2 = 0U; /*!< Reserved */ 800a402: 683b ldr r3, [r7, #0] 800a404: 2200 movs r2, #0 800a406: 735a strb r2, [r3, #13] if (hsd->SdCard.CardType == CARD_SDSC) 800a408: 687b ldr r3, [r7, #4] 800a40a: 6b9b ldr r3, [r3, #56] ; 0x38 800a40c: 2b00 cmp r3, #0 800a40e: d163 bne.n 800a4d8 { pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U)); 800a410: 687b ldr r3, [r7, #4] 800a412: 6e1b ldr r3, [r3, #96] ; 0x60 800a414: 009a lsls r2, r3, #2 800a416: f640 73fc movw r3, #4092 ; 0xffc 800a41a: 4013 ands r3, r2 800a41c: 687a ldr r2, [r7, #4] 800a41e: 6e52 ldr r2, [r2, #100] ; 0x64 800a420: 0f92 lsrs r2, r2, #30 800a422: 431a orrs r2, r3 800a424: 683b ldr r3, [r7, #0] 800a426: 611a str r2, [r3, #16] pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U); 800a428: 687b ldr r3, [r7, #4] 800a42a: 6e5b ldr r3, [r3, #100] ; 0x64 800a42c: 0edb lsrs r3, r3, #27 800a42e: b2db uxtb r3, r3 800a430: f003 0307 and.w r3, r3, #7 800a434: b2da uxtb r2, r3 800a436: 683b ldr r3, [r7, #0] 800a438: 751a strb r2, [r3, #20] pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U); 800a43a: 687b ldr r3, [r7, #4] 800a43c: 6e5b ldr r3, [r3, #100] ; 0x64 800a43e: 0e1b lsrs r3, r3, #24 800a440: b2db uxtb r3, r3 800a442: f003 0307 and.w r3, r3, #7 800a446: b2da uxtb r2, r3 800a448: 683b ldr r3, [r7, #0] 800a44a: 755a strb r2, [r3, #21] pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U); 800a44c: 687b ldr r3, [r7, #4] 800a44e: 6e5b ldr r3, [r3, #100] ; 0x64 800a450: 0d5b lsrs r3, r3, #21 800a452: b2db uxtb r3, r3 800a454: f003 0307 and.w r3, r3, #7 800a458: b2da uxtb r2, r3 800a45a: 683b ldr r3, [r7, #0] 800a45c: 759a strb r2, [r3, #22] pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U); 800a45e: 687b ldr r3, [r7, #4] 800a460: 6e5b ldr r3, [r3, #100] ; 0x64 800a462: 0c9b lsrs r3, r3, #18 800a464: b2db uxtb r3, r3 800a466: f003 0307 and.w r3, r3, #7 800a46a: b2da uxtb r2, r3 800a46c: 683b ldr r3, [r7, #0] 800a46e: 75da strb r2, [r3, #23] pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U); 800a470: 687b ldr r3, [r7, #4] 800a472: 6e5b ldr r3, [r3, #100] ; 0x64 800a474: 0bdb lsrs r3, r3, #15 800a476: b2db uxtb r3, r3 800a478: f003 0307 and.w r3, r3, #7 800a47c: b2da uxtb r2, r3 800a47e: 683b ldr r3, [r7, #0] 800a480: 761a strb r2, [r3, #24] hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1U) ; 800a482: 683b ldr r3, [r7, #0] 800a484: 691b ldr r3, [r3, #16] 800a486: 1c5a adds r2, r3, #1 800a488: 687b ldr r3, [r7, #4] 800a48a: 649a str r2, [r3, #72] ; 0x48 hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); 800a48c: 683b ldr r3, [r7, #0] 800a48e: 7e1b ldrb r3, [r3, #24] 800a490: b2db uxtb r3, r3 800a492: f003 0307 and.w r3, r3, #7 800a496: 3302 adds r3, #2 800a498: 2201 movs r2, #1 800a49a: fa02 f303 lsl.w r3, r2, r3 800a49e: 687a ldr r2, [r7, #4] 800a4a0: 6c92 ldr r2, [r2, #72] ; 0x48 800a4a2: fb02 f203 mul.w r2, r2, r3 800a4a6: 687b ldr r3, [r7, #4] 800a4a8: 649a str r2, [r3, #72] ; 0x48 hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); 800a4aa: 683b ldr r3, [r7, #0] 800a4ac: 7a1b ldrb r3, [r3, #8] 800a4ae: b2db uxtb r3, r3 800a4b0: f003 030f and.w r3, r3, #15 800a4b4: 2201 movs r2, #1 800a4b6: 409a lsls r2, r3 800a4b8: 687b ldr r3, [r7, #4] 800a4ba: 64da str r2, [r3, #76] ; 0x4c hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U); 800a4bc: 687b ldr r3, [r7, #4] 800a4be: 6c9b ldr r3, [r3, #72] ; 0x48 800a4c0: 687a ldr r2, [r7, #4] 800a4c2: 6cd2 ldr r2, [r2, #76] ; 0x4c 800a4c4: 0a52 lsrs r2, r2, #9 800a4c6: fb02 f203 mul.w r2, r2, r3 800a4ca: 687b ldr r3, [r7, #4] 800a4cc: 651a str r2, [r3, #80] ; 0x50 hsd->SdCard.LogBlockSize = 512U; 800a4ce: 687b ldr r3, [r7, #4] 800a4d0: f44f 7200 mov.w r2, #512 ; 0x200 800a4d4: 655a str r2, [r3, #84] ; 0x54 800a4d6: e031 b.n 800a53c } else if (hsd->SdCard.CardType == CARD_SDHC_SDXC) 800a4d8: 687b ldr r3, [r7, #4] 800a4da: 6b9b ldr r3, [r3, #56] ; 0x38 800a4dc: 2b01 cmp r3, #1 800a4de: d11d bne.n 800a51c { /* Byte 7 */ pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U)); 800a4e0: 687b ldr r3, [r7, #4] 800a4e2: 6e1b ldr r3, [r3, #96] ; 0x60 800a4e4: 041b lsls r3, r3, #16 800a4e6: f403 127c and.w r2, r3, #4128768 ; 0x3f0000 800a4ea: 687b ldr r3, [r7, #4] 800a4ec: 6e5b ldr r3, [r3, #100] ; 0x64 800a4ee: 0c1b lsrs r3, r3, #16 800a4f0: 431a orrs r2, r3 800a4f2: 683b ldr r3, [r7, #0] 800a4f4: 611a str r2, [r3, #16] hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U); 800a4f6: 683b ldr r3, [r7, #0] 800a4f8: 691b ldr r3, [r3, #16] 800a4fa: 3301 adds r3, #1 800a4fc: 029a lsls r2, r3, #10 800a4fe: 687b ldr r3, [r7, #4] 800a500: 649a str r2, [r3, #72] ; 0x48 hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr; 800a502: 687b ldr r3, [r7, #4] 800a504: 6c9a ldr r2, [r3, #72] ; 0x48 800a506: 687b ldr r3, [r7, #4] 800a508: 651a str r2, [r3, #80] ; 0x50 hsd->SdCard.BlockSize = 512U; 800a50a: 687b ldr r3, [r7, #4] 800a50c: f44f 7200 mov.w r2, #512 ; 0x200 800a510: 64da str r2, [r3, #76] ; 0x4c hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize; 800a512: 687b ldr r3, [r7, #4] 800a514: 6cda ldr r2, [r3, #76] ; 0x4c 800a516: 687b ldr r3, [r7, #4] 800a518: 655a str r2, [r3, #84] ; 0x54 800a51a: e00f b.n 800a53c } else { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 800a51c: 687b ldr r3, [r7, #4] 800a51e: 681b ldr r3, [r3, #0] 800a520: 4a58 ldr r2, [pc, #352] ; (800a684 ) 800a522: 639a str r2, [r3, #56] ; 0x38 hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; 800a524: 687b ldr r3, [r7, #4] 800a526: 6b5b ldr r3, [r3, #52] ; 0x34 800a528: f043 5280 orr.w r2, r3, #268435456 ; 0x10000000 800a52c: 687b ldr r3, [r7, #4] 800a52e: 635a str r2, [r3, #52] ; 0x34 hsd->State = HAL_SD_STATE_READY; 800a530: 687b ldr r3, [r7, #4] 800a532: 2201 movs r2, #1 800a534: f883 2030 strb.w r2, [r3, #48] ; 0x30 return HAL_ERROR; 800a538: 2301 movs r3, #1 800a53a: e09d b.n 800a678 } pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U); 800a53c: 687b ldr r3, [r7, #4] 800a53e: 6e5b ldr r3, [r3, #100] ; 0x64 800a540: 0b9b lsrs r3, r3, #14 800a542: b2db uxtb r3, r3 800a544: f003 0301 and.w r3, r3, #1 800a548: b2da uxtb r2, r3 800a54a: 683b ldr r3, [r7, #0] 800a54c: 765a strb r2, [r3, #25] pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U); 800a54e: 687b ldr r3, [r7, #4] 800a550: 6e5b ldr r3, [r3, #100] ; 0x64 800a552: 09db lsrs r3, r3, #7 800a554: b2db uxtb r3, r3 800a556: f003 037f and.w r3, r3, #127 ; 0x7f 800a55a: b2da uxtb r2, r3 800a55c: 683b ldr r3, [r7, #0] 800a55e: 769a strb r2, [r3, #26] pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU); 800a560: 687b ldr r3, [r7, #4] 800a562: 6e5b ldr r3, [r3, #100] ; 0x64 800a564: b2db uxtb r3, r3 800a566: f003 037f and.w r3, r3, #127 ; 0x7f 800a56a: b2da uxtb r2, r3 800a56c: 683b ldr r3, [r7, #0] 800a56e: 76da strb r2, [r3, #27] pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U); 800a570: 687b ldr r3, [r7, #4] 800a572: 6e9b ldr r3, [r3, #104] ; 0x68 800a574: 0fdb lsrs r3, r3, #31 800a576: b2da uxtb r2, r3 800a578: 683b ldr r3, [r7, #0] 800a57a: 771a strb r2, [r3, #28] pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U); 800a57c: 687b ldr r3, [r7, #4] 800a57e: 6e9b ldr r3, [r3, #104] ; 0x68 800a580: 0f5b lsrs r3, r3, #29 800a582: b2db uxtb r3, r3 800a584: f003 0303 and.w r3, r3, #3 800a588: b2da uxtb r2, r3 800a58a: 683b ldr r3, [r7, #0] 800a58c: 775a strb r2, [r3, #29] pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U); 800a58e: 687b ldr r3, [r7, #4] 800a590: 6e9b ldr r3, [r3, #104] ; 0x68 800a592: 0e9b lsrs r3, r3, #26 800a594: b2db uxtb r3, r3 800a596: f003 0307 and.w r3, r3, #7 800a59a: b2da uxtb r2, r3 800a59c: 683b ldr r3, [r7, #0] 800a59e: 779a strb r2, [r3, #30] pCSD->MaxWrBlockLen = (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U); 800a5a0: 687b ldr r3, [r7, #4] 800a5a2: 6e9b ldr r3, [r3, #104] ; 0x68 800a5a4: 0d9b lsrs r3, r3, #22 800a5a6: b2db uxtb r3, r3 800a5a8: f003 030f and.w r3, r3, #15 800a5ac: b2da uxtb r2, r3 800a5ae: 683b ldr r3, [r7, #0] 800a5b0: 77da strb r2, [r3, #31] pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U); 800a5b2: 687b ldr r3, [r7, #4] 800a5b4: 6e9b ldr r3, [r3, #104] ; 0x68 800a5b6: 0d5b lsrs r3, r3, #21 800a5b8: b2db uxtb r3, r3 800a5ba: f003 0301 and.w r3, r3, #1 800a5be: b2da uxtb r2, r3 800a5c0: 683b ldr r3, [r7, #0] 800a5c2: f883 2020 strb.w r2, [r3, #32] pCSD->Reserved3 = 0; 800a5c6: 683b ldr r3, [r7, #0] 800a5c8: 2200 movs r2, #0 800a5ca: f883 2021 strb.w r2, [r3, #33] ; 0x21 pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U); 800a5ce: 687b ldr r3, [r7, #4] 800a5d0: 6e9b ldr r3, [r3, #104] ; 0x68 800a5d2: 0c1b lsrs r3, r3, #16 800a5d4: b2db uxtb r3, r3 800a5d6: f003 0301 and.w r3, r3, #1 800a5da: b2da uxtb r2, r3 800a5dc: 683b ldr r3, [r7, #0] 800a5de: f883 2022 strb.w r2, [r3, #34] ; 0x22 pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U); 800a5e2: 687b ldr r3, [r7, #4] 800a5e4: 6e9b ldr r3, [r3, #104] ; 0x68 800a5e6: 0bdb lsrs r3, r3, #15 800a5e8: b2db uxtb r3, r3 800a5ea: f003 0301 and.w r3, r3, #1 800a5ee: b2da uxtb r2, r3 800a5f0: 683b ldr r3, [r7, #0] 800a5f2: f883 2023 strb.w r2, [r3, #35] ; 0x23 pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U); 800a5f6: 687b ldr r3, [r7, #4] 800a5f8: 6e9b ldr r3, [r3, #104] ; 0x68 800a5fa: 0b9b lsrs r3, r3, #14 800a5fc: b2db uxtb r3, r3 800a5fe: f003 0301 and.w r3, r3, #1 800a602: b2da uxtb r2, r3 800a604: 683b ldr r3, [r7, #0] 800a606: f883 2024 strb.w r2, [r3, #36] ; 0x24 pCSD->PermWrProtect = (uint8_t)((hsd->CSD[3] & 0x00002000U) >> 13U); 800a60a: 687b ldr r3, [r7, #4] 800a60c: 6e9b ldr r3, [r3, #104] ; 0x68 800a60e: 0b5b lsrs r3, r3, #13 800a610: b2db uxtb r3, r3 800a612: f003 0301 and.w r3, r3, #1 800a616: b2da uxtb r2, r3 800a618: 683b ldr r3, [r7, #0] 800a61a: f883 2025 strb.w r2, [r3, #37] ; 0x25 pCSD->TempWrProtect = (uint8_t)((hsd->CSD[3] & 0x00001000U) >> 12U); 800a61e: 687b ldr r3, [r7, #4] 800a620: 6e9b ldr r3, [r3, #104] ; 0x68 800a622: 0b1b lsrs r3, r3, #12 800a624: b2db uxtb r3, r3 800a626: f003 0301 and.w r3, r3, #1 800a62a: b2da uxtb r2, r3 800a62c: 683b ldr r3, [r7, #0] 800a62e: f883 2026 strb.w r2, [r3, #38] ; 0x26 pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U); 800a632: 687b ldr r3, [r7, #4] 800a634: 6e9b ldr r3, [r3, #104] ; 0x68 800a636: 0a9b lsrs r3, r3, #10 800a638: b2db uxtb r3, r3 800a63a: f003 0303 and.w r3, r3, #3 800a63e: b2da uxtb r2, r3 800a640: 683b ldr r3, [r7, #0] 800a642: f883 2027 strb.w r2, [r3, #39] ; 0x27 pCSD->ECC = (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U); 800a646: 687b ldr r3, [r7, #4] 800a648: 6e9b ldr r3, [r3, #104] ; 0x68 800a64a: 0a1b lsrs r3, r3, #8 800a64c: b2db uxtb r3, r3 800a64e: f003 0303 and.w r3, r3, #3 800a652: b2da uxtb r2, r3 800a654: 683b ldr r3, [r7, #0] 800a656: f883 2028 strb.w r2, [r3, #40] ; 0x28 pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U); 800a65a: 687b ldr r3, [r7, #4] 800a65c: 6e9b ldr r3, [r3, #104] ; 0x68 800a65e: 085b lsrs r3, r3, #1 800a660: b2db uxtb r3, r3 800a662: f003 037f and.w r3, r3, #127 ; 0x7f 800a666: b2da uxtb r2, r3 800a668: 683b ldr r3, [r7, #0] 800a66a: f883 2029 strb.w r2, [r3, #41] ; 0x29 pCSD->Reserved4 = 1; 800a66e: 683b ldr r3, [r7, #0] 800a670: 2201 movs r2, #1 800a672: f883 202a strb.w r2, [r3, #42] ; 0x2a return HAL_OK; 800a676: 2300 movs r3, #0 } 800a678: 4618 mov r0, r3 800a67a: 370c adds r7, #12 800a67c: 46bd mov sp, r7 800a67e: f85d 7b04 ldr.w r7, [sp], #4 800a682: 4770 bx lr 800a684: 1fe00fff .word 0x1fe00fff 0800a688 : * @param pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that * will contain the SD card status information * @retval HAL status */ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus) { 800a688: b580 push {r7, lr} 800a68a: b094 sub sp, #80 ; 0x50 800a68c: af00 add r7, sp, #0 800a68e: 6078 str r0, [r7, #4] 800a690: 6039 str r1, [r7, #0] uint32_t sd_status[16]; uint32_t errorstate; HAL_StatusTypeDef status = HAL_OK; 800a692: 2300 movs r3, #0 800a694: f887 304f strb.w r3, [r7, #79] ; 0x4f if (hsd->State == HAL_SD_STATE_BUSY) 800a698: 687b ldr r3, [r7, #4] 800a69a: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 800a69e: b2db uxtb r3, r3 800a6a0: 2b03 cmp r3, #3 800a6a2: d101 bne.n 800a6a8 { return HAL_ERROR; 800a6a4: 2301 movs r3, #1 800a6a6: e0a7 b.n 800a7f8 } errorstate = SD_SendSDStatus(hsd, sd_status); 800a6a8: f107 0308 add.w r3, r7, #8 800a6ac: 4619 mov r1, r3 800a6ae: 6878 ldr r0, [r7, #4] 800a6b0: f000 fb62 bl 800ad78 800a6b4: 64b8 str r0, [r7, #72] ; 0x48 if (errorstate != HAL_SD_ERROR_NONE) 800a6b6: 6cbb ldr r3, [r7, #72] ; 0x48 800a6b8: 2b00 cmp r3, #0 800a6ba: d011 beq.n 800a6e0 { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 800a6bc: 687b ldr r3, [r7, #4] 800a6be: 681b ldr r3, [r3, #0] 800a6c0: 4a4f ldr r2, [pc, #316] ; (800a800 ) 800a6c2: 639a str r2, [r3, #56] ; 0x38 hsd->ErrorCode |= errorstate; 800a6c4: 687b ldr r3, [r7, #4] 800a6c6: 6b5a ldr r2, [r3, #52] ; 0x34 800a6c8: 6cbb ldr r3, [r7, #72] ; 0x48 800a6ca: 431a orrs r2, r3 800a6cc: 687b ldr r3, [r7, #4] 800a6ce: 635a str r2, [r3, #52] ; 0x34 hsd->State = HAL_SD_STATE_READY; 800a6d0: 687b ldr r3, [r7, #4] 800a6d2: 2201 movs r2, #1 800a6d4: f883 2030 strb.w r2, [r3, #48] ; 0x30 status = HAL_ERROR; 800a6d8: 2301 movs r3, #1 800a6da: f887 304f strb.w r3, [r7, #79] ; 0x4f 800a6de: e070 b.n 800a7c2 } else { pStatus->DataBusWidth = (uint8_t)((sd_status[0] & 0xC0U) >> 6U); 800a6e0: 68bb ldr r3, [r7, #8] 800a6e2: 099b lsrs r3, r3, #6 800a6e4: b2db uxtb r3, r3 800a6e6: f003 0303 and.w r3, r3, #3 800a6ea: b2da uxtb r2, r3 800a6ec: 683b ldr r3, [r7, #0] 800a6ee: 701a strb r2, [r3, #0] pStatus->SecuredMode = (uint8_t)((sd_status[0] & 0x20U) >> 5U); 800a6f0: 68bb ldr r3, [r7, #8] 800a6f2: 095b lsrs r3, r3, #5 800a6f4: b2db uxtb r3, r3 800a6f6: f003 0301 and.w r3, r3, #1 800a6fa: b2da uxtb r2, r3 800a6fc: 683b ldr r3, [r7, #0] 800a6fe: 705a strb r2, [r3, #1] pStatus->CardType = (uint16_t)(((sd_status[0] & 0x00FF0000U) >> 8U) | ((sd_status[0] & 0xFF000000U) >> 24U)); 800a700: 68bb ldr r3, [r7, #8] 800a702: 0a1b lsrs r3, r3, #8 800a704: b29b uxth r3, r3 800a706: f023 03ff bic.w r3, r3, #255 ; 0xff 800a70a: b29a uxth r2, r3 800a70c: 68bb ldr r3, [r7, #8] 800a70e: 0e1b lsrs r3, r3, #24 800a710: b29b uxth r3, r3 800a712: 4313 orrs r3, r2 800a714: b29a uxth r2, r3 800a716: 683b ldr r3, [r7, #0] 800a718: 805a strh r2, [r3, #2] pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U) | ((sd_status[1] & 0xFF00U) << 8U) | 800a71a: 68fb ldr r3, [r7, #12] 800a71c: 061a lsls r2, r3, #24 800a71e: 68fb ldr r3, [r7, #12] 800a720: 021b lsls r3, r3, #8 800a722: f403 037f and.w r3, r3, #16711680 ; 0xff0000 800a726: 431a orrs r2, r3 ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U) >> 24U)); 800a728: 68fb ldr r3, [r7, #12] 800a72a: 0a1b lsrs r3, r3, #8 800a72c: f403 437f and.w r3, r3, #65280 ; 0xff00 pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U) | ((sd_status[1] & 0xFF00U) << 8U) | 800a730: 431a orrs r2, r3 ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U) >> 24U)); 800a732: 68fb ldr r3, [r7, #12] 800a734: 0e1b lsrs r3, r3, #24 800a736: 431a orrs r2, r3 pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U) | ((sd_status[1] & 0xFF00U) << 8U) | 800a738: 683b ldr r3, [r7, #0] 800a73a: 605a str r2, [r3, #4] pStatus->SpeedClass = (uint8_t)(sd_status[2] & 0xFFU); 800a73c: 693b ldr r3, [r7, #16] 800a73e: b2da uxtb r2, r3 800a740: 683b ldr r3, [r7, #0] 800a742: 721a strb r2, [r3, #8] pStatus->PerformanceMove = (uint8_t)((sd_status[2] & 0xFF00U) >> 8U); 800a744: 693b ldr r3, [r7, #16] 800a746: 0a1b lsrs r3, r3, #8 800a748: b2da uxtb r2, r3 800a74a: 683b ldr r3, [r7, #0] 800a74c: 725a strb r2, [r3, #9] pStatus->AllocationUnitSize = (uint8_t)((sd_status[2] & 0xF00000U) >> 20U); 800a74e: 693b ldr r3, [r7, #16] 800a750: 0d1b lsrs r3, r3, #20 800a752: b2db uxtb r3, r3 800a754: f003 030f and.w r3, r3, #15 800a758: b2da uxtb r2, r3 800a75a: 683b ldr r3, [r7, #0] 800a75c: 729a strb r2, [r3, #10] pStatus->EraseSize = (uint16_t)(((sd_status[2] & 0xFF000000U) >> 16U) | (sd_status[3] & 0xFFU)); 800a75e: 693b ldr r3, [r7, #16] 800a760: 0c1b lsrs r3, r3, #16 800a762: b29b uxth r3, r3 800a764: f023 03ff bic.w r3, r3, #255 ; 0xff 800a768: b29a uxth r2, r3 800a76a: 697b ldr r3, [r7, #20] 800a76c: b29b uxth r3, r3 800a76e: b2db uxtb r3, r3 800a770: b29b uxth r3, r3 800a772: 4313 orrs r3, r2 800a774: b29a uxth r2, r3 800a776: 683b ldr r3, [r7, #0] 800a778: 819a strh r2, [r3, #12] pStatus->EraseTimeout = (uint8_t)((sd_status[3] & 0xFC00U) >> 10U); 800a77a: 697b ldr r3, [r7, #20] 800a77c: 0a9b lsrs r3, r3, #10 800a77e: b2db uxtb r3, r3 800a780: f003 033f and.w r3, r3, #63 ; 0x3f 800a784: b2da uxtb r2, r3 800a786: 683b ldr r3, [r7, #0] 800a788: 739a strb r2, [r3, #14] pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U); 800a78a: 697b ldr r3, [r7, #20] 800a78c: 0a1b lsrs r3, r3, #8 800a78e: b2db uxtb r3, r3 800a790: f003 0303 and.w r3, r3, #3 800a794: b2da uxtb r2, r3 800a796: 683b ldr r3, [r7, #0] 800a798: 73da strb r2, [r3, #15] pStatus->UhsSpeedGrade = (uint8_t)((sd_status[3] & 0x00F0U) >> 4U); 800a79a: 697b ldr r3, [r7, #20] 800a79c: 091b lsrs r3, r3, #4 800a79e: b2db uxtb r3, r3 800a7a0: f003 030f and.w r3, r3, #15 800a7a4: b2da uxtb r2, r3 800a7a6: 683b ldr r3, [r7, #0] 800a7a8: 741a strb r2, [r3, #16] pStatus->UhsAllocationUnitSize = (uint8_t)(sd_status[3] & 0x000FU) ; 800a7aa: 697b ldr r3, [r7, #20] 800a7ac: b2db uxtb r3, r3 800a7ae: f003 030f and.w r3, r3, #15 800a7b2: b2da uxtb r2, r3 800a7b4: 683b ldr r3, [r7, #0] 800a7b6: 745a strb r2, [r3, #17] pStatus->VideoSpeedClass = (uint8_t)((sd_status[4] & 0xFF000000U) >> 24U); 800a7b8: 69bb ldr r3, [r7, #24] 800a7ba: 0e1b lsrs r3, r3, #24 800a7bc: b2da uxtb r2, r3 800a7be: 683b ldr r3, [r7, #0] 800a7c0: 749a strb r2, [r3, #18] } /* Set Block Size for Card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); 800a7c2: 687b ldr r3, [r7, #4] 800a7c4: 681b ldr r3, [r3, #0] 800a7c6: f44f 7100 mov.w r1, #512 ; 0x200 800a7ca: 4618 mov r0, r3 800a7cc: f003 f820 bl 800d810 800a7d0: 64b8 str r0, [r7, #72] ; 0x48 if (errorstate != HAL_SD_ERROR_NONE) 800a7d2: 6cbb ldr r3, [r7, #72] ; 0x48 800a7d4: 2b00 cmp r3, #0 800a7d6: d00d beq.n 800a7f4 { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 800a7d8: 687b ldr r3, [r7, #4] 800a7da: 681b ldr r3, [r3, #0] 800a7dc: 4a08 ldr r2, [pc, #32] ; (800a800 ) 800a7de: 639a str r2, [r3, #56] ; 0x38 hsd->ErrorCode = errorstate; 800a7e0: 687b ldr r3, [r7, #4] 800a7e2: 6cba ldr r2, [r7, #72] ; 0x48 800a7e4: 635a str r2, [r3, #52] ; 0x34 hsd->State = HAL_SD_STATE_READY; 800a7e6: 687b ldr r3, [r7, #4] 800a7e8: 2201 movs r2, #1 800a7ea: f883 2030 strb.w r2, [r3, #48] ; 0x30 status = HAL_ERROR; 800a7ee: 2301 movs r3, #1 800a7f0: f887 304f strb.w r3, [r7, #79] ; 0x4f } return status; 800a7f4: f897 304f ldrb.w r3, [r7, #79] ; 0x4f } 800a7f8: 4618 mov r0, r3 800a7fa: 3750 adds r7, #80 ; 0x50 800a7fc: 46bd mov sp, r7 800a7fe: bd80 pop {r7, pc} 800a800: 1fe00fff .word 0x1fe00fff 0800a804 : * @param pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that * will contain the SD card status information * @retval HAL status */ HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo) { 800a804: b480 push {r7} 800a806: b083 sub sp, #12 800a808: af00 add r7, sp, #0 800a80a: 6078 str r0, [r7, #4] 800a80c: 6039 str r1, [r7, #0] pCardInfo->CardType = (uint32_t)(hsd->SdCard.CardType); 800a80e: 687b ldr r3, [r7, #4] 800a810: 6b9a ldr r2, [r3, #56] ; 0x38 800a812: 683b ldr r3, [r7, #0] 800a814: 601a str r2, [r3, #0] pCardInfo->CardVersion = (uint32_t)(hsd->SdCard.CardVersion); 800a816: 687b ldr r3, [r7, #4] 800a818: 6bda ldr r2, [r3, #60] ; 0x3c 800a81a: 683b ldr r3, [r7, #0] 800a81c: 605a str r2, [r3, #4] pCardInfo->Class = (uint32_t)(hsd->SdCard.Class); 800a81e: 687b ldr r3, [r7, #4] 800a820: 6c1a ldr r2, [r3, #64] ; 0x40 800a822: 683b ldr r3, [r7, #0] 800a824: 609a str r2, [r3, #8] pCardInfo->RelCardAdd = (uint32_t)(hsd->SdCard.RelCardAdd); 800a826: 687b ldr r3, [r7, #4] 800a828: 6c5a ldr r2, [r3, #68] ; 0x44 800a82a: 683b ldr r3, [r7, #0] 800a82c: 60da str r2, [r3, #12] pCardInfo->BlockNbr = (uint32_t)(hsd->SdCard.BlockNbr); 800a82e: 687b ldr r3, [r7, #4] 800a830: 6c9a ldr r2, [r3, #72] ; 0x48 800a832: 683b ldr r3, [r7, #0] 800a834: 611a str r2, [r3, #16] pCardInfo->BlockSize = (uint32_t)(hsd->SdCard.BlockSize); 800a836: 687b ldr r3, [r7, #4] 800a838: 6cda ldr r2, [r3, #76] ; 0x4c 800a83a: 683b ldr r3, [r7, #0] 800a83c: 615a str r2, [r3, #20] pCardInfo->LogBlockNbr = (uint32_t)(hsd->SdCard.LogBlockNbr); 800a83e: 687b ldr r3, [r7, #4] 800a840: 6d1a ldr r2, [r3, #80] ; 0x50 800a842: 683b ldr r3, [r7, #0] 800a844: 619a str r2, [r3, #24] pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize); 800a846: 687b ldr r3, [r7, #4] 800a848: 6d5a ldr r2, [r3, #84] ; 0x54 800a84a: 683b ldr r3, [r7, #0] 800a84c: 61da str r2, [r3, #28] return HAL_OK; 800a84e: 2300 movs r3, #0 } 800a850: 4618 mov r0, r3 800a852: 370c adds r7, #12 800a854: 46bd mov sp, r7 800a856: f85d 7b04 ldr.w r7, [sp], #4 800a85a: 4770 bx lr 0800a85c : * @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer * @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer * @retval HAL status */ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode) { 800a85c: b590 push {r4, r7, lr} 800a85e: b08d sub sp, #52 ; 0x34 800a860: af02 add r7, sp, #8 800a862: 6078 str r0, [r7, #4] 800a864: 6039 str r1, [r7, #0] SDMMC_InitTypeDef Init; uint32_t errorstate; uint32_t sdmmc_clk = 0U; 800a866: 2300 movs r3, #0 800a868: 623b str r3, [r7, #32] HAL_StatusTypeDef status = HAL_OK; 800a86a: 2300 movs r3, #0 800a86c: f887 3027 strb.w r3, [r7, #39] ; 0x27 /* Check the parameters */ assert_param(IS_SDMMC_BUS_WIDE(WideMode)); /* Change State */ hsd->State = HAL_SD_STATE_BUSY; 800a870: 687b ldr r3, [r7, #4] 800a872: 2203 movs r2, #3 800a874: f883 2030 strb.w r2, [r3, #48] ; 0x30 if (hsd->SdCard.CardType != CARD_SECURED) 800a878: 687b ldr r3, [r7, #4] 800a87a: 6b9b ldr r3, [r3, #56] ; 0x38 800a87c: 2b03 cmp r3, #3 800a87e: d02e beq.n 800a8de { if (WideMode == SDMMC_BUS_WIDE_8B) 800a880: 683b ldr r3, [r7, #0] 800a882: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 800a886: d106 bne.n 800a896 { hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; 800a888: 687b ldr r3, [r7, #4] 800a88a: 6b5b ldr r3, [r3, #52] ; 0x34 800a88c: f043 5280 orr.w r2, r3, #268435456 ; 0x10000000 800a890: 687b ldr r3, [r7, #4] 800a892: 635a str r2, [r3, #52] ; 0x34 800a894: e029 b.n 800a8ea } else if (WideMode == SDMMC_BUS_WIDE_4B) 800a896: 683b ldr r3, [r7, #0] 800a898: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 800a89c: d10a bne.n 800a8b4 { errorstate = SD_WideBus_Enable(hsd); 800a89e: 6878 ldr r0, [r7, #4] 800a8a0: f000 fb62 bl 800af68 800a8a4: 61f8 str r0, [r7, #28] hsd->ErrorCode |= errorstate; 800a8a6: 687b ldr r3, [r7, #4] 800a8a8: 6b5a ldr r2, [r3, #52] ; 0x34 800a8aa: 69fb ldr r3, [r7, #28] 800a8ac: 431a orrs r2, r3 800a8ae: 687b ldr r3, [r7, #4] 800a8b0: 635a str r2, [r3, #52] ; 0x34 800a8b2: e01a b.n 800a8ea } else if (WideMode == SDMMC_BUS_WIDE_1B) 800a8b4: 683b ldr r3, [r7, #0] 800a8b6: 2b00 cmp r3, #0 800a8b8: d10a bne.n 800a8d0 { errorstate = SD_WideBus_Disable(hsd); 800a8ba: 6878 ldr r0, [r7, #4] 800a8bc: f000 fb9f bl 800affe 800a8c0: 61f8 str r0, [r7, #28] hsd->ErrorCode |= errorstate; 800a8c2: 687b ldr r3, [r7, #4] 800a8c4: 6b5a ldr r2, [r3, #52] ; 0x34 800a8c6: 69fb ldr r3, [r7, #28] 800a8c8: 431a orrs r2, r3 800a8ca: 687b ldr r3, [r7, #4] 800a8cc: 635a str r2, [r3, #52] ; 0x34 800a8ce: e00c b.n 800a8ea } else { /* WideMode is not a valid argument*/ hsd->ErrorCode |= HAL_SD_ERROR_PARAM; 800a8d0: 687b ldr r3, [r7, #4] 800a8d2: 6b5b ldr r3, [r3, #52] ; 0x34 800a8d4: f043 6200 orr.w r2, r3, #134217728 ; 0x8000000 800a8d8: 687b ldr r3, [r7, #4] 800a8da: 635a str r2, [r3, #52] ; 0x34 800a8dc: e005 b.n 800a8ea } } else { /* MMC Card does not support this feature */ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; 800a8de: 687b ldr r3, [r7, #4] 800a8e0: 6b5b ldr r3, [r3, #52] ; 0x34 800a8e2: f043 5280 orr.w r2, r3, #268435456 ; 0x10000000 800a8e6: 687b ldr r3, [r7, #4] 800a8e8: 635a str r2, [r3, #52] ; 0x34 } if (hsd->ErrorCode != HAL_SD_ERROR_NONE) 800a8ea: 687b ldr r3, [r7, #4] 800a8ec: 6b5b ldr r3, [r3, #52] ; 0x34 800a8ee: 2b00 cmp r3, #0 800a8f0: d007 beq.n 800a902 { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 800a8f2: 687b ldr r3, [r7, #4] 800a8f4: 681b ldr r3, [r3, #0] 800a8f6: 4a5e ldr r2, [pc, #376] ; (800aa70 ) 800a8f8: 639a str r2, [r3, #56] ; 0x38 status = HAL_ERROR; 800a8fa: 2301 movs r3, #1 800a8fc: f887 3027 strb.w r3, [r7, #39] ; 0x27 800a900: e094 b.n 800aa2c } else { sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC); 800a902: f44f 3080 mov.w r0, #65536 ; 0x10000 800a906: f7fd fcef bl 80082e8 800a90a: 6238 str r0, [r7, #32] if (sdmmc_clk != 0U) 800a90c: 6a3b ldr r3, [r7, #32] 800a90e: 2b00 cmp r3, #0 800a910: f000 8083 beq.w 800aa1a { /* Configure the SDMMC peripheral */ Init.ClockEdge = hsd->Init.ClockEdge; 800a914: 687b ldr r3, [r7, #4] 800a916: 685b ldr r3, [r3, #4] 800a918: 60bb str r3, [r7, #8] Init.ClockPowerSave = hsd->Init.ClockPowerSave; 800a91a: 687b ldr r3, [r7, #4] 800a91c: 689b ldr r3, [r3, #8] 800a91e: 60fb str r3, [r7, #12] Init.BusWide = WideMode; 800a920: 683b ldr r3, [r7, #0] 800a922: 613b str r3, [r7, #16] Init.HardwareFlowControl = hsd->Init.HardwareFlowControl; 800a924: 687b ldr r3, [r7, #4] 800a926: 691b ldr r3, [r3, #16] 800a928: 617b str r3, [r7, #20] /* Check if user Clock div < Normal speed 25Mhz, no change in Clockdiv */ if (hsd->Init.ClockDiv >= (sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ))) 800a92a: 687b ldr r3, [r7, #4] 800a92c: 695a ldr r2, [r3, #20] 800a92e: 6a3b ldr r3, [r7, #32] 800a930: 4950 ldr r1, [pc, #320] ; (800aa74 ) 800a932: fba1 1303 umull r1, r3, r1, r3 800a936: 0e1b lsrs r3, r3, #24 800a938: 429a cmp r2, r3 800a93a: d303 bcc.n 800a944 { Init.ClockDiv = hsd->Init.ClockDiv; 800a93c: 687b ldr r3, [r7, #4] 800a93e: 695b ldr r3, [r3, #20] 800a940: 61bb str r3, [r7, #24] 800a942: e05a b.n 800a9fa } else if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) 800a944: 687b ldr r3, [r7, #4] 800a946: 6d9b ldr r3, [r3, #88] ; 0x58 800a948: f5b3 7f00 cmp.w r3, #512 ; 0x200 800a94c: d103 bne.n 800a956 { /* UltraHigh speed SD card,user Clock div */ Init.ClockDiv = hsd->Init.ClockDiv; 800a94e: 687b ldr r3, [r7, #4] 800a950: 695b ldr r3, [r3, #20] 800a952: 61bb str r3, [r7, #24] 800a954: e051 b.n 800a9fa } else if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) 800a956: 687b ldr r3, [r7, #4] 800a958: 6d9b ldr r3, [r3, #88] ; 0x58 800a95a: f5b3 7f80 cmp.w r3, #256 ; 0x100 800a95e: d126 bne.n 800a9ae { /* High speed SD card, Max Frequency = 50Mhz */ if (hsd->Init.ClockDiv == 0U) 800a960: 687b ldr r3, [r7, #4] 800a962: 695b ldr r3, [r3, #20] 800a964: 2b00 cmp r3, #0 800a966: d10e bne.n 800a986 { if (sdmmc_clk > SD_HIGH_SPEED_FREQ) 800a968: 6a3b ldr r3, [r7, #32] 800a96a: 4a43 ldr r2, [pc, #268] ; (800aa78 ) 800a96c: 4293 cmp r3, r2 800a96e: d906 bls.n 800a97e { Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ); 800a970: 6a3b ldr r3, [r7, #32] 800a972: 4a40 ldr r2, [pc, #256] ; (800aa74 ) 800a974: fba2 2303 umull r2, r3, r2, r3 800a978: 0e5b lsrs r3, r3, #25 800a97a: 61bb str r3, [r7, #24] 800a97c: e03d b.n 800a9fa } else { Init.ClockDiv = hsd->Init.ClockDiv; 800a97e: 687b ldr r3, [r7, #4] 800a980: 695b ldr r3, [r3, #20] 800a982: 61bb str r3, [r7, #24] 800a984: e039 b.n 800a9fa } } else { if ((sdmmc_clk / (2U * hsd->Init.ClockDiv)) > SD_HIGH_SPEED_FREQ) 800a986: 687b ldr r3, [r7, #4] 800a988: 695b ldr r3, [r3, #20] 800a98a: 005b lsls r3, r3, #1 800a98c: 6a3a ldr r2, [r7, #32] 800a98e: fbb2 f3f3 udiv r3, r2, r3 800a992: 4a39 ldr r2, [pc, #228] ; (800aa78 ) 800a994: 4293 cmp r3, r2 800a996: d906 bls.n 800a9a6 { Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ); 800a998: 6a3b ldr r3, [r7, #32] 800a99a: 4a36 ldr r2, [pc, #216] ; (800aa74 ) 800a99c: fba2 2303 umull r2, r3, r2, r3 800a9a0: 0e5b lsrs r3, r3, #25 800a9a2: 61bb str r3, [r7, #24] 800a9a4: e029 b.n 800a9fa } else { Init.ClockDiv = hsd->Init.ClockDiv; 800a9a6: 687b ldr r3, [r7, #4] 800a9a8: 695b ldr r3, [r3, #20] 800a9aa: 61bb str r3, [r7, #24] 800a9ac: e025 b.n 800a9fa } } else { /* No High speed SD card, Max Frequency = 25Mhz */ if (hsd->Init.ClockDiv == 0U) 800a9ae: 687b ldr r3, [r7, #4] 800a9b0: 695b ldr r3, [r3, #20] 800a9b2: 2b00 cmp r3, #0 800a9b4: d10e bne.n 800a9d4 { if (sdmmc_clk > SD_NORMAL_SPEED_FREQ) 800a9b6: 6a3b ldr r3, [r7, #32] 800a9b8: 4a30 ldr r2, [pc, #192] ; (800aa7c ) 800a9ba: 4293 cmp r3, r2 800a9bc: d906 bls.n 800a9cc { Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ); 800a9be: 6a3b ldr r3, [r7, #32] 800a9c0: 4a2c ldr r2, [pc, #176] ; (800aa74 ) 800a9c2: fba2 2303 umull r2, r3, r2, r3 800a9c6: 0e1b lsrs r3, r3, #24 800a9c8: 61bb str r3, [r7, #24] 800a9ca: e016 b.n 800a9fa } else { Init.ClockDiv = hsd->Init.ClockDiv; 800a9cc: 687b ldr r3, [r7, #4] 800a9ce: 695b ldr r3, [r3, #20] 800a9d0: 61bb str r3, [r7, #24] 800a9d2: e012 b.n 800a9fa } } else { if ((sdmmc_clk / (2U * hsd->Init.ClockDiv)) > SD_NORMAL_SPEED_FREQ) 800a9d4: 687b ldr r3, [r7, #4] 800a9d6: 695b ldr r3, [r3, #20] 800a9d8: 005b lsls r3, r3, #1 800a9da: 6a3a ldr r2, [r7, #32] 800a9dc: fbb2 f3f3 udiv r3, r2, r3 800a9e0: 4a26 ldr r2, [pc, #152] ; (800aa7c ) 800a9e2: 4293 cmp r3, r2 800a9e4: d906 bls.n 800a9f4 { Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ); 800a9e6: 6a3b ldr r3, [r7, #32] 800a9e8: 4a22 ldr r2, [pc, #136] ; (800aa74 ) 800a9ea: fba2 2303 umull r2, r3, r2, r3 800a9ee: 0e1b lsrs r3, r3, #24 800a9f0: 61bb str r3, [r7, #24] 800a9f2: e002 b.n 800a9fa } else { Init.ClockDiv = hsd->Init.ClockDiv; 800a9f4: 687b ldr r3, [r7, #4] 800a9f6: 695b ldr r3, [r3, #20] 800a9f8: 61bb str r3, [r7, #24] #if (USE_SD_TRANSCEIVER != 0U) Init.TranceiverPresent = hsd->Init.TranceiverPresent; #endif /* USE_SD_TRANSCEIVER */ (void)SDMMC_Init(hsd->Instance, Init); 800a9fa: 687b ldr r3, [r7, #4] 800a9fc: 681c ldr r4, [r3, #0] 800a9fe: 466a mov r2, sp 800aa00: f107 0314 add.w r3, r7, #20 800aa04: e893 0003 ldmia.w r3, {r0, r1} 800aa08: e882 0003 stmia.w r2, {r0, r1} 800aa0c: f107 0308 add.w r3, r7, #8 800aa10: cb0e ldmia r3, {r1, r2, r3} 800aa12: 4620 mov r0, r4 800aa14: f002 fe1e bl 800d654 800aa18: e008 b.n 800aa2c } else { hsd->ErrorCode |= SDMMC_ERROR_INVALID_PARAMETER; 800aa1a: 687b ldr r3, [r7, #4] 800aa1c: 6b5b ldr r3, [r3, #52] ; 0x34 800aa1e: f043 6200 orr.w r2, r3, #134217728 ; 0x8000000 800aa22: 687b ldr r3, [r7, #4] 800aa24: 635a str r2, [r3, #52] ; 0x34 status = HAL_ERROR; 800aa26: 2301 movs r3, #1 800aa28: f887 3027 strb.w r3, [r7, #39] ; 0x27 } } /* Set Block Size for Card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); 800aa2c: 687b ldr r3, [r7, #4] 800aa2e: 681b ldr r3, [r3, #0] 800aa30: f44f 7100 mov.w r1, #512 ; 0x200 800aa34: 4618 mov r0, r3 800aa36: f002 feeb bl 800d810 800aa3a: 61f8 str r0, [r7, #28] if (errorstate != HAL_SD_ERROR_NONE) 800aa3c: 69fb ldr r3, [r7, #28] 800aa3e: 2b00 cmp r3, #0 800aa40: d00c beq.n 800aa5c { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); 800aa42: 687b ldr r3, [r7, #4] 800aa44: 681b ldr r3, [r3, #0] 800aa46: 4a0a ldr r2, [pc, #40] ; (800aa70 ) 800aa48: 639a str r2, [r3, #56] ; 0x38 hsd->ErrorCode |= errorstate; 800aa4a: 687b ldr r3, [r7, #4] 800aa4c: 6b5a ldr r2, [r3, #52] ; 0x34 800aa4e: 69fb ldr r3, [r7, #28] 800aa50: 431a orrs r2, r3 800aa52: 687b ldr r3, [r7, #4] 800aa54: 635a str r2, [r3, #52] ; 0x34 status = HAL_ERROR; 800aa56: 2301 movs r3, #1 800aa58: f887 3027 strb.w r3, [r7, #39] ; 0x27 } /* Change State */ hsd->State = HAL_SD_STATE_READY; 800aa5c: 687b ldr r3, [r7, #4] 800aa5e: 2201 movs r2, #1 800aa60: f883 2030 strb.w r2, [r3, #48] ; 0x30 return status; 800aa64: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 } 800aa68: 4618 mov r0, r3 800aa6a: 372c adds r7, #44 ; 0x2c 800aa6c: 46bd mov sp, r7 800aa6e: bd90 pop {r4, r7, pc} 800aa70: 1fe00fff .word 0x1fe00fff 800aa74: 55e63b89 .word 0x55e63b89 800aa78: 02faf080 .word 0x02faf080 800aa7c: 017d7840 .word 0x017d7840 0800aa80 : * @brief Gets the current sd card data state. * @param hsd: pointer to SD handle * @retval Card state */ HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) { 800aa80: b580 push {r7, lr} 800aa82: b086 sub sp, #24 800aa84: af00 add r7, sp, #0 800aa86: 6078 str r0, [r7, #4] uint32_t cardstate; uint32_t errorstate; uint32_t resp1 = 0; 800aa88: 2300 movs r3, #0 800aa8a: 60fb str r3, [r7, #12] errorstate = SD_SendStatus(hsd, &resp1); 800aa8c: f107 030c add.w r3, r7, #12 800aa90: 4619 mov r1, r3 800aa92: 6878 ldr r0, [r7, #4] 800aa94: f000 fa40 bl 800af18 800aa98: 6178 str r0, [r7, #20] if (errorstate != HAL_SD_ERROR_NONE) 800aa9a: 697b ldr r3, [r7, #20] 800aa9c: 2b00 cmp r3, #0 800aa9e: d005 beq.n 800aaac { hsd->ErrorCode |= errorstate; 800aaa0: 687b ldr r3, [r7, #4] 800aaa2: 6b5a ldr r2, [r3, #52] ; 0x34 800aaa4: 697b ldr r3, [r7, #20] 800aaa6: 431a orrs r2, r3 800aaa8: 687b ldr r3, [r7, #4] 800aaaa: 635a str r2, [r3, #52] ; 0x34 } cardstate = ((resp1 >> 9U) & 0x0FU); 800aaac: 68fb ldr r3, [r7, #12] 800aaae: 0a5b lsrs r3, r3, #9 800aab0: f003 030f and.w r3, r3, #15 800aab4: 613b str r3, [r7, #16] return (HAL_SD_CardStateTypeDef)cardstate; 800aab6: 693b ldr r3, [r7, #16] } 800aab8: 4618 mov r0, r3 800aaba: 3718 adds r7, #24 800aabc: 46bd mov sp, r7 800aabe: bd80 pop {r7, pc} 0800aac0 : * @brief Initializes the sd card. * @param hsd: Pointer to SD handle * @retval SD Card error state */ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) { 800aac0: b580 push {r7, lr} 800aac2: b090 sub sp, #64 ; 0x40 800aac4: af00 add r7, sp, #0 800aac6: 6078 str r0, [r7, #4] HAL_SD_CardCSDTypeDef CSD; uint32_t errorstate; uint16_t sd_rca = 0U; 800aac8: 2300 movs r3, #0 800aaca: 817b strh r3, [r7, #10] uint32_t tickstart = HAL_GetTick(); 800aacc: f7f8 fb8c bl 80031e8 800aad0: 63f8 str r0, [r7, #60] ; 0x3c /* Check the power State */ if (SDMMC_GetPowerState(hsd->Instance) == 0U) 800aad2: 687b ldr r3, [r7, #4] 800aad4: 681b ldr r3, [r3, #0] 800aad6: 4618 mov r0, r3 800aad8: f002 fe15 bl 800d706 800aadc: 4603 mov r3, r0 800aade: 2b00 cmp r3, #0 800aae0: d102 bne.n 800aae8 { /* Power off */ return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; 800aae2: f04f 6380 mov.w r3, #67108864 ; 0x4000000 800aae6: e0b5 b.n 800ac54 } if (hsd->SdCard.CardType != CARD_SECURED) 800aae8: 687b ldr r3, [r7, #4] 800aaea: 6b9b ldr r3, [r3, #56] ; 0x38 800aaec: 2b03 cmp r3, #3 800aaee: d02e beq.n 800ab4e { /* Send CMD2 ALL_SEND_CID */ errorstate = SDMMC_CmdSendCID(hsd->Instance); 800aaf0: 687b ldr r3, [r7, #4] 800aaf2: 681b ldr r3, [r3, #0] 800aaf4: 4618 mov r0, r3 800aaf6: f003 f860 bl 800dbba 800aafa: 63b8 str r0, [r7, #56] ; 0x38 if (errorstate != HAL_SD_ERROR_NONE) 800aafc: 6bbb ldr r3, [r7, #56] ; 0x38 800aafe: 2b00 cmp r3, #0 800ab00: d001 beq.n 800ab06 { return errorstate; 800ab02: 6bbb ldr r3, [r7, #56] ; 0x38 800ab04: e0a6 b.n 800ac54 } else { /* Get Card identification number data */ hsd->CID[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); 800ab06: 687b ldr r3, [r7, #4] 800ab08: 681b ldr r3, [r3, #0] 800ab0a: 2100 movs r1, #0 800ab0c: 4618 mov r0, r3 800ab0e: f002 fe40 bl 800d792 800ab12: 4602 mov r2, r0 800ab14: 687b ldr r3, [r7, #4] 800ab16: 66da str r2, [r3, #108] ; 0x6c hsd->CID[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); 800ab18: 687b ldr r3, [r7, #4] 800ab1a: 681b ldr r3, [r3, #0] 800ab1c: 2104 movs r1, #4 800ab1e: 4618 mov r0, r3 800ab20: f002 fe37 bl 800d792 800ab24: 4602 mov r2, r0 800ab26: 687b ldr r3, [r7, #4] 800ab28: 671a str r2, [r3, #112] ; 0x70 hsd->CID[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); 800ab2a: 687b ldr r3, [r7, #4] 800ab2c: 681b ldr r3, [r3, #0] 800ab2e: 2108 movs r1, #8 800ab30: 4618 mov r0, r3 800ab32: f002 fe2e bl 800d792 800ab36: 4602 mov r2, r0 800ab38: 687b ldr r3, [r7, #4] 800ab3a: 675a str r2, [r3, #116] ; 0x74 hsd->CID[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); 800ab3c: 687b ldr r3, [r7, #4] 800ab3e: 681b ldr r3, [r3, #0] 800ab40: 210c movs r1, #12 800ab42: 4618 mov r0, r3 800ab44: f002 fe25 bl 800d792 800ab48: 4602 mov r2, r0 800ab4a: 687b ldr r3, [r7, #4] 800ab4c: 679a str r2, [r3, #120] ; 0x78 } } if (hsd->SdCard.CardType != CARD_SECURED) 800ab4e: 687b ldr r3, [r7, #4] 800ab50: 6b9b ldr r3, [r3, #56] ; 0x38 800ab52: 2b03 cmp r3, #3 800ab54: d01d beq.n 800ab92 { /* Send CMD3 SET_REL_ADDR with argument 0 */ /* SD Card publishes its RCA. */ while (sd_rca == 0U) 800ab56: e019 b.n 800ab8c { errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca); 800ab58: 687b ldr r3, [r7, #4] 800ab5a: 681b ldr r3, [r3, #0] 800ab5c: f107 020a add.w r2, r7, #10 800ab60: 4611 mov r1, r2 800ab62: 4618 mov r0, r3 800ab64: f003 f868 bl 800dc38 800ab68: 63b8 str r0, [r7, #56] ; 0x38 if (errorstate != HAL_SD_ERROR_NONE) 800ab6a: 6bbb ldr r3, [r7, #56] ; 0x38 800ab6c: 2b00 cmp r3, #0 800ab6e: d001 beq.n 800ab74 { return errorstate; 800ab70: 6bbb ldr r3, [r7, #56] ; 0x38 800ab72: e06f b.n 800ac54 } if ((HAL_GetTick() - tickstart) >= SDMMC_CMDTIMEOUT) 800ab74: f7f8 fb38 bl 80031e8 800ab78: 4602 mov r2, r0 800ab7a: 6bfb ldr r3, [r7, #60] ; 0x3c 800ab7c: 1ad3 subs r3, r2, r3 800ab7e: f241 3287 movw r2, #4999 ; 0x1387 800ab82: 4293 cmp r3, r2 800ab84: d902 bls.n 800ab8c { return HAL_SD_ERROR_TIMEOUT; 800ab86: f04f 4300 mov.w r3, #2147483648 ; 0x80000000 800ab8a: e063 b.n 800ac54 while (sd_rca == 0U) 800ab8c: 897b ldrh r3, [r7, #10] 800ab8e: 2b00 cmp r3, #0 800ab90: d0e2 beq.n 800ab58 } } } if (hsd->SdCard.CardType != CARD_SECURED) 800ab92: 687b ldr r3, [r7, #4] 800ab94: 6b9b ldr r3, [r3, #56] ; 0x38 800ab96: 2b03 cmp r3, #3 800ab98: d036 beq.n 800ac08 { /* Get the SD card RCA */ hsd->SdCard.RelCardAdd = sd_rca; 800ab9a: 897b ldrh r3, [r7, #10] 800ab9c: 461a mov r2, r3 800ab9e: 687b ldr r3, [r7, #4] 800aba0: 645a str r2, [r3, #68] ; 0x44 /* Send CMD9 SEND_CSD with argument as card's RCA */ errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); 800aba2: 687b ldr r3, [r7, #4] 800aba4: 681a ldr r2, [r3, #0] 800aba6: 687b ldr r3, [r7, #4] 800aba8: 6c5b ldr r3, [r3, #68] ; 0x44 800abaa: 041b lsls r3, r3, #16 800abac: 4619 mov r1, r3 800abae: 4610 mov r0, r2 800abb0: f003 f822 bl 800dbf8 800abb4: 63b8 str r0, [r7, #56] ; 0x38 if (errorstate != HAL_SD_ERROR_NONE) 800abb6: 6bbb ldr r3, [r7, #56] ; 0x38 800abb8: 2b00 cmp r3, #0 800abba: d001 beq.n 800abc0 { return errorstate; 800abbc: 6bbb ldr r3, [r7, #56] ; 0x38 800abbe: e049 b.n 800ac54 } else { /* Get Card Specific Data */ hsd->CSD[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); 800abc0: 687b ldr r3, [r7, #4] 800abc2: 681b ldr r3, [r3, #0] 800abc4: 2100 movs r1, #0 800abc6: 4618 mov r0, r3 800abc8: f002 fde3 bl 800d792 800abcc: 4602 mov r2, r0 800abce: 687b ldr r3, [r7, #4] 800abd0: 65da str r2, [r3, #92] ; 0x5c hsd->CSD[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); 800abd2: 687b ldr r3, [r7, #4] 800abd4: 681b ldr r3, [r3, #0] 800abd6: 2104 movs r1, #4 800abd8: 4618 mov r0, r3 800abda: f002 fdda bl 800d792 800abde: 4602 mov r2, r0 800abe0: 687b ldr r3, [r7, #4] 800abe2: 661a str r2, [r3, #96] ; 0x60 hsd->CSD[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); 800abe4: 687b ldr r3, [r7, #4] 800abe6: 681b ldr r3, [r3, #0] 800abe8: 2108 movs r1, #8 800abea: 4618 mov r0, r3 800abec: f002 fdd1 bl 800d792 800abf0: 4602 mov r2, r0 800abf2: 687b ldr r3, [r7, #4] 800abf4: 665a str r2, [r3, #100] ; 0x64 hsd->CSD[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); 800abf6: 687b ldr r3, [r7, #4] 800abf8: 681b ldr r3, [r3, #0] 800abfa: 210c movs r1, #12 800abfc: 4618 mov r0, r3 800abfe: f002 fdc8 bl 800d792 800ac02: 4602 mov r2, r0 800ac04: 687b ldr r3, [r7, #4] 800ac06: 669a str r2, [r3, #104] ; 0x68 } } /* Get the Card Class */ hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20U); 800ac08: 687b ldr r3, [r7, #4] 800ac0a: 681b ldr r3, [r3, #0] 800ac0c: 2104 movs r1, #4 800ac0e: 4618 mov r0, r3 800ac10: f002 fdbf bl 800d792 800ac14: 4603 mov r3, r0 800ac16: 0d1a lsrs r2, r3, #20 800ac18: 687b ldr r3, [r7, #4] 800ac1a: 641a str r2, [r3, #64] ; 0x40 /* Get CSD parameters */ if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK) 800ac1c: f107 030c add.w r3, r7, #12 800ac20: 4619 mov r1, r3 800ac22: 6878 ldr r0, [r7, #4] 800ac24: f7ff fb8c bl 800a340 800ac28: 4603 mov r3, r0 800ac2a: 2b00 cmp r3, #0 800ac2c: d002 beq.n 800ac34 { return HAL_SD_ERROR_UNSUPPORTED_FEATURE; 800ac2e: f04f 5380 mov.w r3, #268435456 ; 0x10000000 800ac32: e00f b.n 800ac54 } /* Select the Card */ errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U)); 800ac34: 687b ldr r3, [r7, #4] 800ac36: 681a ldr r2, [r3, #0] 800ac38: 687b ldr r3, [r7, #4] 800ac3a: 6c5b ldr r3, [r3, #68] ; 0x44 800ac3c: 041b lsls r3, r3, #16 800ac3e: 4619 mov r1, r3 800ac40: 4610 mov r0, r2 800ac42: f002 fed1 bl 800d9e8 800ac46: 63b8 str r0, [r7, #56] ; 0x38 if (errorstate != HAL_SD_ERROR_NONE) 800ac48: 6bbb ldr r3, [r7, #56] ; 0x38 800ac4a: 2b00 cmp r3, #0 800ac4c: d001 beq.n 800ac52 { return errorstate; 800ac4e: 6bbb ldr r3, [r7, #56] ; 0x38 800ac50: e000 b.n 800ac54 } /* All cards are initialized */ return HAL_SD_ERROR_NONE; 800ac52: 2300 movs r3, #0 } 800ac54: 4618 mov r0, r3 800ac56: 3740 adds r7, #64 ; 0x40 800ac58: 46bd mov sp, r7 800ac5a: bd80 pop {r7, pc} 0800ac5c : * in the SD handle. * @param hsd: Pointer to SD handle * @retval error state */ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) { 800ac5c: b580 push {r7, lr} 800ac5e: b086 sub sp, #24 800ac60: af00 add r7, sp, #0 800ac62: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 800ac64: 2300 movs r3, #0 800ac66: 60bb str r3, [r7, #8] uint32_t response = 0U; 800ac68: 2300 movs r3, #0 800ac6a: 617b str r3, [r7, #20] uint32_t validvoltage = 0U; 800ac6c: 2300 movs r3, #0 800ac6e: 613b str r3, [r7, #16] #if (USE_SD_TRANSCEIVER != 0U) uint32_t tickstart = HAL_GetTick(); #endif /* USE_SD_TRANSCEIVER */ /* CMD0: GO_IDLE_STATE */ errorstate = SDMMC_CmdGoIdleState(hsd->Instance); 800ac70: 687b ldr r3, [r7, #4] 800ac72: 681b ldr r3, [r3, #0] 800ac74: 4618 mov r0, r3 800ac76: f002 feda bl 800da2e 800ac7a: 60f8 str r0, [r7, #12] if (errorstate != HAL_SD_ERROR_NONE) 800ac7c: 68fb ldr r3, [r7, #12] 800ac7e: 2b00 cmp r3, #0 800ac80: d001 beq.n 800ac86 { return errorstate; 800ac82: 68fb ldr r3, [r7, #12] 800ac84: e072 b.n 800ad6c } /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */ errorstate = SDMMC_CmdOperCond(hsd->Instance); 800ac86: 687b ldr r3, [r7, #4] 800ac88: 681b ldr r3, [r3, #0] 800ac8a: 4618 mov r0, r3 800ac8c: f002 feed bl 800da6a 800ac90: 60f8 str r0, [r7, #12] if (errorstate == SDMMC_ERROR_TIMEOUT) /* No response to CMD8 */ 800ac92: 68fb ldr r3, [r7, #12] 800ac94: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 800ac98: d10d bne.n 800acb6 { hsd->SdCard.CardVersion = CARD_V1_X; 800ac9a: 687b ldr r3, [r7, #4] 800ac9c: 2200 movs r2, #0 800ac9e: 63da str r2, [r3, #60] ; 0x3c /* CMD0: GO_IDLE_STATE */ errorstate = SDMMC_CmdGoIdleState(hsd->Instance); 800aca0: 687b ldr r3, [r7, #4] 800aca2: 681b ldr r3, [r3, #0] 800aca4: 4618 mov r0, r3 800aca6: f002 fec2 bl 800da2e 800acaa: 60f8 str r0, [r7, #12] if (errorstate != HAL_SD_ERROR_NONE) 800acac: 68fb ldr r3, [r7, #12] 800acae: 2b00 cmp r3, #0 800acb0: d004 beq.n 800acbc { return errorstate; 800acb2: 68fb ldr r3, [r7, #12] 800acb4: e05a b.n 800ad6c } } else { hsd->SdCard.CardVersion = CARD_V2_X; 800acb6: 687b ldr r3, [r7, #4] 800acb8: 2201 movs r2, #1 800acba: 63da str r2, [r3, #60] ; 0x3c } if (hsd->SdCard.CardVersion == CARD_V2_X) 800acbc: 687b ldr r3, [r7, #4] 800acbe: 6bdb ldr r3, [r3, #60] ; 0x3c 800acc0: 2b01 cmp r3, #1 800acc2: d137 bne.n 800ad34 { /* SEND CMD55 APP_CMD with RCA as 0 */ errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); 800acc4: 687b ldr r3, [r7, #4] 800acc6: 681b ldr r3, [r3, #0] 800acc8: 2100 movs r1, #0 800acca: 4618 mov r0, r3 800accc: f002 feed bl 800daaa 800acd0: 60f8 str r0, [r7, #12] if (errorstate != HAL_SD_ERROR_NONE) 800acd2: 68fb ldr r3, [r7, #12] 800acd4: 2b00 cmp r3, #0 800acd6: d02d beq.n 800ad34 { return HAL_SD_ERROR_UNSUPPORTED_FEATURE; 800acd8: f04f 5380 mov.w r3, #268435456 ; 0x10000000 800acdc: e046 b.n 800ad6c /* SD CARD */ /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ while ((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U)) { /* SEND CMD55 APP_CMD with RCA as 0 */ errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); 800acde: 687b ldr r3, [r7, #4] 800ace0: 681b ldr r3, [r3, #0] 800ace2: 2100 movs r1, #0 800ace4: 4618 mov r0, r3 800ace6: f002 fee0 bl 800daaa 800acea: 60f8 str r0, [r7, #12] if (errorstate != HAL_SD_ERROR_NONE) 800acec: 68fb ldr r3, [r7, #12] 800acee: 2b00 cmp r3, #0 800acf0: d001 beq.n 800acf6 { return errorstate; 800acf2: 68fb ldr r3, [r7, #12] 800acf4: e03a b.n 800ad6c } /* Send CMD41 */ errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | 800acf6: 687b ldr r3, [r7, #4] 800acf8: 681b ldr r3, [r3, #0] 800acfa: 491e ldr r1, [pc, #120] ; (800ad74 ) 800acfc: 4618 mov r0, r3 800acfe: f002 fef7 bl 800daf0 800ad02: 60f8 str r0, [r7, #12] SD_SWITCH_1_8V_CAPACITY); if (errorstate != HAL_SD_ERROR_NONE) 800ad04: 68fb ldr r3, [r7, #12] 800ad06: 2b00 cmp r3, #0 800ad08: d002 beq.n 800ad10 { return HAL_SD_ERROR_UNSUPPORTED_FEATURE; 800ad0a: f04f 5380 mov.w r3, #268435456 ; 0x10000000 800ad0e: e02d b.n 800ad6c } /* Get command response */ response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); 800ad10: 687b ldr r3, [r7, #4] 800ad12: 681b ldr r3, [r3, #0] 800ad14: 2100 movs r1, #0 800ad16: 4618 mov r0, r3 800ad18: f002 fd3b bl 800d792 800ad1c: 6178 str r0, [r7, #20] /* Get operating voltage*/ validvoltage = (((response >> 31U) == 1U) ? 1U : 0U); 800ad1e: 697b ldr r3, [r7, #20] 800ad20: 0fdb lsrs r3, r3, #31 800ad22: 2b01 cmp r3, #1 800ad24: d101 bne.n 800ad2a 800ad26: 2301 movs r3, #1 800ad28: e000 b.n 800ad2c 800ad2a: 2300 movs r3, #0 800ad2c: 613b str r3, [r7, #16] count++; 800ad2e: 68bb ldr r3, [r7, #8] 800ad30: 3301 adds r3, #1 800ad32: 60bb str r3, [r7, #8] while ((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U)) 800ad34: 68bb ldr r3, [r7, #8] 800ad36: f64f 72fe movw r2, #65534 ; 0xfffe 800ad3a: 4293 cmp r3, r2 800ad3c: d802 bhi.n 800ad44 800ad3e: 693b ldr r3, [r7, #16] 800ad40: 2b00 cmp r3, #0 800ad42: d0cc beq.n 800acde } if (count >= SDMMC_MAX_VOLT_TRIAL) 800ad44: 68bb ldr r3, [r7, #8] 800ad46: f64f 72fe movw r2, #65534 ; 0xfffe 800ad4a: 4293 cmp r3, r2 800ad4c: d902 bls.n 800ad54 { return HAL_SD_ERROR_INVALID_VOLTRANGE; 800ad4e: f04f 7380 mov.w r3, #16777216 ; 0x1000000 800ad52: e00b b.n 800ad6c } /* Set default card type */ hsd->SdCard.CardType = CARD_SDSC; 800ad54: 687b ldr r3, [r7, #4] 800ad56: 2200 movs r2, #0 800ad58: 639a str r2, [r3, #56] ; 0x38 if ((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) 800ad5a: 697b ldr r3, [r7, #20] 800ad5c: f003 4380 and.w r3, r3, #1073741824 ; 0x40000000 800ad60: 2b00 cmp r3, #0 800ad62: d002 beq.n 800ad6a { hsd->SdCard.CardType = CARD_SDHC_SDXC; 800ad64: 687b ldr r3, [r7, #4] 800ad66: 2201 movs r2, #1 800ad68: 639a str r2, [r3, #56] ; 0x38 } } #endif /* USE_SD_TRANSCEIVER */ } return HAL_SD_ERROR_NONE; 800ad6a: 2300 movs r3, #0 } 800ad6c: 4618 mov r0, r3 800ad6e: 3718 adds r7, #24 800ad70: 46bd mov sp, r7 800ad72: bd80 pop {r7, pc} 800ad74: c1100000 .word 0xc1100000 0800ad78 : * @param pSDstatus: Pointer to the buffer that will contain the SD card status * SD Status register) * @retval error state */ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) { 800ad78: b580 push {r7, lr} 800ad7a: b08c sub sp, #48 ; 0x30 800ad7c: af00 add r7, sp, #0 800ad7e: 6078 str r0, [r7, #4] 800ad80: 6039 str r1, [r7, #0] SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); 800ad82: f7f8 fa31 bl 80031e8 800ad86: 6278 str r0, [r7, #36] ; 0x24 uint32_t count; uint32_t *pData = pSDstatus; 800ad88: 683b ldr r3, [r7, #0] 800ad8a: 62bb str r3, [r7, #40] ; 0x28 /* Check SD response */ if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) 800ad8c: 687b ldr r3, [r7, #4] 800ad8e: 681b ldr r3, [r3, #0] 800ad90: 2100 movs r1, #0 800ad92: 4618 mov r0, r3 800ad94: f002 fcfd bl 800d792 800ad98: 4603 mov r3, r0 800ad9a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 800ad9e: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 800ada2: d102 bne.n 800adaa { return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; 800ada4: f44f 6300 mov.w r3, #2048 ; 0x800 800ada8: e0b0 b.n 800af0c } /* Set block size for card if it is not equal to current block size for card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U); 800adaa: 687b ldr r3, [r7, #4] 800adac: 681b ldr r3, [r3, #0] 800adae: 2140 movs r1, #64 ; 0x40 800adb0: 4618 mov r0, r3 800adb2: f002 fd2d bl 800d810 800adb6: 6238 str r0, [r7, #32] if (errorstate != HAL_SD_ERROR_NONE) 800adb8: 6a3b ldr r3, [r7, #32] 800adba: 2b00 cmp r3, #0 800adbc: d005 beq.n 800adca { hsd->ErrorCode |= HAL_SD_ERROR_NONE; 800adbe: 687b ldr r3, [r7, #4] 800adc0: 6b5a ldr r2, [r3, #52] ; 0x34 800adc2: 687b ldr r3, [r7, #4] 800adc4: 635a str r2, [r3, #52] ; 0x34 return errorstate; 800adc6: 6a3b ldr r3, [r7, #32] 800adc8: e0a0 b.n 800af0c } /* Send CMD55 */ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); 800adca: 687b ldr r3, [r7, #4] 800adcc: 681a ldr r2, [r3, #0] 800adce: 687b ldr r3, [r7, #4] 800add0: 6c5b ldr r3, [r3, #68] ; 0x44 800add2: 041b lsls r3, r3, #16 800add4: 4619 mov r1, r3 800add6: 4610 mov r0, r2 800add8: f002 fe67 bl 800daaa 800addc: 6238 str r0, [r7, #32] if (errorstate != HAL_SD_ERROR_NONE) 800adde: 6a3b ldr r3, [r7, #32] 800ade0: 2b00 cmp r3, #0 800ade2: d005 beq.n 800adf0 { hsd->ErrorCode |= HAL_SD_ERROR_NONE; 800ade4: 687b ldr r3, [r7, #4] 800ade6: 6b5a ldr r2, [r3, #52] ; 0x34 800ade8: 687b ldr r3, [r7, #4] 800adea: 635a str r2, [r3, #52] ; 0x34 return errorstate; 800adec: 6a3b ldr r3, [r7, #32] 800adee: e08d b.n 800af0c } /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; 800adf0: f04f 33ff mov.w r3, #4294967295 800adf4: 60bb str r3, [r7, #8] config.DataLength = 64U; 800adf6: 2340 movs r3, #64 ; 0x40 800adf8: 60fb str r3, [r7, #12] config.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B; 800adfa: 2360 movs r3, #96 ; 0x60 800adfc: 613b str r3, [r7, #16] config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; 800adfe: 2302 movs r3, #2 800ae00: 617b str r3, [r7, #20] config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; 800ae02: 2300 movs r3, #0 800ae04: 61bb str r3, [r7, #24] config.DPSM = SDMMC_DPSM_ENABLE; 800ae06: 2301 movs r3, #1 800ae08: 61fb str r3, [r7, #28] (void)SDMMC_ConfigData(hsd->Instance, &config); 800ae0a: 687b ldr r3, [r7, #4] 800ae0c: 681b ldr r3, [r3, #0] 800ae0e: f107 0208 add.w r2, r7, #8 800ae12: 4611 mov r1, r2 800ae14: 4618 mov r0, r3 800ae16: f002 fccf bl 800d7b8 /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */ errorstate = SDMMC_CmdStatusRegister(hsd->Instance); 800ae1a: 687b ldr r3, [r7, #4] 800ae1c: 681b ldr r3, [r3, #0] 800ae1e: 4618 mov r0, r3 800ae20: f002 ff4f bl 800dcc2 800ae24: 6238 str r0, [r7, #32] if (errorstate != HAL_SD_ERROR_NONE) 800ae26: 6a3b ldr r3, [r7, #32] 800ae28: 2b00 cmp r3, #0 800ae2a: d02b beq.n 800ae84 { hsd->ErrorCode |= HAL_SD_ERROR_NONE; 800ae2c: 687b ldr r3, [r7, #4] 800ae2e: 6b5a ldr r2, [r3, #52] ; 0x34 800ae30: 687b ldr r3, [r7, #4] 800ae32: 635a str r2, [r3, #52] ; 0x34 return errorstate; 800ae34: 6a3b ldr r3, [r7, #32] 800ae36: e069 b.n 800af0c } /* Get status data */ while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) 800ae38: 687b ldr r3, [r7, #4] 800ae3a: 681b ldr r3, [r3, #0] 800ae3c: 6b5b ldr r3, [r3, #52] ; 0x34 800ae3e: f403 4300 and.w r3, r3, #32768 ; 0x8000 800ae42: 2b00 cmp r3, #0 800ae44: d013 beq.n 800ae6e { for (count = 0U; count < 8U; count++) 800ae46: 2300 movs r3, #0 800ae48: 62fb str r3, [r7, #44] ; 0x2c 800ae4a: e00d b.n 800ae68 { *pData = SDMMC_ReadFIFO(hsd->Instance); 800ae4c: 687b ldr r3, [r7, #4] 800ae4e: 681b ldr r3, [r3, #0] 800ae50: 4618 mov r0, r3 800ae52: f002 fc29 bl 800d6a8 800ae56: 4602 mov r2, r0 800ae58: 6abb ldr r3, [r7, #40] ; 0x28 800ae5a: 601a str r2, [r3, #0] pData++; 800ae5c: 6abb ldr r3, [r7, #40] ; 0x28 800ae5e: 3304 adds r3, #4 800ae60: 62bb str r3, [r7, #40] ; 0x28 for (count = 0U; count < 8U; count++) 800ae62: 6afb ldr r3, [r7, #44] ; 0x2c 800ae64: 3301 adds r3, #1 800ae66: 62fb str r3, [r7, #44] ; 0x2c 800ae68: 6afb ldr r3, [r7, #44] ; 0x2c 800ae6a: 2b07 cmp r3, #7 800ae6c: d9ee bls.n 800ae4c } } if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) 800ae6e: f7f8 f9bb bl 80031e8 800ae72: 4602 mov r2, r0 800ae74: 6a7b ldr r3, [r7, #36] ; 0x24 800ae76: 1ad3 subs r3, r2, r3 800ae78: f1b3 3fff cmp.w r3, #4294967295 800ae7c: d102 bne.n 800ae84 { return HAL_SD_ERROR_TIMEOUT; 800ae7e: f04f 4300 mov.w r3, #2147483648 ; 0x80000000 800ae82: e043 b.n 800af0c while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) 800ae84: 687b ldr r3, [r7, #4] 800ae86: 681b ldr r3, [r3, #0] 800ae88: 6b5b ldr r3, [r3, #52] ; 0x34 800ae8a: f403 7395 and.w r3, r3, #298 ; 0x12a 800ae8e: 2b00 cmp r3, #0 800ae90: d0d2 beq.n 800ae38 } } if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) 800ae92: 687b ldr r3, [r7, #4] 800ae94: 681b ldr r3, [r3, #0] 800ae96: 6b5b ldr r3, [r3, #52] ; 0x34 800ae98: f003 0308 and.w r3, r3, #8 800ae9c: 2b00 cmp r3, #0 800ae9e: d001 beq.n 800aea4 { return HAL_SD_ERROR_DATA_TIMEOUT; 800aea0: 2308 movs r3, #8 800aea2: e033 b.n 800af0c } else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) 800aea4: 687b ldr r3, [r7, #4] 800aea6: 681b ldr r3, [r3, #0] 800aea8: 6b5b ldr r3, [r3, #52] ; 0x34 800aeaa: f003 0302 and.w r3, r3, #2 800aeae: 2b00 cmp r3, #0 800aeb0: d001 beq.n 800aeb6 { return HAL_SD_ERROR_DATA_CRC_FAIL; 800aeb2: 2302 movs r3, #2 800aeb4: e02a b.n 800af0c } else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) 800aeb6: 687b ldr r3, [r7, #4] 800aeb8: 681b ldr r3, [r3, #0] 800aeba: 6b5b ldr r3, [r3, #52] ; 0x34 800aebc: f003 0320 and.w r3, r3, #32 800aec0: 2b00 cmp r3, #0 800aec2: d017 beq.n 800aef4 { return HAL_SD_ERROR_RX_OVERRUN; 800aec4: 2320 movs r3, #32 800aec6: e021 b.n 800af0c /* Nothing to do */ } while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DPSMACT))) { *pData = SDMMC_ReadFIFO(hsd->Instance); 800aec8: 687b ldr r3, [r7, #4] 800aeca: 681b ldr r3, [r3, #0] 800aecc: 4618 mov r0, r3 800aece: f002 fbeb bl 800d6a8 800aed2: 4602 mov r2, r0 800aed4: 6abb ldr r3, [r7, #40] ; 0x28 800aed6: 601a str r2, [r3, #0] pData++; 800aed8: 6abb ldr r3, [r7, #40] ; 0x28 800aeda: 3304 adds r3, #4 800aedc: 62bb str r3, [r7, #40] ; 0x28 if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) 800aede: f7f8 f983 bl 80031e8 800aee2: 4602 mov r2, r0 800aee4: 6a7b ldr r3, [r7, #36] ; 0x24 800aee6: 1ad3 subs r3, r2, r3 800aee8: f1b3 3fff cmp.w r3, #4294967295 800aeec: d102 bne.n 800aef4 { return HAL_SD_ERROR_TIMEOUT; 800aeee: f04f 4300 mov.w r3, #2147483648 ; 0x80000000 800aef2: e00b b.n 800af0c while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DPSMACT))) 800aef4: 687b ldr r3, [r7, #4] 800aef6: 681b ldr r3, [r3, #0] 800aef8: 6b5b ldr r3, [r3, #52] ; 0x34 800aefa: f403 5380 and.w r3, r3, #4096 ; 0x1000 800aefe: 2b00 cmp r3, #0 800af00: d1e2 bne.n 800aec8 } } /* Clear all the static status flags*/ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); 800af02: 687b ldr r3, [r7, #4] 800af04: 681b ldr r3, [r3, #0] 800af06: 4a03 ldr r2, [pc, #12] ; (800af14 ) 800af08: 639a str r2, [r3, #56] ; 0x38 return HAL_SD_ERROR_NONE; 800af0a: 2300 movs r3, #0 } 800af0c: 4618 mov r0, r3 800af0e: 3730 adds r7, #48 ; 0x30 800af10: 46bd mov sp, r7 800af12: bd80 pop {r7, pc} 800af14: 18000f3a .word 0x18000f3a 0800af18 : * @param pCardStatus: pointer to the buffer that will contain the SD card * status (Card Status register) * @retval error state */ static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) { 800af18: b580 push {r7, lr} 800af1a: b084 sub sp, #16 800af1c: af00 add r7, sp, #0 800af1e: 6078 str r0, [r7, #4] 800af20: 6039 str r1, [r7, #0] uint32_t errorstate; if (pCardStatus == NULL) 800af22: 683b ldr r3, [r7, #0] 800af24: 2b00 cmp r3, #0 800af26: d102 bne.n 800af2e { return HAL_SD_ERROR_PARAM; 800af28: f04f 6300 mov.w r3, #134217728 ; 0x8000000 800af2c: e018 b.n 800af60 } /* Send Status command */ errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); 800af2e: 687b ldr r3, [r7, #4] 800af30: 681a ldr r2, [r3, #0] 800af32: 687b ldr r3, [r7, #4] 800af34: 6c5b ldr r3, [r3, #68] ; 0x44 800af36: 041b lsls r3, r3, #16 800af38: 4619 mov r1, r3 800af3a: 4610 mov r0, r2 800af3c: f002 fe9e bl 800dc7c 800af40: 60f8 str r0, [r7, #12] if (errorstate != HAL_SD_ERROR_NONE) 800af42: 68fb ldr r3, [r7, #12] 800af44: 2b00 cmp r3, #0 800af46: d001 beq.n 800af4c { return errorstate; 800af48: 68fb ldr r3, [r7, #12] 800af4a: e009 b.n 800af60 } /* Get SD card status */ *pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); 800af4c: 687b ldr r3, [r7, #4] 800af4e: 681b ldr r3, [r3, #0] 800af50: 2100 movs r1, #0 800af52: 4618 mov r0, r3 800af54: f002 fc1d bl 800d792 800af58: 4602 mov r2, r0 800af5a: 683b ldr r3, [r7, #0] 800af5c: 601a str r2, [r3, #0] return HAL_SD_ERROR_NONE; 800af5e: 2300 movs r3, #0 } 800af60: 4618 mov r0, r3 800af62: 3710 adds r7, #16 800af64: 46bd mov sp, r7 800af66: bd80 pop {r7, pc} 0800af68 : * @brief Enables the SDMMC wide bus mode. * @param hsd: pointer to SD handle * @retval error state */ static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) { 800af68: b580 push {r7, lr} 800af6a: b086 sub sp, #24 800af6c: af00 add r7, sp, #0 800af6e: 6078 str r0, [r7, #4] uint32_t scr[2U] = {0UL, 0UL}; 800af70: 2300 movs r3, #0 800af72: 60fb str r3, [r7, #12] 800af74: 2300 movs r3, #0 800af76: 613b str r3, [r7, #16] uint32_t errorstate; if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) 800af78: 687b ldr r3, [r7, #4] 800af7a: 681b ldr r3, [r3, #0] 800af7c: 2100 movs r1, #0 800af7e: 4618 mov r0, r3 800af80: f002 fc07 bl 800d792 800af84: 4603 mov r3, r0 800af86: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 800af8a: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 800af8e: d102 bne.n 800af96 { return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; 800af90: f44f 6300 mov.w r3, #2048 ; 0x800 800af94: e02f b.n 800aff6 } /* Get SCR Register */ errorstate = SD_FindSCR(hsd, scr); 800af96: f107 030c add.w r3, r7, #12 800af9a: 4619 mov r1, r3 800af9c: 6878 ldr r0, [r7, #4] 800af9e: f000 f879 bl 800b094 800afa2: 6178 str r0, [r7, #20] if (errorstate != HAL_SD_ERROR_NONE) 800afa4: 697b ldr r3, [r7, #20] 800afa6: 2b00 cmp r3, #0 800afa8: d001 beq.n 800afae { return errorstate; 800afaa: 697b ldr r3, [r7, #20] 800afac: e023 b.n 800aff6 } /* If requested card supports wide bus operation */ if ((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO) 800afae: 693b ldr r3, [r7, #16] 800afb0: f403 2380 and.w r3, r3, #262144 ; 0x40000 800afb4: 2b00 cmp r3, #0 800afb6: d01c beq.n 800aff2 { /* Send CMD55 APP_CMD with argument as card's RCA.*/ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); 800afb8: 687b ldr r3, [r7, #4] 800afba: 681a ldr r2, [r3, #0] 800afbc: 687b ldr r3, [r7, #4] 800afbe: 6c5b ldr r3, [r3, #68] ; 0x44 800afc0: 041b lsls r3, r3, #16 800afc2: 4619 mov r1, r3 800afc4: 4610 mov r0, r2 800afc6: f002 fd70 bl 800daaa 800afca: 6178 str r0, [r7, #20] if (errorstate != HAL_SD_ERROR_NONE) 800afcc: 697b ldr r3, [r7, #20] 800afce: 2b00 cmp r3, #0 800afd0: d001 beq.n 800afd6 { return errorstate; 800afd2: 697b ldr r3, [r7, #20] 800afd4: e00f b.n 800aff6 } /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U); 800afd6: 687b ldr r3, [r7, #4] 800afd8: 681b ldr r3, [r3, #0] 800afda: 2102 movs r1, #2 800afdc: 4618 mov r0, r3 800afde: f002 fda7 bl 800db30 800afe2: 6178 str r0, [r7, #20] if (errorstate != HAL_SD_ERROR_NONE) 800afe4: 697b ldr r3, [r7, #20] 800afe6: 2b00 cmp r3, #0 800afe8: d001 beq.n 800afee { return errorstate; 800afea: 697b ldr r3, [r7, #20] 800afec: e003 b.n 800aff6 } return HAL_SD_ERROR_NONE; 800afee: 2300 movs r3, #0 800aff0: e001 b.n 800aff6 } else { return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; 800aff2: f04f 6380 mov.w r3, #67108864 ; 0x4000000 } } 800aff6: 4618 mov r0, r3 800aff8: 3718 adds r7, #24 800affa: 46bd mov sp, r7 800affc: bd80 pop {r7, pc} 0800affe : * @brief Disables the SDMMC wide bus mode. * @param hsd: Pointer to SD handle * @retval error state */ static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) { 800affe: b580 push {r7, lr} 800b000: b086 sub sp, #24 800b002: af00 add r7, sp, #0 800b004: 6078 str r0, [r7, #4] uint32_t scr[2U] = {0UL, 0UL}; 800b006: 2300 movs r3, #0 800b008: 60fb str r3, [r7, #12] 800b00a: 2300 movs r3, #0 800b00c: 613b str r3, [r7, #16] uint32_t errorstate; if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) 800b00e: 687b ldr r3, [r7, #4] 800b010: 681b ldr r3, [r3, #0] 800b012: 2100 movs r1, #0 800b014: 4618 mov r0, r3 800b016: f002 fbbc bl 800d792 800b01a: 4603 mov r3, r0 800b01c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 800b020: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 800b024: d102 bne.n 800b02c { return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; 800b026: f44f 6300 mov.w r3, #2048 ; 0x800 800b02a: e02f b.n 800b08c } /* Get SCR Register */ errorstate = SD_FindSCR(hsd, scr); 800b02c: f107 030c add.w r3, r7, #12 800b030: 4619 mov r1, r3 800b032: 6878 ldr r0, [r7, #4] 800b034: f000 f82e bl 800b094 800b038: 6178 str r0, [r7, #20] if (errorstate != HAL_SD_ERROR_NONE) 800b03a: 697b ldr r3, [r7, #20] 800b03c: 2b00 cmp r3, #0 800b03e: d001 beq.n 800b044 { return errorstate; 800b040: 697b ldr r3, [r7, #20] 800b042: e023 b.n 800b08c } /* If requested card supports 1 bit mode operation */ if ((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO) 800b044: 693b ldr r3, [r7, #16] 800b046: f403 3380 and.w r3, r3, #65536 ; 0x10000 800b04a: 2b00 cmp r3, #0 800b04c: d01c beq.n 800b088 { /* Send CMD55 APP_CMD with argument as card's RCA */ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); 800b04e: 687b ldr r3, [r7, #4] 800b050: 681a ldr r2, [r3, #0] 800b052: 687b ldr r3, [r7, #4] 800b054: 6c5b ldr r3, [r3, #68] ; 0x44 800b056: 041b lsls r3, r3, #16 800b058: 4619 mov r1, r3 800b05a: 4610 mov r0, r2 800b05c: f002 fd25 bl 800daaa 800b060: 6178 str r0, [r7, #20] if (errorstate != HAL_SD_ERROR_NONE) 800b062: 697b ldr r3, [r7, #20] 800b064: 2b00 cmp r3, #0 800b066: d001 beq.n 800b06c { return errorstate; 800b068: 697b ldr r3, [r7, #20] 800b06a: e00f b.n 800b08c } /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */ errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U); 800b06c: 687b ldr r3, [r7, #4] 800b06e: 681b ldr r3, [r3, #0] 800b070: 2100 movs r1, #0 800b072: 4618 mov r0, r3 800b074: f002 fd5c bl 800db30 800b078: 6178 str r0, [r7, #20] if (errorstate != HAL_SD_ERROR_NONE) 800b07a: 697b ldr r3, [r7, #20] 800b07c: 2b00 cmp r3, #0 800b07e: d001 beq.n 800b084 { return errorstate; 800b080: 697b ldr r3, [r7, #20] 800b082: e003 b.n 800b08c } return HAL_SD_ERROR_NONE; 800b084: 2300 movs r3, #0 800b086: e001 b.n 800b08c } else { return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; 800b088: f04f 6380 mov.w r3, #67108864 ; 0x4000000 } } 800b08c: 4618 mov r0, r3 800b08e: 3718 adds r7, #24 800b090: 46bd mov sp, r7 800b092: bd80 pop {r7, pc} 0800b094 : * @param hsd: Pointer to SD handle * @param pSCR: pointer to the buffer that will contain the SCR value * @retval error state */ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) { 800b094: b580 push {r7, lr} 800b096: b08e sub sp, #56 ; 0x38 800b098: af00 add r7, sp, #0 800b09a: 6078 str r0, [r7, #4] 800b09c: 6039 str r1, [r7, #0] SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); 800b09e: f7f8 f8a3 bl 80031e8 800b0a2: 6338 str r0, [r7, #48] ; 0x30 uint32_t index = 0U; 800b0a4: 2300 movs r3, #0 800b0a6: 637b str r3, [r7, #52] ; 0x34 uint32_t tempscr[2U] = {0UL, 0UL}; 800b0a8: 2300 movs r3, #0 800b0aa: 60bb str r3, [r7, #8] 800b0ac: 2300 movs r3, #0 800b0ae: 60fb str r3, [r7, #12] uint32_t *scr = pSCR; 800b0b0: 683b ldr r3, [r7, #0] 800b0b2: 62fb str r3, [r7, #44] ; 0x2c /* Set Block Size To 8 Bytes */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U); 800b0b4: 687b ldr r3, [r7, #4] 800b0b6: 681b ldr r3, [r3, #0] 800b0b8: 2108 movs r1, #8 800b0ba: 4618 mov r0, r3 800b0bc: f002 fba8 bl 800d810 800b0c0: 62b8 str r0, [r7, #40] ; 0x28 if (errorstate != HAL_SD_ERROR_NONE) 800b0c2: 6abb ldr r3, [r7, #40] ; 0x28 800b0c4: 2b00 cmp r3, #0 800b0c6: d001 beq.n 800b0cc { return errorstate; 800b0c8: 6abb ldr r3, [r7, #40] ; 0x28 800b0ca: e0ad b.n 800b228 } /* Send CMD55 APP_CMD with argument as card's RCA */ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U)); 800b0cc: 687b ldr r3, [r7, #4] 800b0ce: 681a ldr r2, [r3, #0] 800b0d0: 687b ldr r3, [r7, #4] 800b0d2: 6c5b ldr r3, [r3, #68] ; 0x44 800b0d4: 041b lsls r3, r3, #16 800b0d6: 4619 mov r1, r3 800b0d8: 4610 mov r0, r2 800b0da: f002 fce6 bl 800daaa 800b0de: 62b8 str r0, [r7, #40] ; 0x28 if (errorstate != HAL_SD_ERROR_NONE) 800b0e0: 6abb ldr r3, [r7, #40] ; 0x28 800b0e2: 2b00 cmp r3, #0 800b0e4: d001 beq.n 800b0ea { return errorstate; 800b0e6: 6abb ldr r3, [r7, #40] ; 0x28 800b0e8: e09e b.n 800b228 } config.DataTimeOut = SDMMC_DATATIMEOUT; 800b0ea: f04f 33ff mov.w r3, #4294967295 800b0ee: 613b str r3, [r7, #16] config.DataLength = 8U; 800b0f0: 2308 movs r3, #8 800b0f2: 617b str r3, [r7, #20] config.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B; 800b0f4: 2330 movs r3, #48 ; 0x30 800b0f6: 61bb str r3, [r7, #24] config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; 800b0f8: 2302 movs r3, #2 800b0fa: 61fb str r3, [r7, #28] config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; 800b0fc: 2300 movs r3, #0 800b0fe: 623b str r3, [r7, #32] config.DPSM = SDMMC_DPSM_ENABLE; 800b100: 2301 movs r3, #1 800b102: 627b str r3, [r7, #36] ; 0x24 (void)SDMMC_ConfigData(hsd->Instance, &config); 800b104: 687b ldr r3, [r7, #4] 800b106: 681b ldr r3, [r3, #0] 800b108: f107 0210 add.w r2, r7, #16 800b10c: 4611 mov r1, r2 800b10e: 4618 mov r0, r3 800b110: f002 fb52 bl 800d7b8 /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */ errorstate = SDMMC_CmdSendSCR(hsd->Instance); 800b114: 687b ldr r3, [r7, #4] 800b116: 681b ldr r3, [r3, #0] 800b118: 4618 mov r0, r3 800b11a: f002 fd2c bl 800db76 800b11e: 62b8 str r0, [r7, #40] ; 0x28 if (errorstate != HAL_SD_ERROR_NONE) 800b120: 6abb ldr r3, [r7, #40] ; 0x28 800b122: 2b00 cmp r3, #0 800b124: d027 beq.n 800b176 { return errorstate; 800b126: 6abb ldr r3, [r7, #40] ; 0x28 800b128: e07e b.n 800b228 } while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DATAEND)) { if ((!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE)) && (index == 0U)) 800b12a: 687b ldr r3, [r7, #4] 800b12c: 681b ldr r3, [r3, #0] 800b12e: 6b5b ldr r3, [r3, #52] ; 0x34 800b130: f403 2300 and.w r3, r3, #524288 ; 0x80000 800b134: 2b00 cmp r3, #0 800b136: d113 bne.n 800b160 800b138: 6b7b ldr r3, [r7, #52] ; 0x34 800b13a: 2b00 cmp r3, #0 800b13c: d110 bne.n 800b160 { tempscr[0] = SDMMC_ReadFIFO(hsd->Instance); 800b13e: 687b ldr r3, [r7, #4] 800b140: 681b ldr r3, [r3, #0] 800b142: 4618 mov r0, r3 800b144: f002 fab0 bl 800d6a8 800b148: 4603 mov r3, r0 800b14a: 60bb str r3, [r7, #8] tempscr[1] = SDMMC_ReadFIFO(hsd->Instance); 800b14c: 687b ldr r3, [r7, #4] 800b14e: 681b ldr r3, [r3, #0] 800b150: 4618 mov r0, r3 800b152: f002 faa9 bl 800d6a8 800b156: 4603 mov r3, r0 800b158: 60fb str r3, [r7, #12] index++; 800b15a: 6b7b ldr r3, [r7, #52] ; 0x34 800b15c: 3301 adds r3, #1 800b15e: 637b str r3, [r7, #52] ; 0x34 } if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) 800b160: f7f8 f842 bl 80031e8 800b164: 4602 mov r2, r0 800b166: 6b3b ldr r3, [r7, #48] ; 0x30 800b168: 1ad3 subs r3, r2, r3 800b16a: f1b3 3fff cmp.w r3, #4294967295 800b16e: d102 bne.n 800b176 { return HAL_SD_ERROR_TIMEOUT; 800b170: f04f 4300 mov.w r3, #2147483648 ; 0x80000000 800b174: e058 b.n 800b228 while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND | 800b176: 687b ldr r3, [r7, #4] 800b178: 681b ldr r3, [r3, #0] 800b17a: 6b5a ldr r2, [r3, #52] ; 0x34 800b17c: f240 532a movw r3, #1322 ; 0x52a 800b180: 4013 ands r3, r2 800b182: 2b00 cmp r3, #0 800b184: d0d1 beq.n 800b12a } } if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) 800b186: 687b ldr r3, [r7, #4] 800b188: 681b ldr r3, [r3, #0] 800b18a: 6b5b ldr r3, [r3, #52] ; 0x34 800b18c: f003 0308 and.w r3, r3, #8 800b190: 2b00 cmp r3, #0 800b192: d005 beq.n 800b1a0 { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); 800b194: 687b ldr r3, [r7, #4] 800b196: 681b ldr r3, [r3, #0] 800b198: 2208 movs r2, #8 800b19a: 639a str r2, [r3, #56] ; 0x38 return HAL_SD_ERROR_DATA_TIMEOUT; 800b19c: 2308 movs r3, #8 800b19e: e043 b.n 800b228 } else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) 800b1a0: 687b ldr r3, [r7, #4] 800b1a2: 681b ldr r3, [r3, #0] 800b1a4: 6b5b ldr r3, [r3, #52] ; 0x34 800b1a6: f003 0302 and.w r3, r3, #2 800b1aa: 2b00 cmp r3, #0 800b1ac: d005 beq.n 800b1ba { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); 800b1ae: 687b ldr r3, [r7, #4] 800b1b0: 681b ldr r3, [r3, #0] 800b1b2: 2202 movs r2, #2 800b1b4: 639a str r2, [r3, #56] ; 0x38 return HAL_SD_ERROR_DATA_CRC_FAIL; 800b1b6: 2302 movs r3, #2 800b1b8: e036 b.n 800b228 } else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) 800b1ba: 687b ldr r3, [r7, #4] 800b1bc: 681b ldr r3, [r3, #0] 800b1be: 6b5b ldr r3, [r3, #52] ; 0x34 800b1c0: f003 0320 and.w r3, r3, #32 800b1c4: 2b00 cmp r3, #0 800b1c6: d005 beq.n 800b1d4 { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); 800b1c8: 687b ldr r3, [r7, #4] 800b1ca: 681b ldr r3, [r3, #0] 800b1cc: 2220 movs r2, #32 800b1ce: 639a str r2, [r3, #56] ; 0x38 return HAL_SD_ERROR_RX_OVERRUN; 800b1d0: 2320 movs r3, #32 800b1d2: e029 b.n 800b228 } else { /* No error flag set */ /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); 800b1d4: 687b ldr r3, [r7, #4] 800b1d6: 681b ldr r3, [r3, #0] 800b1d8: 4a15 ldr r2, [pc, #84] ; (800b230 ) 800b1da: 639a str r2, [r3, #56] ; 0x38 *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) | \ 800b1dc: 68fb ldr r3, [r7, #12] 800b1de: 061a lsls r2, r3, #24 800b1e0: 68fb ldr r3, [r7, #12] 800b1e2: 021b lsls r3, r3, #8 800b1e4: f403 037f and.w r3, r3, #16711680 ; 0xff0000 800b1e8: 431a orrs r2, r3 ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24)); 800b1ea: 68fb ldr r3, [r7, #12] 800b1ec: 0a1b lsrs r3, r3, #8 800b1ee: f403 437f and.w r3, r3, #65280 ; 0xff00 *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) | \ 800b1f2: 431a orrs r2, r3 ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24)); 800b1f4: 68fb ldr r3, [r7, #12] 800b1f6: 0e1b lsrs r3, r3, #24 800b1f8: 431a orrs r2, r3 *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) | \ 800b1fa: 6afb ldr r3, [r7, #44] ; 0x2c 800b1fc: 601a str r2, [r3, #0] scr++; 800b1fe: 6afb ldr r3, [r7, #44] ; 0x2c 800b200: 3304 adds r3, #4 800b202: 62fb str r3, [r7, #44] ; 0x2c *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) | \ 800b204: 68bb ldr r3, [r7, #8] 800b206: 061a lsls r2, r3, #24 800b208: 68bb ldr r3, [r7, #8] 800b20a: 021b lsls r3, r3, #8 800b20c: f403 037f and.w r3, r3, #16711680 ; 0xff0000 800b210: 431a orrs r2, r3 ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24)); 800b212: 68bb ldr r3, [r7, #8] 800b214: 0a1b lsrs r3, r3, #8 800b216: f403 437f and.w r3, r3, #65280 ; 0xff00 *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) | \ 800b21a: 431a orrs r2, r3 ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24)); 800b21c: 68bb ldr r3, [r7, #8] 800b21e: 0e1b lsrs r3, r3, #24 800b220: 431a orrs r2, r3 *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) | \ 800b222: 6afb ldr r3, [r7, #44] ; 0x2c 800b224: 601a str r2, [r3, #0] } return HAL_SD_ERROR_NONE; 800b226: 2300 movs r3, #0 } 800b228: 4618 mov r0, r3 800b22a: 3738 adds r7, #56 ; 0x38 800b22c: 46bd mov sp, r7 800b22e: bd80 pop {r7, pc} 800b230: 18000f3a .word 0x18000f3a 0800b234 : * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { 800b234: b580 push {r7, lr} 800b236: b084 sub sp, #16 800b238: af00 add r7, sp, #0 800b23a: 6078 str r0, [r7, #4] uint32_t crc_length; uint32_t packet_length; /* Check the SPI handle allocation */ if (hspi == NULL) 800b23c: 687b ldr r3, [r7, #4] 800b23e: 2b00 cmp r3, #0 800b240: d101 bne.n 800b246 { return HAL_ERROR; 800b242: 2301 movs r3, #1 800b244: e0f1 b.n 800b42a assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.TxCRCInitializationPattern)); assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.RxCRCInitializationPattern)); } #else hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 800b246: 687b ldr r3, [r7, #4] 800b248: 2200 movs r2, #0 800b24a: 629a str r2, [r3, #40] ; 0x28 #endif /* USE_SPI_CRC */ /* Verify that the SPI instance supports Data Size higher than 16bits */ if ((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (hspi->Init.DataSize > SPI_DATASIZE_16BIT)) 800b24c: 687b ldr r3, [r7, #4] 800b24e: 681b ldr r3, [r3, #0] 800b250: 4a78 ldr r2, [pc, #480] ; (800b434 ) 800b252: 4293 cmp r3, r2 800b254: d00f beq.n 800b276 800b256: 687b ldr r3, [r7, #4] 800b258: 681b ldr r3, [r3, #0] 800b25a: 4a77 ldr r2, [pc, #476] ; (800b438 ) 800b25c: 4293 cmp r3, r2 800b25e: d00a beq.n 800b276 800b260: 687b ldr r3, [r7, #4] 800b262: 681b ldr r3, [r3, #0] 800b264: 4a75 ldr r2, [pc, #468] ; (800b43c ) 800b266: 4293 cmp r3, r2 800b268: d005 beq.n 800b276 800b26a: 687b ldr r3, [r7, #4] 800b26c: 68db ldr r3, [r3, #12] 800b26e: 2b0f cmp r3, #15 800b270: d901 bls.n 800b276 { return HAL_ERROR; 800b272: 2301 movs r3, #1 800b274: e0d9 b.n 800b42a } /* Verify that the SPI instance supports requested data packing */ packet_length = SPI_GetPacketSize(hspi); 800b276: 6878 ldr r0, [r7, #4] 800b278: f000 f8e2 bl 800b440 800b27c: 60f8 str r0, [r7, #12] if (((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (packet_length > SPI_LOWEND_FIFO_SIZE)) || 800b27e: 687b ldr r3, [r7, #4] 800b280: 681b ldr r3, [r3, #0] 800b282: 4a6c ldr r2, [pc, #432] ; (800b434 ) 800b284: 4293 cmp r3, r2 800b286: d00c beq.n 800b2a2 800b288: 687b ldr r3, [r7, #4] 800b28a: 681b ldr r3, [r3, #0] 800b28c: 4a6a ldr r2, [pc, #424] ; (800b438 ) 800b28e: 4293 cmp r3, r2 800b290: d007 beq.n 800b2a2 800b292: 687b ldr r3, [r7, #4] 800b294: 681b ldr r3, [r3, #0] 800b296: 4a69 ldr r2, [pc, #420] ; (800b43c ) 800b298: 4293 cmp r3, r2 800b29a: d002 beq.n 800b2a2 800b29c: 68fb ldr r3, [r7, #12] 800b29e: 2b08 cmp r3, #8 800b2a0: d811 bhi.n 800b2c6 ((IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (packet_length > SPI_HIGHEND_FIFO_SIZE))) 800b2a2: 687b ldr r3, [r7, #4] 800b2a4: 681b ldr r3, [r3, #0] if (((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (packet_length > SPI_LOWEND_FIFO_SIZE)) || 800b2a6: 4a63 ldr r2, [pc, #396] ; (800b434 ) 800b2a8: 4293 cmp r3, r2 800b2aa: d009 beq.n 800b2c0 ((IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (packet_length > SPI_HIGHEND_FIFO_SIZE))) 800b2ac: 687b ldr r3, [r7, #4] 800b2ae: 681b ldr r3, [r3, #0] 800b2b0: 4a61 ldr r2, [pc, #388] ; (800b438 ) 800b2b2: 4293 cmp r3, r2 800b2b4: d004 beq.n 800b2c0 800b2b6: 687b ldr r3, [r7, #4] 800b2b8: 681b ldr r3, [r3, #0] 800b2ba: 4a60 ldr r2, [pc, #384] ; (800b43c ) 800b2bc: 4293 cmp r3, r2 800b2be: d104 bne.n 800b2ca 800b2c0: 68fb ldr r3, [r7, #12] 800b2c2: 2b10 cmp r3, #16 800b2c4: d901 bls.n 800b2ca { return HAL_ERROR; 800b2c6: 2301 movs r3, #1 800b2c8: e0af b.n 800b42a { crc_length = hspi->Init.DataSize << SPI_CFG1_CRCSIZE_Pos; } #endif /* USE_SPI_CRC */ if (hspi->State == HAL_SPI_STATE_RESET) 800b2ca: 687b ldr r3, [r7, #4] 800b2cc: f893 3081 ldrb.w r3, [r3, #129] ; 0x81 800b2d0: b2db uxtb r3, r3 800b2d2: 2b00 cmp r3, #0 800b2d4: d106 bne.n 800b2e4 { /* Allocate lock resource and initialize it */ hspi->Lock = HAL_UNLOCKED; 800b2d6: 687b ldr r3, [r7, #4] 800b2d8: 2200 movs r2, #0 800b2da: f883 2080 strb.w r2, [r3, #128] ; 0x80 /* Init the low level hardware : GPIO, CLOCK, NVIC... */ hspi->MspInitCallback(hspi); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_SPI_MspInit(hspi); 800b2de: 6878 ldr r0, [r7, #4] 800b2e0: f7f7 fd1c bl 8002d1c #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } hspi->State = HAL_SPI_STATE_BUSY; 800b2e4: 687b ldr r3, [r7, #4] 800b2e6: 2202 movs r2, #2 800b2e8: f883 2081 strb.w r2, [r3, #129] ; 0x81 /* Disable the selected SPI peripheral */ __HAL_SPI_DISABLE(hspi); 800b2ec: 687b ldr r3, [r7, #4] 800b2ee: 681b ldr r3, [r3, #0] 800b2f0: 681a ldr r2, [r3, #0] 800b2f2: 687b ldr r3, [r7, #4] 800b2f4: 681b ldr r3, [r3, #0] 800b2f6: f022 0201 bic.w r2, r2, #1 800b2fa: 601a str r2, [r3, #0] #if (USE_SPI_CRC == 0) /* Keep the default value of CRCSIZE in case of CRC is not used */ crc_length = hspi->Instance->CFG1 & SPI_CFG1_CRCSIZE; 800b2fc: 687b ldr r3, [r7, #4] 800b2fe: 681b ldr r3, [r3, #0] 800b300: 689b ldr r3, [r3, #8] 800b302: f403 13f8 and.w r3, r3, #2031616 ; 0x1f0000 800b306: 60bb str r3, [r7, #8] /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, Communication speed, First bit, CRC calculation state, CRC Length */ /* SPIx NSS Software Management Configuration */ if ((hspi->Init.NSS == SPI_NSS_SOFT) && (((hspi->Init.Mode == SPI_MODE_MASTER) && \ 800b308: 687b ldr r3, [r7, #4] 800b30a: 699b ldr r3, [r3, #24] 800b30c: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000 800b310: d119 bne.n 800b346 800b312: 687b ldr r3, [r7, #4] 800b314: 685b ldr r3, [r3, #4] 800b316: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 800b31a: d103 bne.n 800b324 (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW)) || \ 800b31c: 687b ldr r3, [r7, #4] 800b31e: 6b9b ldr r3, [r3, #56] ; 0x38 if ((hspi->Init.NSS == SPI_NSS_SOFT) && (((hspi->Init.Mode == SPI_MODE_MASTER) && \ 800b320: 2b00 cmp r3, #0 800b322: d008 beq.n 800b336 ((hspi->Init.Mode == SPI_MODE_SLAVE) && \ 800b324: 687b ldr r3, [r7, #4] 800b326: 685b ldr r3, [r3, #4] (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW)) || \ 800b328: 2b00 cmp r3, #0 800b32a: d10c bne.n 800b346 (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_HIGH)))) 800b32c: 687b ldr r3, [r7, #4] 800b32e: 6b9b ldr r3, [r3, #56] ; 0x38 ((hspi->Init.Mode == SPI_MODE_SLAVE) && \ 800b330: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 800b334: d107 bne.n 800b346 { SET_BIT(hspi->Instance->CR1, SPI_CR1_SSI); 800b336: 687b ldr r3, [r7, #4] 800b338: 681b ldr r3, [r3, #0] 800b33a: 681a ldr r2, [r3, #0] 800b33c: 687b ldr r3, [r7, #4] 800b33e: 681b ldr r3, [r3, #0] 800b340: f442 5280 orr.w r2, r2, #4096 ; 0x1000 800b344: 601a str r2, [r3, #0] } /* SPIx CFG1 Configuration */ WRITE_REG(hspi->Instance->CFG1, (hspi->Init.BaudRatePrescaler | hspi->Init.CRCCalculation | crc_length | 800b346: 687b ldr r3, [r7, #4] 800b348: 69da ldr r2, [r3, #28] 800b34a: 687b ldr r3, [r7, #4] 800b34c: 6a9b ldr r3, [r3, #40] ; 0x28 800b34e: 431a orrs r2, r3 800b350: 68bb ldr r3, [r7, #8] 800b352: 431a orrs r2, r3 800b354: 687b ldr r3, [r7, #4] 800b356: 6bdb ldr r3, [r3, #60] ; 0x3c 800b358: ea42 0103 orr.w r1, r2, r3 800b35c: 687b ldr r3, [r7, #4] 800b35e: 68da ldr r2, [r3, #12] 800b360: 687b ldr r3, [r7, #4] 800b362: 681b ldr r3, [r3, #0] 800b364: 430a orrs r2, r1 800b366: 609a str r2, [r3, #8] hspi->Init.FifoThreshold | hspi->Init.DataSize)); /* SPIx CFG2 Configuration */ WRITE_REG(hspi->Instance->CFG2, (hspi->Init.NSSPMode | hspi->Init.TIMode | 800b368: 687b ldr r3, [r7, #4] 800b36a: 6b5a ldr r2, [r3, #52] ; 0x34 800b36c: 687b ldr r3, [r7, #4] 800b36e: 6a5b ldr r3, [r3, #36] ; 0x24 800b370: 431a orrs r2, r3 800b372: 687b ldr r3, [r7, #4] 800b374: 6b9b ldr r3, [r3, #56] ; 0x38 800b376: 431a orrs r2, r3 800b378: 687b ldr r3, [r7, #4] 800b37a: 699b ldr r3, [r3, #24] 800b37c: 431a orrs r2, r3 800b37e: 687b ldr r3, [r7, #4] 800b380: 691b ldr r3, [r3, #16] 800b382: 431a orrs r2, r3 800b384: 687b ldr r3, [r7, #4] 800b386: 695b ldr r3, [r3, #20] 800b388: 431a orrs r2, r3 800b38a: 687b ldr r3, [r7, #4] 800b38c: 6a1b ldr r3, [r3, #32] 800b38e: 431a orrs r2, r3 800b390: 687b ldr r3, [r7, #4] 800b392: 685b ldr r3, [r3, #4] 800b394: 431a orrs r2, r3 800b396: 687b ldr r3, [r7, #4] 800b398: 6cdb ldr r3, [r3, #76] ; 0x4c 800b39a: 431a orrs r2, r3 800b39c: 687b ldr r3, [r7, #4] 800b39e: 689b ldr r3, [r3, #8] 800b3a0: 431a orrs r2, r3 800b3a2: 687b ldr r3, [r7, #4] 800b3a4: 6c9b ldr r3, [r3, #72] ; 0x48 800b3a6: ea42 0103 orr.w r1, r2, r3 800b3aa: 687b ldr r3, [r7, #4] 800b3ac: 6d9a ldr r2, [r3, #88] ; 0x58 800b3ae: 687b ldr r3, [r7, #4] 800b3b0: 681b ldr r3, [r3, #0] 800b3b2: 430a orrs r2, r1 800b3b4: 60da str r2, [r3, #12] WRITE_REG(hspi->Instance->CRCPOLY, hspi->Init.CRCPolynomial); } #endif /* USE_SPI_CRC */ /* Insure that Underrun configuration is managed only by Salve */ if (hspi->Init.Mode == SPI_MODE_SLAVE) 800b3b6: 687b ldr r3, [r7, #4] 800b3b8: 685b ldr r3, [r3, #4] 800b3ba: 2b00 cmp r3, #0 800b3bc: d113 bne.n 800b3e6 /* Set Default Underrun configuration */ #if (USE_SPI_CRC != 0UL) if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_DISABLE) #endif /* USE_SPI_CRC */ { MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, SPI_CFG1_UDRDET_0); 800b3be: 687b ldr r3, [r7, #4] 800b3c0: 681b ldr r3, [r3, #0] 800b3c2: 689b ldr r3, [r3, #8] 800b3c4: f423 52c0 bic.w r2, r3, #6144 ; 0x1800 800b3c8: 687b ldr r3, [r7, #4] 800b3ca: 681b ldr r3, [r3, #0] 800b3cc: f442 6200 orr.w r2, r2, #2048 ; 0x800 800b3d0: 609a str r2, [r3, #8] } MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, SPI_CFG1_UDRCFG_1); 800b3d2: 687b ldr r3, [r7, #4] 800b3d4: 681b ldr r3, [r3, #0] 800b3d6: 689b ldr r3, [r3, #8] 800b3d8: f423 62c0 bic.w r2, r3, #1536 ; 0x600 800b3dc: 687b ldr r3, [r7, #4] 800b3de: 681b ldr r3, [r3, #0] 800b3e0: f442 6280 orr.w r2, r2, #1024 ; 0x400 800b3e4: 609a str r2, [r3, #8] } #if defined(SPI_I2SCFGR_I2SMOD) /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); 800b3e6: 687b ldr r3, [r7, #4] 800b3e8: 681b ldr r3, [r3, #0] 800b3ea: 6d1a ldr r2, [r3, #80] ; 0x50 800b3ec: 687b ldr r3, [r7, #4] 800b3ee: 681b ldr r3, [r3, #0] 800b3f0: f022 0201 bic.w r2, r2, #1 800b3f4: 651a str r2, [r3, #80] ; 0x50 #endif /* SPI_I2SCFGR_I2SMOD */ /* Insure that AFCNTR is managed only by Master */ if ((hspi->Init.Mode & SPI_MODE_MASTER) == SPI_MODE_MASTER) 800b3f6: 687b ldr r3, [r7, #4] 800b3f8: 685b ldr r3, [r3, #4] 800b3fa: f403 0380 and.w r3, r3, #4194304 ; 0x400000 800b3fe: 2b00 cmp r3, #0 800b400: d00a beq.n 800b418 { /* Alternate function GPIOs control */ MODIFY_REG(hspi->Instance->CFG2, SPI_CFG2_AFCNTR, (hspi->Init.MasterKeepIOState)); 800b402: 687b ldr r3, [r7, #4] 800b404: 681b ldr r3, [r3, #0] 800b406: 68db ldr r3, [r3, #12] 800b408: f023 4100 bic.w r1, r3, #2147483648 ; 0x80000000 800b40c: 687b ldr r3, [r7, #4] 800b40e: 6d5a ldr r2, [r3, #84] ; 0x54 800b410: 687b ldr r3, [r7, #4] 800b412: 681b ldr r3, [r3, #0] 800b414: 430a orrs r2, r1 800b416: 60da str r2, [r3, #12] } hspi->ErrorCode = HAL_SPI_ERROR_NONE; 800b418: 687b ldr r3, [r7, #4] 800b41a: 2200 movs r2, #0 800b41c: f8c3 2084 str.w r2, [r3, #132] ; 0x84 hspi->State = HAL_SPI_STATE_READY; 800b420: 687b ldr r3, [r7, #4] 800b422: 2201 movs r2, #1 800b424: f883 2081 strb.w r2, [r3, #129] ; 0x81 return HAL_OK; 800b428: 2300 movs r3, #0 } 800b42a: 4618 mov r0, r3 800b42c: 3710 adds r7, #16 800b42e: 46bd mov sp, r7 800b430: bd80 pop {r7, pc} 800b432: bf00 nop 800b434: 40013000 .word 0x40013000 800b438: 40003800 .word 0x40003800 800b43c: 40003c00 .word 0x40003c00 0800b440 : * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval Packet size occupied in the fifo */ static uint32_t SPI_GetPacketSize(SPI_HandleTypeDef *hspi) { 800b440: b480 push {r7} 800b442: b085 sub sp, #20 800b444: af00 add r7, sp, #0 800b446: 6078 str r0, [r7, #4] uint32_t fifo_threashold = (hspi->Init.FifoThreshold >> SPI_CFG1_FTHLV_Pos) + 1UL; 800b448: 687b ldr r3, [r7, #4] 800b44a: 6bdb ldr r3, [r3, #60] ; 0x3c 800b44c: 095b lsrs r3, r3, #5 800b44e: 3301 adds r3, #1 800b450: 60fb str r3, [r7, #12] uint32_t data_size = (hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) + 1UL; 800b452: 687b ldr r3, [r7, #4] 800b454: 68db ldr r3, [r3, #12] 800b456: 3301 adds r3, #1 800b458: 60bb str r3, [r7, #8] /* Convert data size to Byte */ data_size = (data_size + 7UL) / 8UL; 800b45a: 68bb ldr r3, [r7, #8] 800b45c: 3307 adds r3, #7 800b45e: 08db lsrs r3, r3, #3 800b460: 60bb str r3, [r7, #8] return data_size * fifo_threashold; 800b462: 68bb ldr r3, [r7, #8] 800b464: 68fa ldr r2, [r7, #12] 800b466: fb02 f303 mul.w r3, r2, r3 } 800b46a: 4618 mov r0, r3 800b46c: 3714 adds r7, #20 800b46e: 46bd mov sp, r7 800b470: f85d 7b04 ldr.w r7, [sp], #4 800b474: 4770 bx lr 0800b476 : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 800b476: b580 push {r7, lr} 800b478: b082 sub sp, #8 800b47a: af00 add r7, sp, #0 800b47c: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 800b47e: 687b ldr r3, [r7, #4] 800b480: 2b00 cmp r3, #0 800b482: d101 bne.n 800b488 { return HAL_ERROR; 800b484: 2301 movs r3, #1 800b486: e042 b.n 800b50e { /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); } if (huart->gState == HAL_UART_STATE_RESET) 800b488: 687b ldr r3, [r7, #4] 800b48a: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 800b48e: 2b00 cmp r3, #0 800b490: d106 bne.n 800b4a0 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 800b492: 687b ldr r3, [r7, #4] 800b494: 2200 movs r2, #0 800b496: f883 2080 strb.w r2, [r3, #128] ; 0x80 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 800b49a: 6878 ldr r0, [r7, #4] 800b49c: f7f6 fbe0 bl 8001c60 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 800b4a0: 687b ldr r3, [r7, #4] 800b4a2: 2224 movs r2, #36 ; 0x24 800b4a4: f8c3 2084 str.w r2, [r3, #132] ; 0x84 __HAL_UART_DISABLE(huart); 800b4a8: 687b ldr r3, [r7, #4] 800b4aa: 681b ldr r3, [r3, #0] 800b4ac: 681a ldr r2, [r3, #0] 800b4ae: 687b ldr r3, [r7, #4] 800b4b0: 681b ldr r3, [r3, #0] 800b4b2: f022 0201 bic.w r2, r2, #1 800b4b6: 601a str r2, [r3, #0] /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) 800b4b8: 6878 ldr r0, [r7, #4] 800b4ba: f000 f82d bl 800b518 800b4be: 4603 mov r3, r0 800b4c0: 2b01 cmp r3, #1 800b4c2: d101 bne.n 800b4c8 { return HAL_ERROR; 800b4c4: 2301 movs r3, #1 800b4c6: e022 b.n 800b50e } if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) 800b4c8: 687b ldr r3, [r7, #4] 800b4ca: 6a9b ldr r3, [r3, #40] ; 0x28 800b4cc: 2b00 cmp r3, #0 800b4ce: d002 beq.n 800b4d6 { UART_AdvFeatureConfig(huart); 800b4d0: 6878 ldr r0, [r7, #4] 800b4d2: f000 fe7f bl 800c1d4 } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 800b4d6: 687b ldr r3, [r7, #4] 800b4d8: 681b ldr r3, [r3, #0] 800b4da: 685a ldr r2, [r3, #4] 800b4dc: 687b ldr r3, [r7, #4] 800b4de: 681b ldr r3, [r3, #0] 800b4e0: f422 4290 bic.w r2, r2, #18432 ; 0x4800 800b4e4: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 800b4e6: 687b ldr r3, [r7, #4] 800b4e8: 681b ldr r3, [r3, #0] 800b4ea: 689a ldr r2, [r3, #8] 800b4ec: 687b ldr r3, [r7, #4] 800b4ee: 681b ldr r3, [r3, #0] 800b4f0: f022 022a bic.w r2, r2, #42 ; 0x2a 800b4f4: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); 800b4f6: 687b ldr r3, [r7, #4] 800b4f8: 681b ldr r3, [r3, #0] 800b4fa: 681a ldr r2, [r3, #0] 800b4fc: 687b ldr r3, [r7, #4] 800b4fe: 681b ldr r3, [r3, #0] 800b500: f042 0201 orr.w r2, r2, #1 800b504: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); 800b506: 6878 ldr r0, [r7, #4] 800b508: f000 ff06 bl 800c318 800b50c: 4603 mov r3, r0 } 800b50e: 4618 mov r0, r3 800b510: 3708 adds r7, #8 800b512: 46bd mov sp, r7 800b514: bd80 pop {r7, pc} ... 0800b518 : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { 800b518: b5b0 push {r4, r5, r7, lr} 800b51a: b08e sub sp, #56 ; 0x38 800b51c: af00 add r7, sp, #0 800b51e: 6078 str r0, [r7, #4] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; 800b520: 2300 movs r3, #0 800b522: f887 3032 strb.w r3, [r7, #50] ; 0x32 * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 800b526: 687b ldr r3, [r7, #4] 800b528: 689a ldr r2, [r3, #8] 800b52a: 687b ldr r3, [r7, #4] 800b52c: 691b ldr r3, [r3, #16] 800b52e: 431a orrs r2, r3 800b530: 687b ldr r3, [r7, #4] 800b532: 695b ldr r3, [r3, #20] 800b534: 431a orrs r2, r3 800b536: 687b ldr r3, [r7, #4] 800b538: 69db ldr r3, [r3, #28] 800b53a: 4313 orrs r3, r2 800b53c: 637b str r3, [r7, #52] ; 0x34 MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 800b53e: 687b ldr r3, [r7, #4] 800b540: 681b ldr r3, [r3, #0] 800b542: 681a ldr r2, [r3, #0] 800b544: 4bbf ldr r3, [pc, #764] ; (800b844 ) 800b546: 4013 ands r3, r2 800b548: 687a ldr r2, [r7, #4] 800b54a: 6812 ldr r2, [r2, #0] 800b54c: 6b79 ldr r1, [r7, #52] ; 0x34 800b54e: 430b orrs r3, r1 800b550: 6013 str r3, [r2, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 800b552: 687b ldr r3, [r7, #4] 800b554: 681b ldr r3, [r3, #0] 800b556: 685b ldr r3, [r3, #4] 800b558: f423 5140 bic.w r1, r3, #12288 ; 0x3000 800b55c: 687b ldr r3, [r7, #4] 800b55e: 68da ldr r2, [r3, #12] 800b560: 687b ldr r3, [r7, #4] 800b562: 681b ldr r3, [r3, #0] 800b564: 430a orrs r2, r1 800b566: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; 800b568: 687b ldr r3, [r7, #4] 800b56a: 699b ldr r3, [r3, #24] 800b56c: 637b str r3, [r7, #52] ; 0x34 if (!(UART_INSTANCE_LOWPOWER(huart))) 800b56e: 687b ldr r3, [r7, #4] 800b570: 681b ldr r3, [r3, #0] 800b572: 4ab5 ldr r2, [pc, #724] ; (800b848 ) 800b574: 4293 cmp r3, r2 800b576: d004 beq.n 800b582 { tmpreg |= huart->Init.OneBitSampling; 800b578: 687b ldr r3, [r7, #4] 800b57a: 6a1b ldr r3, [r3, #32] 800b57c: 6b7a ldr r2, [r7, #52] ; 0x34 800b57e: 4313 orrs r3, r2 800b580: 637b str r3, [r7, #52] ; 0x34 } MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); 800b582: 687b ldr r3, [r7, #4] 800b584: 681b ldr r3, [r3, #0] 800b586: 689a ldr r2, [r3, #8] 800b588: 4bb0 ldr r3, [pc, #704] ; (800b84c ) 800b58a: 4013 ands r3, r2 800b58c: 687a ldr r2, [r7, #4] 800b58e: 6812 ldr r2, [r2, #0] 800b590: 6b79 ldr r1, [r7, #52] ; 0x34 800b592: 430b orrs r3, r1 800b594: 6093 str r3, [r2, #8] /*-------------------------- USART PRESC Configuration -----------------------*/ /* Configure * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); 800b596: 687b ldr r3, [r7, #4] 800b598: 681b ldr r3, [r3, #0] 800b59a: 6adb ldr r3, [r3, #44] ; 0x2c 800b59c: f023 010f bic.w r1, r3, #15 800b5a0: 687b ldr r3, [r7, #4] 800b5a2: 6a5a ldr r2, [r3, #36] ; 0x24 800b5a4: 687b ldr r3, [r7, #4] 800b5a6: 681b ldr r3, [r3, #0] 800b5a8: 430a orrs r2, r1 800b5aa: 62da str r2, [r3, #44] ; 0x2c /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); 800b5ac: 687b ldr r3, [r7, #4] 800b5ae: 681b ldr r3, [r3, #0] 800b5b0: 4aa7 ldr r2, [pc, #668] ; (800b850 ) 800b5b2: 4293 cmp r3, r2 800b5b4: d176 bne.n 800b6a4 800b5b6: 4ba7 ldr r3, [pc, #668] ; (800b854 ) 800b5b8: 6d5b ldr r3, [r3, #84] ; 0x54 800b5ba: f003 0338 and.w r3, r3, #56 ; 0x38 800b5be: 2b28 cmp r3, #40 ; 0x28 800b5c0: d86c bhi.n 800b69c 800b5c2: a201 add r2, pc, #4 ; (adr r2, 800b5c8 ) 800b5c4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b5c8: 0800b66d .word 0x0800b66d 800b5cc: 0800b69d .word 0x0800b69d 800b5d0: 0800b69d .word 0x0800b69d 800b5d4: 0800b69d .word 0x0800b69d 800b5d8: 0800b69d .word 0x0800b69d 800b5dc: 0800b69d .word 0x0800b69d 800b5e0: 0800b69d .word 0x0800b69d 800b5e4: 0800b69d .word 0x0800b69d 800b5e8: 0800b675 .word 0x0800b675 800b5ec: 0800b69d .word 0x0800b69d 800b5f0: 0800b69d .word 0x0800b69d 800b5f4: 0800b69d .word 0x0800b69d 800b5f8: 0800b69d .word 0x0800b69d 800b5fc: 0800b69d .word 0x0800b69d 800b600: 0800b69d .word 0x0800b69d 800b604: 0800b69d .word 0x0800b69d 800b608: 0800b67d .word 0x0800b67d 800b60c: 0800b69d .word 0x0800b69d 800b610: 0800b69d .word 0x0800b69d 800b614: 0800b69d .word 0x0800b69d 800b618: 0800b69d .word 0x0800b69d 800b61c: 0800b69d .word 0x0800b69d 800b620: 0800b69d .word 0x0800b69d 800b624: 0800b69d .word 0x0800b69d 800b628: 0800b685 .word 0x0800b685 800b62c: 0800b69d .word 0x0800b69d 800b630: 0800b69d .word 0x0800b69d 800b634: 0800b69d .word 0x0800b69d 800b638: 0800b69d .word 0x0800b69d 800b63c: 0800b69d .word 0x0800b69d 800b640: 0800b69d .word 0x0800b69d 800b644: 0800b69d .word 0x0800b69d 800b648: 0800b68d .word 0x0800b68d 800b64c: 0800b69d .word 0x0800b69d 800b650: 0800b69d .word 0x0800b69d 800b654: 0800b69d .word 0x0800b69d 800b658: 0800b69d .word 0x0800b69d 800b65c: 0800b69d .word 0x0800b69d 800b660: 0800b69d .word 0x0800b69d 800b664: 0800b69d .word 0x0800b69d 800b668: 0800b695 .word 0x0800b695 800b66c: 2301 movs r3, #1 800b66e: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b672: e326 b.n 800bcc2 800b674: 2304 movs r3, #4 800b676: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b67a: e322 b.n 800bcc2 800b67c: 2308 movs r3, #8 800b67e: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b682: e31e b.n 800bcc2 800b684: 2310 movs r3, #16 800b686: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b68a: e31a b.n 800bcc2 800b68c: 2320 movs r3, #32 800b68e: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b692: e316 b.n 800bcc2 800b694: 2340 movs r3, #64 ; 0x40 800b696: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b69a: e312 b.n 800bcc2 800b69c: 2380 movs r3, #128 ; 0x80 800b69e: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b6a2: e30e b.n 800bcc2 800b6a4: 687b ldr r3, [r7, #4] 800b6a6: 681b ldr r3, [r3, #0] 800b6a8: 4a6b ldr r2, [pc, #428] ; (800b858 ) 800b6aa: 4293 cmp r3, r2 800b6ac: d130 bne.n 800b710 800b6ae: 4b69 ldr r3, [pc, #420] ; (800b854 ) 800b6b0: 6d5b ldr r3, [r3, #84] ; 0x54 800b6b2: f003 0307 and.w r3, r3, #7 800b6b6: 2b05 cmp r3, #5 800b6b8: d826 bhi.n 800b708 800b6ba: a201 add r2, pc, #4 ; (adr r2, 800b6c0 ) 800b6bc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b6c0: 0800b6d9 .word 0x0800b6d9 800b6c4: 0800b6e1 .word 0x0800b6e1 800b6c8: 0800b6e9 .word 0x0800b6e9 800b6cc: 0800b6f1 .word 0x0800b6f1 800b6d0: 0800b6f9 .word 0x0800b6f9 800b6d4: 0800b701 .word 0x0800b701 800b6d8: 2300 movs r3, #0 800b6da: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b6de: e2f0 b.n 800bcc2 800b6e0: 2304 movs r3, #4 800b6e2: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b6e6: e2ec b.n 800bcc2 800b6e8: 2308 movs r3, #8 800b6ea: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b6ee: e2e8 b.n 800bcc2 800b6f0: 2310 movs r3, #16 800b6f2: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b6f6: e2e4 b.n 800bcc2 800b6f8: 2320 movs r3, #32 800b6fa: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b6fe: e2e0 b.n 800bcc2 800b700: 2340 movs r3, #64 ; 0x40 800b702: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b706: e2dc b.n 800bcc2 800b708: 2380 movs r3, #128 ; 0x80 800b70a: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b70e: e2d8 b.n 800bcc2 800b710: 687b ldr r3, [r7, #4] 800b712: 681b ldr r3, [r3, #0] 800b714: 4a51 ldr r2, [pc, #324] ; (800b85c ) 800b716: 4293 cmp r3, r2 800b718: d130 bne.n 800b77c 800b71a: 4b4e ldr r3, [pc, #312] ; (800b854 ) 800b71c: 6d5b ldr r3, [r3, #84] ; 0x54 800b71e: f003 0307 and.w r3, r3, #7 800b722: 2b05 cmp r3, #5 800b724: d826 bhi.n 800b774 800b726: a201 add r2, pc, #4 ; (adr r2, 800b72c ) 800b728: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b72c: 0800b745 .word 0x0800b745 800b730: 0800b74d .word 0x0800b74d 800b734: 0800b755 .word 0x0800b755 800b738: 0800b75d .word 0x0800b75d 800b73c: 0800b765 .word 0x0800b765 800b740: 0800b76d .word 0x0800b76d 800b744: 2300 movs r3, #0 800b746: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b74a: e2ba b.n 800bcc2 800b74c: 2304 movs r3, #4 800b74e: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b752: e2b6 b.n 800bcc2 800b754: 2308 movs r3, #8 800b756: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b75a: e2b2 b.n 800bcc2 800b75c: 2310 movs r3, #16 800b75e: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b762: e2ae b.n 800bcc2 800b764: 2320 movs r3, #32 800b766: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b76a: e2aa b.n 800bcc2 800b76c: 2340 movs r3, #64 ; 0x40 800b76e: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b772: e2a6 b.n 800bcc2 800b774: 2380 movs r3, #128 ; 0x80 800b776: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b77a: e2a2 b.n 800bcc2 800b77c: 687b ldr r3, [r7, #4] 800b77e: 681b ldr r3, [r3, #0] 800b780: 4a37 ldr r2, [pc, #220] ; (800b860 ) 800b782: 4293 cmp r3, r2 800b784: d130 bne.n 800b7e8 800b786: 4b33 ldr r3, [pc, #204] ; (800b854 ) 800b788: 6d5b ldr r3, [r3, #84] ; 0x54 800b78a: f003 0307 and.w r3, r3, #7 800b78e: 2b05 cmp r3, #5 800b790: d826 bhi.n 800b7e0 800b792: a201 add r2, pc, #4 ; (adr r2, 800b798 ) 800b794: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b798: 0800b7b1 .word 0x0800b7b1 800b79c: 0800b7b9 .word 0x0800b7b9 800b7a0: 0800b7c1 .word 0x0800b7c1 800b7a4: 0800b7c9 .word 0x0800b7c9 800b7a8: 0800b7d1 .word 0x0800b7d1 800b7ac: 0800b7d9 .word 0x0800b7d9 800b7b0: 2300 movs r3, #0 800b7b2: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b7b6: e284 b.n 800bcc2 800b7b8: 2304 movs r3, #4 800b7ba: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b7be: e280 b.n 800bcc2 800b7c0: 2308 movs r3, #8 800b7c2: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b7c6: e27c b.n 800bcc2 800b7c8: 2310 movs r3, #16 800b7ca: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b7ce: e278 b.n 800bcc2 800b7d0: 2320 movs r3, #32 800b7d2: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b7d6: e274 b.n 800bcc2 800b7d8: 2340 movs r3, #64 ; 0x40 800b7da: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b7de: e270 b.n 800bcc2 800b7e0: 2380 movs r3, #128 ; 0x80 800b7e2: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b7e6: e26c b.n 800bcc2 800b7e8: 687b ldr r3, [r7, #4] 800b7ea: 681b ldr r3, [r3, #0] 800b7ec: 4a1d ldr r2, [pc, #116] ; (800b864 ) 800b7ee: 4293 cmp r3, r2 800b7f0: d142 bne.n 800b878 800b7f2: 4b18 ldr r3, [pc, #96] ; (800b854 ) 800b7f4: 6d5b ldr r3, [r3, #84] ; 0x54 800b7f6: f003 0307 and.w r3, r3, #7 800b7fa: 2b05 cmp r3, #5 800b7fc: d838 bhi.n 800b870 800b7fe: a201 add r2, pc, #4 ; (adr r2, 800b804 ) 800b800: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b804: 0800b81d .word 0x0800b81d 800b808: 0800b825 .word 0x0800b825 800b80c: 0800b82d .word 0x0800b82d 800b810: 0800b835 .word 0x0800b835 800b814: 0800b83d .word 0x0800b83d 800b818: 0800b869 .word 0x0800b869 800b81c: 2300 movs r3, #0 800b81e: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b822: e24e b.n 800bcc2 800b824: 2304 movs r3, #4 800b826: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b82a: e24a b.n 800bcc2 800b82c: 2308 movs r3, #8 800b82e: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b832: e246 b.n 800bcc2 800b834: 2310 movs r3, #16 800b836: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b83a: e242 b.n 800bcc2 800b83c: 2320 movs r3, #32 800b83e: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b842: e23e b.n 800bcc2 800b844: cfff69f3 .word 0xcfff69f3 800b848: 58000c00 .word 0x58000c00 800b84c: 11fff4ff .word 0x11fff4ff 800b850: 40011000 .word 0x40011000 800b854: 58024400 .word 0x58024400 800b858: 40004400 .word 0x40004400 800b85c: 40004800 .word 0x40004800 800b860: 40004c00 .word 0x40004c00 800b864: 40005000 .word 0x40005000 800b868: 2340 movs r3, #64 ; 0x40 800b86a: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b86e: e228 b.n 800bcc2 800b870: 2380 movs r3, #128 ; 0x80 800b872: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b876: e224 b.n 800bcc2 800b878: 687b ldr r3, [r7, #4] 800b87a: 681b ldr r3, [r3, #0] 800b87c: 4ab1 ldr r2, [pc, #708] ; (800bb44 ) 800b87e: 4293 cmp r3, r2 800b880: d176 bne.n 800b970 800b882: 4bb1 ldr r3, [pc, #708] ; (800bb48 ) 800b884: 6d5b ldr r3, [r3, #84] ; 0x54 800b886: f003 0338 and.w r3, r3, #56 ; 0x38 800b88a: 2b28 cmp r3, #40 ; 0x28 800b88c: d86c bhi.n 800b968 800b88e: a201 add r2, pc, #4 ; (adr r2, 800b894 ) 800b890: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b894: 0800b939 .word 0x0800b939 800b898: 0800b969 .word 0x0800b969 800b89c: 0800b969 .word 0x0800b969 800b8a0: 0800b969 .word 0x0800b969 800b8a4: 0800b969 .word 0x0800b969 800b8a8: 0800b969 .word 0x0800b969 800b8ac: 0800b969 .word 0x0800b969 800b8b0: 0800b969 .word 0x0800b969 800b8b4: 0800b941 .word 0x0800b941 800b8b8: 0800b969 .word 0x0800b969 800b8bc: 0800b969 .word 0x0800b969 800b8c0: 0800b969 .word 0x0800b969 800b8c4: 0800b969 .word 0x0800b969 800b8c8: 0800b969 .word 0x0800b969 800b8cc: 0800b969 .word 0x0800b969 800b8d0: 0800b969 .word 0x0800b969 800b8d4: 0800b949 .word 0x0800b949 800b8d8: 0800b969 .word 0x0800b969 800b8dc: 0800b969 .word 0x0800b969 800b8e0: 0800b969 .word 0x0800b969 800b8e4: 0800b969 .word 0x0800b969 800b8e8: 0800b969 .word 0x0800b969 800b8ec: 0800b969 .word 0x0800b969 800b8f0: 0800b969 .word 0x0800b969 800b8f4: 0800b951 .word 0x0800b951 800b8f8: 0800b969 .word 0x0800b969 800b8fc: 0800b969 .word 0x0800b969 800b900: 0800b969 .word 0x0800b969 800b904: 0800b969 .word 0x0800b969 800b908: 0800b969 .word 0x0800b969 800b90c: 0800b969 .word 0x0800b969 800b910: 0800b969 .word 0x0800b969 800b914: 0800b959 .word 0x0800b959 800b918: 0800b969 .word 0x0800b969 800b91c: 0800b969 .word 0x0800b969 800b920: 0800b969 .word 0x0800b969 800b924: 0800b969 .word 0x0800b969 800b928: 0800b969 .word 0x0800b969 800b92c: 0800b969 .word 0x0800b969 800b930: 0800b969 .word 0x0800b969 800b934: 0800b961 .word 0x0800b961 800b938: 2301 movs r3, #1 800b93a: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b93e: e1c0 b.n 800bcc2 800b940: 2304 movs r3, #4 800b942: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b946: e1bc b.n 800bcc2 800b948: 2308 movs r3, #8 800b94a: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b94e: e1b8 b.n 800bcc2 800b950: 2310 movs r3, #16 800b952: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b956: e1b4 b.n 800bcc2 800b958: 2320 movs r3, #32 800b95a: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b95e: e1b0 b.n 800bcc2 800b960: 2340 movs r3, #64 ; 0x40 800b962: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b966: e1ac b.n 800bcc2 800b968: 2380 movs r3, #128 ; 0x80 800b96a: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b96e: e1a8 b.n 800bcc2 800b970: 687b ldr r3, [r7, #4] 800b972: 681b ldr r3, [r3, #0] 800b974: 4a75 ldr r2, [pc, #468] ; (800bb4c ) 800b976: 4293 cmp r3, r2 800b978: d130 bne.n 800b9dc 800b97a: 4b73 ldr r3, [pc, #460] ; (800bb48 ) 800b97c: 6d5b ldr r3, [r3, #84] ; 0x54 800b97e: f003 0307 and.w r3, r3, #7 800b982: 2b05 cmp r3, #5 800b984: d826 bhi.n 800b9d4 800b986: a201 add r2, pc, #4 ; (adr r2, 800b98c ) 800b988: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b98c: 0800b9a5 .word 0x0800b9a5 800b990: 0800b9ad .word 0x0800b9ad 800b994: 0800b9b5 .word 0x0800b9b5 800b998: 0800b9bd .word 0x0800b9bd 800b99c: 0800b9c5 .word 0x0800b9c5 800b9a0: 0800b9cd .word 0x0800b9cd 800b9a4: 2300 movs r3, #0 800b9a6: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b9aa: e18a b.n 800bcc2 800b9ac: 2304 movs r3, #4 800b9ae: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b9b2: e186 b.n 800bcc2 800b9b4: 2308 movs r3, #8 800b9b6: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b9ba: e182 b.n 800bcc2 800b9bc: 2310 movs r3, #16 800b9be: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b9c2: e17e b.n 800bcc2 800b9c4: 2320 movs r3, #32 800b9c6: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b9ca: e17a b.n 800bcc2 800b9cc: 2340 movs r3, #64 ; 0x40 800b9ce: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b9d2: e176 b.n 800bcc2 800b9d4: 2380 movs r3, #128 ; 0x80 800b9d6: f887 3033 strb.w r3, [r7, #51] ; 0x33 800b9da: e172 b.n 800bcc2 800b9dc: 687b ldr r3, [r7, #4] 800b9de: 681b ldr r3, [r3, #0] 800b9e0: 4a5b ldr r2, [pc, #364] ; (800bb50 ) 800b9e2: 4293 cmp r3, r2 800b9e4: d130 bne.n 800ba48 800b9e6: 4b58 ldr r3, [pc, #352] ; (800bb48 ) 800b9e8: 6d5b ldr r3, [r3, #84] ; 0x54 800b9ea: f003 0307 and.w r3, r3, #7 800b9ee: 2b05 cmp r3, #5 800b9f0: d826 bhi.n 800ba40 800b9f2: a201 add r2, pc, #4 ; (adr r2, 800b9f8 ) 800b9f4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b9f8: 0800ba11 .word 0x0800ba11 800b9fc: 0800ba19 .word 0x0800ba19 800ba00: 0800ba21 .word 0x0800ba21 800ba04: 0800ba29 .word 0x0800ba29 800ba08: 0800ba31 .word 0x0800ba31 800ba0c: 0800ba39 .word 0x0800ba39 800ba10: 2300 movs r3, #0 800ba12: f887 3033 strb.w r3, [r7, #51] ; 0x33 800ba16: e154 b.n 800bcc2 800ba18: 2304 movs r3, #4 800ba1a: f887 3033 strb.w r3, [r7, #51] ; 0x33 800ba1e: e150 b.n 800bcc2 800ba20: 2308 movs r3, #8 800ba22: f887 3033 strb.w r3, [r7, #51] ; 0x33 800ba26: e14c b.n 800bcc2 800ba28: 2310 movs r3, #16 800ba2a: f887 3033 strb.w r3, [r7, #51] ; 0x33 800ba2e: e148 b.n 800bcc2 800ba30: 2320 movs r3, #32 800ba32: f887 3033 strb.w r3, [r7, #51] ; 0x33 800ba36: e144 b.n 800bcc2 800ba38: 2340 movs r3, #64 ; 0x40 800ba3a: f887 3033 strb.w r3, [r7, #51] ; 0x33 800ba3e: e140 b.n 800bcc2 800ba40: 2380 movs r3, #128 ; 0x80 800ba42: f887 3033 strb.w r3, [r7, #51] ; 0x33 800ba46: e13c b.n 800bcc2 800ba48: 687b ldr r3, [r7, #4] 800ba4a: 681b ldr r3, [r3, #0] 800ba4c: 4a41 ldr r2, [pc, #260] ; (800bb54 ) 800ba4e: 4293 cmp r3, r2 800ba50: f040 8082 bne.w 800bb58 800ba54: 4b3c ldr r3, [pc, #240] ; (800bb48 ) 800ba56: 6d5b ldr r3, [r3, #84] ; 0x54 800ba58: f003 0338 and.w r3, r3, #56 ; 0x38 800ba5c: 2b28 cmp r3, #40 ; 0x28 800ba5e: d86d bhi.n 800bb3c 800ba60: a201 add r2, pc, #4 ; (adr r2, 800ba68 ) 800ba62: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800ba66: bf00 nop 800ba68: 0800bb0d .word 0x0800bb0d 800ba6c: 0800bb3d .word 0x0800bb3d 800ba70: 0800bb3d .word 0x0800bb3d 800ba74: 0800bb3d .word 0x0800bb3d 800ba78: 0800bb3d .word 0x0800bb3d 800ba7c: 0800bb3d .word 0x0800bb3d 800ba80: 0800bb3d .word 0x0800bb3d 800ba84: 0800bb3d .word 0x0800bb3d 800ba88: 0800bb15 .word 0x0800bb15 800ba8c: 0800bb3d .word 0x0800bb3d 800ba90: 0800bb3d .word 0x0800bb3d 800ba94: 0800bb3d .word 0x0800bb3d 800ba98: 0800bb3d .word 0x0800bb3d 800ba9c: 0800bb3d .word 0x0800bb3d 800baa0: 0800bb3d .word 0x0800bb3d 800baa4: 0800bb3d .word 0x0800bb3d 800baa8: 0800bb1d .word 0x0800bb1d 800baac: 0800bb3d .word 0x0800bb3d 800bab0: 0800bb3d .word 0x0800bb3d 800bab4: 0800bb3d .word 0x0800bb3d 800bab8: 0800bb3d .word 0x0800bb3d 800babc: 0800bb3d .word 0x0800bb3d 800bac0: 0800bb3d .word 0x0800bb3d 800bac4: 0800bb3d .word 0x0800bb3d 800bac8: 0800bb25 .word 0x0800bb25 800bacc: 0800bb3d .word 0x0800bb3d 800bad0: 0800bb3d .word 0x0800bb3d 800bad4: 0800bb3d .word 0x0800bb3d 800bad8: 0800bb3d .word 0x0800bb3d 800badc: 0800bb3d .word 0x0800bb3d 800bae0: 0800bb3d .word 0x0800bb3d 800bae4: 0800bb3d .word 0x0800bb3d 800bae8: 0800bb2d .word 0x0800bb2d 800baec: 0800bb3d .word 0x0800bb3d 800baf0: 0800bb3d .word 0x0800bb3d 800baf4: 0800bb3d .word 0x0800bb3d 800baf8: 0800bb3d .word 0x0800bb3d 800bafc: 0800bb3d .word 0x0800bb3d 800bb00: 0800bb3d .word 0x0800bb3d 800bb04: 0800bb3d .word 0x0800bb3d 800bb08: 0800bb35 .word 0x0800bb35 800bb0c: 2301 movs r3, #1 800bb0e: f887 3033 strb.w r3, [r7, #51] ; 0x33 800bb12: e0d6 b.n 800bcc2 800bb14: 2304 movs r3, #4 800bb16: f887 3033 strb.w r3, [r7, #51] ; 0x33 800bb1a: e0d2 b.n 800bcc2 800bb1c: 2308 movs r3, #8 800bb1e: f887 3033 strb.w r3, [r7, #51] ; 0x33 800bb22: e0ce b.n 800bcc2 800bb24: 2310 movs r3, #16 800bb26: f887 3033 strb.w r3, [r7, #51] ; 0x33 800bb2a: e0ca b.n 800bcc2 800bb2c: 2320 movs r3, #32 800bb2e: f887 3033 strb.w r3, [r7, #51] ; 0x33 800bb32: e0c6 b.n 800bcc2 800bb34: 2340 movs r3, #64 ; 0x40 800bb36: f887 3033 strb.w r3, [r7, #51] ; 0x33 800bb3a: e0c2 b.n 800bcc2 800bb3c: 2380 movs r3, #128 ; 0x80 800bb3e: f887 3033 strb.w r3, [r7, #51] ; 0x33 800bb42: e0be b.n 800bcc2 800bb44: 40011400 .word 0x40011400 800bb48: 58024400 .word 0x58024400 800bb4c: 40007800 .word 0x40007800 800bb50: 40007c00 .word 0x40007c00 800bb54: 40011800 .word 0x40011800 800bb58: 687b ldr r3, [r7, #4] 800bb5a: 681b ldr r3, [r3, #0] 800bb5c: 4aad ldr r2, [pc, #692] ; (800be14 ) 800bb5e: 4293 cmp r3, r2 800bb60: d176 bne.n 800bc50 800bb62: 4bad ldr r3, [pc, #692] ; (800be18 ) 800bb64: 6d5b ldr r3, [r3, #84] ; 0x54 800bb66: f003 0338 and.w r3, r3, #56 ; 0x38 800bb6a: 2b28 cmp r3, #40 ; 0x28 800bb6c: d86c bhi.n 800bc48 800bb6e: a201 add r2, pc, #4 ; (adr r2, 800bb74 ) 800bb70: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800bb74: 0800bc19 .word 0x0800bc19 800bb78: 0800bc49 .word 0x0800bc49 800bb7c: 0800bc49 .word 0x0800bc49 800bb80: 0800bc49 .word 0x0800bc49 800bb84: 0800bc49 .word 0x0800bc49 800bb88: 0800bc49 .word 0x0800bc49 800bb8c: 0800bc49 .word 0x0800bc49 800bb90: 0800bc49 .word 0x0800bc49 800bb94: 0800bc21 .word 0x0800bc21 800bb98: 0800bc49 .word 0x0800bc49 800bb9c: 0800bc49 .word 0x0800bc49 800bba0: 0800bc49 .word 0x0800bc49 800bba4: 0800bc49 .word 0x0800bc49 800bba8: 0800bc49 .word 0x0800bc49 800bbac: 0800bc49 .word 0x0800bc49 800bbb0: 0800bc49 .word 0x0800bc49 800bbb4: 0800bc29 .word 0x0800bc29 800bbb8: 0800bc49 .word 0x0800bc49 800bbbc: 0800bc49 .word 0x0800bc49 800bbc0: 0800bc49 .word 0x0800bc49 800bbc4: 0800bc49 .word 0x0800bc49 800bbc8: 0800bc49 .word 0x0800bc49 800bbcc: 0800bc49 .word 0x0800bc49 800bbd0: 0800bc49 .word 0x0800bc49 800bbd4: 0800bc31 .word 0x0800bc31 800bbd8: 0800bc49 .word 0x0800bc49 800bbdc: 0800bc49 .word 0x0800bc49 800bbe0: 0800bc49 .word 0x0800bc49 800bbe4: 0800bc49 .word 0x0800bc49 800bbe8: 0800bc49 .word 0x0800bc49 800bbec: 0800bc49 .word 0x0800bc49 800bbf0: 0800bc49 .word 0x0800bc49 800bbf4: 0800bc39 .word 0x0800bc39 800bbf8: 0800bc49 .word 0x0800bc49 800bbfc: 0800bc49 .word 0x0800bc49 800bc00: 0800bc49 .word 0x0800bc49 800bc04: 0800bc49 .word 0x0800bc49 800bc08: 0800bc49 .word 0x0800bc49 800bc0c: 0800bc49 .word 0x0800bc49 800bc10: 0800bc49 .word 0x0800bc49 800bc14: 0800bc41 .word 0x0800bc41 800bc18: 2301 movs r3, #1 800bc1a: f887 3033 strb.w r3, [r7, #51] ; 0x33 800bc1e: e050 b.n 800bcc2 800bc20: 2304 movs r3, #4 800bc22: f887 3033 strb.w r3, [r7, #51] ; 0x33 800bc26: e04c b.n 800bcc2 800bc28: 2308 movs r3, #8 800bc2a: f887 3033 strb.w r3, [r7, #51] ; 0x33 800bc2e: e048 b.n 800bcc2 800bc30: 2310 movs r3, #16 800bc32: f887 3033 strb.w r3, [r7, #51] ; 0x33 800bc36: e044 b.n 800bcc2 800bc38: 2320 movs r3, #32 800bc3a: f887 3033 strb.w r3, [r7, #51] ; 0x33 800bc3e: e040 b.n 800bcc2 800bc40: 2340 movs r3, #64 ; 0x40 800bc42: f887 3033 strb.w r3, [r7, #51] ; 0x33 800bc46: e03c b.n 800bcc2 800bc48: 2380 movs r3, #128 ; 0x80 800bc4a: f887 3033 strb.w r3, [r7, #51] ; 0x33 800bc4e: e038 b.n 800bcc2 800bc50: 687b ldr r3, [r7, #4] 800bc52: 681b ldr r3, [r3, #0] 800bc54: 4a71 ldr r2, [pc, #452] ; (800be1c ) 800bc56: 4293 cmp r3, r2 800bc58: d130 bne.n 800bcbc 800bc5a: 4b6f ldr r3, [pc, #444] ; (800be18 ) 800bc5c: 6d9b ldr r3, [r3, #88] ; 0x58 800bc5e: f003 0307 and.w r3, r3, #7 800bc62: 2b05 cmp r3, #5 800bc64: d826 bhi.n 800bcb4 800bc66: a201 add r2, pc, #4 ; (adr r2, 800bc6c ) 800bc68: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800bc6c: 0800bc85 .word 0x0800bc85 800bc70: 0800bc8d .word 0x0800bc8d 800bc74: 0800bc95 .word 0x0800bc95 800bc78: 0800bc9d .word 0x0800bc9d 800bc7c: 0800bca5 .word 0x0800bca5 800bc80: 0800bcad .word 0x0800bcad 800bc84: 2302 movs r3, #2 800bc86: f887 3033 strb.w r3, [r7, #51] ; 0x33 800bc8a: e01a b.n 800bcc2 800bc8c: 2304 movs r3, #4 800bc8e: f887 3033 strb.w r3, [r7, #51] ; 0x33 800bc92: e016 b.n 800bcc2 800bc94: 2308 movs r3, #8 800bc96: f887 3033 strb.w r3, [r7, #51] ; 0x33 800bc9a: e012 b.n 800bcc2 800bc9c: 2310 movs r3, #16 800bc9e: f887 3033 strb.w r3, [r7, #51] ; 0x33 800bca2: e00e b.n 800bcc2 800bca4: 2320 movs r3, #32 800bca6: f887 3033 strb.w r3, [r7, #51] ; 0x33 800bcaa: e00a b.n 800bcc2 800bcac: 2340 movs r3, #64 ; 0x40 800bcae: f887 3033 strb.w r3, [r7, #51] ; 0x33 800bcb2: e006 b.n 800bcc2 800bcb4: 2380 movs r3, #128 ; 0x80 800bcb6: f887 3033 strb.w r3, [r7, #51] ; 0x33 800bcba: e002 b.n 800bcc2 800bcbc: 2380 movs r3, #128 ; 0x80 800bcbe: f887 3033 strb.w r3, [r7, #51] ; 0x33 /* Check LPUART instance */ if (UART_INSTANCE_LOWPOWER(huart)) 800bcc2: 687b ldr r3, [r7, #4] 800bcc4: 681b ldr r3, [r3, #0] 800bcc6: 4a55 ldr r2, [pc, #340] ; (800be1c ) 800bcc8: 4293 cmp r3, r2 800bcca: f040 80f0 bne.w 800beae { /* Retrieve frequency clock */ switch (clocksource) 800bcce: f897 3033 ldrb.w r3, [r7, #51] ; 0x33 800bcd2: 2b20 cmp r3, #32 800bcd4: dc46 bgt.n 800bd64 800bcd6: 2b02 cmp r3, #2 800bcd8: db75 blt.n 800bdc6 800bcda: 3b02 subs r3, #2 800bcdc: 2b1e cmp r3, #30 800bcde: d872 bhi.n 800bdc6 800bce0: a201 add r2, pc, #4 ; (adr r2, 800bce8 ) 800bce2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800bce6: bf00 nop 800bce8: 0800bd6b .word 0x0800bd6b 800bcec: 0800bdc7 .word 0x0800bdc7 800bcf0: 0800bd73 .word 0x0800bd73 800bcf4: 0800bdc7 .word 0x0800bdc7 800bcf8: 0800bdc7 .word 0x0800bdc7 800bcfc: 0800bdc7 .word 0x0800bdc7 800bd00: 0800bd83 .word 0x0800bd83 800bd04: 0800bdc7 .word 0x0800bdc7 800bd08: 0800bdc7 .word 0x0800bdc7 800bd0c: 0800bdc7 .word 0x0800bdc7 800bd10: 0800bdc7 .word 0x0800bdc7 800bd14: 0800bdc7 .word 0x0800bdc7 800bd18: 0800bdc7 .word 0x0800bdc7 800bd1c: 0800bdc7 .word 0x0800bdc7 800bd20: 0800bd93 .word 0x0800bd93 800bd24: 0800bdc7 .word 0x0800bdc7 800bd28: 0800bdc7 .word 0x0800bdc7 800bd2c: 0800bdc7 .word 0x0800bdc7 800bd30: 0800bdc7 .word 0x0800bdc7 800bd34: 0800bdc7 .word 0x0800bdc7 800bd38: 0800bdc7 .word 0x0800bdc7 800bd3c: 0800bdc7 .word 0x0800bdc7 800bd40: 0800bdc7 .word 0x0800bdc7 800bd44: 0800bdc7 .word 0x0800bdc7 800bd48: 0800bdc7 .word 0x0800bdc7 800bd4c: 0800bdc7 .word 0x0800bdc7 800bd50: 0800bdc7 .word 0x0800bdc7 800bd54: 0800bdc7 .word 0x0800bdc7 800bd58: 0800bdc7 .word 0x0800bdc7 800bd5c: 0800bdc7 .word 0x0800bdc7 800bd60: 0800bdb9 .word 0x0800bdb9 800bd64: 2b40 cmp r3, #64 ; 0x40 800bd66: d02a beq.n 800bdbe 800bd68: e02d b.n 800bdc6 { case UART_CLOCKSOURCE_D3PCLK1: pclk = HAL_RCCEx_GetD3PCLK1Freq(); 800bd6a: f7fc fee7 bl 8008b3c 800bd6e: 62f8 str r0, [r7, #44] ; 0x2c break; 800bd70: e02f b.n 800bdd2 case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800bd72: f107 0314 add.w r3, r7, #20 800bd76: 4618 mov r0, r3 800bd78: f7fc fef6 bl 8008b68 pclk = pll2_clocks.PLL2_Q_Frequency; 800bd7c: 69bb ldr r3, [r7, #24] 800bd7e: 62fb str r3, [r7, #44] ; 0x2c break; 800bd80: e027 b.n 800bdd2 case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800bd82: f107 0308 add.w r3, r7, #8 800bd86: 4618 mov r0, r3 800bd88: f7fd f842 bl 8008e10 pclk = pll3_clocks.PLL3_Q_Frequency; 800bd8c: 68fb ldr r3, [r7, #12] 800bd8e: 62fb str r3, [r7, #44] ; 0x2c break; 800bd90: e01f b.n 800bdd2 case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800bd92: 4b21 ldr r3, [pc, #132] ; (800be18 ) 800bd94: 681b ldr r3, [r3, #0] 800bd96: f003 0320 and.w r3, r3, #32 800bd9a: 2b00 cmp r3, #0 800bd9c: d009 beq.n 800bdb2 { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 800bd9e: 4b1e ldr r3, [pc, #120] ; (800be18 ) 800bda0: 681b ldr r3, [r3, #0] 800bda2: 08db lsrs r3, r3, #3 800bda4: f003 0303 and.w r3, r3, #3 800bda8: 4a1d ldr r2, [pc, #116] ; (800be20 ) 800bdaa: fa22 f303 lsr.w r3, r2, r3 800bdae: 62fb str r3, [r7, #44] ; 0x2c } else { pclk = (uint32_t) HSI_VALUE; } break; 800bdb0: e00f b.n 800bdd2 pclk = (uint32_t) HSI_VALUE; 800bdb2: 4b1b ldr r3, [pc, #108] ; (800be20 ) 800bdb4: 62fb str r3, [r7, #44] ; 0x2c break; 800bdb6: e00c b.n 800bdd2 case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 800bdb8: 4b1a ldr r3, [pc, #104] ; (800be24 ) 800bdba: 62fb str r3, [r7, #44] ; 0x2c break; 800bdbc: e009 b.n 800bdd2 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 800bdbe: f44f 4300 mov.w r3, #32768 ; 0x8000 800bdc2: 62fb str r3, [r7, #44] ; 0x2c break; 800bdc4: e005 b.n 800bdd2 default: pclk = 0U; 800bdc6: 2300 movs r3, #0 800bdc8: 62fb str r3, [r7, #44] ; 0x2c ret = HAL_ERROR; 800bdca: 2301 movs r3, #1 800bdcc: f887 3032 strb.w r3, [r7, #50] ; 0x32 break; 800bdd0: bf00 nop } /* If proper clock source reported */ if (pclk != 0U) 800bdd2: 6afb ldr r3, [r7, #44] ; 0x2c 800bdd4: 2b00 cmp r3, #0 800bdd6: f000 81e6 beq.w 800c1a6 { /* Compute clock after Prescaler */ lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); 800bdda: 687b ldr r3, [r7, #4] 800bddc: 6a5b ldr r3, [r3, #36] ; 0x24 800bdde: 4a12 ldr r2, [pc, #72] ; (800be28 ) 800bde0: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 800bde4: 461a mov r2, r3 800bde6: 6afb ldr r3, [r7, #44] ; 0x2c 800bde8: fbb3 f3f2 udiv r3, r3, r2 800bdec: 623b str r3, [r7, #32] /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 800bdee: 687b ldr r3, [r7, #4] 800bdf0: 685a ldr r2, [r3, #4] 800bdf2: 4613 mov r3, r2 800bdf4: 005b lsls r3, r3, #1 800bdf6: 4413 add r3, r2 800bdf8: 6a3a ldr r2, [r7, #32] 800bdfa: 429a cmp r2, r3 800bdfc: d305 bcc.n 800be0a (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) 800bdfe: 687b ldr r3, [r7, #4] 800be00: 685b ldr r3, [r3, #4] 800be02: 031b lsls r3, r3, #12 if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 800be04: 6a3a ldr r2, [r7, #32] 800be06: 429a cmp r2, r3 800be08: d910 bls.n 800be2c { ret = HAL_ERROR; 800be0a: 2301 movs r3, #1 800be0c: f887 3032 strb.w r3, [r7, #50] ; 0x32 800be10: e1c9 b.n 800c1a6 800be12: bf00 nop 800be14: 40011c00 .word 0x40011c00 800be18: 58024400 .word 0x58024400 800be1c: 58000c00 .word 0x58000c00 800be20: 03d09000 .word 0x03d09000 800be24: 003d0900 .word 0x003d0900 800be28: 0800e664 .word 0x0800e664 } else { /* Check computed UsartDiv value is in allocated range (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 800be2c: 6afb ldr r3, [r7, #44] ; 0x2c 800be2e: 4618 mov r0, r3 800be30: f04f 0100 mov.w r1, #0 800be34: 687b ldr r3, [r7, #4] 800be36: 6a5b ldr r3, [r3, #36] ; 0x24 800be38: 4ac1 ldr r2, [pc, #772] ; (800c140 ) 800be3a: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 800be3e: b29a uxth r2, r3 800be40: f04f 0300 mov.w r3, #0 800be44: f7f4 fa52 bl 80002ec <__aeabi_uldivmod> 800be48: 4602 mov r2, r0 800be4a: 460b mov r3, r1 800be4c: 4610 mov r0, r2 800be4e: 4619 mov r1, r3 800be50: f04f 0200 mov.w r2, #0 800be54: f04f 0300 mov.w r3, #0 800be58: 020b lsls r3, r1, #8 800be5a: ea43 6310 orr.w r3, r3, r0, lsr #24 800be5e: 0202 lsls r2, r0, #8 800be60: 6879 ldr r1, [r7, #4] 800be62: 6849 ldr r1, [r1, #4] 800be64: 0849 lsrs r1, r1, #1 800be66: 4608 mov r0, r1 800be68: f04f 0100 mov.w r1, #0 800be6c: 1814 adds r4, r2, r0 800be6e: eb43 0501 adc.w r5, r3, r1 800be72: 687b ldr r3, [r7, #4] 800be74: 685b ldr r3, [r3, #4] 800be76: 461a mov r2, r3 800be78: f04f 0300 mov.w r3, #0 800be7c: 4620 mov r0, r4 800be7e: 4629 mov r1, r5 800be80: f7f4 fa34 bl 80002ec <__aeabi_uldivmod> 800be84: 4602 mov r2, r0 800be86: 460b mov r3, r1 800be88: 4613 mov r3, r2 800be8a: 62bb str r3, [r7, #40] ; 0x28 if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) 800be8c: 6abb ldr r3, [r7, #40] ; 0x28 800be8e: f5b3 7f40 cmp.w r3, #768 ; 0x300 800be92: d308 bcc.n 800bea6 800be94: 6abb ldr r3, [r7, #40] ; 0x28 800be96: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 800be9a: d204 bcs.n 800bea6 { huart->Instance->BRR = usartdiv; 800be9c: 687b ldr r3, [r7, #4] 800be9e: 681b ldr r3, [r3, #0] 800bea0: 6aba ldr r2, [r7, #40] ; 0x28 800bea2: 60da str r2, [r3, #12] 800bea4: e17f b.n 800c1a6 } else { ret = HAL_ERROR; 800bea6: 2301 movs r3, #1 800bea8: f887 3032 strb.w r3, [r7, #50] ; 0x32 800beac: e17b b.n 800c1a6 } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 800beae: 687b ldr r3, [r7, #4] 800beb0: 69db ldr r3, [r3, #28] 800beb2: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 800beb6: f040 80bd bne.w 800c034 { switch (clocksource) 800beba: f897 3033 ldrb.w r3, [r7, #51] ; 0x33 800bebe: 2b20 cmp r3, #32 800bec0: dc48 bgt.n 800bf54 800bec2: 2b00 cmp r3, #0 800bec4: db7b blt.n 800bfbe 800bec6: 2b20 cmp r3, #32 800bec8: d879 bhi.n 800bfbe 800beca: a201 add r2, pc, #4 ; (adr r2, 800bed0 ) 800becc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800bed0: 0800bf5b .word 0x0800bf5b 800bed4: 0800bf63 .word 0x0800bf63 800bed8: 0800bfbf .word 0x0800bfbf 800bedc: 0800bfbf .word 0x0800bfbf 800bee0: 0800bf6b .word 0x0800bf6b 800bee4: 0800bfbf .word 0x0800bfbf 800bee8: 0800bfbf .word 0x0800bfbf 800beec: 0800bfbf .word 0x0800bfbf 800bef0: 0800bf7b .word 0x0800bf7b 800bef4: 0800bfbf .word 0x0800bfbf 800bef8: 0800bfbf .word 0x0800bfbf 800befc: 0800bfbf .word 0x0800bfbf 800bf00: 0800bfbf .word 0x0800bfbf 800bf04: 0800bfbf .word 0x0800bfbf 800bf08: 0800bfbf .word 0x0800bfbf 800bf0c: 0800bfbf .word 0x0800bfbf 800bf10: 0800bf8b .word 0x0800bf8b 800bf14: 0800bfbf .word 0x0800bfbf 800bf18: 0800bfbf .word 0x0800bfbf 800bf1c: 0800bfbf .word 0x0800bfbf 800bf20: 0800bfbf .word 0x0800bfbf 800bf24: 0800bfbf .word 0x0800bfbf 800bf28: 0800bfbf .word 0x0800bfbf 800bf2c: 0800bfbf .word 0x0800bfbf 800bf30: 0800bfbf .word 0x0800bfbf 800bf34: 0800bfbf .word 0x0800bfbf 800bf38: 0800bfbf .word 0x0800bfbf 800bf3c: 0800bfbf .word 0x0800bfbf 800bf40: 0800bfbf .word 0x0800bfbf 800bf44: 0800bfbf .word 0x0800bfbf 800bf48: 0800bfbf .word 0x0800bfbf 800bf4c: 0800bfbf .word 0x0800bfbf 800bf50: 0800bfb1 .word 0x0800bfb1 800bf54: 2b40 cmp r3, #64 ; 0x40 800bf56: d02e beq.n 800bfb6 800bf58: e031 b.n 800bfbe { case UART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 800bf5a: f7fb fa8d bl 8007478 800bf5e: 62f8 str r0, [r7, #44] ; 0x2c break; 800bf60: e033 b.n 800bfca case UART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 800bf62: f7fb fa9f bl 80074a4 800bf66: 62f8 str r0, [r7, #44] ; 0x2c break; 800bf68: e02f b.n 800bfca case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800bf6a: f107 0314 add.w r3, r7, #20 800bf6e: 4618 mov r0, r3 800bf70: f7fc fdfa bl 8008b68 pclk = pll2_clocks.PLL2_Q_Frequency; 800bf74: 69bb ldr r3, [r7, #24] 800bf76: 62fb str r3, [r7, #44] ; 0x2c break; 800bf78: e027 b.n 800bfca case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800bf7a: f107 0308 add.w r3, r7, #8 800bf7e: 4618 mov r0, r3 800bf80: f7fc ff46 bl 8008e10 pclk = pll3_clocks.PLL3_Q_Frequency; 800bf84: 68fb ldr r3, [r7, #12] 800bf86: 62fb str r3, [r7, #44] ; 0x2c break; 800bf88: e01f b.n 800bfca case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800bf8a: 4b6e ldr r3, [pc, #440] ; (800c144 ) 800bf8c: 681b ldr r3, [r3, #0] 800bf8e: f003 0320 and.w r3, r3, #32 800bf92: 2b00 cmp r3, #0 800bf94: d009 beq.n 800bfaa { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 800bf96: 4b6b ldr r3, [pc, #428] ; (800c144 ) 800bf98: 681b ldr r3, [r3, #0] 800bf9a: 08db lsrs r3, r3, #3 800bf9c: f003 0303 and.w r3, r3, #3 800bfa0: 4a69 ldr r2, [pc, #420] ; (800c148 ) 800bfa2: fa22 f303 lsr.w r3, r2, r3 800bfa6: 62fb str r3, [r7, #44] ; 0x2c } else { pclk = (uint32_t) HSI_VALUE; } break; 800bfa8: e00f b.n 800bfca pclk = (uint32_t) HSI_VALUE; 800bfaa: 4b67 ldr r3, [pc, #412] ; (800c148 ) 800bfac: 62fb str r3, [r7, #44] ; 0x2c break; 800bfae: e00c b.n 800bfca case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 800bfb0: 4b66 ldr r3, [pc, #408] ; (800c14c ) 800bfb2: 62fb str r3, [r7, #44] ; 0x2c break; 800bfb4: e009 b.n 800bfca case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 800bfb6: f44f 4300 mov.w r3, #32768 ; 0x8000 800bfba: 62fb str r3, [r7, #44] ; 0x2c break; 800bfbc: e005 b.n 800bfca default: pclk = 0U; 800bfbe: 2300 movs r3, #0 800bfc0: 62fb str r3, [r7, #44] ; 0x2c ret = HAL_ERROR; 800bfc2: 2301 movs r3, #1 800bfc4: f887 3032 strb.w r3, [r7, #50] ; 0x32 break; 800bfc8: bf00 nop } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) 800bfca: 6afb ldr r3, [r7, #44] ; 0x2c 800bfcc: 2b00 cmp r3, #0 800bfce: f000 80ea beq.w 800c1a6 { usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 800bfd2: 687b ldr r3, [r7, #4] 800bfd4: 6a5b ldr r3, [r3, #36] ; 0x24 800bfd6: 4a5a ldr r2, [pc, #360] ; (800c140 ) 800bfd8: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 800bfdc: 461a mov r2, r3 800bfde: 6afb ldr r3, [r7, #44] ; 0x2c 800bfe0: fbb3 f3f2 udiv r3, r3, r2 800bfe4: 005a lsls r2, r3, #1 800bfe6: 687b ldr r3, [r7, #4] 800bfe8: 685b ldr r3, [r3, #4] 800bfea: 085b lsrs r3, r3, #1 800bfec: 441a add r2, r3 800bfee: 687b ldr r3, [r7, #4] 800bff0: 685b ldr r3, [r3, #4] 800bff2: fbb2 f3f3 udiv r3, r2, r3 800bff6: 62bb str r3, [r7, #40] ; 0x28 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 800bff8: 6abb ldr r3, [r7, #40] ; 0x28 800bffa: 2b0f cmp r3, #15 800bffc: d916 bls.n 800c02c 800bffe: 6abb ldr r3, [r7, #40] ; 0x28 800c000: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 800c004: d212 bcs.n 800c02c { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); 800c006: 6abb ldr r3, [r7, #40] ; 0x28 800c008: b29b uxth r3, r3 800c00a: f023 030f bic.w r3, r3, #15 800c00e: 84fb strh r3, [r7, #38] ; 0x26 brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 800c010: 6abb ldr r3, [r7, #40] ; 0x28 800c012: 085b lsrs r3, r3, #1 800c014: b29b uxth r3, r3 800c016: f003 0307 and.w r3, r3, #7 800c01a: b29a uxth r2, r3 800c01c: 8cfb ldrh r3, [r7, #38] ; 0x26 800c01e: 4313 orrs r3, r2 800c020: 84fb strh r3, [r7, #38] ; 0x26 huart->Instance->BRR = brrtemp; 800c022: 687b ldr r3, [r7, #4] 800c024: 681b ldr r3, [r3, #0] 800c026: 8cfa ldrh r2, [r7, #38] ; 0x26 800c028: 60da str r2, [r3, #12] 800c02a: e0bc b.n 800c1a6 } else { ret = HAL_ERROR; 800c02c: 2301 movs r3, #1 800c02e: f887 3032 strb.w r3, [r7, #50] ; 0x32 800c032: e0b8 b.n 800c1a6 } } } else { switch (clocksource) 800c034: f897 3033 ldrb.w r3, [r7, #51] ; 0x33 800c038: 2b20 cmp r3, #32 800c03a: dc4b bgt.n 800c0d4 800c03c: 2b00 cmp r3, #0 800c03e: f2c0 8087 blt.w 800c150 800c042: 2b20 cmp r3, #32 800c044: f200 8084 bhi.w 800c150 800c048: a201 add r2, pc, #4 ; (adr r2, 800c050 ) 800c04a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c04e: bf00 nop 800c050: 0800c0db .word 0x0800c0db 800c054: 0800c0e3 .word 0x0800c0e3 800c058: 0800c151 .word 0x0800c151 800c05c: 0800c151 .word 0x0800c151 800c060: 0800c0eb .word 0x0800c0eb 800c064: 0800c151 .word 0x0800c151 800c068: 0800c151 .word 0x0800c151 800c06c: 0800c151 .word 0x0800c151 800c070: 0800c0fb .word 0x0800c0fb 800c074: 0800c151 .word 0x0800c151 800c078: 0800c151 .word 0x0800c151 800c07c: 0800c151 .word 0x0800c151 800c080: 0800c151 .word 0x0800c151 800c084: 0800c151 .word 0x0800c151 800c088: 0800c151 .word 0x0800c151 800c08c: 0800c151 .word 0x0800c151 800c090: 0800c10b .word 0x0800c10b 800c094: 0800c151 .word 0x0800c151 800c098: 0800c151 .word 0x0800c151 800c09c: 0800c151 .word 0x0800c151 800c0a0: 0800c151 .word 0x0800c151 800c0a4: 0800c151 .word 0x0800c151 800c0a8: 0800c151 .word 0x0800c151 800c0ac: 0800c151 .word 0x0800c151 800c0b0: 0800c151 .word 0x0800c151 800c0b4: 0800c151 .word 0x0800c151 800c0b8: 0800c151 .word 0x0800c151 800c0bc: 0800c151 .word 0x0800c151 800c0c0: 0800c151 .word 0x0800c151 800c0c4: 0800c151 .word 0x0800c151 800c0c8: 0800c151 .word 0x0800c151 800c0cc: 0800c151 .word 0x0800c151 800c0d0: 0800c131 .word 0x0800c131 800c0d4: 2b40 cmp r3, #64 ; 0x40 800c0d6: d02e beq.n 800c136 800c0d8: e03a b.n 800c150 { case UART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 800c0da: f7fb f9cd bl 8007478 800c0de: 62f8 str r0, [r7, #44] ; 0x2c break; 800c0e0: e03c b.n 800c15c case UART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 800c0e2: f7fb f9df bl 80074a4 800c0e6: 62f8 str r0, [r7, #44] ; 0x2c break; 800c0e8: e038 b.n 800c15c case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800c0ea: f107 0314 add.w r3, r7, #20 800c0ee: 4618 mov r0, r3 800c0f0: f7fc fd3a bl 8008b68 pclk = pll2_clocks.PLL2_Q_Frequency; 800c0f4: 69bb ldr r3, [r7, #24] 800c0f6: 62fb str r3, [r7, #44] ; 0x2c break; 800c0f8: e030 b.n 800c15c case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800c0fa: f107 0308 add.w r3, r7, #8 800c0fe: 4618 mov r0, r3 800c100: f7fc fe86 bl 8008e10 pclk = pll3_clocks.PLL3_Q_Frequency; 800c104: 68fb ldr r3, [r7, #12] 800c106: 62fb str r3, [r7, #44] ; 0x2c break; 800c108: e028 b.n 800c15c case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800c10a: 4b0e ldr r3, [pc, #56] ; (800c144 ) 800c10c: 681b ldr r3, [r3, #0] 800c10e: f003 0320 and.w r3, r3, #32 800c112: 2b00 cmp r3, #0 800c114: d009 beq.n 800c12a { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 800c116: 4b0b ldr r3, [pc, #44] ; (800c144 ) 800c118: 681b ldr r3, [r3, #0] 800c11a: 08db lsrs r3, r3, #3 800c11c: f003 0303 and.w r3, r3, #3 800c120: 4a09 ldr r2, [pc, #36] ; (800c148 ) 800c122: fa22 f303 lsr.w r3, r2, r3 800c126: 62fb str r3, [r7, #44] ; 0x2c } else { pclk = (uint32_t) HSI_VALUE; } break; 800c128: e018 b.n 800c15c pclk = (uint32_t) HSI_VALUE; 800c12a: 4b07 ldr r3, [pc, #28] ; (800c148 ) 800c12c: 62fb str r3, [r7, #44] ; 0x2c break; 800c12e: e015 b.n 800c15c case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 800c130: 4b06 ldr r3, [pc, #24] ; (800c14c ) 800c132: 62fb str r3, [r7, #44] ; 0x2c break; 800c134: e012 b.n 800c15c case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 800c136: f44f 4300 mov.w r3, #32768 ; 0x8000 800c13a: 62fb str r3, [r7, #44] ; 0x2c break; 800c13c: e00e b.n 800c15c 800c13e: bf00 nop 800c140: 0800e664 .word 0x0800e664 800c144: 58024400 .word 0x58024400 800c148: 03d09000 .word 0x03d09000 800c14c: 003d0900 .word 0x003d0900 default: pclk = 0U; 800c150: 2300 movs r3, #0 800c152: 62fb str r3, [r7, #44] ; 0x2c ret = HAL_ERROR; 800c154: 2301 movs r3, #1 800c156: f887 3032 strb.w r3, [r7, #50] ; 0x32 break; 800c15a: bf00 nop } if (pclk != 0U) 800c15c: 6afb ldr r3, [r7, #44] ; 0x2c 800c15e: 2b00 cmp r3, #0 800c160: d021 beq.n 800c1a6 { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 800c162: 687b ldr r3, [r7, #4] 800c164: 6a5b ldr r3, [r3, #36] ; 0x24 800c166: 4a1a ldr r2, [pc, #104] ; (800c1d0 ) 800c168: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 800c16c: 461a mov r2, r3 800c16e: 6afb ldr r3, [r7, #44] ; 0x2c 800c170: fbb3 f2f2 udiv r2, r3, r2 800c174: 687b ldr r3, [r7, #4] 800c176: 685b ldr r3, [r3, #4] 800c178: 085b lsrs r3, r3, #1 800c17a: 441a add r2, r3 800c17c: 687b ldr r3, [r7, #4] 800c17e: 685b ldr r3, [r3, #4] 800c180: fbb2 f3f3 udiv r3, r2, r3 800c184: 62bb str r3, [r7, #40] ; 0x28 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 800c186: 6abb ldr r3, [r7, #40] ; 0x28 800c188: 2b0f cmp r3, #15 800c18a: d909 bls.n 800c1a0 800c18c: 6abb ldr r3, [r7, #40] ; 0x28 800c18e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 800c192: d205 bcs.n 800c1a0 { huart->Instance->BRR = (uint16_t)usartdiv; 800c194: 6abb ldr r3, [r7, #40] ; 0x28 800c196: b29a uxth r2, r3 800c198: 687b ldr r3, [r7, #4] 800c19a: 681b ldr r3, [r3, #0] 800c19c: 60da str r2, [r3, #12] 800c19e: e002 b.n 800c1a6 } else { ret = HAL_ERROR; 800c1a0: 2301 movs r3, #1 800c1a2: f887 3032 strb.w r3, [r7, #50] ; 0x32 } } } /* Initialize the number of data to process during RX/TX ISR execution */ huart->NbTxDataToProcess = 1; 800c1a6: 687b ldr r3, [r7, #4] 800c1a8: 2201 movs r2, #1 800c1aa: f8a3 206a strh.w r2, [r3, #106] ; 0x6a huart->NbRxDataToProcess = 1; 800c1ae: 687b ldr r3, [r7, #4] 800c1b0: 2201 movs r2, #1 800c1b2: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 /* Clear ISR function pointers */ huart->RxISR = NULL; 800c1b6: 687b ldr r3, [r7, #4] 800c1b8: 2200 movs r2, #0 800c1ba: 671a str r2, [r3, #112] ; 0x70 huart->TxISR = NULL; 800c1bc: 687b ldr r3, [r7, #4] 800c1be: 2200 movs r2, #0 800c1c0: 675a str r2, [r3, #116] ; 0x74 return ret; 800c1c2: f897 3032 ldrb.w r3, [r7, #50] ; 0x32 } 800c1c6: 4618 mov r0, r3 800c1c8: 3738 adds r7, #56 ; 0x38 800c1ca: 46bd mov sp, r7 800c1cc: bdb0 pop {r4, r5, r7, pc} 800c1ce: bf00 nop 800c1d0: 0800e664 .word 0x0800e664 0800c1d4 : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { 800c1d4: b480 push {r7} 800c1d6: b083 sub sp, #12 800c1d8: af00 add r7, sp, #0 800c1da: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) 800c1dc: 687b ldr r3, [r7, #4] 800c1de: 6a9b ldr r3, [r3, #40] ; 0x28 800c1e0: f003 0301 and.w r3, r3, #1 800c1e4: 2b00 cmp r3, #0 800c1e6: d00a beq.n 800c1fe { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); 800c1e8: 687b ldr r3, [r7, #4] 800c1ea: 681b ldr r3, [r3, #0] 800c1ec: 685b ldr r3, [r3, #4] 800c1ee: f423 3100 bic.w r1, r3, #131072 ; 0x20000 800c1f2: 687b ldr r3, [r7, #4] 800c1f4: 6ada ldr r2, [r3, #44] ; 0x2c 800c1f6: 687b ldr r3, [r7, #4] 800c1f8: 681b ldr r3, [r3, #0] 800c1fa: 430a orrs r2, r1 800c1fc: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) 800c1fe: 687b ldr r3, [r7, #4] 800c200: 6a9b ldr r3, [r3, #40] ; 0x28 800c202: f003 0302 and.w r3, r3, #2 800c206: 2b00 cmp r3, #0 800c208: d00a beq.n 800c220 { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); 800c20a: 687b ldr r3, [r7, #4] 800c20c: 681b ldr r3, [r3, #0] 800c20e: 685b ldr r3, [r3, #4] 800c210: f423 3180 bic.w r1, r3, #65536 ; 0x10000 800c214: 687b ldr r3, [r7, #4] 800c216: 6b1a ldr r2, [r3, #48] ; 0x30 800c218: 687b ldr r3, [r7, #4] 800c21a: 681b ldr r3, [r3, #0] 800c21c: 430a orrs r2, r1 800c21e: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) 800c220: 687b ldr r3, [r7, #4] 800c222: 6a9b ldr r3, [r3, #40] ; 0x28 800c224: f003 0304 and.w r3, r3, #4 800c228: 2b00 cmp r3, #0 800c22a: d00a beq.n 800c242 { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); 800c22c: 687b ldr r3, [r7, #4] 800c22e: 681b ldr r3, [r3, #0] 800c230: 685b ldr r3, [r3, #4] 800c232: f423 2180 bic.w r1, r3, #262144 ; 0x40000 800c236: 687b ldr r3, [r7, #4] 800c238: 6b5a ldr r2, [r3, #52] ; 0x34 800c23a: 687b ldr r3, [r7, #4] 800c23c: 681b ldr r3, [r3, #0] 800c23e: 430a orrs r2, r1 800c240: 605a str r2, [r3, #4] } /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) 800c242: 687b ldr r3, [r7, #4] 800c244: 6a9b ldr r3, [r3, #40] ; 0x28 800c246: f003 0308 and.w r3, r3, #8 800c24a: 2b00 cmp r3, #0 800c24c: d00a beq.n 800c264 { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); 800c24e: 687b ldr r3, [r7, #4] 800c250: 681b ldr r3, [r3, #0] 800c252: 685b ldr r3, [r3, #4] 800c254: f423 4100 bic.w r1, r3, #32768 ; 0x8000 800c258: 687b ldr r3, [r7, #4] 800c25a: 6b9a ldr r2, [r3, #56] ; 0x38 800c25c: 687b ldr r3, [r7, #4] 800c25e: 681b ldr r3, [r3, #0] 800c260: 430a orrs r2, r1 800c262: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) 800c264: 687b ldr r3, [r7, #4] 800c266: 6a9b ldr r3, [r3, #40] ; 0x28 800c268: f003 0310 and.w r3, r3, #16 800c26c: 2b00 cmp r3, #0 800c26e: d00a beq.n 800c286 { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); 800c270: 687b ldr r3, [r7, #4] 800c272: 681b ldr r3, [r3, #0] 800c274: 689b ldr r3, [r3, #8] 800c276: f423 5180 bic.w r1, r3, #4096 ; 0x1000 800c27a: 687b ldr r3, [r7, #4] 800c27c: 6bda ldr r2, [r3, #60] ; 0x3c 800c27e: 687b ldr r3, [r7, #4] 800c280: 681b ldr r3, [r3, #0] 800c282: 430a orrs r2, r1 800c284: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) 800c286: 687b ldr r3, [r7, #4] 800c288: 6a9b ldr r3, [r3, #40] ; 0x28 800c28a: f003 0320 and.w r3, r3, #32 800c28e: 2b00 cmp r3, #0 800c290: d00a beq.n 800c2a8 { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); 800c292: 687b ldr r3, [r7, #4] 800c294: 681b ldr r3, [r3, #0] 800c296: 689b ldr r3, [r3, #8] 800c298: f423 5100 bic.w r1, r3, #8192 ; 0x2000 800c29c: 687b ldr r3, [r7, #4] 800c29e: 6c1a ldr r2, [r3, #64] ; 0x40 800c2a0: 687b ldr r3, [r7, #4] 800c2a2: 681b ldr r3, [r3, #0] 800c2a4: 430a orrs r2, r1 800c2a6: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) 800c2a8: 687b ldr r3, [r7, #4] 800c2aa: 6a9b ldr r3, [r3, #40] ; 0x28 800c2ac: f003 0340 and.w r3, r3, #64 ; 0x40 800c2b0: 2b00 cmp r3, #0 800c2b2: d01a beq.n 800c2ea { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); 800c2b4: 687b ldr r3, [r7, #4] 800c2b6: 681b ldr r3, [r3, #0] 800c2b8: 685b ldr r3, [r3, #4] 800c2ba: f423 1180 bic.w r1, r3, #1048576 ; 0x100000 800c2be: 687b ldr r3, [r7, #4] 800c2c0: 6c5a ldr r2, [r3, #68] ; 0x44 800c2c2: 687b ldr r3, [r7, #4] 800c2c4: 681b ldr r3, [r3, #0] 800c2c6: 430a orrs r2, r1 800c2c8: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) 800c2ca: 687b ldr r3, [r7, #4] 800c2cc: 6c5b ldr r3, [r3, #68] ; 0x44 800c2ce: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 800c2d2: d10a bne.n 800c2ea { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); 800c2d4: 687b ldr r3, [r7, #4] 800c2d6: 681b ldr r3, [r3, #0] 800c2d8: 685b ldr r3, [r3, #4] 800c2da: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000 800c2de: 687b ldr r3, [r7, #4] 800c2e0: 6c9a ldr r2, [r3, #72] ; 0x48 800c2e2: 687b ldr r3, [r7, #4] 800c2e4: 681b ldr r3, [r3, #0] 800c2e6: 430a orrs r2, r1 800c2e8: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) 800c2ea: 687b ldr r3, [r7, #4] 800c2ec: 6a9b ldr r3, [r3, #40] ; 0x28 800c2ee: f003 0380 and.w r3, r3, #128 ; 0x80 800c2f2: 2b00 cmp r3, #0 800c2f4: d00a beq.n 800c30c { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); 800c2f6: 687b ldr r3, [r7, #4] 800c2f8: 681b ldr r3, [r3, #0] 800c2fa: 685b ldr r3, [r3, #4] 800c2fc: f423 2100 bic.w r1, r3, #524288 ; 0x80000 800c300: 687b ldr r3, [r7, #4] 800c302: 6cda ldr r2, [r3, #76] ; 0x4c 800c304: 687b ldr r3, [r7, #4] 800c306: 681b ldr r3, [r3, #0] 800c308: 430a orrs r2, r1 800c30a: 605a str r2, [r3, #4] } } 800c30c: bf00 nop 800c30e: 370c adds r7, #12 800c310: 46bd mov sp, r7 800c312: f85d 7b04 ldr.w r7, [sp], #4 800c316: 4770 bx lr 0800c318 : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { 800c318: b580 push {r7, lr} 800c31a: b086 sub sp, #24 800c31c: af02 add r7, sp, #8 800c31e: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 800c320: 687b ldr r3, [r7, #4] 800c322: 2200 movs r2, #0 800c324: f8c3 208c str.w r2, [r3, #140] ; 0x8c /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 800c328: f7f6 ff5e bl 80031e8 800c32c: 60f8 str r0, [r7, #12] /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) 800c32e: 687b ldr r3, [r7, #4] 800c330: 681b ldr r3, [r3, #0] 800c332: 681b ldr r3, [r3, #0] 800c334: f003 0308 and.w r3, r3, #8 800c338: 2b08 cmp r3, #8 800c33a: d10e bne.n 800c35a { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 800c33c: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 800c340: 9300 str r3, [sp, #0] 800c342: 68fb ldr r3, [r7, #12] 800c344: 2200 movs r2, #0 800c346: f44f 1100 mov.w r1, #2097152 ; 0x200000 800c34a: 6878 ldr r0, [r7, #4] 800c34c: f000 f82f bl 800c3ae 800c350: 4603 mov r3, r0 800c352: 2b00 cmp r3, #0 800c354: d001 beq.n 800c35a { /* Timeout occurred */ return HAL_TIMEOUT; 800c356: 2303 movs r3, #3 800c358: e025 b.n 800c3a6 } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) 800c35a: 687b ldr r3, [r7, #4] 800c35c: 681b ldr r3, [r3, #0] 800c35e: 681b ldr r3, [r3, #0] 800c360: f003 0304 and.w r3, r3, #4 800c364: 2b04 cmp r3, #4 800c366: d10e bne.n 800c386 { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 800c368: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 800c36c: 9300 str r3, [sp, #0] 800c36e: 68fb ldr r3, [r7, #12] 800c370: 2200 movs r2, #0 800c372: f44f 0180 mov.w r1, #4194304 ; 0x400000 800c376: 6878 ldr r0, [r7, #4] 800c378: f000 f819 bl 800c3ae 800c37c: 4603 mov r3, r0 800c37e: 2b00 cmp r3, #0 800c380: d001 beq.n 800c386 { /* Timeout occurred */ return HAL_TIMEOUT; 800c382: 2303 movs r3, #3 800c384: e00f b.n 800c3a6 } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; 800c386: 687b ldr r3, [r7, #4] 800c388: 2220 movs r2, #32 800c38a: f8c3 2084 str.w r2, [r3, #132] ; 0x84 huart->RxState = HAL_UART_STATE_READY; 800c38e: 687b ldr r3, [r7, #4] 800c390: 2220 movs r2, #32 800c392: f8c3 2088 str.w r2, [r3, #136] ; 0x88 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800c396: 687b ldr r3, [r7, #4] 800c398: 2200 movs r2, #0 800c39a: 66da str r2, [r3, #108] ; 0x6c __HAL_UNLOCK(huart); 800c39c: 687b ldr r3, [r7, #4] 800c39e: 2200 movs r2, #0 800c3a0: f883 2080 strb.w r2, [r3, #128] ; 0x80 return HAL_OK; 800c3a4: 2300 movs r3, #0 } 800c3a6: 4618 mov r0, r3 800c3a8: 3710 adds r7, #16 800c3aa: 46bd mov sp, r7 800c3ac: bd80 pop {r7, pc} 0800c3ae : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 800c3ae: b580 push {r7, lr} 800c3b0: b09c sub sp, #112 ; 0x70 800c3b2: af00 add r7, sp, #0 800c3b4: 60f8 str r0, [r7, #12] 800c3b6: 60b9 str r1, [r7, #8] 800c3b8: 603b str r3, [r7, #0] 800c3ba: 4613 mov r3, r2 800c3bc: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 800c3be: e0a9 b.n 800c514 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 800c3c0: 6fbb ldr r3, [r7, #120] ; 0x78 800c3c2: f1b3 3fff cmp.w r3, #4294967295 800c3c6: f000 80a5 beq.w 800c514 { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 800c3ca: f7f6 ff0d bl 80031e8 800c3ce: 4602 mov r2, r0 800c3d0: 683b ldr r3, [r7, #0] 800c3d2: 1ad3 subs r3, r2, r3 800c3d4: 6fba ldr r2, [r7, #120] ; 0x78 800c3d6: 429a cmp r2, r3 800c3d8: d302 bcc.n 800c3e0 800c3da: 6fbb ldr r3, [r7, #120] ; 0x78 800c3dc: 2b00 cmp r3, #0 800c3de: d140 bne.n 800c462 { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | 800c3e0: 68fb ldr r3, [r7, #12] 800c3e2: 681b ldr r3, [r3, #0] 800c3e4: 653b str r3, [r7, #80] ; 0x50 */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800c3e6: 6d3b ldr r3, [r7, #80] ; 0x50 800c3e8: e853 3f00 ldrex r3, [r3] 800c3ec: 64fb str r3, [r7, #76] ; 0x4c return(result); 800c3ee: 6cfb ldr r3, [r7, #76] ; 0x4c 800c3f0: f423 73d0 bic.w r3, r3, #416 ; 0x1a0 800c3f4: 667b str r3, [r7, #100] ; 0x64 800c3f6: 68fb ldr r3, [r7, #12] 800c3f8: 681b ldr r3, [r3, #0] 800c3fa: 461a mov r2, r3 800c3fc: 6e7b ldr r3, [r7, #100] ; 0x64 800c3fe: 65fb str r3, [r7, #92] ; 0x5c 800c400: 65ba str r2, [r7, #88] ; 0x58 */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800c402: 6db9 ldr r1, [r7, #88] ; 0x58 800c404: 6dfa ldr r2, [r7, #92] ; 0x5c 800c406: e841 2300 strex r3, r2, [r1] 800c40a: 657b str r3, [r7, #84] ; 0x54 return(result); 800c40c: 6d7b ldr r3, [r7, #84] ; 0x54 800c40e: 2b00 cmp r3, #0 800c410: d1e6 bne.n 800c3e0 USART_CR1_TXEIE_TXFNFIE)); ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 800c412: 68fb ldr r3, [r7, #12] 800c414: 681b ldr r3, [r3, #0] 800c416: 3308 adds r3, #8 800c418: 63fb str r3, [r7, #60] ; 0x3c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800c41a: 6bfb ldr r3, [r7, #60] ; 0x3c 800c41c: e853 3f00 ldrex r3, [r3] 800c420: 63bb str r3, [r7, #56] ; 0x38 return(result); 800c422: 6bbb ldr r3, [r7, #56] ; 0x38 800c424: f023 0301 bic.w r3, r3, #1 800c428: 663b str r3, [r7, #96] ; 0x60 800c42a: 68fb ldr r3, [r7, #12] 800c42c: 681b ldr r3, [r3, #0] 800c42e: 3308 adds r3, #8 800c430: 6e3a ldr r2, [r7, #96] ; 0x60 800c432: 64ba str r2, [r7, #72] ; 0x48 800c434: 647b str r3, [r7, #68] ; 0x44 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800c436: 6c79 ldr r1, [r7, #68] ; 0x44 800c438: 6cba ldr r2, [r7, #72] ; 0x48 800c43a: e841 2300 strex r3, r2, [r1] 800c43e: 643b str r3, [r7, #64] ; 0x40 return(result); 800c440: 6c3b ldr r3, [r7, #64] ; 0x40 800c442: 2b00 cmp r3, #0 800c444: d1e5 bne.n 800c412 huart->gState = HAL_UART_STATE_READY; 800c446: 68fb ldr r3, [r7, #12] 800c448: 2220 movs r2, #32 800c44a: f8c3 2084 str.w r2, [r3, #132] ; 0x84 huart->RxState = HAL_UART_STATE_READY; 800c44e: 68fb ldr r3, [r7, #12] 800c450: 2220 movs r2, #32 800c452: f8c3 2088 str.w r2, [r3, #136] ; 0x88 __HAL_UNLOCK(huart); 800c456: 68fb ldr r3, [r7, #12] 800c458: 2200 movs r2, #0 800c45a: f883 2080 strb.w r2, [r3, #128] ; 0x80 return HAL_TIMEOUT; 800c45e: 2303 movs r3, #3 800c460: e069 b.n 800c536 } if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) 800c462: 68fb ldr r3, [r7, #12] 800c464: 681b ldr r3, [r3, #0] 800c466: 681b ldr r3, [r3, #0] 800c468: f003 0304 and.w r3, r3, #4 800c46c: 2b00 cmp r3, #0 800c46e: d051 beq.n 800c514 { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) 800c470: 68fb ldr r3, [r7, #12] 800c472: 681b ldr r3, [r3, #0] 800c474: 69db ldr r3, [r3, #28] 800c476: f403 6300 and.w r3, r3, #2048 ; 0x800 800c47a: f5b3 6f00 cmp.w r3, #2048 ; 0x800 800c47e: d149 bne.n 800c514 { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 800c480: 68fb ldr r3, [r7, #12] 800c482: 681b ldr r3, [r3, #0] 800c484: f44f 6200 mov.w r2, #2048 ; 0x800 800c488: 621a str r2, [r3, #32] /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | 800c48a: 68fb ldr r3, [r7, #12] 800c48c: 681b ldr r3, [r3, #0] 800c48e: 62bb str r3, [r7, #40] ; 0x28 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800c490: 6abb ldr r3, [r7, #40] ; 0x28 800c492: e853 3f00 ldrex r3, [r3] 800c496: 627b str r3, [r7, #36] ; 0x24 return(result); 800c498: 6a7b ldr r3, [r7, #36] ; 0x24 800c49a: f423 73d0 bic.w r3, r3, #416 ; 0x1a0 800c49e: 66fb str r3, [r7, #108] ; 0x6c 800c4a0: 68fb ldr r3, [r7, #12] 800c4a2: 681b ldr r3, [r3, #0] 800c4a4: 461a mov r2, r3 800c4a6: 6efb ldr r3, [r7, #108] ; 0x6c 800c4a8: 637b str r3, [r7, #52] ; 0x34 800c4aa: 633a str r2, [r7, #48] ; 0x30 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800c4ac: 6b39 ldr r1, [r7, #48] ; 0x30 800c4ae: 6b7a ldr r2, [r7, #52] ; 0x34 800c4b0: e841 2300 strex r3, r2, [r1] 800c4b4: 62fb str r3, [r7, #44] ; 0x2c return(result); 800c4b6: 6afb ldr r3, [r7, #44] ; 0x2c 800c4b8: 2b00 cmp r3, #0 800c4ba: d1e6 bne.n 800c48a USART_CR1_TXEIE_TXFNFIE)); ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 800c4bc: 68fb ldr r3, [r7, #12] 800c4be: 681b ldr r3, [r3, #0] 800c4c0: 3308 adds r3, #8 800c4c2: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800c4c4: 697b ldr r3, [r7, #20] 800c4c6: e853 3f00 ldrex r3, [r3] 800c4ca: 613b str r3, [r7, #16] return(result); 800c4cc: 693b ldr r3, [r7, #16] 800c4ce: f023 0301 bic.w r3, r3, #1 800c4d2: 66bb str r3, [r7, #104] ; 0x68 800c4d4: 68fb ldr r3, [r7, #12] 800c4d6: 681b ldr r3, [r3, #0] 800c4d8: 3308 adds r3, #8 800c4da: 6eba ldr r2, [r7, #104] ; 0x68 800c4dc: 623a str r2, [r7, #32] 800c4de: 61fb str r3, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800c4e0: 69f9 ldr r1, [r7, #28] 800c4e2: 6a3a ldr r2, [r7, #32] 800c4e4: e841 2300 strex r3, r2, [r1] 800c4e8: 61bb str r3, [r7, #24] return(result); 800c4ea: 69bb ldr r3, [r7, #24] 800c4ec: 2b00 cmp r3, #0 800c4ee: d1e5 bne.n 800c4bc huart->gState = HAL_UART_STATE_READY; 800c4f0: 68fb ldr r3, [r7, #12] 800c4f2: 2220 movs r2, #32 800c4f4: f8c3 2084 str.w r2, [r3, #132] ; 0x84 huart->RxState = HAL_UART_STATE_READY; 800c4f8: 68fb ldr r3, [r7, #12] 800c4fa: 2220 movs r2, #32 800c4fc: f8c3 2088 str.w r2, [r3, #136] ; 0x88 huart->ErrorCode = HAL_UART_ERROR_RTO; 800c500: 68fb ldr r3, [r7, #12] 800c502: 2220 movs r2, #32 800c504: f8c3 208c str.w r2, [r3, #140] ; 0x8c /* Process Unlocked */ __HAL_UNLOCK(huart); 800c508: 68fb ldr r3, [r7, #12] 800c50a: 2200 movs r2, #0 800c50c: f883 2080 strb.w r2, [r3, #128] ; 0x80 return HAL_TIMEOUT; 800c510: 2303 movs r3, #3 800c512: e010 b.n 800c536 while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 800c514: 68fb ldr r3, [r7, #12] 800c516: 681b ldr r3, [r3, #0] 800c518: 69da ldr r2, [r3, #28] 800c51a: 68bb ldr r3, [r7, #8] 800c51c: 4013 ands r3, r2 800c51e: 68ba ldr r2, [r7, #8] 800c520: 429a cmp r2, r3 800c522: bf0c ite eq 800c524: 2301 moveq r3, #1 800c526: 2300 movne r3, #0 800c528: b2db uxtb r3, r3 800c52a: 461a mov r2, r3 800c52c: 79fb ldrb r3, [r7, #7] 800c52e: 429a cmp r2, r3 800c530: f43f af46 beq.w 800c3c0 } } } } return HAL_OK; 800c534: 2300 movs r3, #0 } 800c536: 4618 mov r0, r3 800c538: 3770 adds r7, #112 ; 0x70 800c53a: 46bd mov sp, r7 800c53c: bd80 pop {r7, pc} 0800c53e : * @brief Disable the FIFO mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) { 800c53e: b480 push {r7} 800c540: b085 sub sp, #20 800c542: af00 add r7, sp, #0 800c544: 6078 str r0, [r7, #4] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); 800c546: 687b ldr r3, [r7, #4] 800c548: f893 3080 ldrb.w r3, [r3, #128] ; 0x80 800c54c: 2b01 cmp r3, #1 800c54e: d101 bne.n 800c554 800c550: 2302 movs r3, #2 800c552: e027 b.n 800c5a4 800c554: 687b ldr r3, [r7, #4] 800c556: 2201 movs r2, #1 800c558: f883 2080 strb.w r2, [r3, #128] ; 0x80 huart->gState = HAL_UART_STATE_BUSY; 800c55c: 687b ldr r3, [r7, #4] 800c55e: 2224 movs r2, #36 ; 0x24 800c560: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 800c564: 687b ldr r3, [r7, #4] 800c566: 681b ldr r3, [r3, #0] 800c568: 681b ldr r3, [r3, #0] 800c56a: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 800c56c: 687b ldr r3, [r7, #4] 800c56e: 681b ldr r3, [r3, #0] 800c570: 681a ldr r2, [r3, #0] 800c572: 687b ldr r3, [r7, #4] 800c574: 681b ldr r3, [r3, #0] 800c576: f022 0201 bic.w r2, r2, #1 800c57a: 601a str r2, [r3, #0] /* Enable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); 800c57c: 68fb ldr r3, [r7, #12] 800c57e: f023 5300 bic.w r3, r3, #536870912 ; 0x20000000 800c582: 60fb str r3, [r7, #12] huart->FifoMode = UART_FIFOMODE_DISABLE; 800c584: 687b ldr r3, [r7, #4] 800c586: 2200 movs r2, #0 800c588: 665a str r2, [r3, #100] ; 0x64 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 800c58a: 687b ldr r3, [r7, #4] 800c58c: 681b ldr r3, [r3, #0] 800c58e: 68fa ldr r2, [r7, #12] 800c590: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 800c592: 687b ldr r3, [r7, #4] 800c594: 2220 movs r2, #32 800c596: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Process Unlocked */ __HAL_UNLOCK(huart); 800c59a: 687b ldr r3, [r7, #4] 800c59c: 2200 movs r2, #0 800c59e: f883 2080 strb.w r2, [r3, #128] ; 0x80 return HAL_OK; 800c5a2: 2300 movs r3, #0 } 800c5a4: 4618 mov r0, r3 800c5a6: 3714 adds r7, #20 800c5a8: 46bd mov sp, r7 800c5aa: f85d 7b04 ldr.w r7, [sp], #4 800c5ae: 4770 bx lr 0800c5b0 : * @arg @ref UART_TXFIFO_THRESHOLD_7_8 * @arg @ref UART_TXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 800c5b0: b580 push {r7, lr} 800c5b2: b084 sub sp, #16 800c5b4: af00 add r7, sp, #0 800c5b6: 6078 str r0, [r7, #4] 800c5b8: 6039 str r1, [r7, #0] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 800c5ba: 687b ldr r3, [r7, #4] 800c5bc: f893 3080 ldrb.w r3, [r3, #128] ; 0x80 800c5c0: 2b01 cmp r3, #1 800c5c2: d101 bne.n 800c5c8 800c5c4: 2302 movs r3, #2 800c5c6: e02d b.n 800c624 800c5c8: 687b ldr r3, [r7, #4] 800c5ca: 2201 movs r2, #1 800c5cc: f883 2080 strb.w r2, [r3, #128] ; 0x80 huart->gState = HAL_UART_STATE_BUSY; 800c5d0: 687b ldr r3, [r7, #4] 800c5d2: 2224 movs r2, #36 ; 0x24 800c5d4: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 800c5d8: 687b ldr r3, [r7, #4] 800c5da: 681b ldr r3, [r3, #0] 800c5dc: 681b ldr r3, [r3, #0] 800c5de: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 800c5e0: 687b ldr r3, [r7, #4] 800c5e2: 681b ldr r3, [r3, #0] 800c5e4: 681a ldr r2, [r3, #0] 800c5e6: 687b ldr r3, [r7, #4] 800c5e8: 681b ldr r3, [r3, #0] 800c5ea: f022 0201 bic.w r2, r2, #1 800c5ee: 601a str r2, [r3, #0] /* Update TX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); 800c5f0: 687b ldr r3, [r7, #4] 800c5f2: 681b ldr r3, [r3, #0] 800c5f4: 689b ldr r3, [r3, #8] 800c5f6: f023 4160 bic.w r1, r3, #3758096384 ; 0xe0000000 800c5fa: 687b ldr r3, [r7, #4] 800c5fc: 681b ldr r3, [r3, #0] 800c5fe: 683a ldr r2, [r7, #0] 800c600: 430a orrs r2, r1 800c602: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 800c604: 6878 ldr r0, [r7, #4] 800c606: f000 f84f bl 800c6a8 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 800c60a: 687b ldr r3, [r7, #4] 800c60c: 681b ldr r3, [r3, #0] 800c60e: 68fa ldr r2, [r7, #12] 800c610: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 800c612: 687b ldr r3, [r7, #4] 800c614: 2220 movs r2, #32 800c616: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Process Unlocked */ __HAL_UNLOCK(huart); 800c61a: 687b ldr r3, [r7, #4] 800c61c: 2200 movs r2, #0 800c61e: f883 2080 strb.w r2, [r3, #128] ; 0x80 return HAL_OK; 800c622: 2300 movs r3, #0 } 800c624: 4618 mov r0, r3 800c626: 3710 adds r7, #16 800c628: 46bd mov sp, r7 800c62a: bd80 pop {r7, pc} 0800c62c : * @arg @ref UART_RXFIFO_THRESHOLD_7_8 * @arg @ref UART_RXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 800c62c: b580 push {r7, lr} 800c62e: b084 sub sp, #16 800c630: af00 add r7, sp, #0 800c632: 6078 str r0, [r7, #4] 800c634: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 800c636: 687b ldr r3, [r7, #4] 800c638: f893 3080 ldrb.w r3, [r3, #128] ; 0x80 800c63c: 2b01 cmp r3, #1 800c63e: d101 bne.n 800c644 800c640: 2302 movs r3, #2 800c642: e02d b.n 800c6a0 800c644: 687b ldr r3, [r7, #4] 800c646: 2201 movs r2, #1 800c648: f883 2080 strb.w r2, [r3, #128] ; 0x80 huart->gState = HAL_UART_STATE_BUSY; 800c64c: 687b ldr r3, [r7, #4] 800c64e: 2224 movs r2, #36 ; 0x24 800c650: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 800c654: 687b ldr r3, [r7, #4] 800c656: 681b ldr r3, [r3, #0] 800c658: 681b ldr r3, [r3, #0] 800c65a: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 800c65c: 687b ldr r3, [r7, #4] 800c65e: 681b ldr r3, [r3, #0] 800c660: 681a ldr r2, [r3, #0] 800c662: 687b ldr r3, [r7, #4] 800c664: 681b ldr r3, [r3, #0] 800c666: f022 0201 bic.w r2, r2, #1 800c66a: 601a str r2, [r3, #0] /* Update RX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); 800c66c: 687b ldr r3, [r7, #4] 800c66e: 681b ldr r3, [r3, #0] 800c670: 689b ldr r3, [r3, #8] 800c672: f023 6160 bic.w r1, r3, #234881024 ; 0xe000000 800c676: 687b ldr r3, [r7, #4] 800c678: 681b ldr r3, [r3, #0] 800c67a: 683a ldr r2, [r7, #0] 800c67c: 430a orrs r2, r1 800c67e: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 800c680: 6878 ldr r0, [r7, #4] 800c682: f000 f811 bl 800c6a8 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 800c686: 687b ldr r3, [r7, #4] 800c688: 681b ldr r3, [r3, #0] 800c68a: 68fa ldr r2, [r7, #12] 800c68c: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 800c68e: 687b ldr r3, [r7, #4] 800c690: 2220 movs r2, #32 800c692: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Process Unlocked */ __HAL_UNLOCK(huart); 800c696: 687b ldr r3, [r7, #4] 800c698: 2200 movs r2, #0 800c69a: f883 2080 strb.w r2, [r3, #128] ; 0x80 return HAL_OK; 800c69e: 2300 movs r3, #0 } 800c6a0: 4618 mov r0, r3 800c6a2: 3710 adds r7, #16 800c6a4: 46bd mov sp, r7 800c6a6: bd80 pop {r7, pc} 0800c6a8 : * the UART configuration registers. * @param huart UART handle. * @retval None */ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) { 800c6a8: b480 push {r7} 800c6aa: b085 sub sp, #20 800c6ac: af00 add r7, sp, #0 800c6ae: 6078 str r0, [r7, #4] uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) 800c6b0: 687b ldr r3, [r7, #4] 800c6b2: 6e5b ldr r3, [r3, #100] ; 0x64 800c6b4: 2b00 cmp r3, #0 800c6b6: d108 bne.n 800c6ca { huart->NbTxDataToProcess = 1U; 800c6b8: 687b ldr r3, [r7, #4] 800c6ba: 2201 movs r2, #1 800c6bc: f8a3 206a strh.w r2, [r3, #106] ; 0x6a huart->NbRxDataToProcess = 1U; 800c6c0: 687b ldr r3, [r7, #4] 800c6c2: 2201 movs r2, #1 800c6c4: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } 800c6c8: e031 b.n 800c72e rx_fifo_depth = RX_FIFO_DEPTH; 800c6ca: 2310 movs r3, #16 800c6cc: 73fb strb r3, [r7, #15] tx_fifo_depth = TX_FIFO_DEPTH; 800c6ce: 2310 movs r3, #16 800c6d0: 73bb strb r3, [r7, #14] rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); 800c6d2: 687b ldr r3, [r7, #4] 800c6d4: 681b ldr r3, [r3, #0] 800c6d6: 689b ldr r3, [r3, #8] 800c6d8: 0e5b lsrs r3, r3, #25 800c6da: b2db uxtb r3, r3 800c6dc: f003 0307 and.w r3, r3, #7 800c6e0: 737b strb r3, [r7, #13] tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); 800c6e2: 687b ldr r3, [r7, #4] 800c6e4: 681b ldr r3, [r3, #0] 800c6e6: 689b ldr r3, [r3, #8] 800c6e8: 0f5b lsrs r3, r3, #29 800c6ea: b2db uxtb r3, r3 800c6ec: f003 0307 and.w r3, r3, #7 800c6f0: 733b strb r3, [r7, #12] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 800c6f2: 7bbb ldrb r3, [r7, #14] 800c6f4: 7b3a ldrb r2, [r7, #12] 800c6f6: 4911 ldr r1, [pc, #68] ; (800c73c ) 800c6f8: 5c8a ldrb r2, [r1, r2] 800c6fa: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[tx_fifo_threshold]; 800c6fe: 7b3a ldrb r2, [r7, #12] 800c700: 490f ldr r1, [pc, #60] ; (800c740 ) 800c702: 5c8a ldrb r2, [r1, r2] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 800c704: fb93 f3f2 sdiv r3, r3, r2 800c708: b29a uxth r2, r3 800c70a: 687b ldr r3, [r7, #4] 800c70c: f8a3 206a strh.w r2, [r3, #106] ; 0x6a huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 800c710: 7bfb ldrb r3, [r7, #15] 800c712: 7b7a ldrb r2, [r7, #13] 800c714: 4909 ldr r1, [pc, #36] ; (800c73c ) 800c716: 5c8a ldrb r2, [r1, r2] 800c718: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[rx_fifo_threshold]; 800c71c: 7b7a ldrb r2, [r7, #13] 800c71e: 4908 ldr r1, [pc, #32] ; (800c740 ) 800c720: 5c8a ldrb r2, [r1, r2] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 800c722: fb93 f3f2 sdiv r3, r3, r2 800c726: b29a uxth r2, r3 800c728: 687b ldr r3, [r7, #4] 800c72a: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 } 800c72e: bf00 nop 800c730: 3714 adds r7, #20 800c732: 46bd mov sp, r7 800c734: f85d 7b04 ldr.w r7, [sp], #4 800c738: 4770 bx lr 800c73a: bf00 nop 800c73c: 0800e67c .word 0x0800e67c 800c740: 0800e684 .word 0x0800e684 0800c744 : * parameters in the USART_InitTypeDef and initialize the associated handle. * @param husart USART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) { 800c744: b580 push {r7, lr} 800c746: b082 sub sp, #8 800c748: af00 add r7, sp, #0 800c74a: 6078 str r0, [r7, #4] /* Check the USART handle allocation */ if (husart == NULL) 800c74c: 687b ldr r3, [r7, #4] 800c74e: 2b00 cmp r3, #0 800c750: d101 bne.n 800c756 { return HAL_ERROR; 800c752: 2301 movs r3, #1 800c754: e03c b.n 800c7d0 } /* Check the parameters */ assert_param(IS_USART_INSTANCE(husart->Instance)); if (husart->State == HAL_USART_STATE_RESET) 800c756: 687b ldr r3, [r7, #4] 800c758: f893 3059 ldrb.w r3, [r3, #89] ; 0x59 800c75c: b2db uxtb r3, r3 800c75e: 2b00 cmp r3, #0 800c760: d106 bne.n 800c770 { /* Allocate lock resource and initialize it */ husart->Lock = HAL_UNLOCKED; 800c762: 687b ldr r3, [r7, #4] 800c764: 2200 movs r2, #0 800c766: f883 2058 strb.w r2, [r3, #88] ; 0x58 /* Init the low level hardware */ husart->MspInitCallback(husart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_USART_MspInit(husart); 800c76a: 6878 ldr r0, [r7, #4] 800c76c: f7f5 fe9e bl 80024ac #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } husart->State = HAL_USART_STATE_BUSY; 800c770: 687b ldr r3, [r7, #4] 800c772: 2202 movs r2, #2 800c774: f883 2059 strb.w r2, [r3, #89] ; 0x59 /* Disable the Peripheral */ __HAL_USART_DISABLE(husart); 800c778: 687b ldr r3, [r7, #4] 800c77a: 681b ldr r3, [r3, #0] 800c77c: 681a ldr r2, [r3, #0] 800c77e: 687b ldr r3, [r7, #4] 800c780: 681b ldr r3, [r3, #0] 800c782: f022 0201 bic.w r2, r2, #1 800c786: 601a str r2, [r3, #0] /* Set the Usart Communication parameters */ if (USART_SetConfig(husart) == HAL_ERROR) 800c788: 6878 ldr r0, [r7, #4] 800c78a: f000 f85b bl 800c844 800c78e: 4603 mov r3, r0 800c790: 2b01 cmp r3, #1 800c792: d101 bne.n 800c798 { return HAL_ERROR; 800c794: 2301 movs r3, #1 800c796: e01b b.n 800c7d0 /* In Synchronous mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register - HDSEL, SCEN and IREN bits in the USART_CR3 register. */ husart->Instance->CR2 &= ~USART_CR2_LINEN; 800c798: 687b ldr r3, [r7, #4] 800c79a: 681b ldr r3, [r3, #0] 800c79c: 685a ldr r2, [r3, #4] 800c79e: 687b ldr r3, [r7, #4] 800c7a0: 681b ldr r3, [r3, #0] 800c7a2: f422 4280 bic.w r2, r2, #16384 ; 0x4000 800c7a6: 605a str r2, [r3, #4] husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); 800c7a8: 687b ldr r3, [r7, #4] 800c7aa: 681b ldr r3, [r3, #0] 800c7ac: 689a ldr r2, [r3, #8] 800c7ae: 687b ldr r3, [r7, #4] 800c7b0: 681b ldr r3, [r3, #0] 800c7b2: f022 022a bic.w r2, r2, #42 ; 0x2a 800c7b6: 609a str r2, [r3, #8] /* Enable the Peripheral */ __HAL_USART_ENABLE(husart); 800c7b8: 687b ldr r3, [r7, #4] 800c7ba: 681b ldr r3, [r3, #0] 800c7bc: 681a ldr r2, [r3, #0] 800c7be: 687b ldr r3, [r7, #4] 800c7c0: 681b ldr r3, [r3, #0] 800c7c2: f042 0201 orr.w r2, r2, #1 800c7c6: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving husart->State to Ready */ return (USART_CheckIdleState(husart)); 800c7c8: 6878 ldr r0, [r7, #4] 800c7ca: f000 fddd bl 800d388 800c7ce: 4603 mov r3, r0 } 800c7d0: 4618 mov r0, r3 800c7d2: 3708 adds r7, #8 800c7d4: 46bd mov sp, r7 800c7d6: bd80 pop {r7, pc} 0800c7d8 : * @param Timeout timeout duration. * @retval HAL status */ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 800c7d8: b580 push {r7, lr} 800c7da: b084 sub sp, #16 800c7dc: af00 add r7, sp, #0 800c7de: 60f8 str r0, [r7, #12] 800c7e0: 60b9 str r1, [r7, #8] 800c7e2: 603b str r3, [r7, #0] 800c7e4: 4613 mov r3, r2 800c7e6: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status) 800c7e8: e018 b.n 800c81c { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 800c7ea: 69bb ldr r3, [r7, #24] 800c7ec: f1b3 3fff cmp.w r3, #4294967295 800c7f0: d014 beq.n 800c81c { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 800c7f2: f7f6 fcf9 bl 80031e8 800c7f6: 4602 mov r2, r0 800c7f8: 683b ldr r3, [r7, #0] 800c7fa: 1ad3 subs r3, r2, r3 800c7fc: 69ba ldr r2, [r7, #24] 800c7fe: 429a cmp r2, r3 800c800: d302 bcc.n 800c808 800c802: 69bb ldr r3, [r7, #24] 800c804: 2b00 cmp r3, #0 800c806: d109 bne.n 800c81c { husart->State = HAL_USART_STATE_READY; 800c808: 68fb ldr r3, [r7, #12] 800c80a: 2201 movs r2, #1 800c80c: f883 2059 strb.w r2, [r3, #89] ; 0x59 /* Process Unlocked */ __HAL_UNLOCK(husart); 800c810: 68fb ldr r3, [r7, #12] 800c812: 2200 movs r2, #0 800c814: f883 2058 strb.w r2, [r3, #88] ; 0x58 return HAL_TIMEOUT; 800c818: 2303 movs r3, #3 800c81a: e00f b.n 800c83c while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status) 800c81c: 68fb ldr r3, [r7, #12] 800c81e: 681b ldr r3, [r3, #0] 800c820: 69da ldr r2, [r3, #28] 800c822: 68bb ldr r3, [r7, #8] 800c824: 4013 ands r3, r2 800c826: 68ba ldr r2, [r7, #8] 800c828: 429a cmp r2, r3 800c82a: bf0c ite eq 800c82c: 2301 moveq r3, #1 800c82e: 2300 movne r3, #0 800c830: b2db uxtb r3, r3 800c832: 461a mov r2, r3 800c834: 79fb ldrb r3, [r7, #7] 800c836: 429a cmp r2, r3 800c838: d0d7 beq.n 800c7ea } } } return HAL_OK; 800c83a: 2300 movs r3, #0 } 800c83c: 4618 mov r0, r3 800c83e: 3710 adds r7, #16 800c840: 46bd mov sp, r7 800c842: bd80 pop {r7, pc} 0800c844 : * @brief Configure the USART peripheral. * @param husart USART handle. * @retval HAL status */ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) { 800c844: b580 push {r7, lr} 800c846: b08e sub sp, #56 ; 0x38 800c848: af00 add r7, sp, #0 800c84a: 6078 str r0, [r7, #4] uint32_t tmpreg; USART_ClockSourceTypeDef clocksource; HAL_StatusTypeDef ret = HAL_OK; 800c84c: 2300 movs r3, #0 800c84e: f887 3036 strb.w r3, [r7, #54] ; 0x36 uint16_t brrtemp; uint32_t usartdiv = 0x00000000; 800c852: 2300 movs r3, #0 800c854: 633b str r3, [r7, #48] ; 0x30 * the USART Word Length, Parity and Mode: * set the M bits according to husart->Init.WordLength value * set PCE and PS bits according to husart->Init.Parity value * set TE and RE bits according to husart->Init.Mode value * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */ tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8; 800c856: 687b ldr r3, [r7, #4] 800c858: 689a ldr r2, [r3, #8] 800c85a: 687b ldr r3, [r7, #4] 800c85c: 691b ldr r3, [r3, #16] 800c85e: 431a orrs r2, r3 800c860: 687b ldr r3, [r7, #4] 800c862: 695b ldr r3, [r3, #20] 800c864: 4313 orrs r3, r2 800c866: f443 4300 orr.w r3, r3, #32768 ; 0x8000 800c86a: 62fb str r3, [r7, #44] ; 0x2c MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 800c86c: 687b ldr r3, [r7, #4] 800c86e: 681b ldr r3, [r3, #0] 800c870: 681a ldr r2, [r3, #0] 800c872: 4bc9 ldr r3, [pc, #804] ; (800cb98 ) 800c874: 4013 ands r3, r2 800c876: 687a ldr r2, [r7, #4] 800c878: 6812 ldr r2, [r2, #0] 800c87a: 6af9 ldr r1, [r7, #44] ; 0x2c 800c87c: 430b orrs r3, r1 800c87e: 6013 str r3, [r2, #0] /* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits: * set CPOL bit according to husart->Init.CLKPolarity value * set CPHA bit according to husart->Init.CLKPhase value * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only) * set STOP[13:12] bits according to husart->Init.StopBits value */ tmpreg = (uint32_t)(USART_CLOCK_ENABLE); 800c880: f44f 6300 mov.w r3, #2048 ; 0x800 800c884: 62fb str r3, [r7, #44] ; 0x2c tmpreg |= (uint32_t)husart->Init.CLKLastBit; 800c886: 687b ldr r3, [r7, #4] 800c888: 6a1b ldr r3, [r3, #32] 800c88a: 6afa ldr r2, [r7, #44] ; 0x2c 800c88c: 4313 orrs r3, r2 800c88e: 62fb str r3, [r7, #44] ; 0x2c tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase); 800c890: 687b ldr r3, [r7, #4] 800c892: 699a ldr r2, [r3, #24] 800c894: 687b ldr r3, [r7, #4] 800c896: 69db ldr r3, [r3, #28] 800c898: 4313 orrs r3, r2 800c89a: 6afa ldr r2, [r7, #44] ; 0x2c 800c89c: 4313 orrs r3, r2 800c89e: 62fb str r3, [r7, #44] ; 0x2c tmpreg |= (uint32_t)husart->Init.StopBits; 800c8a0: 687b ldr r3, [r7, #4] 800c8a2: 68db ldr r3, [r3, #12] 800c8a4: 6afa ldr r2, [r7, #44] ; 0x2c 800c8a6: 4313 orrs r3, r2 800c8a8: 62fb str r3, [r7, #44] ; 0x2c MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg); 800c8aa: 687b ldr r3, [r7, #4] 800c8ac: 681b ldr r3, [r3, #0] 800c8ae: 685a ldr r2, [r3, #4] 800c8b0: 4bba ldr r3, [pc, #744] ; (800cb9c ) 800c8b2: 4013 ands r3, r2 800c8b4: 687a ldr r2, [r7, #4] 800c8b6: 6812 ldr r2, [r2, #0] 800c8b8: 6af9 ldr r1, [r7, #44] ; 0x2c 800c8ba: 430b orrs r3, r1 800c8bc: 6053 str r3, [r2, #4] /*-------------------------- USART PRESC Configuration -----------------------*/ /* Configure * - USART Clock Prescaler : set PRESCALER according to husart->Init.ClockPrescaler value */ MODIFY_REG(husart->Instance->PRESC, USART_PRESC_PRESCALER, husart->Init.ClockPrescaler); 800c8be: 687b ldr r3, [r7, #4] 800c8c0: 681b ldr r3, [r3, #0] 800c8c2: 6adb ldr r3, [r3, #44] ; 0x2c 800c8c4: f023 010f bic.w r1, r3, #15 800c8c8: 687b ldr r3, [r7, #4] 800c8ca: 6a5a ldr r2, [r3, #36] ; 0x24 800c8cc: 687b ldr r3, [r7, #4] 800c8ce: 681b ldr r3, [r3, #0] 800c8d0: 430a orrs r2, r1 800c8d2: 62da str r2, [r3, #44] ; 0x2c /*-------------------------- USART BRR Configuration -----------------------*/ /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */ USART_GETCLOCKSOURCE(husart, clocksource); 800c8d4: 687b ldr r3, [r7, #4] 800c8d6: 681b ldr r3, [r3, #0] 800c8d8: 4ab1 ldr r2, [pc, #708] ; (800cba0 ) 800c8da: 4293 cmp r3, r2 800c8dc: d176 bne.n 800c9cc 800c8de: 4bb1 ldr r3, [pc, #708] ; (800cba4 ) 800c8e0: 6d5b ldr r3, [r3, #84] ; 0x54 800c8e2: f003 0338 and.w r3, r3, #56 ; 0x38 800c8e6: 2b28 cmp r3, #40 ; 0x28 800c8e8: d86c bhi.n 800c9c4 800c8ea: a201 add r2, pc, #4 ; (adr r2, 800c8f0 ) 800c8ec: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c8f0: 0800c995 .word 0x0800c995 800c8f4: 0800c9c5 .word 0x0800c9c5 800c8f8: 0800c9c5 .word 0x0800c9c5 800c8fc: 0800c9c5 .word 0x0800c9c5 800c900: 0800c9c5 .word 0x0800c9c5 800c904: 0800c9c5 .word 0x0800c9c5 800c908: 0800c9c5 .word 0x0800c9c5 800c90c: 0800c9c5 .word 0x0800c9c5 800c910: 0800c99d .word 0x0800c99d 800c914: 0800c9c5 .word 0x0800c9c5 800c918: 0800c9c5 .word 0x0800c9c5 800c91c: 0800c9c5 .word 0x0800c9c5 800c920: 0800c9c5 .word 0x0800c9c5 800c924: 0800c9c5 .word 0x0800c9c5 800c928: 0800c9c5 .word 0x0800c9c5 800c92c: 0800c9c5 .word 0x0800c9c5 800c930: 0800c9a5 .word 0x0800c9a5 800c934: 0800c9c5 .word 0x0800c9c5 800c938: 0800c9c5 .word 0x0800c9c5 800c93c: 0800c9c5 .word 0x0800c9c5 800c940: 0800c9c5 .word 0x0800c9c5 800c944: 0800c9c5 .word 0x0800c9c5 800c948: 0800c9c5 .word 0x0800c9c5 800c94c: 0800c9c5 .word 0x0800c9c5 800c950: 0800c9ad .word 0x0800c9ad 800c954: 0800c9c5 .word 0x0800c9c5 800c958: 0800c9c5 .word 0x0800c9c5 800c95c: 0800c9c5 .word 0x0800c9c5 800c960: 0800c9c5 .word 0x0800c9c5 800c964: 0800c9c5 .word 0x0800c9c5 800c968: 0800c9c5 .word 0x0800c9c5 800c96c: 0800c9c5 .word 0x0800c9c5 800c970: 0800c9b5 .word 0x0800c9b5 800c974: 0800c9c5 .word 0x0800c9c5 800c978: 0800c9c5 .word 0x0800c9c5 800c97c: 0800c9c5 .word 0x0800c9c5 800c980: 0800c9c5 .word 0x0800c9c5 800c984: 0800c9c5 .word 0x0800c9c5 800c988: 0800c9c5 .word 0x0800c9c5 800c98c: 0800c9c5 .word 0x0800c9c5 800c990: 0800c9bd .word 0x0800c9bd 800c994: 2301 movs r3, #1 800c996: f887 3037 strb.w r3, [r7, #55] ; 0x37 800c99a: e18e b.n 800ccba 800c99c: 2302 movs r3, #2 800c99e: f887 3037 strb.w r3, [r7, #55] ; 0x37 800c9a2: e18a b.n 800ccba 800c9a4: 2304 movs r3, #4 800c9a6: f887 3037 strb.w r3, [r7, #55] ; 0x37 800c9aa: e186 b.n 800ccba 800c9ac: 2308 movs r3, #8 800c9ae: f887 3037 strb.w r3, [r7, #55] ; 0x37 800c9b2: e182 b.n 800ccba 800c9b4: 2310 movs r3, #16 800c9b6: f887 3037 strb.w r3, [r7, #55] ; 0x37 800c9ba: e17e b.n 800ccba 800c9bc: 2320 movs r3, #32 800c9be: f887 3037 strb.w r3, [r7, #55] ; 0x37 800c9c2: e17a b.n 800ccba 800c9c4: 2340 movs r3, #64 ; 0x40 800c9c6: f887 3037 strb.w r3, [r7, #55] ; 0x37 800c9ca: e176 b.n 800ccba 800c9cc: 687b ldr r3, [r7, #4] 800c9ce: 681b ldr r3, [r3, #0] 800c9d0: 4a75 ldr r2, [pc, #468] ; (800cba8 ) 800c9d2: 4293 cmp r3, r2 800c9d4: d130 bne.n 800ca38 800c9d6: 4b73 ldr r3, [pc, #460] ; (800cba4 ) 800c9d8: 6d5b ldr r3, [r3, #84] ; 0x54 800c9da: f003 0307 and.w r3, r3, #7 800c9de: 2b05 cmp r3, #5 800c9e0: d826 bhi.n 800ca30 800c9e2: a201 add r2, pc, #4 ; (adr r2, 800c9e8 ) 800c9e4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c9e8: 0800ca01 .word 0x0800ca01 800c9ec: 0800ca09 .word 0x0800ca09 800c9f0: 0800ca11 .word 0x0800ca11 800c9f4: 0800ca19 .word 0x0800ca19 800c9f8: 0800ca21 .word 0x0800ca21 800c9fc: 0800ca29 .word 0x0800ca29 800ca00: 2300 movs r3, #0 800ca02: f887 3037 strb.w r3, [r7, #55] ; 0x37 800ca06: e158 b.n 800ccba 800ca08: 2302 movs r3, #2 800ca0a: f887 3037 strb.w r3, [r7, #55] ; 0x37 800ca0e: e154 b.n 800ccba 800ca10: 2304 movs r3, #4 800ca12: f887 3037 strb.w r3, [r7, #55] ; 0x37 800ca16: e150 b.n 800ccba 800ca18: 2308 movs r3, #8 800ca1a: f887 3037 strb.w r3, [r7, #55] ; 0x37 800ca1e: e14c b.n 800ccba 800ca20: 2310 movs r3, #16 800ca22: f887 3037 strb.w r3, [r7, #55] ; 0x37 800ca26: e148 b.n 800ccba 800ca28: 2320 movs r3, #32 800ca2a: f887 3037 strb.w r3, [r7, #55] ; 0x37 800ca2e: e144 b.n 800ccba 800ca30: 2340 movs r3, #64 ; 0x40 800ca32: f887 3037 strb.w r3, [r7, #55] ; 0x37 800ca36: e140 b.n 800ccba 800ca38: 687b ldr r3, [r7, #4] 800ca3a: 681b ldr r3, [r3, #0] 800ca3c: 4a5b ldr r2, [pc, #364] ; (800cbac ) 800ca3e: 4293 cmp r3, r2 800ca40: d130 bne.n 800caa4 800ca42: 4b58 ldr r3, [pc, #352] ; (800cba4 ) 800ca44: 6d5b ldr r3, [r3, #84] ; 0x54 800ca46: f003 0307 and.w r3, r3, #7 800ca4a: 2b05 cmp r3, #5 800ca4c: d826 bhi.n 800ca9c 800ca4e: a201 add r2, pc, #4 ; (adr r2, 800ca54 ) 800ca50: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800ca54: 0800ca6d .word 0x0800ca6d 800ca58: 0800ca75 .word 0x0800ca75 800ca5c: 0800ca7d .word 0x0800ca7d 800ca60: 0800ca85 .word 0x0800ca85 800ca64: 0800ca8d .word 0x0800ca8d 800ca68: 0800ca95 .word 0x0800ca95 800ca6c: 2300 movs r3, #0 800ca6e: f887 3037 strb.w r3, [r7, #55] ; 0x37 800ca72: e122 b.n 800ccba 800ca74: 2302 movs r3, #2 800ca76: f887 3037 strb.w r3, [r7, #55] ; 0x37 800ca7a: e11e b.n 800ccba 800ca7c: 2304 movs r3, #4 800ca7e: f887 3037 strb.w r3, [r7, #55] ; 0x37 800ca82: e11a b.n 800ccba 800ca84: 2308 movs r3, #8 800ca86: f887 3037 strb.w r3, [r7, #55] ; 0x37 800ca8a: e116 b.n 800ccba 800ca8c: 2310 movs r3, #16 800ca8e: f887 3037 strb.w r3, [r7, #55] ; 0x37 800ca92: e112 b.n 800ccba 800ca94: 2320 movs r3, #32 800ca96: f887 3037 strb.w r3, [r7, #55] ; 0x37 800ca9a: e10e b.n 800ccba 800ca9c: 2340 movs r3, #64 ; 0x40 800ca9e: f887 3037 strb.w r3, [r7, #55] ; 0x37 800caa2: e10a b.n 800ccba 800caa4: 687b ldr r3, [r7, #4] 800caa6: 681b ldr r3, [r3, #0] 800caa8: 4a41 ldr r2, [pc, #260] ; (800cbb0 ) 800caaa: 4293 cmp r3, r2 800caac: f040 8086 bne.w 800cbbc 800cab0: 4b3c ldr r3, [pc, #240] ; (800cba4 ) 800cab2: 6d5b ldr r3, [r3, #84] ; 0x54 800cab4: f003 0338 and.w r3, r3, #56 ; 0x38 800cab8: 2b28 cmp r3, #40 ; 0x28 800caba: d87b bhi.n 800cbb4 800cabc: a201 add r2, pc, #4 ; (adr r2, 800cac4 ) 800cabe: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800cac2: bf00 nop 800cac4: 0800cb69 .word 0x0800cb69 800cac8: 0800cbb5 .word 0x0800cbb5 800cacc: 0800cbb5 .word 0x0800cbb5 800cad0: 0800cbb5 .word 0x0800cbb5 800cad4: 0800cbb5 .word 0x0800cbb5 800cad8: 0800cbb5 .word 0x0800cbb5 800cadc: 0800cbb5 .word 0x0800cbb5 800cae0: 0800cbb5 .word 0x0800cbb5 800cae4: 0800cb71 .word 0x0800cb71 800cae8: 0800cbb5 .word 0x0800cbb5 800caec: 0800cbb5 .word 0x0800cbb5 800caf0: 0800cbb5 .word 0x0800cbb5 800caf4: 0800cbb5 .word 0x0800cbb5 800caf8: 0800cbb5 .word 0x0800cbb5 800cafc: 0800cbb5 .word 0x0800cbb5 800cb00: 0800cbb5 .word 0x0800cbb5 800cb04: 0800cb79 .word 0x0800cb79 800cb08: 0800cbb5 .word 0x0800cbb5 800cb0c: 0800cbb5 .word 0x0800cbb5 800cb10: 0800cbb5 .word 0x0800cbb5 800cb14: 0800cbb5 .word 0x0800cbb5 800cb18: 0800cbb5 .word 0x0800cbb5 800cb1c: 0800cbb5 .word 0x0800cbb5 800cb20: 0800cbb5 .word 0x0800cbb5 800cb24: 0800cb81 .word 0x0800cb81 800cb28: 0800cbb5 .word 0x0800cbb5 800cb2c: 0800cbb5 .word 0x0800cbb5 800cb30: 0800cbb5 .word 0x0800cbb5 800cb34: 0800cbb5 .word 0x0800cbb5 800cb38: 0800cbb5 .word 0x0800cbb5 800cb3c: 0800cbb5 .word 0x0800cbb5 800cb40: 0800cbb5 .word 0x0800cbb5 800cb44: 0800cb89 .word 0x0800cb89 800cb48: 0800cbb5 .word 0x0800cbb5 800cb4c: 0800cbb5 .word 0x0800cbb5 800cb50: 0800cbb5 .word 0x0800cbb5 800cb54: 0800cbb5 .word 0x0800cbb5 800cb58: 0800cbb5 .word 0x0800cbb5 800cb5c: 0800cbb5 .word 0x0800cbb5 800cb60: 0800cbb5 .word 0x0800cbb5 800cb64: 0800cb91 .word 0x0800cb91 800cb68: 2301 movs r3, #1 800cb6a: f887 3037 strb.w r3, [r7, #55] ; 0x37 800cb6e: e0a4 b.n 800ccba 800cb70: 2302 movs r3, #2 800cb72: f887 3037 strb.w r3, [r7, #55] ; 0x37 800cb76: e0a0 b.n 800ccba 800cb78: 2304 movs r3, #4 800cb7a: f887 3037 strb.w r3, [r7, #55] ; 0x37 800cb7e: e09c b.n 800ccba 800cb80: 2308 movs r3, #8 800cb82: f887 3037 strb.w r3, [r7, #55] ; 0x37 800cb86: e098 b.n 800ccba 800cb88: 2310 movs r3, #16 800cb8a: f887 3037 strb.w r3, [r7, #55] ; 0x37 800cb8e: e094 b.n 800ccba 800cb90: 2320 movs r3, #32 800cb92: f887 3037 strb.w r3, [r7, #55] ; 0x37 800cb96: e090 b.n 800ccba 800cb98: cfff69f3 .word 0xcfff69f3 800cb9c: ffffc0f6 .word 0xffffc0f6 800cba0: 40011000 .word 0x40011000 800cba4: 58024400 .word 0x58024400 800cba8: 40004400 .word 0x40004400 800cbac: 40004800 .word 0x40004800 800cbb0: 40011400 .word 0x40011400 800cbb4: 2340 movs r3, #64 ; 0x40 800cbb6: f887 3037 strb.w r3, [r7, #55] ; 0x37 800cbba: e07e b.n 800ccba 800cbbc: 687b ldr r3, [r7, #4] 800cbbe: 681b ldr r3, [r3, #0] 800cbc0: 4ab7 ldr r2, [pc, #732] ; (800cea0 ) 800cbc2: 4293 cmp r3, r2 800cbc4: d176 bne.n 800ccb4 800cbc6: 4bb7 ldr r3, [pc, #732] ; (800cea4 ) 800cbc8: 6d5b ldr r3, [r3, #84] ; 0x54 800cbca: f003 0338 and.w r3, r3, #56 ; 0x38 800cbce: 2b28 cmp r3, #40 ; 0x28 800cbd0: d86c bhi.n 800ccac 800cbd2: a201 add r2, pc, #4 ; (adr r2, 800cbd8 ) 800cbd4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800cbd8: 0800cc7d .word 0x0800cc7d 800cbdc: 0800ccad .word 0x0800ccad 800cbe0: 0800ccad .word 0x0800ccad 800cbe4: 0800ccad .word 0x0800ccad 800cbe8: 0800ccad .word 0x0800ccad 800cbec: 0800ccad .word 0x0800ccad 800cbf0: 0800ccad .word 0x0800ccad 800cbf4: 0800ccad .word 0x0800ccad 800cbf8: 0800cc85 .word 0x0800cc85 800cbfc: 0800ccad .word 0x0800ccad 800cc00: 0800ccad .word 0x0800ccad 800cc04: 0800ccad .word 0x0800ccad 800cc08: 0800ccad .word 0x0800ccad 800cc0c: 0800ccad .word 0x0800ccad 800cc10: 0800ccad .word 0x0800ccad 800cc14: 0800ccad .word 0x0800ccad 800cc18: 0800cc8d .word 0x0800cc8d 800cc1c: 0800ccad .word 0x0800ccad 800cc20: 0800ccad .word 0x0800ccad 800cc24: 0800ccad .word 0x0800ccad 800cc28: 0800ccad .word 0x0800ccad 800cc2c: 0800ccad .word 0x0800ccad 800cc30: 0800ccad .word 0x0800ccad 800cc34: 0800ccad .word 0x0800ccad 800cc38: 0800cc95 .word 0x0800cc95 800cc3c: 0800ccad .word 0x0800ccad 800cc40: 0800ccad .word 0x0800ccad 800cc44: 0800ccad .word 0x0800ccad 800cc48: 0800ccad .word 0x0800ccad 800cc4c: 0800ccad .word 0x0800ccad 800cc50: 0800ccad .word 0x0800ccad 800cc54: 0800ccad .word 0x0800ccad 800cc58: 0800cc9d .word 0x0800cc9d 800cc5c: 0800ccad .word 0x0800ccad 800cc60: 0800ccad .word 0x0800ccad 800cc64: 0800ccad .word 0x0800ccad 800cc68: 0800ccad .word 0x0800ccad 800cc6c: 0800ccad .word 0x0800ccad 800cc70: 0800ccad .word 0x0800ccad 800cc74: 0800ccad .word 0x0800ccad 800cc78: 0800cca5 .word 0x0800cca5 800cc7c: 2301 movs r3, #1 800cc7e: f887 3037 strb.w r3, [r7, #55] ; 0x37 800cc82: e01a b.n 800ccba 800cc84: 2302 movs r3, #2 800cc86: f887 3037 strb.w r3, [r7, #55] ; 0x37 800cc8a: e016 b.n 800ccba 800cc8c: 2304 movs r3, #4 800cc8e: f887 3037 strb.w r3, [r7, #55] ; 0x37 800cc92: e012 b.n 800ccba 800cc94: 2308 movs r3, #8 800cc96: f887 3037 strb.w r3, [r7, #55] ; 0x37 800cc9a: e00e b.n 800ccba 800cc9c: 2310 movs r3, #16 800cc9e: f887 3037 strb.w r3, [r7, #55] ; 0x37 800cca2: e00a b.n 800ccba 800cca4: 2320 movs r3, #32 800cca6: f887 3037 strb.w r3, [r7, #55] ; 0x37 800ccaa: e006 b.n 800ccba 800ccac: 2340 movs r3, #64 ; 0x40 800ccae: f887 3037 strb.w r3, [r7, #55] ; 0x37 800ccb2: e002 b.n 800ccba 800ccb4: 2340 movs r3, #64 ; 0x40 800ccb6: f887 3037 strb.w r3, [r7, #55] ; 0x37 switch (clocksource) 800ccba: f897 3037 ldrb.w r3, [r7, #55] ; 0x37 800ccbe: 2b20 cmp r3, #32 800ccc0: f200 832f bhi.w 800d322 800ccc4: a201 add r2, pc, #4 ; (adr r2, 800cccc ) 800ccc6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800ccca: bf00 nop 800cccc: 0800cd51 .word 0x0800cd51 800ccd0: 0800ce07 .word 0x0800ce07 800ccd4: 0800cec7 .word 0x0800cec7 800ccd8: 0800d323 .word 0x0800d323 800ccdc: 0800cf81 .word 0x0800cf81 800cce0: 0800d323 .word 0x0800d323 800cce4: 0800d323 .word 0x0800d323 800cce8: 0800d323 .word 0x0800d323 800ccec: 0800d03b .word 0x0800d03b 800ccf0: 0800d323 .word 0x0800d323 800ccf4: 0800d323 .word 0x0800d323 800ccf8: 0800d323 .word 0x0800d323 800ccfc: 0800d323 .word 0x0800d323 800cd00: 0800d323 .word 0x0800d323 800cd04: 0800d323 .word 0x0800d323 800cd08: 0800d323 .word 0x0800d323 800cd0c: 0800d1b3 .word 0x0800d1b3 800cd10: 0800d323 .word 0x0800d323 800cd14: 0800d323 .word 0x0800d323 800cd18: 0800d323 .word 0x0800d323 800cd1c: 0800d323 .word 0x0800d323 800cd20: 0800d323 .word 0x0800d323 800cd24: 0800d323 .word 0x0800d323 800cd28: 0800d323 .word 0x0800d323 800cd2c: 0800d323 .word 0x0800d323 800cd30: 0800d323 .word 0x0800d323 800cd34: 0800d323 .word 0x0800d323 800cd38: 0800d323 .word 0x0800d323 800cd3c: 0800d323 .word 0x0800d323 800cd40: 0800d323 .word 0x0800d323 800cd44: 0800d323 .word 0x0800d323 800cd48: 0800d323 .word 0x0800d323 800cd4c: 0800d271 .word 0x0800d271 { case USART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 800cd50: f7fa fb92 bl 8007478 800cd54: 62b8 str r0, [r7, #40] ; 0x28 usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler)); 800cd56: 687b ldr r3, [r7, #4] 800cd58: 6a5b ldr r3, [r3, #36] ; 0x24 800cd5a: 2b00 cmp r3, #0 800cd5c: d044 beq.n 800cde8 800cd5e: 687b ldr r3, [r7, #4] 800cd60: 6a5b ldr r3, [r3, #36] ; 0x24 800cd62: 2b01 cmp r3, #1 800cd64: d03e beq.n 800cde4 800cd66: 687b ldr r3, [r7, #4] 800cd68: 6a5b ldr r3, [r3, #36] ; 0x24 800cd6a: 2b02 cmp r3, #2 800cd6c: d038 beq.n 800cde0 800cd6e: 687b ldr r3, [r7, #4] 800cd70: 6a5b ldr r3, [r3, #36] ; 0x24 800cd72: 2b03 cmp r3, #3 800cd74: d032 beq.n 800cddc 800cd76: 687b ldr r3, [r7, #4] 800cd78: 6a5b ldr r3, [r3, #36] ; 0x24 800cd7a: 2b04 cmp r3, #4 800cd7c: d02c beq.n 800cdd8 800cd7e: 687b ldr r3, [r7, #4] 800cd80: 6a5b ldr r3, [r3, #36] ; 0x24 800cd82: 2b05 cmp r3, #5 800cd84: d026 beq.n 800cdd4 800cd86: 687b ldr r3, [r7, #4] 800cd88: 6a5b ldr r3, [r3, #36] ; 0x24 800cd8a: 2b06 cmp r3, #6 800cd8c: d020 beq.n 800cdd0 800cd8e: 687b ldr r3, [r7, #4] 800cd90: 6a5b ldr r3, [r3, #36] ; 0x24 800cd92: 2b07 cmp r3, #7 800cd94: d01a beq.n 800cdcc 800cd96: 687b ldr r3, [r7, #4] 800cd98: 6a5b ldr r3, [r3, #36] ; 0x24 800cd9a: 2b08 cmp r3, #8 800cd9c: d014 beq.n 800cdc8 800cd9e: 687b ldr r3, [r7, #4] 800cda0: 6a5b ldr r3, [r3, #36] ; 0x24 800cda2: 2b09 cmp r3, #9 800cda4: d00e beq.n 800cdc4 800cda6: 687b ldr r3, [r7, #4] 800cda8: 6a5b ldr r3, [r3, #36] ; 0x24 800cdaa: 2b0a cmp r3, #10 800cdac: d008 beq.n 800cdc0 800cdae: 687b ldr r3, [r7, #4] 800cdb0: 6a5b ldr r3, [r3, #36] ; 0x24 800cdb2: 2b0b cmp r3, #11 800cdb4: d102 bne.n 800cdbc 800cdb6: f44f 7380 mov.w r3, #256 ; 0x100 800cdba: e016 b.n 800cdea 800cdbc: 2301 movs r3, #1 800cdbe: e014 b.n 800cdea 800cdc0: 2380 movs r3, #128 ; 0x80 800cdc2: e012 b.n 800cdea 800cdc4: 2340 movs r3, #64 ; 0x40 800cdc6: e010 b.n 800cdea 800cdc8: 2320 movs r3, #32 800cdca: e00e b.n 800cdea 800cdcc: 2310 movs r3, #16 800cdce: e00c b.n 800cdea 800cdd0: 230c movs r3, #12 800cdd2: e00a b.n 800cdea 800cdd4: 230a movs r3, #10 800cdd6: e008 b.n 800cdea 800cdd8: 2308 movs r3, #8 800cdda: e006 b.n 800cdea 800cddc: 2306 movs r3, #6 800cdde: e004 b.n 800cdea 800cde0: 2304 movs r3, #4 800cde2: e002 b.n 800cdea 800cde4: 2302 movs r3, #2 800cde6: e000 b.n 800cdea 800cde8: 2301 movs r3, #1 800cdea: 6aba ldr r2, [r7, #40] ; 0x28 800cdec: fbb2 f3f3 udiv r3, r2, r3 800cdf0: 005a lsls r2, r3, #1 800cdf2: 687b ldr r3, [r7, #4] 800cdf4: 685b ldr r3, [r3, #4] 800cdf6: 085b lsrs r3, r3, #1 800cdf8: 441a add r2, r3 800cdfa: 687b ldr r3, [r7, #4] 800cdfc: 685b ldr r3, [r3, #4] 800cdfe: fbb2 f3f3 udiv r3, r2, r3 800ce02: 633b str r3, [r7, #48] ; 0x30 break; 800ce04: e291 b.n 800d32a case USART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 800ce06: f7fa fb4d bl 80074a4 800ce0a: 62b8 str r0, [r7, #40] ; 0x28 usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler)); 800ce0c: 687b ldr r3, [r7, #4] 800ce0e: 6a5b ldr r3, [r3, #36] ; 0x24 800ce10: 2b00 cmp r3, #0 800ce12: d049 beq.n 800cea8 800ce14: 687b ldr r3, [r7, #4] 800ce16: 6a5b ldr r3, [r3, #36] ; 0x24 800ce18: 2b01 cmp r3, #1 800ce1a: d03e beq.n 800ce9a 800ce1c: 687b ldr r3, [r7, #4] 800ce1e: 6a5b ldr r3, [r3, #36] ; 0x24 800ce20: 2b02 cmp r3, #2 800ce22: d038 beq.n 800ce96 800ce24: 687b ldr r3, [r7, #4] 800ce26: 6a5b ldr r3, [r3, #36] ; 0x24 800ce28: 2b03 cmp r3, #3 800ce2a: d032 beq.n 800ce92 800ce2c: 687b ldr r3, [r7, #4] 800ce2e: 6a5b ldr r3, [r3, #36] ; 0x24 800ce30: 2b04 cmp r3, #4 800ce32: d02c beq.n 800ce8e 800ce34: 687b ldr r3, [r7, #4] 800ce36: 6a5b ldr r3, [r3, #36] ; 0x24 800ce38: 2b05 cmp r3, #5 800ce3a: d026 beq.n 800ce8a 800ce3c: 687b ldr r3, [r7, #4] 800ce3e: 6a5b ldr r3, [r3, #36] ; 0x24 800ce40: 2b06 cmp r3, #6 800ce42: d020 beq.n 800ce86 800ce44: 687b ldr r3, [r7, #4] 800ce46: 6a5b ldr r3, [r3, #36] ; 0x24 800ce48: 2b07 cmp r3, #7 800ce4a: d01a beq.n 800ce82 800ce4c: 687b ldr r3, [r7, #4] 800ce4e: 6a5b ldr r3, [r3, #36] ; 0x24 800ce50: 2b08 cmp r3, #8 800ce52: d014 beq.n 800ce7e 800ce54: 687b ldr r3, [r7, #4] 800ce56: 6a5b ldr r3, [r3, #36] ; 0x24 800ce58: 2b09 cmp r3, #9 800ce5a: d00e beq.n 800ce7a 800ce5c: 687b ldr r3, [r7, #4] 800ce5e: 6a5b ldr r3, [r3, #36] ; 0x24 800ce60: 2b0a cmp r3, #10 800ce62: d008 beq.n 800ce76 800ce64: 687b ldr r3, [r7, #4] 800ce66: 6a5b ldr r3, [r3, #36] ; 0x24 800ce68: 2b0b cmp r3, #11 800ce6a: d102 bne.n 800ce72 800ce6c: f44f 7380 mov.w r3, #256 ; 0x100 800ce70: e01b b.n 800ceaa 800ce72: 2301 movs r3, #1 800ce74: e019 b.n 800ceaa 800ce76: 2380 movs r3, #128 ; 0x80 800ce78: e017 b.n 800ceaa 800ce7a: 2340 movs r3, #64 ; 0x40 800ce7c: e015 b.n 800ceaa 800ce7e: 2320 movs r3, #32 800ce80: e013 b.n 800ceaa 800ce82: 2310 movs r3, #16 800ce84: e011 b.n 800ceaa 800ce86: 230c movs r3, #12 800ce88: e00f b.n 800ceaa 800ce8a: 230a movs r3, #10 800ce8c: e00d b.n 800ceaa 800ce8e: 2308 movs r3, #8 800ce90: e00b b.n 800ceaa 800ce92: 2306 movs r3, #6 800ce94: e009 b.n 800ceaa 800ce96: 2304 movs r3, #4 800ce98: e007 b.n 800ceaa 800ce9a: 2302 movs r3, #2 800ce9c: e005 b.n 800ceaa 800ce9e: bf00 nop 800cea0: 40011c00 .word 0x40011c00 800cea4: 58024400 .word 0x58024400 800cea8: 2301 movs r3, #1 800ceaa: 6aba ldr r2, [r7, #40] ; 0x28 800ceac: fbb2 f3f3 udiv r3, r2, r3 800ceb0: 005a lsls r2, r3, #1 800ceb2: 687b ldr r3, [r7, #4] 800ceb4: 685b ldr r3, [r3, #4] 800ceb6: 085b lsrs r3, r3, #1 800ceb8: 441a add r2, r3 800ceba: 687b ldr r3, [r7, #4] 800cebc: 685b ldr r3, [r3, #4] 800cebe: fbb2 f3f3 udiv r3, r2, r3 800cec2: 633b str r3, [r7, #48] ; 0x30 break; 800cec4: e231 b.n 800d32a case USART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800cec6: f107 0318 add.w r3, r7, #24 800ceca: 4618 mov r0, r3 800cecc: f7fb fe4c bl 8008b68 usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pll2_clocks.PLL2_Q_Frequency, husart->Init.BaudRate, 800ced0: 69fa ldr r2, [r7, #28] 800ced2: 687b ldr r3, [r7, #4] 800ced4: 6a5b ldr r3, [r3, #36] ; 0x24 800ced6: 2b00 cmp r3, #0 800ced8: d044 beq.n 800cf64 800ceda: 687b ldr r3, [r7, #4] 800cedc: 6a5b ldr r3, [r3, #36] ; 0x24 800cede: 2b01 cmp r3, #1 800cee0: d03e beq.n 800cf60 800cee2: 687b ldr r3, [r7, #4] 800cee4: 6a5b ldr r3, [r3, #36] ; 0x24 800cee6: 2b02 cmp r3, #2 800cee8: d038 beq.n 800cf5c 800ceea: 687b ldr r3, [r7, #4] 800ceec: 6a5b ldr r3, [r3, #36] ; 0x24 800ceee: 2b03 cmp r3, #3 800cef0: d032 beq.n 800cf58 800cef2: 687b ldr r3, [r7, #4] 800cef4: 6a5b ldr r3, [r3, #36] ; 0x24 800cef6: 2b04 cmp r3, #4 800cef8: d02c beq.n 800cf54 800cefa: 687b ldr r3, [r7, #4] 800cefc: 6a5b ldr r3, [r3, #36] ; 0x24 800cefe: 2b05 cmp r3, #5 800cf00: d026 beq.n 800cf50 800cf02: 687b ldr r3, [r7, #4] 800cf04: 6a5b ldr r3, [r3, #36] ; 0x24 800cf06: 2b06 cmp r3, #6 800cf08: d020 beq.n 800cf4c 800cf0a: 687b ldr r3, [r7, #4] 800cf0c: 6a5b ldr r3, [r3, #36] ; 0x24 800cf0e: 2b07 cmp r3, #7 800cf10: d01a beq.n 800cf48 800cf12: 687b ldr r3, [r7, #4] 800cf14: 6a5b ldr r3, [r3, #36] ; 0x24 800cf16: 2b08 cmp r3, #8 800cf18: d014 beq.n 800cf44 800cf1a: 687b ldr r3, [r7, #4] 800cf1c: 6a5b ldr r3, [r3, #36] ; 0x24 800cf1e: 2b09 cmp r3, #9 800cf20: d00e beq.n 800cf40 800cf22: 687b ldr r3, [r7, #4] 800cf24: 6a5b ldr r3, [r3, #36] ; 0x24 800cf26: 2b0a cmp r3, #10 800cf28: d008 beq.n 800cf3c 800cf2a: 687b ldr r3, [r7, #4] 800cf2c: 6a5b ldr r3, [r3, #36] ; 0x24 800cf2e: 2b0b cmp r3, #11 800cf30: d102 bne.n 800cf38 800cf32: f44f 7380 mov.w r3, #256 ; 0x100 800cf36: e016 b.n 800cf66 800cf38: 2301 movs r3, #1 800cf3a: e014 b.n 800cf66 800cf3c: 2380 movs r3, #128 ; 0x80 800cf3e: e012 b.n 800cf66 800cf40: 2340 movs r3, #64 ; 0x40 800cf42: e010 b.n 800cf66 800cf44: 2320 movs r3, #32 800cf46: e00e b.n 800cf66 800cf48: 2310 movs r3, #16 800cf4a: e00c b.n 800cf66 800cf4c: 230c movs r3, #12 800cf4e: e00a b.n 800cf66 800cf50: 230a movs r3, #10 800cf52: e008 b.n 800cf66 800cf54: 2308 movs r3, #8 800cf56: e006 b.n 800cf66 800cf58: 2306 movs r3, #6 800cf5a: e004 b.n 800cf66 800cf5c: 2304 movs r3, #4 800cf5e: e002 b.n 800cf66 800cf60: 2302 movs r3, #2 800cf62: e000 b.n 800cf66 800cf64: 2301 movs r3, #1 800cf66: fbb2 f3f3 udiv r3, r2, r3 800cf6a: 005a lsls r2, r3, #1 800cf6c: 687b ldr r3, [r7, #4] 800cf6e: 685b ldr r3, [r3, #4] 800cf70: 085b lsrs r3, r3, #1 800cf72: 441a add r2, r3 800cf74: 687b ldr r3, [r7, #4] 800cf76: 685b ldr r3, [r3, #4] 800cf78: fbb2 f3f3 udiv r3, r2, r3 800cf7c: 633b str r3, [r7, #48] ; 0x30 husart->Init.ClockPrescaler)); break; 800cf7e: e1d4 b.n 800d32a case USART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800cf80: f107 030c add.w r3, r7, #12 800cf84: 4618 mov r0, r3 800cf86: f7fb ff43 bl 8008e10 usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pll3_clocks.PLL3_Q_Frequency, husart->Init.BaudRate, 800cf8a: 693a ldr r2, [r7, #16] 800cf8c: 687b ldr r3, [r7, #4] 800cf8e: 6a5b ldr r3, [r3, #36] ; 0x24 800cf90: 2b00 cmp r3, #0 800cf92: d044 beq.n 800d01e 800cf94: 687b ldr r3, [r7, #4] 800cf96: 6a5b ldr r3, [r3, #36] ; 0x24 800cf98: 2b01 cmp r3, #1 800cf9a: d03e beq.n 800d01a 800cf9c: 687b ldr r3, [r7, #4] 800cf9e: 6a5b ldr r3, [r3, #36] ; 0x24 800cfa0: 2b02 cmp r3, #2 800cfa2: d038 beq.n 800d016 800cfa4: 687b ldr r3, [r7, #4] 800cfa6: 6a5b ldr r3, [r3, #36] ; 0x24 800cfa8: 2b03 cmp r3, #3 800cfaa: d032 beq.n 800d012 800cfac: 687b ldr r3, [r7, #4] 800cfae: 6a5b ldr r3, [r3, #36] ; 0x24 800cfb0: 2b04 cmp r3, #4 800cfb2: d02c beq.n 800d00e 800cfb4: 687b ldr r3, [r7, #4] 800cfb6: 6a5b ldr r3, [r3, #36] ; 0x24 800cfb8: 2b05 cmp r3, #5 800cfba: d026 beq.n 800d00a 800cfbc: 687b ldr r3, [r7, #4] 800cfbe: 6a5b ldr r3, [r3, #36] ; 0x24 800cfc0: 2b06 cmp r3, #6 800cfc2: d020 beq.n 800d006 800cfc4: 687b ldr r3, [r7, #4] 800cfc6: 6a5b ldr r3, [r3, #36] ; 0x24 800cfc8: 2b07 cmp r3, #7 800cfca: d01a beq.n 800d002 800cfcc: 687b ldr r3, [r7, #4] 800cfce: 6a5b ldr r3, [r3, #36] ; 0x24 800cfd0: 2b08 cmp r3, #8 800cfd2: d014 beq.n 800cffe 800cfd4: 687b ldr r3, [r7, #4] 800cfd6: 6a5b ldr r3, [r3, #36] ; 0x24 800cfd8: 2b09 cmp r3, #9 800cfda: d00e beq.n 800cffa 800cfdc: 687b ldr r3, [r7, #4] 800cfde: 6a5b ldr r3, [r3, #36] ; 0x24 800cfe0: 2b0a cmp r3, #10 800cfe2: d008 beq.n 800cff6 800cfe4: 687b ldr r3, [r7, #4] 800cfe6: 6a5b ldr r3, [r3, #36] ; 0x24 800cfe8: 2b0b cmp r3, #11 800cfea: d102 bne.n 800cff2 800cfec: f44f 7380 mov.w r3, #256 ; 0x100 800cff0: e016 b.n 800d020 800cff2: 2301 movs r3, #1 800cff4: e014 b.n 800d020 800cff6: 2380 movs r3, #128 ; 0x80 800cff8: e012 b.n 800d020 800cffa: 2340 movs r3, #64 ; 0x40 800cffc: e010 b.n 800d020 800cffe: 2320 movs r3, #32 800d000: e00e b.n 800d020 800d002: 2310 movs r3, #16 800d004: e00c b.n 800d020 800d006: 230c movs r3, #12 800d008: e00a b.n 800d020 800d00a: 230a movs r3, #10 800d00c: e008 b.n 800d020 800d00e: 2308 movs r3, #8 800d010: e006 b.n 800d020 800d012: 2306 movs r3, #6 800d014: e004 b.n 800d020 800d016: 2304 movs r3, #4 800d018: e002 b.n 800d020 800d01a: 2302 movs r3, #2 800d01c: e000 b.n 800d020 800d01e: 2301 movs r3, #1 800d020: fbb2 f3f3 udiv r3, r2, r3 800d024: 005a lsls r2, r3, #1 800d026: 687b ldr r3, [r7, #4] 800d028: 685b ldr r3, [r3, #4] 800d02a: 085b lsrs r3, r3, #1 800d02c: 441a add r2, r3 800d02e: 687b ldr r3, [r7, #4] 800d030: 685b ldr r3, [r3, #4] 800d032: fbb2 f3f3 udiv r3, r2, r3 800d036: 633b str r3, [r7, #48] ; 0x30 husart->Init.ClockPrescaler)); break; 800d038: e177 b.n 800d32a case USART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800d03a: 4b8a ldr r3, [pc, #552] ; (800d264 ) 800d03c: 681b ldr r3, [r3, #0] 800d03e: f003 0320 and.w r3, r3, #32 800d042: 2b00 cmp r3, #0 800d044: d05d beq.n 800d102 { usartdiv = (uint32_t)(USART_DIV_SAMPLING8((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)), husart->Init.BaudRate, husart->Init.ClockPrescaler)); 800d046: 4b87 ldr r3, [pc, #540] ; (800d264 ) 800d048: 681b ldr r3, [r3, #0] 800d04a: 08db lsrs r3, r3, #3 800d04c: f003 0303 and.w r3, r3, #3 800d050: 4a85 ldr r2, [pc, #532] ; (800d268 ) 800d052: 40da lsrs r2, r3 800d054: 687b ldr r3, [r7, #4] 800d056: 6a5b ldr r3, [r3, #36] ; 0x24 800d058: 2b00 cmp r3, #0 800d05a: d044 beq.n 800d0e6 800d05c: 687b ldr r3, [r7, #4] 800d05e: 6a5b ldr r3, [r3, #36] ; 0x24 800d060: 2b01 cmp r3, #1 800d062: d03e beq.n 800d0e2 800d064: 687b ldr r3, [r7, #4] 800d066: 6a5b ldr r3, [r3, #36] ; 0x24 800d068: 2b02 cmp r3, #2 800d06a: d038 beq.n 800d0de 800d06c: 687b ldr r3, [r7, #4] 800d06e: 6a5b ldr r3, [r3, #36] ; 0x24 800d070: 2b03 cmp r3, #3 800d072: d032 beq.n 800d0da 800d074: 687b ldr r3, [r7, #4] 800d076: 6a5b ldr r3, [r3, #36] ; 0x24 800d078: 2b04 cmp r3, #4 800d07a: d02c beq.n 800d0d6 800d07c: 687b ldr r3, [r7, #4] 800d07e: 6a5b ldr r3, [r3, #36] ; 0x24 800d080: 2b05 cmp r3, #5 800d082: d026 beq.n 800d0d2 800d084: 687b ldr r3, [r7, #4] 800d086: 6a5b ldr r3, [r3, #36] ; 0x24 800d088: 2b06 cmp r3, #6 800d08a: d020 beq.n 800d0ce 800d08c: 687b ldr r3, [r7, #4] 800d08e: 6a5b ldr r3, [r3, #36] ; 0x24 800d090: 2b07 cmp r3, #7 800d092: d01a beq.n 800d0ca 800d094: 687b ldr r3, [r7, #4] 800d096: 6a5b ldr r3, [r3, #36] ; 0x24 800d098: 2b08 cmp r3, #8 800d09a: d014 beq.n 800d0c6 800d09c: 687b ldr r3, [r7, #4] 800d09e: 6a5b ldr r3, [r3, #36] ; 0x24 800d0a0: 2b09 cmp r3, #9 800d0a2: d00e beq.n 800d0c2 800d0a4: 687b ldr r3, [r7, #4] 800d0a6: 6a5b ldr r3, [r3, #36] ; 0x24 800d0a8: 2b0a cmp r3, #10 800d0aa: d008 beq.n 800d0be 800d0ac: 687b ldr r3, [r7, #4] 800d0ae: 6a5b ldr r3, [r3, #36] ; 0x24 800d0b0: 2b0b cmp r3, #11 800d0b2: d102 bne.n 800d0ba 800d0b4: f44f 7380 mov.w r3, #256 ; 0x100 800d0b8: e016 b.n 800d0e8 800d0ba: 2301 movs r3, #1 800d0bc: e014 b.n 800d0e8 800d0be: 2380 movs r3, #128 ; 0x80 800d0c0: e012 b.n 800d0e8 800d0c2: 2340 movs r3, #64 ; 0x40 800d0c4: e010 b.n 800d0e8 800d0c6: 2320 movs r3, #32 800d0c8: e00e b.n 800d0e8 800d0ca: 2310 movs r3, #16 800d0cc: e00c b.n 800d0e8 800d0ce: 230c movs r3, #12 800d0d0: e00a b.n 800d0e8 800d0d2: 230a movs r3, #10 800d0d4: e008 b.n 800d0e8 800d0d6: 2308 movs r3, #8 800d0d8: e006 b.n 800d0e8 800d0da: 2306 movs r3, #6 800d0dc: e004 b.n 800d0e8 800d0de: 2304 movs r3, #4 800d0e0: e002 b.n 800d0e8 800d0e2: 2302 movs r3, #2 800d0e4: e000 b.n 800d0e8 800d0e6: 2301 movs r3, #1 800d0e8: fbb2 f3f3 udiv r3, r2, r3 800d0ec: 005a lsls r2, r3, #1 800d0ee: 687b ldr r3, [r7, #4] 800d0f0: 685b ldr r3, [r3, #4] 800d0f2: 085b lsrs r3, r3, #1 800d0f4: 441a add r2, r3 800d0f6: 687b ldr r3, [r7, #4] 800d0f8: 685b ldr r3, [r3, #4] 800d0fa: fbb2 f3f3 udiv r3, r2, r3 800d0fe: 633b str r3, [r7, #48] ; 0x30 } else { usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); } break; 800d100: e113 b.n 800d32a usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); 800d102: 687b ldr r3, [r7, #4] 800d104: 6a5b ldr r3, [r3, #36] ; 0x24 800d106: 2b00 cmp r3, #0 800d108: d044 beq.n 800d194 800d10a: 687b ldr r3, [r7, #4] 800d10c: 6a5b ldr r3, [r3, #36] ; 0x24 800d10e: 2b01 cmp r3, #1 800d110: d03e beq.n 800d190 800d112: 687b ldr r3, [r7, #4] 800d114: 6a5b ldr r3, [r3, #36] ; 0x24 800d116: 2b02 cmp r3, #2 800d118: d038 beq.n 800d18c 800d11a: 687b ldr r3, [r7, #4] 800d11c: 6a5b ldr r3, [r3, #36] ; 0x24 800d11e: 2b03 cmp r3, #3 800d120: d032 beq.n 800d188 800d122: 687b ldr r3, [r7, #4] 800d124: 6a5b ldr r3, [r3, #36] ; 0x24 800d126: 2b04 cmp r3, #4 800d128: d02c beq.n 800d184 800d12a: 687b ldr r3, [r7, #4] 800d12c: 6a5b ldr r3, [r3, #36] ; 0x24 800d12e: 2b05 cmp r3, #5 800d130: d026 beq.n 800d180 800d132: 687b ldr r3, [r7, #4] 800d134: 6a5b ldr r3, [r3, #36] ; 0x24 800d136: 2b06 cmp r3, #6 800d138: d020 beq.n 800d17c 800d13a: 687b ldr r3, [r7, #4] 800d13c: 6a5b ldr r3, [r3, #36] ; 0x24 800d13e: 2b07 cmp r3, #7 800d140: d01a beq.n 800d178 800d142: 687b ldr r3, [r7, #4] 800d144: 6a5b ldr r3, [r3, #36] ; 0x24 800d146: 2b08 cmp r3, #8 800d148: d014 beq.n 800d174 800d14a: 687b ldr r3, [r7, #4] 800d14c: 6a5b ldr r3, [r3, #36] ; 0x24 800d14e: 2b09 cmp r3, #9 800d150: d00e beq.n 800d170 800d152: 687b ldr r3, [r7, #4] 800d154: 6a5b ldr r3, [r3, #36] ; 0x24 800d156: 2b0a cmp r3, #10 800d158: d008 beq.n 800d16c 800d15a: 687b ldr r3, [r7, #4] 800d15c: 6a5b ldr r3, [r3, #36] ; 0x24 800d15e: 2b0b cmp r3, #11 800d160: d102 bne.n 800d168 800d162: f44f 7380 mov.w r3, #256 ; 0x100 800d166: e016 b.n 800d196 800d168: 2301 movs r3, #1 800d16a: e014 b.n 800d196 800d16c: 2380 movs r3, #128 ; 0x80 800d16e: e012 b.n 800d196 800d170: 2340 movs r3, #64 ; 0x40 800d172: e010 b.n 800d196 800d174: 2320 movs r3, #32 800d176: e00e b.n 800d196 800d178: 2310 movs r3, #16 800d17a: e00c b.n 800d196 800d17c: 230c movs r3, #12 800d17e: e00a b.n 800d196 800d180: 230a movs r3, #10 800d182: e008 b.n 800d196 800d184: 2308 movs r3, #8 800d186: e006 b.n 800d196 800d188: 2306 movs r3, #6 800d18a: e004 b.n 800d196 800d18c: 2304 movs r3, #4 800d18e: e002 b.n 800d196 800d190: 2302 movs r3, #2 800d192: e000 b.n 800d196 800d194: 2301 movs r3, #1 800d196: 4a34 ldr r2, [pc, #208] ; (800d268 ) 800d198: fbb2 f3f3 udiv r3, r2, r3 800d19c: 005a lsls r2, r3, #1 800d19e: 687b ldr r3, [r7, #4] 800d1a0: 685b ldr r3, [r3, #4] 800d1a2: 085b lsrs r3, r3, #1 800d1a4: 441a add r2, r3 800d1a6: 687b ldr r3, [r7, #4] 800d1a8: 685b ldr r3, [r3, #4] 800d1aa: fbb2 f3f3 udiv r3, r2, r3 800d1ae: 633b str r3, [r7, #48] ; 0x30 break; 800d1b0: e0bb b.n 800d32a case USART_CLOCKSOURCE_CSI: usartdiv = (uint32_t)(USART_DIV_SAMPLING8(CSI_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); 800d1b2: 687b ldr r3, [r7, #4] 800d1b4: 6a5b ldr r3, [r3, #36] ; 0x24 800d1b6: 2b00 cmp r3, #0 800d1b8: d044 beq.n 800d244 800d1ba: 687b ldr r3, [r7, #4] 800d1bc: 6a5b ldr r3, [r3, #36] ; 0x24 800d1be: 2b01 cmp r3, #1 800d1c0: d03e beq.n 800d240 800d1c2: 687b ldr r3, [r7, #4] 800d1c4: 6a5b ldr r3, [r3, #36] ; 0x24 800d1c6: 2b02 cmp r3, #2 800d1c8: d038 beq.n 800d23c 800d1ca: 687b ldr r3, [r7, #4] 800d1cc: 6a5b ldr r3, [r3, #36] ; 0x24 800d1ce: 2b03 cmp r3, #3 800d1d0: d032 beq.n 800d238 800d1d2: 687b ldr r3, [r7, #4] 800d1d4: 6a5b ldr r3, [r3, #36] ; 0x24 800d1d6: 2b04 cmp r3, #4 800d1d8: d02c beq.n 800d234 800d1da: 687b ldr r3, [r7, #4] 800d1dc: 6a5b ldr r3, [r3, #36] ; 0x24 800d1de: 2b05 cmp r3, #5 800d1e0: d026 beq.n 800d230 800d1e2: 687b ldr r3, [r7, #4] 800d1e4: 6a5b ldr r3, [r3, #36] ; 0x24 800d1e6: 2b06 cmp r3, #6 800d1e8: d020 beq.n 800d22c 800d1ea: 687b ldr r3, [r7, #4] 800d1ec: 6a5b ldr r3, [r3, #36] ; 0x24 800d1ee: 2b07 cmp r3, #7 800d1f0: d01a beq.n 800d228 800d1f2: 687b ldr r3, [r7, #4] 800d1f4: 6a5b ldr r3, [r3, #36] ; 0x24 800d1f6: 2b08 cmp r3, #8 800d1f8: d014 beq.n 800d224 800d1fa: 687b ldr r3, [r7, #4] 800d1fc: 6a5b ldr r3, [r3, #36] ; 0x24 800d1fe: 2b09 cmp r3, #9 800d200: d00e beq.n 800d220 800d202: 687b ldr r3, [r7, #4] 800d204: 6a5b ldr r3, [r3, #36] ; 0x24 800d206: 2b0a cmp r3, #10 800d208: d008 beq.n 800d21c 800d20a: 687b ldr r3, [r7, #4] 800d20c: 6a5b ldr r3, [r3, #36] ; 0x24 800d20e: 2b0b cmp r3, #11 800d210: d102 bne.n 800d218 800d212: f44f 7380 mov.w r3, #256 ; 0x100 800d216: e016 b.n 800d246 800d218: 2301 movs r3, #1 800d21a: e014 b.n 800d246 800d21c: 2380 movs r3, #128 ; 0x80 800d21e: e012 b.n 800d246 800d220: 2340 movs r3, #64 ; 0x40 800d222: e010 b.n 800d246 800d224: 2320 movs r3, #32 800d226: e00e b.n 800d246 800d228: 2310 movs r3, #16 800d22a: e00c b.n 800d246 800d22c: 230c movs r3, #12 800d22e: e00a b.n 800d246 800d230: 230a movs r3, #10 800d232: e008 b.n 800d246 800d234: 2308 movs r3, #8 800d236: e006 b.n 800d246 800d238: 2306 movs r3, #6 800d23a: e004 b.n 800d246 800d23c: 2304 movs r3, #4 800d23e: e002 b.n 800d246 800d240: 2302 movs r3, #2 800d242: e000 b.n 800d246 800d244: 2301 movs r3, #1 800d246: 4a09 ldr r2, [pc, #36] ; (800d26c ) 800d248: fbb2 f3f3 udiv r3, r2, r3 800d24c: 005a lsls r2, r3, #1 800d24e: 687b ldr r3, [r7, #4] 800d250: 685b ldr r3, [r3, #4] 800d252: 085b lsrs r3, r3, #1 800d254: 441a add r2, r3 800d256: 687b ldr r3, [r7, #4] 800d258: 685b ldr r3, [r3, #4] 800d25a: fbb2 f3f3 udiv r3, r2, r3 800d25e: 633b str r3, [r7, #48] ; 0x30 break; 800d260: e063 b.n 800d32a 800d262: bf00 nop 800d264: 58024400 .word 0x58024400 800d268: 03d09000 .word 0x03d09000 800d26c: 003d0900 .word 0x003d0900 case USART_CLOCKSOURCE_LSE: usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); 800d270: 687b ldr r3, [r7, #4] 800d272: 6a5b ldr r3, [r3, #36] ; 0x24 800d274: 2b00 cmp r3, #0 800d276: d044 beq.n 800d302 800d278: 687b ldr r3, [r7, #4] 800d27a: 6a5b ldr r3, [r3, #36] ; 0x24 800d27c: 2b01 cmp r3, #1 800d27e: d03e beq.n 800d2fe 800d280: 687b ldr r3, [r7, #4] 800d282: 6a5b ldr r3, [r3, #36] ; 0x24 800d284: 2b02 cmp r3, #2 800d286: d038 beq.n 800d2fa 800d288: 687b ldr r3, [r7, #4] 800d28a: 6a5b ldr r3, [r3, #36] ; 0x24 800d28c: 2b03 cmp r3, #3 800d28e: d032 beq.n 800d2f6 800d290: 687b ldr r3, [r7, #4] 800d292: 6a5b ldr r3, [r3, #36] ; 0x24 800d294: 2b04 cmp r3, #4 800d296: d02c beq.n 800d2f2 800d298: 687b ldr r3, [r7, #4] 800d29a: 6a5b ldr r3, [r3, #36] ; 0x24 800d29c: 2b05 cmp r3, #5 800d29e: d026 beq.n 800d2ee 800d2a0: 687b ldr r3, [r7, #4] 800d2a2: 6a5b ldr r3, [r3, #36] ; 0x24 800d2a4: 2b06 cmp r3, #6 800d2a6: d020 beq.n 800d2ea 800d2a8: 687b ldr r3, [r7, #4] 800d2aa: 6a5b ldr r3, [r3, #36] ; 0x24 800d2ac: 2b07 cmp r3, #7 800d2ae: d01a beq.n 800d2e6 800d2b0: 687b ldr r3, [r7, #4] 800d2b2: 6a5b ldr r3, [r3, #36] ; 0x24 800d2b4: 2b08 cmp r3, #8 800d2b6: d014 beq.n 800d2e2 800d2b8: 687b ldr r3, [r7, #4] 800d2ba: 6a5b ldr r3, [r3, #36] ; 0x24 800d2bc: 2b09 cmp r3, #9 800d2be: d00e beq.n 800d2de 800d2c0: 687b ldr r3, [r7, #4] 800d2c2: 6a5b ldr r3, [r3, #36] ; 0x24 800d2c4: 2b0a cmp r3, #10 800d2c6: d008 beq.n 800d2da 800d2c8: 687b ldr r3, [r7, #4] 800d2ca: 6a5b ldr r3, [r3, #36] ; 0x24 800d2cc: 2b0b cmp r3, #11 800d2ce: d102 bne.n 800d2d6 800d2d0: f44f 7380 mov.w r3, #256 ; 0x100 800d2d4: e016 b.n 800d304 800d2d6: 2301 movs r3, #1 800d2d8: e014 b.n 800d304 800d2da: 2380 movs r3, #128 ; 0x80 800d2dc: e012 b.n 800d304 800d2de: 2340 movs r3, #64 ; 0x40 800d2e0: e010 b.n 800d304 800d2e2: 2320 movs r3, #32 800d2e4: e00e b.n 800d304 800d2e6: 2310 movs r3, #16 800d2e8: e00c b.n 800d304 800d2ea: 230c movs r3, #12 800d2ec: e00a b.n 800d304 800d2ee: 230a movs r3, #10 800d2f0: e008 b.n 800d304 800d2f2: 2308 movs r3, #8 800d2f4: e006 b.n 800d304 800d2f6: 2306 movs r3, #6 800d2f8: e004 b.n 800d304 800d2fa: 2304 movs r3, #4 800d2fc: e002 b.n 800d304 800d2fe: 2302 movs r3, #2 800d300: e000 b.n 800d304 800d302: 2301 movs r3, #1 800d304: f44f 4200 mov.w r2, #32768 ; 0x8000 800d308: fbb2 f3f3 udiv r3, r2, r3 800d30c: 005a lsls r2, r3, #1 800d30e: 687b ldr r3, [r7, #4] 800d310: 685b ldr r3, [r3, #4] 800d312: 085b lsrs r3, r3, #1 800d314: 441a add r2, r3 800d316: 687b ldr r3, [r7, #4] 800d318: 685b ldr r3, [r3, #4] 800d31a: fbb2 f3f3 udiv r3, r2, r3 800d31e: 633b str r3, [r7, #48] ; 0x30 break; 800d320: e003 b.n 800d32a default: ret = HAL_ERROR; 800d322: 2301 movs r3, #1 800d324: f887 3036 strb.w r3, [r7, #54] ; 0x36 break; 800d328: bf00 nop } /* USARTDIV must be greater than or equal to 0d16 and smaller than or equal to ffff */ if ((usartdiv >= USART_BRR_MIN) && (usartdiv <= USART_BRR_MAX)) 800d32a: 6b3b ldr r3, [r7, #48] ; 0x30 800d32c: 2b0f cmp r3, #15 800d32e: d916 bls.n 800d35e 800d330: 6b3b ldr r3, [r7, #48] ; 0x30 800d332: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 800d336: d212 bcs.n 800d35e { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); 800d338: 6b3b ldr r3, [r7, #48] ; 0x30 800d33a: b29b uxth r3, r3 800d33c: f023 030f bic.w r3, r3, #15 800d340: 84fb strh r3, [r7, #38] ; 0x26 brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 800d342: 6b3b ldr r3, [r7, #48] ; 0x30 800d344: 085b lsrs r3, r3, #1 800d346: b29b uxth r3, r3 800d348: f003 0307 and.w r3, r3, #7 800d34c: b29a uxth r2, r3 800d34e: 8cfb ldrh r3, [r7, #38] ; 0x26 800d350: 4313 orrs r3, r2 800d352: 84fb strh r3, [r7, #38] ; 0x26 husart->Instance->BRR = brrtemp; 800d354: 687b ldr r3, [r7, #4] 800d356: 681b ldr r3, [r3, #0] 800d358: 8cfa ldrh r2, [r7, #38] ; 0x26 800d35a: 60da str r2, [r3, #12] 800d35c: e002 b.n 800d364 } else { ret = HAL_ERROR; 800d35e: 2301 movs r3, #1 800d360: f887 3036 strb.w r3, [r7, #54] ; 0x36 } /* Initialize the number of data to process during RX/TX ISR execution */ husart->NbTxDataToProcess = 1U; 800d364: 687b ldr r3, [r7, #4] 800d366: 2201 movs r2, #1 800d368: 879a strh r2, [r3, #60] ; 0x3c husart->NbRxDataToProcess = 1U; 800d36a: 687b ldr r3, [r7, #4] 800d36c: 2201 movs r2, #1 800d36e: 875a strh r2, [r3, #58] ; 0x3a /* Clear ISR function pointers */ husart->RxISR = NULL; 800d370: 687b ldr r3, [r7, #4] 800d372: 2200 movs r2, #0 800d374: 649a str r2, [r3, #72] ; 0x48 husart->TxISR = NULL; 800d376: 687b ldr r3, [r7, #4] 800d378: 2200 movs r2, #0 800d37a: 64da str r2, [r3, #76] ; 0x4c return ret; 800d37c: f897 3036 ldrb.w r3, [r7, #54] ; 0x36 } 800d380: 4618 mov r0, r3 800d382: 3738 adds r7, #56 ; 0x38 800d384: 46bd mov sp, r7 800d386: bd80 pop {r7, pc} 0800d388 : * @brief Check the USART Idle State. * @param husart USART handle. * @retval HAL status */ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) { 800d388: b580 push {r7, lr} 800d38a: b086 sub sp, #24 800d38c: af02 add r7, sp, #8 800d38e: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the USART ErrorCode */ husart->ErrorCode = HAL_USART_ERROR_NONE; 800d390: 687b ldr r3, [r7, #4] 800d392: 2200 movs r2, #0 800d394: 65da str r2, [r3, #92] ; 0x5c /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 800d396: f7f5 ff27 bl 80031e8 800d39a: 60f8 str r0, [r7, #12] /* Check if the Transmitter is enabled */ if ((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) 800d39c: 687b ldr r3, [r7, #4] 800d39e: 681b ldr r3, [r3, #0] 800d3a0: 681b ldr r3, [r3, #0] 800d3a2: f003 0308 and.w r3, r3, #8 800d3a6: 2b08 cmp r3, #8 800d3a8: d10e bne.n 800d3c8 { /* Wait until TEACK flag is set */ if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK) 800d3aa: f44f 737a mov.w r3, #1000 ; 0x3e8 800d3ae: 9300 str r3, [sp, #0] 800d3b0: 68fb ldr r3, [r7, #12] 800d3b2: 2200 movs r2, #0 800d3b4: f44f 1100 mov.w r1, #2097152 ; 0x200000 800d3b8: 6878 ldr r0, [r7, #4] 800d3ba: f7ff fa0d bl 800c7d8 800d3be: 4603 mov r3, r0 800d3c0: 2b00 cmp r3, #0 800d3c2: d001 beq.n 800d3c8 { /* Timeout occurred */ return HAL_TIMEOUT; 800d3c4: 2303 movs r3, #3 800d3c6: e01e b.n 800d406 } } /* Check if the Receiver is enabled */ if ((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) 800d3c8: 687b ldr r3, [r7, #4] 800d3ca: 681b ldr r3, [r3, #0] 800d3cc: 681b ldr r3, [r3, #0] 800d3ce: f003 0304 and.w r3, r3, #4 800d3d2: 2b04 cmp r3, #4 800d3d4: d10e bne.n 800d3f4 { /* Wait until REACK flag is set */ if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK) 800d3d6: f44f 737a mov.w r3, #1000 ; 0x3e8 800d3da: 9300 str r3, [sp, #0] 800d3dc: 68fb ldr r3, [r7, #12] 800d3de: 2200 movs r2, #0 800d3e0: f44f 0180 mov.w r1, #4194304 ; 0x400000 800d3e4: 6878 ldr r0, [r7, #4] 800d3e6: f7ff f9f7 bl 800c7d8 800d3ea: 4603 mov r3, r0 800d3ec: 2b00 cmp r3, #0 800d3ee: d001 beq.n 800d3f4 { /* Timeout occurred */ return HAL_TIMEOUT; 800d3f0: 2303 movs r3, #3 800d3f2: e008 b.n 800d406 } } /* Initialize the USART state*/ husart->State = HAL_USART_STATE_READY; 800d3f4: 687b ldr r3, [r7, #4] 800d3f6: 2201 movs r2, #1 800d3f8: f883 2059 strb.w r2, [r3, #89] ; 0x59 /* Process Unlocked */ __HAL_UNLOCK(husart); 800d3fc: 687b ldr r3, [r7, #4] 800d3fe: 2200 movs r2, #0 800d400: f883 2058 strb.w r2, [r3, #88] ; 0x58 return HAL_OK; 800d404: 2300 movs r3, #0 } 800d406: 4618 mov r0, r3 800d408: 3710 adds r7, #16 800d40a: 46bd mov sp, r7 800d40c: bd80 pop {r7, pc} 0800d40e : * @brief Disable the FIFO mode. * @param husart USART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart) { 800d40e: b480 push {r7} 800d410: b085 sub sp, #20 800d412: af00 add r7, sp, #0 800d414: 6078 str r0, [r7, #4] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); /* Process Locked */ __HAL_LOCK(husart); 800d416: 687b ldr r3, [r7, #4] 800d418: f893 3058 ldrb.w r3, [r3, #88] ; 0x58 800d41c: 2b01 cmp r3, #1 800d41e: d101 bne.n 800d424 800d420: 2302 movs r3, #2 800d422: e027 b.n 800d474 800d424: 687b ldr r3, [r7, #4] 800d426: 2201 movs r2, #1 800d428: f883 2058 strb.w r2, [r3, #88] ; 0x58 husart->State = HAL_USART_STATE_BUSY; 800d42c: 687b ldr r3, [r7, #4] 800d42e: 2202 movs r2, #2 800d430: f883 2059 strb.w r2, [r3, #89] ; 0x59 /* Save actual USART configuration */ tmpcr1 = READ_REG(husart->Instance->CR1); 800d434: 687b ldr r3, [r7, #4] 800d436: 681b ldr r3, [r3, #0] 800d438: 681b ldr r3, [r3, #0] 800d43a: 60fb str r3, [r7, #12] /* Disable USART */ __HAL_USART_DISABLE(husart); 800d43c: 687b ldr r3, [r7, #4] 800d43e: 681b ldr r3, [r3, #0] 800d440: 681a ldr r2, [r3, #0] 800d442: 687b ldr r3, [r7, #4] 800d444: 681b ldr r3, [r3, #0] 800d446: f022 0201 bic.w r2, r2, #1 800d44a: 601a str r2, [r3, #0] /* Enable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); 800d44c: 68fb ldr r3, [r7, #12] 800d44e: f023 5300 bic.w r3, r3, #536870912 ; 0x20000000 800d452: 60fb str r3, [r7, #12] husart->FifoMode = USART_FIFOMODE_DISABLE; 800d454: 687b ldr r3, [r7, #4] 800d456: 2200 movs r2, #0 800d458: 645a str r2, [r3, #68] ; 0x44 /* Restore USART configuration */ WRITE_REG(husart->Instance->CR1, tmpcr1); 800d45a: 687b ldr r3, [r7, #4] 800d45c: 681b ldr r3, [r3, #0] 800d45e: 68fa ldr r2, [r7, #12] 800d460: 601a str r2, [r3, #0] husart->State = HAL_USART_STATE_READY; 800d462: 687b ldr r3, [r7, #4] 800d464: 2201 movs r2, #1 800d466: f883 2059 strb.w r2, [r3, #89] ; 0x59 /* Process Unlocked */ __HAL_UNLOCK(husart); 800d46a: 687b ldr r3, [r7, #4] 800d46c: 2200 movs r2, #0 800d46e: f883 2058 strb.w r2, [r3, #88] ; 0x58 return HAL_OK; 800d472: 2300 movs r3, #0 } 800d474: 4618 mov r0, r3 800d476: 3714 adds r7, #20 800d478: 46bd mov sp, r7 800d47a: f85d 7b04 ldr.w r7, [sp], #4 800d47e: 4770 bx lr 0800d480 : * @arg @ref USART_TXFIFO_THRESHOLD_7_8 * @arg @ref USART_TXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold) { 800d480: b580 push {r7, lr} 800d482: b084 sub sp, #16 800d484: af00 add r7, sp, #0 800d486: 6078 str r0, [r7, #4] 800d488: 6039 str r1, [r7, #0] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); assert_param(IS_USART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(husart); 800d48a: 687b ldr r3, [r7, #4] 800d48c: f893 3058 ldrb.w r3, [r3, #88] ; 0x58 800d490: 2b01 cmp r3, #1 800d492: d101 bne.n 800d498 800d494: 2302 movs r3, #2 800d496: e02d b.n 800d4f4 800d498: 687b ldr r3, [r7, #4] 800d49a: 2201 movs r2, #1 800d49c: f883 2058 strb.w r2, [r3, #88] ; 0x58 husart->State = HAL_USART_STATE_BUSY; 800d4a0: 687b ldr r3, [r7, #4] 800d4a2: 2202 movs r2, #2 800d4a4: f883 2059 strb.w r2, [r3, #89] ; 0x59 /* Save actual USART configuration */ tmpcr1 = READ_REG(husart->Instance->CR1); 800d4a8: 687b ldr r3, [r7, #4] 800d4aa: 681b ldr r3, [r3, #0] 800d4ac: 681b ldr r3, [r3, #0] 800d4ae: 60fb str r3, [r7, #12] /* Disable USART */ __HAL_USART_DISABLE(husart); 800d4b0: 687b ldr r3, [r7, #4] 800d4b2: 681b ldr r3, [r3, #0] 800d4b4: 681a ldr r2, [r3, #0] 800d4b6: 687b ldr r3, [r7, #4] 800d4b8: 681b ldr r3, [r3, #0] 800d4ba: f022 0201 bic.w r2, r2, #1 800d4be: 601a str r2, [r3, #0] /* Update TX threshold configuration */ MODIFY_REG(husart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); 800d4c0: 687b ldr r3, [r7, #4] 800d4c2: 681b ldr r3, [r3, #0] 800d4c4: 689b ldr r3, [r3, #8] 800d4c6: f023 4160 bic.w r1, r3, #3758096384 ; 0xe0000000 800d4ca: 687b ldr r3, [r7, #4] 800d4cc: 681b ldr r3, [r3, #0] 800d4ce: 683a ldr r2, [r7, #0] 800d4d0: 430a orrs r2, r1 800d4d2: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ USARTEx_SetNbDataToProcess(husart); 800d4d4: 6878 ldr r0, [r7, #4] 800d4d6: f000 f84f bl 800d578 /* Restore USART configuration */ WRITE_REG(husart->Instance->CR1, tmpcr1); 800d4da: 687b ldr r3, [r7, #4] 800d4dc: 681b ldr r3, [r3, #0] 800d4de: 68fa ldr r2, [r7, #12] 800d4e0: 601a str r2, [r3, #0] husart->State = HAL_USART_STATE_READY; 800d4e2: 687b ldr r3, [r7, #4] 800d4e4: 2201 movs r2, #1 800d4e6: f883 2059 strb.w r2, [r3, #89] ; 0x59 /* Process Unlocked */ __HAL_UNLOCK(husart); 800d4ea: 687b ldr r3, [r7, #4] 800d4ec: 2200 movs r2, #0 800d4ee: f883 2058 strb.w r2, [r3, #88] ; 0x58 return HAL_OK; 800d4f2: 2300 movs r3, #0 } 800d4f4: 4618 mov r0, r3 800d4f6: 3710 adds r7, #16 800d4f8: 46bd mov sp, r7 800d4fa: bd80 pop {r7, pc} 0800d4fc : * @arg @ref USART_RXFIFO_THRESHOLD_7_8 * @arg @ref USART_RXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold) { 800d4fc: b580 push {r7, lr} 800d4fe: b084 sub sp, #16 800d500: af00 add r7, sp, #0 800d502: 6078 str r0, [r7, #4] 800d504: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); assert_param(IS_USART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(husart); 800d506: 687b ldr r3, [r7, #4] 800d508: f893 3058 ldrb.w r3, [r3, #88] ; 0x58 800d50c: 2b01 cmp r3, #1 800d50e: d101 bne.n 800d514 800d510: 2302 movs r3, #2 800d512: e02d b.n 800d570 800d514: 687b ldr r3, [r7, #4] 800d516: 2201 movs r2, #1 800d518: f883 2058 strb.w r2, [r3, #88] ; 0x58 husart->State = HAL_USART_STATE_BUSY; 800d51c: 687b ldr r3, [r7, #4] 800d51e: 2202 movs r2, #2 800d520: f883 2059 strb.w r2, [r3, #89] ; 0x59 /* Save actual USART configuration */ tmpcr1 = READ_REG(husart->Instance->CR1); 800d524: 687b ldr r3, [r7, #4] 800d526: 681b ldr r3, [r3, #0] 800d528: 681b ldr r3, [r3, #0] 800d52a: 60fb str r3, [r7, #12] /* Disable USART */ __HAL_USART_DISABLE(husart); 800d52c: 687b ldr r3, [r7, #4] 800d52e: 681b ldr r3, [r3, #0] 800d530: 681a ldr r2, [r3, #0] 800d532: 687b ldr r3, [r7, #4] 800d534: 681b ldr r3, [r3, #0] 800d536: f022 0201 bic.w r2, r2, #1 800d53a: 601a str r2, [r3, #0] /* Update RX threshold configuration */ MODIFY_REG(husart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); 800d53c: 687b ldr r3, [r7, #4] 800d53e: 681b ldr r3, [r3, #0] 800d540: 689b ldr r3, [r3, #8] 800d542: f023 6160 bic.w r1, r3, #234881024 ; 0xe000000 800d546: 687b ldr r3, [r7, #4] 800d548: 681b ldr r3, [r3, #0] 800d54a: 683a ldr r2, [r7, #0] 800d54c: 430a orrs r2, r1 800d54e: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ USARTEx_SetNbDataToProcess(husart); 800d550: 6878 ldr r0, [r7, #4] 800d552: f000 f811 bl 800d578 /* Restore USART configuration */ WRITE_REG(husart->Instance->CR1, tmpcr1); 800d556: 687b ldr r3, [r7, #4] 800d558: 681b ldr r3, [r3, #0] 800d55a: 68fa ldr r2, [r7, #12] 800d55c: 601a str r2, [r3, #0] husart->State = HAL_USART_STATE_READY; 800d55e: 687b ldr r3, [r7, #4] 800d560: 2201 movs r2, #1 800d562: f883 2059 strb.w r2, [r3, #89] ; 0x59 /* Process Unlocked */ __HAL_UNLOCK(husart); 800d566: 687b ldr r3, [r7, #4] 800d568: 2200 movs r2, #0 800d56a: f883 2058 strb.w r2, [r3, #88] ; 0x58 return HAL_OK; 800d56e: 2300 movs r3, #0 } 800d570: 4618 mov r0, r3 800d572: 3710 adds r7, #16 800d574: 46bd mov sp, r7 800d576: bd80 pop {r7, pc} 0800d578 : * the USART configuration registers. * @param husart USART handle. * @retval None */ static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart) { 800d578: b480 push {r7} 800d57a: b085 sub sp, #20 800d57c: af00 add r7, sp, #0 800d57e: 6078 str r0, [r7, #4] uint8_t tx_fifo_threshold; /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */ static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (husart->FifoMode == USART_FIFOMODE_DISABLE) 800d580: 687b ldr r3, [r7, #4] 800d582: 6c5b ldr r3, [r3, #68] ; 0x44 800d584: 2b00 cmp r3, #0 800d586: d106 bne.n 800d596 { husart->NbTxDataToProcess = 1U; 800d588: 687b ldr r3, [r7, #4] 800d58a: 2201 movs r2, #1 800d58c: 879a strh r2, [r3, #60] ; 0x3c husart->NbRxDataToProcess = 1U; 800d58e: 687b ldr r3, [r7, #4] 800d590: 2201 movs r2, #1 800d592: 875a strh r2, [r3, #58] ; 0x3a husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } 800d594: e02f b.n 800d5f6 rx_fifo_depth = RX_FIFO_DEPTH; 800d596: 2310 movs r3, #16 800d598: 73fb strb r3, [r7, #15] tx_fifo_depth = TX_FIFO_DEPTH; 800d59a: 2310 movs r3, #16 800d59c: 73bb strb r3, [r7, #14] rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, 800d59e: 687b ldr r3, [r7, #4] 800d5a0: 681b ldr r3, [r3, #0] 800d5a2: 689b ldr r3, [r3, #8] USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU); 800d5a4: 0e5b lsrs r3, r3, #25 rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, 800d5a6: b2db uxtb r3, r3 800d5a8: f003 0307 and.w r3, r3, #7 800d5ac: 737b strb r3, [r7, #13] tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, 800d5ae: 687b ldr r3, [r7, #4] 800d5b0: 681b ldr r3, [r3, #0] 800d5b2: 689b ldr r3, [r3, #8] USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU); 800d5b4: 0f5b lsrs r3, r3, #29 tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, 800d5b6: b2db uxtb r3, r3 800d5b8: f003 0307 and.w r3, r3, #7 800d5bc: 733b strb r3, [r7, #12] husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 800d5be: 7bbb ldrb r3, [r7, #14] 800d5c0: 7b3a ldrb r2, [r7, #12] 800d5c2: 4910 ldr r1, [pc, #64] ; (800d604 ) 800d5c4: 5c8a ldrb r2, [r1, r2] 800d5c6: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[tx_fifo_threshold]; 800d5ca: 7b3a ldrb r2, [r7, #12] 800d5cc: 490e ldr r1, [pc, #56] ; (800d608 ) 800d5ce: 5c8a ldrb r2, [r1, r2] husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 800d5d0: fb93 f3f2 sdiv r3, r3, r2 800d5d4: b29a uxth r2, r3 800d5d6: 687b ldr r3, [r7, #4] 800d5d8: 879a strh r2, [r3, #60] ; 0x3c husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 800d5da: 7bfb ldrb r3, [r7, #15] 800d5dc: 7b7a ldrb r2, [r7, #13] 800d5de: 4909 ldr r1, [pc, #36] ; (800d604 ) 800d5e0: 5c8a ldrb r2, [r1, r2] 800d5e2: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[rx_fifo_threshold]; 800d5e6: 7b7a ldrb r2, [r7, #13] 800d5e8: 4907 ldr r1, [pc, #28] ; (800d608 ) 800d5ea: 5c8a ldrb r2, [r1, r2] husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 800d5ec: fb93 f3f2 sdiv r3, r3, r2 800d5f0: b29a uxth r2, r3 800d5f2: 687b ldr r3, [r7, #4] 800d5f4: 875a strh r2, [r3, #58] ; 0x3a } 800d5f6: bf00 nop 800d5f8: 3714 adds r7, #20 800d5fa: 46bd mov sp, r7 800d5fc: f85d 7b04 ldr.w r7, [sp], #4 800d600: 4770 bx lr 800d602: bf00 nop 800d604: 0800e68c .word 0x0800e68c 800d608: 0800e694 .word 0x0800e694 0800d60c : * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains * the configuration information for the specified WWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) { 800d60c: b580 push {r7, lr} 800d60e: b082 sub sp, #8 800d610: af00 add r7, sp, #0 800d612: 6078 str r0, [r7, #4] /* Check the WWDG handle allocation */ if (hwwdg == NULL) 800d614: 687b ldr r3, [r7, #4] 800d616: 2b00 cmp r3, #0 800d618: d101 bne.n 800d61e { return HAL_ERROR; 800d61a: 2301 movs r3, #1 800d61c: e016 b.n 800d64c /* Init the low level hardware */ hwwdg->MspInitCallback(hwwdg); #else /* Init the low level hardware */ HAL_WWDG_MspInit(hwwdg); 800d61e: 6878 ldr r0, [r7, #4] 800d620: f7f5 fc56 bl 8002ed0 #endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ /* Set WWDG Counter */ WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter)); 800d624: 687b ldr r3, [r7, #4] 800d626: 68da ldr r2, [r3, #12] 800d628: 687b ldr r3, [r7, #4] 800d62a: 681b ldr r3, [r3, #0] 800d62c: f042 0280 orr.w r2, r2, #128 ; 0x80 800d630: 601a str r2, [r3, #0] /* Set WWDG Prescaler and Window */ WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window)); 800d632: 687b ldr r3, [r7, #4] 800d634: 691a ldr r2, [r3, #16] 800d636: 687b ldr r3, [r7, #4] 800d638: 685b ldr r3, [r3, #4] 800d63a: ea42 0103 orr.w r1, r2, r3 800d63e: 687b ldr r3, [r7, #4] 800d640: 689a ldr r2, [r3, #8] 800d642: 687b ldr r3, [r7, #4] 800d644: 681b ldr r3, [r3, #0] 800d646: 430a orrs r2, r1 800d648: 605a str r2, [r3, #4] /* Return function status */ return HAL_OK; 800d64a: 2300 movs r3, #0 } 800d64c: 4618 mov r0, r3 800d64e: 3708 adds r7, #8 800d650: 46bd mov sp, r7 800d652: bd80 pop {r7, pc} 0800d654 : * @param SDMMCx: Pointer to SDMMC register base * @param Init: SDMMC initialization structure * @retval HAL status */ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) { 800d654: b084 sub sp, #16 800d656: b480 push {r7} 800d658: b085 sub sp, #20 800d65a: af00 add r7, sp, #0 800d65c: 6078 str r0, [r7, #4] 800d65e: f107 001c add.w r0, r7, #28 800d662: e880 000e stmia.w r0, {r1, r2, r3} uint32_t tmpreg = 0; 800d666: 2300 movs r3, #0 800d668: 60fb str r3, [r7, #12] assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide)); assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl)); assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv)); /* Set SDMMC configuration parameters */ tmpreg |= (Init.ClockEdge | \ 800d66a: 69fa ldr r2, [r7, #28] Init.ClockPowerSave | \ 800d66c: 6a3b ldr r3, [r7, #32] tmpreg |= (Init.ClockEdge | \ 800d66e: 431a orrs r2, r3 Init.BusWide | \ 800d670: 6a7b ldr r3, [r7, #36] ; 0x24 Init.ClockPowerSave | \ 800d672: 431a orrs r2, r3 Init.HardwareFlowControl | \ 800d674: 6abb ldr r3, [r7, #40] ; 0x28 Init.BusWide | \ 800d676: 431a orrs r2, r3 Init.ClockDiv 800d678: 6afb ldr r3, [r7, #44] ; 0x2c Init.HardwareFlowControl | \ 800d67a: 4313 orrs r3, r2 tmpreg |= (Init.ClockEdge | \ 800d67c: 68fa ldr r2, [r7, #12] 800d67e: 4313 orrs r3, r2 800d680: 60fb str r3, [r7, #12] ); /* Write to SDMMC CLKCR */ MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg); 800d682: 687b ldr r3, [r7, #4] 800d684: 685a ldr r2, [r3, #4] 800d686: 4b07 ldr r3, [pc, #28] ; (800d6a4 ) 800d688: 4013 ands r3, r2 800d68a: 68fa ldr r2, [r7, #12] 800d68c: 431a orrs r2, r3 800d68e: 687b ldr r3, [r7, #4] 800d690: 605a str r2, [r3, #4] return HAL_OK; 800d692: 2300 movs r3, #0 } 800d694: 4618 mov r0, r3 800d696: 3714 adds r7, #20 800d698: 46bd mov sp, r7 800d69a: f85d 7b04 ldr.w r7, [sp], #4 800d69e: b004 add sp, #16 800d6a0: 4770 bx lr 800d6a2: bf00 nop 800d6a4: ffc02c00 .word 0xffc02c00 0800d6a8 : * @brief Read data (word) from Rx FIFO in blocking mode (polling) * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx) { 800d6a8: b480 push {r7} 800d6aa: b083 sub sp, #12 800d6ac: af00 add r7, sp, #0 800d6ae: 6078 str r0, [r7, #4] /* Read data from Rx FIFO */ return (SDMMCx->FIFO); 800d6b0: 687b ldr r3, [r7, #4] 800d6b2: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 } 800d6b6: 4618 mov r0, r3 800d6b8: 370c adds r7, #12 800d6ba: 46bd mov sp, r7 800d6bc: f85d 7b04 ldr.w r7, [sp], #4 800d6c0: 4770 bx lr 0800d6c2 : * @param SDMMCx: Pointer to SDMMC register base * @param pWriteData: pointer to data to write * @retval HAL status */ HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData) { 800d6c2: b480 push {r7} 800d6c4: b083 sub sp, #12 800d6c6: af00 add r7, sp, #0 800d6c8: 6078 str r0, [r7, #4] 800d6ca: 6039 str r1, [r7, #0] /* Write data to FIFO */ SDMMCx->FIFO = *pWriteData; 800d6cc: 683b ldr r3, [r7, #0] 800d6ce: 681a ldr r2, [r3, #0] 800d6d0: 687b ldr r3, [r7, #4] 800d6d2: f8c3 2080 str.w r2, [r3, #128] ; 0x80 return HAL_OK; 800d6d6: 2300 movs r3, #0 } 800d6d8: 4618 mov r0, r3 800d6da: 370c adds r7, #12 800d6dc: 46bd mov sp, r7 800d6de: f85d 7b04 ldr.w r7, [sp], #4 800d6e2: 4770 bx lr 0800d6e4 : * @brief Set SDMMC Power state to ON. * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx) { 800d6e4: b480 push {r7} 800d6e6: b083 sub sp, #12 800d6e8: af00 add r7, sp, #0 800d6ea: 6078 str r0, [r7, #4] /* Set power state to ON */ SDMMCx->POWER |= SDMMC_POWER_PWRCTRL; 800d6ec: 687b ldr r3, [r7, #4] 800d6ee: 681b ldr r3, [r3, #0] 800d6f0: f043 0203 orr.w r2, r3, #3 800d6f4: 687b ldr r3, [r7, #4] 800d6f6: 601a str r2, [r3, #0] return HAL_OK; 800d6f8: 2300 movs r3, #0 } 800d6fa: 4618 mov r0, r3 800d6fc: 370c adds r7, #12 800d6fe: 46bd mov sp, r7 800d700: f85d 7b04 ldr.w r7, [sp], #4 800d704: 4770 bx lr 0800d706 : * - 0x00: Power OFF * - 0x02: Power UP * - 0x03: Power ON */ uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx) { 800d706: b480 push {r7} 800d708: b083 sub sp, #12 800d70a: af00 add r7, sp, #0 800d70c: 6078 str r0, [r7, #4] return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL); 800d70e: 687b ldr r3, [r7, #4] 800d710: 681b ldr r3, [r3, #0] 800d712: f003 0303 and.w r3, r3, #3 } 800d716: 4618 mov r0, r3 800d718: 370c adds r7, #12 800d71a: 46bd mov sp, r7 800d71c: f85d 7b04 ldr.w r7, [sp], #4 800d720: 4770 bx lr ... 0800d724 : * @param Command: pointer to a SDMMC_CmdInitTypeDef structure that contains * the configuration information for the SDMMC command * @retval HAL status */ HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command) { 800d724: b480 push {r7} 800d726: b085 sub sp, #20 800d728: af00 add r7, sp, #0 800d72a: 6078 str r0, [r7, #4] 800d72c: 6039 str r1, [r7, #0] uint32_t tmpreg = 0; 800d72e: 2300 movs r3, #0 800d730: 60fb str r3, [r7, #12] assert_param(IS_SDMMC_RESPONSE(Command->Response)); assert_param(IS_SDMMC_WAIT(Command->WaitForInterrupt)); assert_param(IS_SDMMC_CPSM(Command->CPSM)); /* Set the SDMMC Argument value */ SDMMCx->ARG = Command->Argument; 800d732: 683b ldr r3, [r7, #0] 800d734: 681a ldr r2, [r3, #0] 800d736: 687b ldr r3, [r7, #4] 800d738: 609a str r2, [r3, #8] /* Set SDMMC command parameters */ tmpreg |= (uint32_t)(Command->CmdIndex | \ 800d73a: 683b ldr r3, [r7, #0] 800d73c: 685a ldr r2, [r3, #4] Command->Response | \ 800d73e: 683b ldr r3, [r7, #0] 800d740: 689b ldr r3, [r3, #8] tmpreg |= (uint32_t)(Command->CmdIndex | \ 800d742: 431a orrs r2, r3 Command->WaitForInterrupt | \ 800d744: 683b ldr r3, [r7, #0] 800d746: 68db ldr r3, [r3, #12] Command->Response | \ 800d748: 431a orrs r2, r3 Command->CPSM); 800d74a: 683b ldr r3, [r7, #0] 800d74c: 691b ldr r3, [r3, #16] Command->WaitForInterrupt | \ 800d74e: 4313 orrs r3, r2 tmpreg |= (uint32_t)(Command->CmdIndex | \ 800d750: 68fa ldr r2, [r7, #12] 800d752: 4313 orrs r3, r2 800d754: 60fb str r3, [r7, #12] /* Write to SDMMC CMD register */ MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, tmpreg); 800d756: 687b ldr r3, [r7, #4] 800d758: 68da ldr r2, [r3, #12] 800d75a: 4b06 ldr r3, [pc, #24] ; (800d774 ) 800d75c: 4013 ands r3, r2 800d75e: 68fa ldr r2, [r7, #12] 800d760: 431a orrs r2, r3 800d762: 687b ldr r3, [r7, #4] 800d764: 60da str r2, [r3, #12] return HAL_OK; 800d766: 2300 movs r3, #0 } 800d768: 4618 mov r0, r3 800d76a: 3714 adds r7, #20 800d76c: 46bd mov sp, r7 800d76e: f85d 7b04 ldr.w r7, [sp], #4 800d772: 4770 bx lr 800d774: fffee0c0 .word 0xfffee0c0 0800d778 : * @brief Return the command index of last command for which response received * @param SDMMCx: Pointer to SDMMC register base * @retval Command index of the last command response received */ uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx) { 800d778: b480 push {r7} 800d77a: b083 sub sp, #12 800d77c: af00 add r7, sp, #0 800d77e: 6078 str r0, [r7, #4] return (uint8_t)(SDMMCx->RESPCMD); 800d780: 687b ldr r3, [r7, #4] 800d782: 691b ldr r3, [r3, #16] 800d784: b2db uxtb r3, r3 } 800d786: 4618 mov r0, r3 800d788: 370c adds r7, #12 800d78a: 46bd mov sp, r7 800d78c: f85d 7b04 ldr.w r7, [sp], #4 800d790: 4770 bx lr 0800d792 : * @arg SDMMC_RESP3: Response Register 3 * @arg SDMMC_RESP4: Response Register 4 * @retval The Corresponding response register value */ uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response) { 800d792: b480 push {r7} 800d794: b085 sub sp, #20 800d796: af00 add r7, sp, #0 800d798: 6078 str r0, [r7, #4] 800d79a: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_SDMMC_RESP(Response)); /* Get the response */ tmp = (uint32_t)(&(SDMMCx->RESP1)) + Response; 800d79c: 687b ldr r3, [r7, #4] 800d79e: 3314 adds r3, #20 800d7a0: 461a mov r2, r3 800d7a2: 683b ldr r3, [r7, #0] 800d7a4: 4413 add r3, r2 800d7a6: 60fb str r3, [r7, #12] return (*(__IO uint32_t *) tmp); 800d7a8: 68fb ldr r3, [r7, #12] 800d7aa: 681b ldr r3, [r3, #0] } 800d7ac: 4618 mov r0, r3 800d7ae: 3714 adds r7, #20 800d7b0: 46bd mov sp, r7 800d7b2: f85d 7b04 ldr.w r7, [sp], #4 800d7b6: 4770 bx lr 0800d7b8 : * @param Data : pointer to a SDMMC_DataInitTypeDef structure * that contains the configuration information for the SDMMC data. * @retval HAL status */ HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data) { 800d7b8: b480 push {r7} 800d7ba: b085 sub sp, #20 800d7bc: af00 add r7, sp, #0 800d7be: 6078 str r0, [r7, #4] 800d7c0: 6039 str r1, [r7, #0] uint32_t tmpreg = 0; 800d7c2: 2300 movs r3, #0 800d7c4: 60fb str r3, [r7, #12] assert_param(IS_SDMMC_TRANSFER_DIR(Data->TransferDir)); assert_param(IS_SDMMC_TRANSFER_MODE(Data->TransferMode)); assert_param(IS_SDMMC_DPSM(Data->DPSM)); /* Set the SDMMC Data TimeOut value */ SDMMCx->DTIMER = Data->DataTimeOut; 800d7c6: 683b ldr r3, [r7, #0] 800d7c8: 681a ldr r2, [r3, #0] 800d7ca: 687b ldr r3, [r7, #4] 800d7cc: 625a str r2, [r3, #36] ; 0x24 /* Set the SDMMC DataLength value */ SDMMCx->DLEN = Data->DataLength; 800d7ce: 683b ldr r3, [r7, #0] 800d7d0: 685a ldr r2, [r3, #4] 800d7d2: 687b ldr r3, [r7, #4] 800d7d4: 629a str r2, [r3, #40] ; 0x28 /* Set the SDMMC data configuration parameters */ tmpreg |= (uint32_t)(Data->DataBlockSize | \ 800d7d6: 683b ldr r3, [r7, #0] 800d7d8: 689a ldr r2, [r3, #8] Data->TransferDir | \ 800d7da: 683b ldr r3, [r7, #0] 800d7dc: 68db ldr r3, [r3, #12] tmpreg |= (uint32_t)(Data->DataBlockSize | \ 800d7de: 431a orrs r2, r3 Data->TransferMode | \ 800d7e0: 683b ldr r3, [r7, #0] 800d7e2: 691b ldr r3, [r3, #16] Data->TransferDir | \ 800d7e4: 431a orrs r2, r3 Data->DPSM); 800d7e6: 683b ldr r3, [r7, #0] 800d7e8: 695b ldr r3, [r3, #20] Data->TransferMode | \ 800d7ea: 4313 orrs r3, r2 tmpreg |= (uint32_t)(Data->DataBlockSize | \ 800d7ec: 68fa ldr r2, [r7, #12] 800d7ee: 4313 orrs r3, r2 800d7f0: 60fb str r3, [r7, #12] /* Write to SDMMC DCTRL */ MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, tmpreg); 800d7f2: 687b ldr r3, [r7, #4] 800d7f4: 6adb ldr r3, [r3, #44] ; 0x2c 800d7f6: f023 02ff bic.w r2, r3, #255 ; 0xff 800d7fa: 68fb ldr r3, [r7, #12] 800d7fc: 431a orrs r2, r3 800d7fe: 687b ldr r3, [r7, #4] 800d800: 62da str r2, [r3, #44] ; 0x2c return HAL_OK; 800d802: 2300 movs r3, #0 } 800d804: 4618 mov r0, r3 800d806: 3714 adds r7, #20 800d808: 46bd mov sp, r7 800d80a: f85d 7b04 ldr.w r7, [sp], #4 800d80e: 4770 bx lr 0800d810 : * @brief Send the Data Block Length command and check the response * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize) { 800d810: b580 push {r7, lr} 800d812: b088 sub sp, #32 800d814: af00 add r7, sp, #0 800d816: 6078 str r0, [r7, #4] 800d818: 6039 str r1, [r7, #0] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)BlockSize; 800d81a: 683b ldr r3, [r7, #0] 800d81c: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCKLEN; 800d81e: 2310 movs r3, #16 800d820: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800d822: f44f 7380 mov.w r3, #256 ; 0x100 800d826: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800d828: 2300 movs r3, #0 800d82a: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800d82c: f44f 5380 mov.w r3, #4096 ; 0x1000 800d830: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800d832: f107 0308 add.w r3, r7, #8 800d836: 4619 mov r1, r3 800d838: 6878 ldr r0, [r7, #4] 800d83a: f7ff ff73 bl 800d724 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCKLEN, SDMMC_CMDTIMEOUT); 800d83e: f241 3288 movw r2, #5000 ; 0x1388 800d842: 2110 movs r1, #16 800d844: 6878 ldr r0, [r7, #4] 800d846: f000 fa5f bl 800dd08 800d84a: 61f8 str r0, [r7, #28] return errorstate; 800d84c: 69fb ldr r3, [r7, #28] } 800d84e: 4618 mov r0, r3 800d850: 3720 adds r7, #32 800d852: 46bd mov sp, r7 800d854: bd80 pop {r7, pc} 0800d856 : * @brief Send the Read Single Block command and check the response * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) { 800d856: b580 push {r7, lr} 800d858: b088 sub sp, #32 800d85a: af00 add r7, sp, #0 800d85c: 6078 str r0, [r7, #4] 800d85e: 6039 str r1, [r7, #0] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; 800d860: 683b ldr r3, [r7, #0] 800d862: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_SINGLE_BLOCK; 800d864: 2311 movs r3, #17 800d866: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800d868: f44f 7380 mov.w r3, #256 ; 0x100 800d86c: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800d86e: 2300 movs r3, #0 800d870: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800d872: f44f 5380 mov.w r3, #4096 ; 0x1000 800d876: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800d878: f107 0308 add.w r3, r7, #8 800d87c: 4619 mov r1, r3 800d87e: 6878 ldr r0, [r7, #4] 800d880: f7ff ff50 bl 800d724 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_SINGLE_BLOCK, SDMMC_CMDTIMEOUT); 800d884: f241 3288 movw r2, #5000 ; 0x1388 800d888: 2111 movs r1, #17 800d88a: 6878 ldr r0, [r7, #4] 800d88c: f000 fa3c bl 800dd08 800d890: 61f8 str r0, [r7, #28] return errorstate; 800d892: 69fb ldr r3, [r7, #28] } 800d894: 4618 mov r0, r3 800d896: 3720 adds r7, #32 800d898: 46bd mov sp, r7 800d89a: bd80 pop {r7, pc} 0800d89c : * @brief Send the Read Multi Block command and check the response * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) { 800d89c: b580 push {r7, lr} 800d89e: b088 sub sp, #32 800d8a0: af00 add r7, sp, #0 800d8a2: 6078 str r0, [r7, #4] 800d8a4: 6039 str r1, [r7, #0] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; 800d8a6: 683b ldr r3, [r7, #0] 800d8a8: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_MULT_BLOCK; 800d8aa: 2312 movs r3, #18 800d8ac: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800d8ae: f44f 7380 mov.w r3, #256 ; 0x100 800d8b2: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800d8b4: 2300 movs r3, #0 800d8b6: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800d8b8: f44f 5380 mov.w r3, #4096 ; 0x1000 800d8bc: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800d8be: f107 0308 add.w r3, r7, #8 800d8c2: 4619 mov r1, r3 800d8c4: 6878 ldr r0, [r7, #4] 800d8c6: f7ff ff2d bl 800d724 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_MULT_BLOCK, SDMMC_CMDTIMEOUT); 800d8ca: f241 3288 movw r2, #5000 ; 0x1388 800d8ce: 2112 movs r1, #18 800d8d0: 6878 ldr r0, [r7, #4] 800d8d2: f000 fa19 bl 800dd08 800d8d6: 61f8 str r0, [r7, #28] return errorstate; 800d8d8: 69fb ldr r3, [r7, #28] } 800d8da: 4618 mov r0, r3 800d8dc: 3720 adds r7, #32 800d8de: 46bd mov sp, r7 800d8e0: bd80 pop {r7, pc} 0800d8e2 : * @brief Send the Write Single Block command and check the response * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) { 800d8e2: b580 push {r7, lr} 800d8e4: b088 sub sp, #32 800d8e6: af00 add r7, sp, #0 800d8e8: 6078 str r0, [r7, #4] 800d8ea: 6039 str r1, [r7, #0] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; 800d8ec: 683b ldr r3, [r7, #0] 800d8ee: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_SINGLE_BLOCK; 800d8f0: 2318 movs r3, #24 800d8f2: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800d8f4: f44f 7380 mov.w r3, #256 ; 0x100 800d8f8: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800d8fa: 2300 movs r3, #0 800d8fc: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800d8fe: f44f 5380 mov.w r3, #4096 ; 0x1000 800d902: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800d904: f107 0308 add.w r3, r7, #8 800d908: 4619 mov r1, r3 800d90a: 6878 ldr r0, [r7, #4] 800d90c: f7ff ff0a bl 800d724 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDMMC_CMDTIMEOUT); 800d910: f241 3288 movw r2, #5000 ; 0x1388 800d914: 2118 movs r1, #24 800d916: 6878 ldr r0, [r7, #4] 800d918: f000 f9f6 bl 800dd08 800d91c: 61f8 str r0, [r7, #28] return errorstate; 800d91e: 69fb ldr r3, [r7, #28] } 800d920: 4618 mov r0, r3 800d922: 3720 adds r7, #32 800d924: 46bd mov sp, r7 800d926: bd80 pop {r7, pc} 0800d928 : * @brief Send the Write Multi Block command and check the response * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) { 800d928: b580 push {r7, lr} 800d92a: b088 sub sp, #32 800d92c: af00 add r7, sp, #0 800d92e: 6078 str r0, [r7, #4] 800d930: 6039 str r1, [r7, #0] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; 800d932: 683b ldr r3, [r7, #0] 800d934: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_MULT_BLOCK; 800d936: 2319 movs r3, #25 800d938: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800d93a: f44f 7380 mov.w r3, #256 ; 0x100 800d93e: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800d940: 2300 movs r3, #0 800d942: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800d944: f44f 5380 mov.w r3, #4096 ; 0x1000 800d948: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800d94a: f107 0308 add.w r3, r7, #8 800d94e: 4619 mov r1, r3 800d950: 6878 ldr r0, [r7, #4] 800d952: f7ff fee7 bl 800d724 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_MULT_BLOCK, SDMMC_CMDTIMEOUT); 800d956: f241 3288 movw r2, #5000 ; 0x1388 800d95a: 2119 movs r1, #25 800d95c: 6878 ldr r0, [r7, #4] 800d95e: f000 f9d3 bl 800dd08 800d962: 61f8 str r0, [r7, #28] return errorstate; 800d964: 69fb ldr r3, [r7, #28] } 800d966: 4618 mov r0, r3 800d968: 3720 adds r7, #32 800d96a: 46bd mov sp, r7 800d96c: bd80 pop {r7, pc} ... 0800d970 : * @brief Send the Stop Transfer command and check the response. * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx) { 800d970: b580 push {r7, lr} 800d972: b088 sub sp, #32 800d974: af00 add r7, sp, #0 800d976: 6078 str r0, [r7, #4] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Send CMD12 STOP_TRANSMISSION */ sdmmc_cmdinit.Argument = 0U; 800d978: 2300 movs r3, #0 800d97a: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION; 800d97c: 230c movs r3, #12 800d97e: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800d980: f44f 7380 mov.w r3, #256 ; 0x100 800d984: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800d986: 2300 movs r3, #0 800d988: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800d98a: f44f 5380 mov.w r3, #4096 ; 0x1000 800d98e: 61bb str r3, [r7, #24] __SDMMC_CMDSTOP_ENABLE(SDMMCx); 800d990: 687b ldr r3, [r7, #4] 800d992: 68db ldr r3, [r3, #12] 800d994: f043 0280 orr.w r2, r3, #128 ; 0x80 800d998: 687b ldr r3, [r7, #4] 800d99a: 60da str r2, [r3, #12] __SDMMC_CMDTRANS_DISABLE(SDMMCx); 800d99c: 687b ldr r3, [r7, #4] 800d99e: 68db ldr r3, [r3, #12] 800d9a0: f023 0240 bic.w r2, r3, #64 ; 0x40 800d9a4: 687b ldr r3, [r7, #4] 800d9a6: 60da str r2, [r3, #12] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800d9a8: f107 0308 add.w r3, r7, #8 800d9ac: 4619 mov r1, r3 800d9ae: 6878 ldr r0, [r7, #4] 800d9b0: f7ff feb8 bl 800d724 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_STOP_TRANSMISSION, SDMMC_STOPTRANSFERTIMEOUT); 800d9b4: 4a0b ldr r2, [pc, #44] ; (800d9e4 ) 800d9b6: 210c movs r1, #12 800d9b8: 6878 ldr r0, [r7, #4] 800d9ba: f000 f9a5 bl 800dd08 800d9be: 61f8 str r0, [r7, #28] __SDMMC_CMDSTOP_DISABLE(SDMMCx); 800d9c0: 687b ldr r3, [r7, #4] 800d9c2: 68db ldr r3, [r3, #12] 800d9c4: f023 0280 bic.w r2, r3, #128 ; 0x80 800d9c8: 687b ldr r3, [r7, #4] 800d9ca: 60da str r2, [r3, #12] /* Ignore Address Out Of Range Error, Not relevant at end of memory */ if (errorstate == SDMMC_ERROR_ADDR_OUT_OF_RANGE) 800d9cc: 69fb ldr r3, [r7, #28] 800d9ce: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 800d9d2: d101 bne.n 800d9d8 { errorstate = SDMMC_ERROR_NONE; 800d9d4: 2300 movs r3, #0 800d9d6: 61fb str r3, [r7, #28] } return errorstate; 800d9d8: 69fb ldr r3, [r7, #28] } 800d9da: 4618 mov r0, r3 800d9dc: 3720 adds r7, #32 800d9de: 46bd mov sp, r7 800d9e0: bd80 pop {r7, pc} 800d9e2: bf00 nop 800d9e4: 05f5e100 .word 0x05f5e100 0800d9e8 : * @param SDMMCx: Pointer to SDMMC register base * @param addr: Address of the card to be selected * @retval HAL status */ uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint32_t Addr) { 800d9e8: b580 push {r7, lr} 800d9ea: b088 sub sp, #32 800d9ec: af00 add r7, sp, #0 800d9ee: 6078 str r0, [r7, #4] 800d9f0: 6039 str r1, [r7, #0] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Send CMD7 SDMMC_SEL_DESEL_CARD */ sdmmc_cmdinit.Argument = (uint32_t)Addr; 800d9f2: 683b ldr r3, [r7, #0] 800d9f4: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEL_DESEL_CARD; 800d9f6: 2307 movs r3, #7 800d9f8: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800d9fa: f44f 7380 mov.w r3, #256 ; 0x100 800d9fe: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800da00: 2300 movs r3, #0 800da02: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800da04: f44f 5380 mov.w r3, #4096 ; 0x1000 800da08: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800da0a: f107 0308 add.w r3, r7, #8 800da0e: 4619 mov r1, r3 800da10: 6878 ldr r0, [r7, #4] 800da12: f7ff fe87 bl 800d724 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEL_DESEL_CARD, SDMMC_CMDTIMEOUT); 800da16: f241 3288 movw r2, #5000 ; 0x1388 800da1a: 2107 movs r1, #7 800da1c: 6878 ldr r0, [r7, #4] 800da1e: f000 f973 bl 800dd08 800da22: 61f8 str r0, [r7, #28] return errorstate; 800da24: 69fb ldr r3, [r7, #28] } 800da26: 4618 mov r0, r3 800da28: 3720 adds r7, #32 800da2a: 46bd mov sp, r7 800da2c: bd80 pop {r7, pc} 0800da2e : * @brief Send the Go Idle State command and check the response. * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx) { 800da2e: b580 push {r7, lr} 800da30: b088 sub sp, #32 800da32: af00 add r7, sp, #0 800da34: 6078 str r0, [r7, #4] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; sdmmc_cmdinit.Argument = 0U; 800da36: 2300 movs r3, #0 800da38: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE; 800da3a: 2300 movs r3, #0 800da3c: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_NO; 800da3e: 2300 movs r3, #0 800da40: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800da42: 2300 movs r3, #0 800da44: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800da46: f44f 5380 mov.w r3, #4096 ; 0x1000 800da4a: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800da4c: f107 0308 add.w r3, r7, #8 800da50: 4619 mov r1, r3 800da52: 6878 ldr r0, [r7, #4] 800da54: f7ff fe66 bl 800d724 /* Check for error conditions */ errorstate = SDMMC_GetCmdError(SDMMCx); 800da58: 6878 ldr r0, [r7, #4] 800da5a: f000 fb97 bl 800e18c 800da5e: 61f8 str r0, [r7, #28] return errorstate; 800da60: 69fb ldr r3, [r7, #28] } 800da62: 4618 mov r0, r3 800da64: 3720 adds r7, #32 800da66: 46bd mov sp, r7 800da68: bd80 pop {r7, pc} 0800da6a : * @brief Send the Operating Condition command and check the response. * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx) { 800da6a: b580 push {r7, lr} 800da6c: b088 sub sp, #32 800da6e: af00 add r7, sp, #0 800da70: 6078 str r0, [r7, #4] /* Send CMD8 to verify SD card interface operating condition */ /* Argument: - [31:12]: Reserved (shall be set to '0') - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) - [7:0]: Check Pattern (recommended 0xAA) */ /* CMD Response: R7 */ sdmmc_cmdinit.Argument = SDMMC_CHECK_PATTERN; 800da72: f44f 73d5 mov.w r3, #426 ; 0x1aa 800da76: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; 800da78: 2308 movs r3, #8 800da7a: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800da7c: f44f 7380 mov.w r3, #256 ; 0x100 800da80: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800da82: 2300 movs r3, #0 800da84: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800da86: f44f 5380 mov.w r3, #4096 ; 0x1000 800da8a: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800da8c: f107 0308 add.w r3, r7, #8 800da90: 4619 mov r1, r3 800da92: 6878 ldr r0, [r7, #4] 800da94: f7ff fe46 bl 800d724 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp7(SDMMCx); 800da98: 6878 ldr r0, [r7, #4] 800da9a: f000 fb29 bl 800e0f0 800da9e: 61f8 str r0, [r7, #28] return errorstate; 800daa0: 69fb ldr r3, [r7, #28] } 800daa2: 4618 mov r0, r3 800daa4: 3720 adds r7, #32 800daa6: 46bd mov sp, r7 800daa8: bd80 pop {r7, pc} 0800daaa : * @param SDMMCx: Pointer to SDMMC register base * @param Argument: Command Argument * @retval HAL status */ uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) { 800daaa: b580 push {r7, lr} 800daac: b088 sub sp, #32 800daae: af00 add r7, sp, #0 800dab0: 6078 str r0, [r7, #4] 800dab2: 6039 str r1, [r7, #0] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; sdmmc_cmdinit.Argument = (uint32_t)Argument; 800dab4: 683b ldr r3, [r7, #0] 800dab6: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD; 800dab8: 2337 movs r3, #55 ; 0x37 800daba: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800dabc: f44f 7380 mov.w r3, #256 ; 0x100 800dac0: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800dac2: 2300 movs r3, #0 800dac4: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800dac6: f44f 5380 mov.w r3, #4096 ; 0x1000 800daca: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800dacc: f107 0308 add.w r3, r7, #8 800dad0: 4619 mov r1, r3 800dad2: 6878 ldr r0, [r7, #4] 800dad4: f7ff fe26 bl 800d724 /* Check for error conditions */ /* If there is a HAL_ERROR, it is a MMC card, else it is a SD card: SD card 2.0 (voltage range mismatch) or SD card 1.x */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_CMD, SDMMC_CMDTIMEOUT); 800dad8: f241 3288 movw r2, #5000 ; 0x1388 800dadc: 2137 movs r1, #55 ; 0x37 800dade: 6878 ldr r0, [r7, #4] 800dae0: f000 f912 bl 800dd08 800dae4: 61f8 str r0, [r7, #28] return errorstate; 800dae6: 69fb ldr r3, [r7, #28] } 800dae8: 4618 mov r0, r3 800daea: 3720 adds r7, #32 800daec: 46bd mov sp, r7 800daee: bd80 pop {r7, pc} 0800daf0 : * @param SDMMCx: Pointer to SDMMC register base * @param Argument: Command Argument * @retval HAL status */ uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) { 800daf0: b580 push {r7, lr} 800daf2: b088 sub sp, #32 800daf4: af00 add r7, sp, #0 800daf6: 6078 str r0, [r7, #4] 800daf8: 6039 str r1, [r7, #0] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; sdmmc_cmdinit.Argument = Argument; 800dafa: 683b ldr r3, [r7, #0] 800dafc: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND; 800dafe: 2329 movs r3, #41 ; 0x29 800db00: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800db02: f44f 7380 mov.w r3, #256 ; 0x100 800db06: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800db08: 2300 movs r3, #0 800db0a: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800db0c: f44f 5380 mov.w r3, #4096 ; 0x1000 800db10: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800db12: f107 0308 add.w r3, r7, #8 800db16: 4619 mov r1, r3 800db18: 6878 ldr r0, [r7, #4] 800db1a: f7ff fe03 bl 800d724 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp3(SDMMCx); 800db1e: 6878 ldr r0, [r7, #4] 800db20: f000 fa2e bl 800df80 800db24: 61f8 str r0, [r7, #28] return errorstate; 800db26: 69fb ldr r3, [r7, #28] } 800db28: 4618 mov r0, r3 800db2a: 3720 adds r7, #32 800db2c: 46bd mov sp, r7 800db2e: bd80 pop {r7, pc} 0800db30 : * @param SDMMCx: Pointer to SDMMC register base * @param BusWidth: BusWidth * @retval HAL status */ uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth) { 800db30: b580 push {r7, lr} 800db32: b088 sub sp, #32 800db34: af00 add r7, sp, #0 800db36: 6078 str r0, [r7, #4] 800db38: 6039 str r1, [r7, #0] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; sdmmc_cmdinit.Argument = (uint32_t)BusWidth; 800db3a: 683b ldr r3, [r7, #0] 800db3c: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH; 800db3e: 2306 movs r3, #6 800db40: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800db42: f44f 7380 mov.w r3, #256 ; 0x100 800db46: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800db48: 2300 movs r3, #0 800db4a: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800db4c: f44f 5380 mov.w r3, #4096 ; 0x1000 800db50: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800db52: f107 0308 add.w r3, r7, #8 800db56: 4619 mov r1, r3 800db58: 6878 ldr r0, [r7, #4] 800db5a: f7ff fde3 bl 800d724 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDMMC_CMDTIMEOUT); 800db5e: f241 3288 movw r2, #5000 ; 0x1388 800db62: 2106 movs r1, #6 800db64: 6878 ldr r0, [r7, #4] 800db66: f000 f8cf bl 800dd08 800db6a: 61f8 str r0, [r7, #28] return errorstate; 800db6c: 69fb ldr r3, [r7, #28] } 800db6e: 4618 mov r0, r3 800db70: 3720 adds r7, #32 800db72: 46bd mov sp, r7 800db74: bd80 pop {r7, pc} 0800db76 : * @brief Send the Send SCR command and check the response. * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx) { 800db76: b580 push {r7, lr} 800db78: b088 sub sp, #32 800db7a: af00 add r7, sp, #0 800db7c: 6078 str r0, [r7, #4] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Send CMD51 SD_APP_SEND_SCR */ sdmmc_cmdinit.Argument = 0U; 800db7e: 2300 movs r3, #0 800db80: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR; 800db82: 2333 movs r3, #51 ; 0x33 800db84: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800db86: f44f 7380 mov.w r3, #256 ; 0x100 800db8a: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800db8c: 2300 movs r3, #0 800db8e: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800db90: f44f 5380 mov.w r3, #4096 ; 0x1000 800db94: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800db96: f107 0308 add.w r3, r7, #8 800db9a: 4619 mov r1, r3 800db9c: 6878 ldr r0, [r7, #4] 800db9e: f7ff fdc1 bl 800d724 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_SEND_SCR, SDMMC_CMDTIMEOUT); 800dba2: f241 3288 movw r2, #5000 ; 0x1388 800dba6: 2133 movs r1, #51 ; 0x33 800dba8: 6878 ldr r0, [r7, #4] 800dbaa: f000 f8ad bl 800dd08 800dbae: 61f8 str r0, [r7, #28] return errorstate; 800dbb0: 69fb ldr r3, [r7, #28] } 800dbb2: 4618 mov r0, r3 800dbb4: 3720 adds r7, #32 800dbb6: 46bd mov sp, r7 800dbb8: bd80 pop {r7, pc} 0800dbba : * @brief Send the Send CID command and check the response. * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx) { 800dbba: b580 push {r7, lr} 800dbbc: b088 sub sp, #32 800dbbe: af00 add r7, sp, #0 800dbc0: 6078 str r0, [r7, #4] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Send CMD2 ALL_SEND_CID */ sdmmc_cmdinit.Argument = 0U; 800dbc2: 2300 movs r3, #0 800dbc4: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID; 800dbc6: 2302 movs r3, #2 800dbc8: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG; 800dbca: f44f 7340 mov.w r3, #768 ; 0x300 800dbce: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800dbd0: 2300 movs r3, #0 800dbd2: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800dbd4: f44f 5380 mov.w r3, #4096 ; 0x1000 800dbd8: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800dbda: f107 0308 add.w r3, r7, #8 800dbde: 4619 mov r1, r3 800dbe0: 6878 ldr r0, [r7, #4] 800dbe2: f7ff fd9f bl 800d724 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp2(SDMMCx); 800dbe6: 6878 ldr r0, [r7, #4] 800dbe8: f000 f980 bl 800deec 800dbec: 61f8 str r0, [r7, #28] return errorstate; 800dbee: 69fb ldr r3, [r7, #28] } 800dbf0: 4618 mov r0, r3 800dbf2: 3720 adds r7, #32 800dbf4: 46bd mov sp, r7 800dbf6: bd80 pop {r7, pc} 0800dbf8 : * @param SDMMCx: Pointer to SDMMC register base * @param Argument: Command Argument * @retval HAL status */ uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) { 800dbf8: b580 push {r7, lr} 800dbfa: b088 sub sp, #32 800dbfc: af00 add r7, sp, #0 800dbfe: 6078 str r0, [r7, #4] 800dc00: 6039 str r1, [r7, #0] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Send CMD9 SEND_CSD */ sdmmc_cmdinit.Argument = Argument; 800dc02: 683b ldr r3, [r7, #0] 800dc04: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_CSD; 800dc06: 2309 movs r3, #9 800dc08: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG; 800dc0a: f44f 7340 mov.w r3, #768 ; 0x300 800dc0e: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800dc10: 2300 movs r3, #0 800dc12: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800dc14: f44f 5380 mov.w r3, #4096 ; 0x1000 800dc18: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800dc1a: f107 0308 add.w r3, r7, #8 800dc1e: 4619 mov r1, r3 800dc20: 6878 ldr r0, [r7, #4] 800dc22: f7ff fd7f bl 800d724 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp2(SDMMCx); 800dc26: 6878 ldr r0, [r7, #4] 800dc28: f000 f960 bl 800deec 800dc2c: 61f8 str r0, [r7, #28] return errorstate; 800dc2e: 69fb ldr r3, [r7, #28] } 800dc30: 4618 mov r0, r3 800dc32: 3720 adds r7, #32 800dc34: 46bd mov sp, r7 800dc36: bd80 pop {r7, pc} 0800dc38 : * @param SDMMCx: Pointer to SDMMC register base * @param pRCA: Card RCA * @retval HAL status */ uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA) { 800dc38: b580 push {r7, lr} 800dc3a: b088 sub sp, #32 800dc3c: af00 add r7, sp, #0 800dc3e: 6078 str r0, [r7, #4] 800dc40: 6039 str r1, [r7, #0] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; /* Send CMD3 SD_CMD_SET_REL_ADDR */ sdmmc_cmdinit.Argument = 0U; 800dc42: 2300 movs r3, #0 800dc44: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; 800dc46: 2303 movs r3, #3 800dc48: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800dc4a: f44f 7380 mov.w r3, #256 ; 0x100 800dc4e: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800dc50: 2300 movs r3, #0 800dc52: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800dc54: f44f 5380 mov.w r3, #4096 ; 0x1000 800dc58: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800dc5a: f107 0308 add.w r3, r7, #8 800dc5e: 4619 mov r1, r3 800dc60: 6878 ldr r0, [r7, #4] 800dc62: f7ff fd5f bl 800d724 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp6(SDMMCx, SDMMC_CMD_SET_REL_ADDR, pRCA); 800dc66: 683a ldr r2, [r7, #0] 800dc68: 2103 movs r1, #3 800dc6a: 6878 ldr r0, [r7, #4] 800dc6c: f000 f9c8 bl 800e000 800dc70: 61f8 str r0, [r7, #28] return errorstate; 800dc72: 69fb ldr r3, [r7, #28] } 800dc74: 4618 mov r0, r3 800dc76: 3720 adds r7, #32 800dc78: 46bd mov sp, r7 800dc7a: bd80 pop {r7, pc} 0800dc7c : * @param SDMMCx: Pointer to SDMMC register base * @param Argument: Command Argument * @retval HAL status */ uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument) { 800dc7c: b580 push {r7, lr} 800dc7e: b088 sub sp, #32 800dc80: af00 add r7, sp, #0 800dc82: 6078 str r0, [r7, #4] 800dc84: 6039 str r1, [r7, #0] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; sdmmc_cmdinit.Argument = Argument; 800dc86: 683b ldr r3, [r7, #0] 800dc88: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS; 800dc8a: 230d movs r3, #13 800dc8c: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800dc8e: f44f 7380 mov.w r3, #256 ; 0x100 800dc92: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800dc94: 2300 movs r3, #0 800dc96: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800dc98: f44f 5380 mov.w r3, #4096 ; 0x1000 800dc9c: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800dc9e: f107 0308 add.w r3, r7, #8 800dca2: 4619 mov r1, r3 800dca4: 6878 ldr r0, [r7, #4] 800dca6: f7ff fd3d bl 800d724 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEND_STATUS, SDMMC_CMDTIMEOUT); 800dcaa: f241 3288 movw r2, #5000 ; 0x1388 800dcae: 210d movs r1, #13 800dcb0: 6878 ldr r0, [r7, #4] 800dcb2: f000 f829 bl 800dd08 800dcb6: 61f8 str r0, [r7, #28] return errorstate; 800dcb8: 69fb ldr r3, [r7, #28] } 800dcba: 4618 mov r0, r3 800dcbc: 3720 adds r7, #32 800dcbe: 46bd mov sp, r7 800dcc0: bd80 pop {r7, pc} 0800dcc2 : * @brief Send the Status register command and check the response. * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx) { 800dcc2: b580 push {r7, lr} 800dcc4: b088 sub sp, #32 800dcc6: af00 add r7, sp, #0 800dcc8: 6078 str r0, [r7, #4] SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; sdmmc_cmdinit.Argument = 0U; 800dcca: 2300 movs r3, #0 800dccc: 60bb str r3, [r7, #8] sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_STATUS; 800dcce: 230d movs r3, #13 800dcd0: 60fb str r3, [r7, #12] sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; 800dcd2: f44f 7380 mov.w r3, #256 ; 0x100 800dcd6: 613b str r3, [r7, #16] sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; 800dcd8: 2300 movs r3, #0 800dcda: 617b str r3, [r7, #20] sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; 800dcdc: f44f 5380 mov.w r3, #4096 ; 0x1000 800dce0: 61bb str r3, [r7, #24] (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); 800dce2: f107 0308 add.w r3, r7, #8 800dce6: 4619 mov r1, r3 800dce8: 6878 ldr r0, [r7, #4] 800dcea: f7ff fd1b bl 800d724 /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_STATUS, SDMMC_CMDTIMEOUT); 800dcee: f241 3288 movw r2, #5000 ; 0x1388 800dcf2: 210d movs r1, #13 800dcf4: 6878 ldr r0, [r7, #4] 800dcf6: f000 f807 bl 800dd08 800dcfa: 61f8 str r0, [r7, #28] return errorstate; 800dcfc: 69fb ldr r3, [r7, #28] } 800dcfe: 4618 mov r0, r3 800dd00: 3720 adds r7, #32 800dd02: 46bd mov sp, r7 800dd04: bd80 pop {r7, pc} ... 0800dd08 : * @param hsd: SD handle * @param SD_CMD: The sent command index * @retval SD Card error state */ uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout) { 800dd08: b580 push {r7, lr} 800dd0a: b088 sub sp, #32 800dd0c: af00 add r7, sp, #0 800dd0e: 60f8 str r0, [r7, #12] 800dd10: 460b mov r3, r1 800dd12: 607a str r2, [r7, #4] 800dd14: 72fb strb r3, [r7, #11] uint32_t response_r1; uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The Timeout is expressed in ms */ uint32_t count = Timeout * (SystemCoreClock / 8U / 1000U); 800dd16: 4b70 ldr r3, [pc, #448] ; (800ded8 ) 800dd18: 681b ldr r3, [r3, #0] 800dd1a: 4a70 ldr r2, [pc, #448] ; (800dedc ) 800dd1c: fba2 2303 umull r2, r3, r2, r3 800dd20: 0a5a lsrs r2, r3, #9 800dd22: 687b ldr r3, [r7, #4] 800dd24: fb02 f303 mul.w r3, r2, r3 800dd28: 61fb str r3, [r7, #28] do { if (count-- == 0U) 800dd2a: 69fb ldr r3, [r7, #28] 800dd2c: 1e5a subs r2, r3, #1 800dd2e: 61fa str r2, [r7, #28] 800dd30: 2b00 cmp r3, #0 800dd32: d102 bne.n 800dd3a { return SDMMC_ERROR_TIMEOUT; 800dd34: f04f 4300 mov.w r3, #2147483648 ; 0x80000000 800dd38: e0c9 b.n 800dece } sta_reg = SDMMCx->STA; 800dd3a: 68fb ldr r3, [r7, #12] 800dd3c: 6b5b ldr r3, [r3, #52] ; 0x34 800dd3e: 61bb str r3, [r7, #24] } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT | 800dd40: 69ba ldr r2, [r7, #24] 800dd42: 4b67 ldr r3, [pc, #412] ; (800dee0 ) 800dd44: 4013 ands r3, r2 SDMMC_FLAG_BUSYD0END)) == 0U) || ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); 800dd46: 2b00 cmp r3, #0 800dd48: d0ef beq.n 800dd2a 800dd4a: 69bb ldr r3, [r7, #24] 800dd4c: f403 5300 and.w r3, r3, #8192 ; 0x2000 800dd50: 2b00 cmp r3, #0 800dd52: d1ea bne.n 800dd2a if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) 800dd54: 68fb ldr r3, [r7, #12] 800dd56: 6b5b ldr r3, [r3, #52] ; 0x34 800dd58: f003 0304 and.w r3, r3, #4 800dd5c: 2b00 cmp r3, #0 800dd5e: d004 beq.n 800dd6a { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); 800dd60: 68fb ldr r3, [r7, #12] 800dd62: 2204 movs r2, #4 800dd64: 639a str r2, [r3, #56] ; 0x38 return SDMMC_ERROR_CMD_RSP_TIMEOUT; 800dd66: 2304 movs r3, #4 800dd68: e0b1 b.n 800dece } else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) 800dd6a: 68fb ldr r3, [r7, #12] 800dd6c: 6b5b ldr r3, [r3, #52] ; 0x34 800dd6e: f003 0301 and.w r3, r3, #1 800dd72: 2b00 cmp r3, #0 800dd74: d004 beq.n 800dd80 { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); 800dd76: 68fb ldr r3, [r7, #12] 800dd78: 2201 movs r2, #1 800dd7a: 639a str r2, [r3, #56] ; 0x38 return SDMMC_ERROR_CMD_CRC_FAIL; 800dd7c: 2301 movs r3, #1 800dd7e: e0a6 b.n 800dece { /* Nothing to do */ } /* Clear all the static flags */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); 800dd80: 68fb ldr r3, [r7, #12] 800dd82: 4a58 ldr r2, [pc, #352] ; (800dee4 ) 800dd84: 639a str r2, [r3, #56] ; 0x38 /* Check response received is of desired command */ if (SDMMC_GetCommandResponse(SDMMCx) != SD_CMD) 800dd86: 68f8 ldr r0, [r7, #12] 800dd88: f7ff fcf6 bl 800d778 800dd8c: 4603 mov r3, r0 800dd8e: 461a mov r2, r3 800dd90: 7afb ldrb r3, [r7, #11] 800dd92: 4293 cmp r3, r2 800dd94: d001 beq.n 800dd9a { return SDMMC_ERROR_CMD_CRC_FAIL; 800dd96: 2301 movs r3, #1 800dd98: e099 b.n 800dece } /* We have received response, retrieve it for analysis */ response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); 800dd9a: 2100 movs r1, #0 800dd9c: 68f8 ldr r0, [r7, #12] 800dd9e: f7ff fcf8 bl 800d792 800dda2: 6178 str r0, [r7, #20] if ((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO) 800dda4: 697a ldr r2, [r7, #20] 800dda6: 4b50 ldr r3, [pc, #320] ; (800dee8 ) 800dda8: 4013 ands r3, r2 800ddaa: 2b00 cmp r3, #0 800ddac: d101 bne.n 800ddb2 { return SDMMC_ERROR_NONE; 800ddae: 2300 movs r3, #0 800ddb0: e08d b.n 800dece } else if ((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE) 800ddb2: 697b ldr r3, [r7, #20] 800ddb4: 2b00 cmp r3, #0 800ddb6: da02 bge.n 800ddbe { return SDMMC_ERROR_ADDR_OUT_OF_RANGE; 800ddb8: f04f 7300 mov.w r3, #33554432 ; 0x2000000 800ddbc: e087 b.n 800dece } else if ((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED) 800ddbe: 697b ldr r3, [r7, #20] 800ddc0: f003 4380 and.w r3, r3, #1073741824 ; 0x40000000 800ddc4: 2b00 cmp r3, #0 800ddc6: d001 beq.n 800ddcc { return SDMMC_ERROR_ADDR_MISALIGNED; 800ddc8: 2340 movs r3, #64 ; 0x40 800ddca: e080 b.n 800dece } else if ((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR) 800ddcc: 697b ldr r3, [r7, #20] 800ddce: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 800ddd2: 2b00 cmp r3, #0 800ddd4: d001 beq.n 800ddda { return SDMMC_ERROR_BLOCK_LEN_ERR; 800ddd6: 2380 movs r3, #128 ; 0x80 800ddd8: e079 b.n 800dece } else if ((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR) 800ddda: 697b ldr r3, [r7, #20] 800dddc: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 800dde0: 2b00 cmp r3, #0 800dde2: d002 beq.n 800ddea { return SDMMC_ERROR_ERASE_SEQ_ERR; 800dde4: f44f 7380 mov.w r3, #256 ; 0x100 800dde8: e071 b.n 800dece } else if ((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM) 800ddea: 697b ldr r3, [r7, #20] 800ddec: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 800ddf0: 2b00 cmp r3, #0 800ddf2: d002 beq.n 800ddfa { return SDMMC_ERROR_BAD_ERASE_PARAM; 800ddf4: f44f 7300 mov.w r3, #512 ; 0x200 800ddf8: e069 b.n 800dece } else if ((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION) 800ddfa: 697b ldr r3, [r7, #20] 800ddfc: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 800de00: 2b00 cmp r3, #0 800de02: d002 beq.n 800de0a { return SDMMC_ERROR_WRITE_PROT_VIOLATION; 800de04: f44f 6380 mov.w r3, #1024 ; 0x400 800de08: e061 b.n 800dece } else if ((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED) 800de0a: 697b ldr r3, [r7, #20] 800de0c: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 800de10: 2b00 cmp r3, #0 800de12: d002 beq.n 800de1a { return SDMMC_ERROR_LOCK_UNLOCK_FAILED; 800de14: f44f 6300 mov.w r3, #2048 ; 0x800 800de18: e059 b.n 800dece } else if ((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED) 800de1a: 697b ldr r3, [r7, #20] 800de1c: f403 0300 and.w r3, r3, #8388608 ; 0x800000 800de20: 2b00 cmp r3, #0 800de22: d002 beq.n 800de2a { return SDMMC_ERROR_COM_CRC_FAILED; 800de24: f44f 5380 mov.w r3, #4096 ; 0x1000 800de28: e051 b.n 800dece } else if ((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD) 800de2a: 697b ldr r3, [r7, #20] 800de2c: f403 0380 and.w r3, r3, #4194304 ; 0x400000 800de30: 2b00 cmp r3, #0 800de32: d002 beq.n 800de3a { return SDMMC_ERROR_ILLEGAL_CMD; 800de34: f44f 5300 mov.w r3, #8192 ; 0x2000 800de38: e049 b.n 800dece } else if ((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED) 800de3a: 697b ldr r3, [r7, #20] 800de3c: f403 1300 and.w r3, r3, #2097152 ; 0x200000 800de40: 2b00 cmp r3, #0 800de42: d002 beq.n 800de4a { return SDMMC_ERROR_CARD_ECC_FAILED; 800de44: f44f 4380 mov.w r3, #16384 ; 0x4000 800de48: e041 b.n 800dece } else if ((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR) 800de4a: 697b ldr r3, [r7, #20] 800de4c: f403 1380 and.w r3, r3, #1048576 ; 0x100000 800de50: 2b00 cmp r3, #0 800de52: d002 beq.n 800de5a { return SDMMC_ERROR_CC_ERR; 800de54: f44f 4300 mov.w r3, #32768 ; 0x8000 800de58: e039 b.n 800dece } else if ((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN) 800de5a: 697b ldr r3, [r7, #20] 800de5c: f403 2380 and.w r3, r3, #262144 ; 0x40000 800de60: 2b00 cmp r3, #0 800de62: d002 beq.n 800de6a { return SDMMC_ERROR_STREAM_READ_UNDERRUN; 800de64: f44f 3300 mov.w r3, #131072 ; 0x20000 800de68: e031 b.n 800dece } else if ((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN) 800de6a: 697b ldr r3, [r7, #20] 800de6c: f403 3300 and.w r3, r3, #131072 ; 0x20000 800de70: 2b00 cmp r3, #0 800de72: d002 beq.n 800de7a { return SDMMC_ERROR_STREAM_WRITE_OVERRUN; 800de74: f44f 2380 mov.w r3, #262144 ; 0x40000 800de78: e029 b.n 800dece } else if ((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE) 800de7a: 697b ldr r3, [r7, #20] 800de7c: f403 3380 and.w r3, r3, #65536 ; 0x10000 800de80: 2b00 cmp r3, #0 800de82: d002 beq.n 800de8a { return SDMMC_ERROR_CID_CSD_OVERWRITE; 800de84: f44f 2300 mov.w r3, #524288 ; 0x80000 800de88: e021 b.n 800dece } else if ((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP) 800de8a: 697b ldr r3, [r7, #20] 800de8c: f403 4300 and.w r3, r3, #32768 ; 0x8000 800de90: 2b00 cmp r3, #0 800de92: d002 beq.n 800de9a { return SDMMC_ERROR_WP_ERASE_SKIP; 800de94: f44f 1380 mov.w r3, #1048576 ; 0x100000 800de98: e019 b.n 800dece } else if ((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED) 800de9a: 697b ldr r3, [r7, #20] 800de9c: f403 4380 and.w r3, r3, #16384 ; 0x4000 800dea0: 2b00 cmp r3, #0 800dea2: d002 beq.n 800deaa { return SDMMC_ERROR_CARD_ECC_DISABLED; 800dea4: f44f 1300 mov.w r3, #2097152 ; 0x200000 800dea8: e011 b.n 800dece } else if ((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET) 800deaa: 697b ldr r3, [r7, #20] 800deac: f403 5300 and.w r3, r3, #8192 ; 0x2000 800deb0: 2b00 cmp r3, #0 800deb2: d002 beq.n 800deba { return SDMMC_ERROR_ERASE_RESET; 800deb4: f44f 0380 mov.w r3, #4194304 ; 0x400000 800deb8: e009 b.n 800dece } else if ((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR) 800deba: 697b ldr r3, [r7, #20] 800debc: f003 0308 and.w r3, r3, #8 800dec0: 2b00 cmp r3, #0 800dec2: d002 beq.n 800deca { return SDMMC_ERROR_AKE_SEQ_ERR; 800dec4: f44f 0300 mov.w r3, #8388608 ; 0x800000 800dec8: e001 b.n 800dece } else { return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; 800deca: f44f 3380 mov.w r3, #65536 ; 0x10000 } } 800dece: 4618 mov r0, r3 800ded0: 3720 adds r7, #32 800ded2: 46bd mov sp, r7 800ded4: bd80 pop {r7, pc} 800ded6: bf00 nop 800ded8: 20000000 .word 0x20000000 800dedc: 10624dd3 .word 0x10624dd3 800dee0: 00200045 .word 0x00200045 800dee4: 002000c5 .word 0x002000c5 800dee8: fdffe008 .word 0xfdffe008 0800deec : * @brief Checks for error conditions for R2 (CID or CSD) response. * @param hsd: SD handle * @retval SD Card error state */ uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx) { 800deec: b480 push {r7} 800deee: b085 sub sp, #20 800def0: af00 add r7, sp, #0 800def2: 6078 str r0, [r7, #4] uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); 800def4: 4b1f ldr r3, [pc, #124] ; (800df74 ) 800def6: 681b ldr r3, [r3, #0] 800def8: 4a1f ldr r2, [pc, #124] ; (800df78 ) 800defa: fba2 2303 umull r2, r3, r2, r3 800defe: 0a5b lsrs r3, r3, #9 800df00: f241 3288 movw r2, #5000 ; 0x1388 800df04: fb02 f303 mul.w r3, r2, r3 800df08: 60fb str r3, [r7, #12] do { if (count-- == 0U) 800df0a: 68fb ldr r3, [r7, #12] 800df0c: 1e5a subs r2, r3, #1 800df0e: 60fa str r2, [r7, #12] 800df10: 2b00 cmp r3, #0 800df12: d102 bne.n 800df1a { return SDMMC_ERROR_TIMEOUT; 800df14: f04f 4300 mov.w r3, #2147483648 ; 0x80000000 800df18: e026 b.n 800df68 } sta_reg = SDMMCx->STA; 800df1a: 687b ldr r3, [r7, #4] 800df1c: 6b5b ldr r3, [r3, #52] ; 0x34 800df1e: 60bb str r3, [r7, #8] } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || 800df20: 68bb ldr r3, [r7, #8] 800df22: f003 0345 and.w r3, r3, #69 ; 0x45 ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); 800df26: 2b00 cmp r3, #0 800df28: d0ef beq.n 800df0a 800df2a: 68bb ldr r3, [r7, #8] 800df2c: f403 5300 and.w r3, r3, #8192 ; 0x2000 } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || 800df30: 2b00 cmp r3, #0 800df32: d1ea bne.n 800df0a if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) 800df34: 687b ldr r3, [r7, #4] 800df36: 6b5b ldr r3, [r3, #52] ; 0x34 800df38: f003 0304 and.w r3, r3, #4 800df3c: 2b00 cmp r3, #0 800df3e: d004 beq.n 800df4a { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); 800df40: 687b ldr r3, [r7, #4] 800df42: 2204 movs r2, #4 800df44: 639a str r2, [r3, #56] ; 0x38 return SDMMC_ERROR_CMD_RSP_TIMEOUT; 800df46: 2304 movs r3, #4 800df48: e00e b.n 800df68 } else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) 800df4a: 687b ldr r3, [r7, #4] 800df4c: 6b5b ldr r3, [r3, #52] ; 0x34 800df4e: f003 0301 and.w r3, r3, #1 800df52: 2b00 cmp r3, #0 800df54: d004 beq.n 800df60 { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); 800df56: 687b ldr r3, [r7, #4] 800df58: 2201 movs r2, #1 800df5a: 639a str r2, [r3, #56] ; 0x38 return SDMMC_ERROR_CMD_CRC_FAIL; 800df5c: 2301 movs r3, #1 800df5e: e003 b.n 800df68 } else { /* No error flag set */ /* Clear all the static flags */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); 800df60: 687b ldr r3, [r7, #4] 800df62: 4a06 ldr r2, [pc, #24] ; (800df7c ) 800df64: 639a str r2, [r3, #56] ; 0x38 } return SDMMC_ERROR_NONE; 800df66: 2300 movs r3, #0 } 800df68: 4618 mov r0, r3 800df6a: 3714 adds r7, #20 800df6c: 46bd mov sp, r7 800df6e: f85d 7b04 ldr.w r7, [sp], #4 800df72: 4770 bx lr 800df74: 20000000 .word 0x20000000 800df78: 10624dd3 .word 0x10624dd3 800df7c: 002000c5 .word 0x002000c5 0800df80 : * @brief Checks for error conditions for R3 (OCR) response. * @param hsd: SD handle * @retval SD Card error state */ uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) { 800df80: b480 push {r7} 800df82: b085 sub sp, #20 800df84: af00 add r7, sp, #0 800df86: 6078 str r0, [r7, #4] uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); 800df88: 4b1a ldr r3, [pc, #104] ; (800dff4 ) 800df8a: 681b ldr r3, [r3, #0] 800df8c: 4a1a ldr r2, [pc, #104] ; (800dff8 ) 800df8e: fba2 2303 umull r2, r3, r2, r3 800df92: 0a5b lsrs r3, r3, #9 800df94: f241 3288 movw r2, #5000 ; 0x1388 800df98: fb02 f303 mul.w r3, r2, r3 800df9c: 60fb str r3, [r7, #12] do { if (count-- == 0U) 800df9e: 68fb ldr r3, [r7, #12] 800dfa0: 1e5a subs r2, r3, #1 800dfa2: 60fa str r2, [r7, #12] 800dfa4: 2b00 cmp r3, #0 800dfa6: d102 bne.n 800dfae { return SDMMC_ERROR_TIMEOUT; 800dfa8: f04f 4300 mov.w r3, #2147483648 ; 0x80000000 800dfac: e01b b.n 800dfe6 } sta_reg = SDMMCx->STA; 800dfae: 687b ldr r3, [r7, #4] 800dfb0: 6b5b ldr r3, [r3, #52] ; 0x34 800dfb2: 60bb str r3, [r7, #8] } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || 800dfb4: 68bb ldr r3, [r7, #8] 800dfb6: f003 0345 and.w r3, r3, #69 ; 0x45 ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); 800dfba: 2b00 cmp r3, #0 800dfbc: d0ef beq.n 800df9e 800dfbe: 68bb ldr r3, [r7, #8] 800dfc0: f403 5300 and.w r3, r3, #8192 ; 0x2000 } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || 800dfc4: 2b00 cmp r3, #0 800dfc6: d1ea bne.n 800df9e if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) 800dfc8: 687b ldr r3, [r7, #4] 800dfca: 6b5b ldr r3, [r3, #52] ; 0x34 800dfcc: f003 0304 and.w r3, r3, #4 800dfd0: 2b00 cmp r3, #0 800dfd2: d004 beq.n 800dfde { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); 800dfd4: 687b ldr r3, [r7, #4] 800dfd6: 2204 movs r2, #4 800dfd8: 639a str r2, [r3, #56] ; 0x38 return SDMMC_ERROR_CMD_RSP_TIMEOUT; 800dfda: 2304 movs r3, #4 800dfdc: e003 b.n 800dfe6 } else { /* Clear all the static flags */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); 800dfde: 687b ldr r3, [r7, #4] 800dfe0: 4a06 ldr r2, [pc, #24] ; (800dffc ) 800dfe2: 639a str r2, [r3, #56] ; 0x38 } return SDMMC_ERROR_NONE; 800dfe4: 2300 movs r3, #0 } 800dfe6: 4618 mov r0, r3 800dfe8: 3714 adds r7, #20 800dfea: 46bd mov sp, r7 800dfec: f85d 7b04 ldr.w r7, [sp], #4 800dff0: 4770 bx lr 800dff2: bf00 nop 800dff4: 20000000 .word 0x20000000 800dff8: 10624dd3 .word 0x10624dd3 800dffc: 002000c5 .word 0x002000c5 0800e000 : * @param pRCA: Pointer to the variable that will contain the SD card relative * address RCA * @retval SD Card error state */ uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA) { 800e000: b580 push {r7, lr} 800e002: b088 sub sp, #32 800e004: af00 add r7, sp, #0 800e006: 60f8 str r0, [r7, #12] 800e008: 460b mov r3, r1 800e00a: 607a str r2, [r7, #4] 800e00c: 72fb strb r3, [r7, #11] uint32_t response_r1; uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); 800e00e: 4b35 ldr r3, [pc, #212] ; (800e0e4 ) 800e010: 681b ldr r3, [r3, #0] 800e012: 4a35 ldr r2, [pc, #212] ; (800e0e8 ) 800e014: fba2 2303 umull r2, r3, r2, r3 800e018: 0a5b lsrs r3, r3, #9 800e01a: f241 3288 movw r2, #5000 ; 0x1388 800e01e: fb02 f303 mul.w r3, r2, r3 800e022: 61fb str r3, [r7, #28] do { if (count-- == 0U) 800e024: 69fb ldr r3, [r7, #28] 800e026: 1e5a subs r2, r3, #1 800e028: 61fa str r2, [r7, #28] 800e02a: 2b00 cmp r3, #0 800e02c: d102 bne.n 800e034 { return SDMMC_ERROR_TIMEOUT; 800e02e: f04f 4300 mov.w r3, #2147483648 ; 0x80000000 800e032: e052 b.n 800e0da } sta_reg = SDMMCx->STA; 800e034: 68fb ldr r3, [r7, #12] 800e036: 6b5b ldr r3, [r3, #52] ; 0x34 800e038: 61bb str r3, [r7, #24] } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || 800e03a: 69bb ldr r3, [r7, #24] 800e03c: f003 0345 and.w r3, r3, #69 ; 0x45 ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); 800e040: 2b00 cmp r3, #0 800e042: d0ef beq.n 800e024 800e044: 69bb ldr r3, [r7, #24] 800e046: f403 5300 and.w r3, r3, #8192 ; 0x2000 } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || 800e04a: 2b00 cmp r3, #0 800e04c: d1ea bne.n 800e024 if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) 800e04e: 68fb ldr r3, [r7, #12] 800e050: 6b5b ldr r3, [r3, #52] ; 0x34 800e052: f003 0304 and.w r3, r3, #4 800e056: 2b00 cmp r3, #0 800e058: d004 beq.n 800e064 { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); 800e05a: 68fb ldr r3, [r7, #12] 800e05c: 2204 movs r2, #4 800e05e: 639a str r2, [r3, #56] ; 0x38 return SDMMC_ERROR_CMD_RSP_TIMEOUT; 800e060: 2304 movs r3, #4 800e062: e03a b.n 800e0da } else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) 800e064: 68fb ldr r3, [r7, #12] 800e066: 6b5b ldr r3, [r3, #52] ; 0x34 800e068: f003 0301 and.w r3, r3, #1 800e06c: 2b00 cmp r3, #0 800e06e: d004 beq.n 800e07a { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); 800e070: 68fb ldr r3, [r7, #12] 800e072: 2201 movs r2, #1 800e074: 639a str r2, [r3, #56] ; 0x38 return SDMMC_ERROR_CMD_CRC_FAIL; 800e076: 2301 movs r3, #1 800e078: e02f b.n 800e0da { /* Nothing to do */ } /* Check response received is of desired command */ if (SDMMC_GetCommandResponse(SDMMCx) != SD_CMD) 800e07a: 68f8 ldr r0, [r7, #12] 800e07c: f7ff fb7c bl 800d778 800e080: 4603 mov r3, r0 800e082: 461a mov r2, r3 800e084: 7afb ldrb r3, [r7, #11] 800e086: 4293 cmp r3, r2 800e088: d001 beq.n 800e08e { return SDMMC_ERROR_CMD_CRC_FAIL; 800e08a: 2301 movs r3, #1 800e08c: e025 b.n 800e0da } /* Clear all the static flags */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); 800e08e: 68fb ldr r3, [r7, #12] 800e090: 4a16 ldr r2, [pc, #88] ; (800e0ec ) 800e092: 639a str r2, [r3, #56] ; 0x38 /* We have received response, retrieve it. */ response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); 800e094: 2100 movs r1, #0 800e096: 68f8 ldr r0, [r7, #12] 800e098: f7ff fb7b bl 800d792 800e09c: 6178 str r0, [r7, #20] if ((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | 800e09e: 697b ldr r3, [r7, #20] 800e0a0: f403 4360 and.w r3, r3, #57344 ; 0xe000 800e0a4: 2b00 cmp r3, #0 800e0a6: d106 bne.n 800e0b6 SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO) { *pRCA = (uint16_t)(response_r1 >> 16); 800e0a8: 697b ldr r3, [r7, #20] 800e0aa: 0c1b lsrs r3, r3, #16 800e0ac: b29a uxth r2, r3 800e0ae: 687b ldr r3, [r7, #4] 800e0b0: 801a strh r2, [r3, #0] return SDMMC_ERROR_NONE; 800e0b2: 2300 movs r3, #0 800e0b4: e011 b.n 800e0da } else if ((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD) 800e0b6: 697b ldr r3, [r7, #20] 800e0b8: f403 4380 and.w r3, r3, #16384 ; 0x4000 800e0bc: 2b00 cmp r3, #0 800e0be: d002 beq.n 800e0c6 { return SDMMC_ERROR_ILLEGAL_CMD; 800e0c0: f44f 5300 mov.w r3, #8192 ; 0x2000 800e0c4: e009 b.n 800e0da } else if ((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED) 800e0c6: 697b ldr r3, [r7, #20] 800e0c8: f403 4300 and.w r3, r3, #32768 ; 0x8000 800e0cc: 2b00 cmp r3, #0 800e0ce: d002 beq.n 800e0d6 { return SDMMC_ERROR_COM_CRC_FAILED; 800e0d0: f44f 5380 mov.w r3, #4096 ; 0x1000 800e0d4: e001 b.n 800e0da } else { return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; 800e0d6: f44f 3380 mov.w r3, #65536 ; 0x10000 } } 800e0da: 4618 mov r0, r3 800e0dc: 3720 adds r7, #32 800e0de: 46bd mov sp, r7 800e0e0: bd80 pop {r7, pc} 800e0e2: bf00 nop 800e0e4: 20000000 .word 0x20000000 800e0e8: 10624dd3 .word 0x10624dd3 800e0ec: 002000c5 .word 0x002000c5 0800e0f0 : * @brief Checks for error conditions for R7 response. * @param hsd: SD handle * @retval SD Card error state */ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) { 800e0f0: b480 push {r7} 800e0f2: b085 sub sp, #20 800e0f4: af00 add r7, sp, #0 800e0f6: 6078 str r0, [r7, #4] uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); 800e0f8: 4b22 ldr r3, [pc, #136] ; (800e184 ) 800e0fa: 681b ldr r3, [r3, #0] 800e0fc: 4a22 ldr r2, [pc, #136] ; (800e188 ) 800e0fe: fba2 2303 umull r2, r3, r2, r3 800e102: 0a5b lsrs r3, r3, #9 800e104: f241 3288 movw r2, #5000 ; 0x1388 800e108: fb02 f303 mul.w r3, r2, r3 800e10c: 60fb str r3, [r7, #12] do { if (count-- == 0U) 800e10e: 68fb ldr r3, [r7, #12] 800e110: 1e5a subs r2, r3, #1 800e112: 60fa str r2, [r7, #12] 800e114: 2b00 cmp r3, #0 800e116: d102 bne.n 800e11e { return SDMMC_ERROR_TIMEOUT; 800e118: f04f 4300 mov.w r3, #2147483648 ; 0x80000000 800e11c: e02c b.n 800e178 } sta_reg = SDMMCx->STA; 800e11e: 687b ldr r3, [r7, #4] 800e120: 6b5b ldr r3, [r3, #52] ; 0x34 800e122: 60bb str r3, [r7, #8] } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || 800e124: 68bb ldr r3, [r7, #8] 800e126: f003 0345 and.w r3, r3, #69 ; 0x45 ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); 800e12a: 2b00 cmp r3, #0 800e12c: d0ef beq.n 800e10e 800e12e: 68bb ldr r3, [r7, #8] 800e130: f403 5300 and.w r3, r3, #8192 ; 0x2000 } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || 800e134: 2b00 cmp r3, #0 800e136: d1ea bne.n 800e10e if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) 800e138: 687b ldr r3, [r7, #4] 800e13a: 6b5b ldr r3, [r3, #52] ; 0x34 800e13c: f003 0304 and.w r3, r3, #4 800e140: 2b00 cmp r3, #0 800e142: d004 beq.n 800e14e { /* Card is not SD V2.0 compliant */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); 800e144: 687b ldr r3, [r7, #4] 800e146: 2204 movs r2, #4 800e148: 639a str r2, [r3, #56] ; 0x38 return SDMMC_ERROR_CMD_RSP_TIMEOUT; 800e14a: 2304 movs r3, #4 800e14c: e014 b.n 800e178 } else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) 800e14e: 687b ldr r3, [r7, #4] 800e150: 6b5b ldr r3, [r3, #52] ; 0x34 800e152: f003 0301 and.w r3, r3, #1 800e156: 2b00 cmp r3, #0 800e158: d004 beq.n 800e164 { /* Card is not SD V2.0 compliant */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); 800e15a: 687b ldr r3, [r7, #4] 800e15c: 2201 movs r2, #1 800e15e: 639a str r2, [r3, #56] ; 0x38 return SDMMC_ERROR_CMD_CRC_FAIL; 800e160: 2301 movs r3, #1 800e162: e009 b.n 800e178 else { /* Nothing to do */ } if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND)) 800e164: 687b ldr r3, [r7, #4] 800e166: 6b5b ldr r3, [r3, #52] ; 0x34 800e168: f003 0340 and.w r3, r3, #64 ; 0x40 800e16c: 2b00 cmp r3, #0 800e16e: d002 beq.n 800e176 { /* Card is SD V2.0 compliant */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND); 800e170: 687b ldr r3, [r7, #4] 800e172: 2240 movs r2, #64 ; 0x40 800e174: 639a str r2, [r3, #56] ; 0x38 } return SDMMC_ERROR_NONE; 800e176: 2300 movs r3, #0 } 800e178: 4618 mov r0, r3 800e17a: 3714 adds r7, #20 800e17c: 46bd mov sp, r7 800e17e: f85d 7b04 ldr.w r7, [sp], #4 800e182: 4770 bx lr 800e184: 20000000 .word 0x20000000 800e188: 10624dd3 .word 0x10624dd3 0800e18c : * @brief Checks for error conditions for CMD0. * @param hsd: SD handle * @retval SD Card error state */ static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx) { 800e18c: b480 push {r7} 800e18e: b085 sub sp, #20 800e190: af00 add r7, sp, #0 800e192: 6078 str r0, [r7, #4] /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); 800e194: 4b11 ldr r3, [pc, #68] ; (800e1dc ) 800e196: 681b ldr r3, [r3, #0] 800e198: 4a11 ldr r2, [pc, #68] ; (800e1e0 ) 800e19a: fba2 2303 umull r2, r3, r2, r3 800e19e: 0a5b lsrs r3, r3, #9 800e1a0: f241 3288 movw r2, #5000 ; 0x1388 800e1a4: fb02 f303 mul.w r3, r2, r3 800e1a8: 60fb str r3, [r7, #12] do { if (count-- == 0U) 800e1aa: 68fb ldr r3, [r7, #12] 800e1ac: 1e5a subs r2, r3, #1 800e1ae: 60fa str r2, [r7, #12] 800e1b0: 2b00 cmp r3, #0 800e1b2: d102 bne.n 800e1ba { return SDMMC_ERROR_TIMEOUT; 800e1b4: f04f 4300 mov.w r3, #2147483648 ; 0x80000000 800e1b8: e009 b.n 800e1ce } } while (!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT)); 800e1ba: 687b ldr r3, [r7, #4] 800e1bc: 6b5b ldr r3, [r3, #52] ; 0x34 800e1be: f003 0380 and.w r3, r3, #128 ; 0x80 800e1c2: 2b00 cmp r3, #0 800e1c4: d0f1 beq.n 800e1aa /* Clear all the static flags */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); 800e1c6: 687b ldr r3, [r7, #4] 800e1c8: 4a06 ldr r2, [pc, #24] ; (800e1e4 ) 800e1ca: 639a str r2, [r3, #56] ; 0x38 return SDMMC_ERROR_NONE; 800e1cc: 2300 movs r3, #0 } 800e1ce: 4618 mov r0, r3 800e1d0: 3714 adds r7, #20 800e1d2: 46bd mov sp, r7 800e1d4: f85d 7b04 ldr.w r7, [sp], #4 800e1d8: 4770 bx lr 800e1da: bf00 nop 800e1dc: 20000000 .word 0x20000000 800e1e0: 10624dd3 .word 0x10624dd3 800e1e4: 002000c5 .word 0x002000c5 0800e1e8 : /* USER CODE BEGIN Variables */ /* USER CODE END Variables */ void MX_FATFS_Init(void) { 800e1e8: b580 push {r7, lr} 800e1ea: af00 add r7, sp, #0 /*## FatFS: Link the SD driver ###########################*/ retSD = FATFS_LinkDriver(&SD_Driver, SDPath); 800e1ec: 4904 ldr r1, [pc, #16] ; (800e200 ) 800e1ee: 4805 ldr r0, [pc, #20] ; (800e204 ) 800e1f0: f000 f9e4 bl 800e5bc 800e1f4: 4603 mov r3, r0 800e1f6: 461a mov r2, r3 800e1f8: 4b03 ldr r3, [pc, #12] ; (800e208 ) 800e1fa: 701a strb r2, [r3, #0] /* USER CODE BEGIN Init */ /* additional user code for init */ /* USER CODE END Init */ } 800e1fc: bf00 nop 800e1fe: bd80 pop {r7, pc} 800e200: 20000af0 .word 0x20000af0 800e204: 0800e69c .word 0x0800e69c 800e208: 20000aec .word 0x20000aec 0800e20c : /** * @brief Initializes the SD card device. * @retval SD status */ __weak uint8_t BSP_SD_Init(void) { 800e20c: b580 push {r7, lr} 800e20e: b082 sub sp, #8 800e210: af00 add r7, sp, #0 uint8_t sd_state = MSD_OK; 800e212: 2300 movs r3, #0 800e214: 71fb strb r3, [r7, #7] /* Check if the SD card is plugged in the slot */ if (BSP_SD_IsDetected() != SD_PRESENT) 800e216: f000 f879 bl 800e30c 800e21a: 4603 mov r3, r0 800e21c: 2b01 cmp r3, #1 800e21e: d001 beq.n 800e224 { return MSD_ERROR_SD_NOT_PRESENT; 800e220: 2302 movs r3, #2 800e222: e012 b.n 800e24a } /* HAL SD initialization */ sd_state = HAL_SD_Init(&hsd1); 800e224: 480b ldr r0, [pc, #44] ; (800e254 ) 800e226: f7fb fc59 bl 8009adc 800e22a: 4603 mov r3, r0 800e22c: 71fb strb r3, [r7, #7] /* Configure SD Bus width (4 bits mode selected) */ if (sd_state == MSD_OK) 800e22e: 79fb ldrb r3, [r7, #7] 800e230: 2b00 cmp r3, #0 800e232: d109 bne.n 800e248 { /* Enable wide operation */ if (HAL_SD_ConfigWideBusOperation(&hsd1, SDMMC_BUS_WIDE_4B) != HAL_OK) 800e234: f44f 4180 mov.w r1, #16384 ; 0x4000 800e238: 4806 ldr r0, [pc, #24] ; (800e254 ) 800e23a: f7fc fb0f bl 800a85c 800e23e: 4603 mov r3, r0 800e240: 2b00 cmp r3, #0 800e242: d001 beq.n 800e248 { sd_state = MSD_ERROR; 800e244: 2301 movs r3, #1 800e246: 71fb strb r3, [r7, #7] } } return sd_state; 800e248: 79fb ldrb r3, [r7, #7] } 800e24a: 4618 mov r0, r3 800e24c: 3708 adds r7, #8 800e24e: 46bd mov sp, r7 800e250: bd80 pop {r7, pc} 800e252: bf00 nop 800e254: 200004a0 .word 0x200004a0 0800e258 : * @param NumOfBlocks: Number of SD blocks to read * @param Timeout: Timeout for read operation * @retval SD status */ __weak uint8_t BSP_SD_ReadBlocks(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks, uint32_t Timeout) { 800e258: b580 push {r7, lr} 800e25a: b088 sub sp, #32 800e25c: af02 add r7, sp, #8 800e25e: 60f8 str r0, [r7, #12] 800e260: 60b9 str r1, [r7, #8] 800e262: 607a str r2, [r7, #4] 800e264: 603b str r3, [r7, #0] uint8_t sd_state = MSD_OK; 800e266: 2300 movs r3, #0 800e268: 75fb strb r3, [r7, #23] if (HAL_SD_ReadBlocks(&hsd1, (uint8_t *)pData, ReadAddr, NumOfBlocks, Timeout) != HAL_OK) 800e26a: 683b ldr r3, [r7, #0] 800e26c: 9300 str r3, [sp, #0] 800e26e: 687b ldr r3, [r7, #4] 800e270: 68ba ldr r2, [r7, #8] 800e272: 68f9 ldr r1, [r7, #12] 800e274: 4806 ldr r0, [pc, #24] ; (800e290 ) 800e276: f7fb fd4b bl 8009d10 800e27a: 4603 mov r3, r0 800e27c: 2b00 cmp r3, #0 800e27e: d001 beq.n 800e284 { sd_state = MSD_ERROR; 800e280: 2301 movs r3, #1 800e282: 75fb strb r3, [r7, #23] } return sd_state; 800e284: 7dfb ldrb r3, [r7, #23] } 800e286: 4618 mov r0, r3 800e288: 3718 adds r7, #24 800e28a: 46bd mov sp, r7 800e28c: bd80 pop {r7, pc} 800e28e: bf00 nop 800e290: 200004a0 .word 0x200004a0 0800e294 : * @param NumOfBlocks: Number of SD blocks to write * @param Timeout: Timeout for write operation * @retval SD status */ __weak uint8_t BSP_SD_WriteBlocks(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks, uint32_t Timeout) { 800e294: b580 push {r7, lr} 800e296: b088 sub sp, #32 800e298: af02 add r7, sp, #8 800e29a: 60f8 str r0, [r7, #12] 800e29c: 60b9 str r1, [r7, #8] 800e29e: 607a str r2, [r7, #4] 800e2a0: 603b str r3, [r7, #0] uint8_t sd_state = MSD_OK; 800e2a2: 2300 movs r3, #0 800e2a4: 75fb strb r3, [r7, #23] if (HAL_SD_WriteBlocks(&hsd1, (uint8_t *)pData, WriteAddr, NumOfBlocks, Timeout) != HAL_OK) 800e2a6: 683b ldr r3, [r7, #0] 800e2a8: 9300 str r3, [sp, #0] 800e2aa: 687b ldr r3, [r7, #4] 800e2ac: 68ba ldr r2, [r7, #8] 800e2ae: 68f9 ldr r1, [r7, #12] 800e2b0: 4806 ldr r0, [pc, #24] ; (800e2cc ) 800e2b2: f7fb feb7 bl 800a024 800e2b6: 4603 mov r3, r0 800e2b8: 2b00 cmp r3, #0 800e2ba: d001 beq.n 800e2c0 { sd_state = MSD_ERROR; 800e2bc: 2301 movs r3, #1 800e2be: 75fb strb r3, [r7, #23] } return sd_state; 800e2c0: 7dfb ldrb r3, [r7, #23] } 800e2c2: 4618 mov r0, r3 800e2c4: 3718 adds r7, #24 800e2c6: 46bd mov sp, r7 800e2c8: bd80 pop {r7, pc} 800e2ca: bf00 nop 800e2cc: 200004a0 .word 0x200004a0 0800e2d0 : * This value can be one of the following values: * @arg SD_TRANSFER_OK: No data transfer is acting * @arg SD_TRANSFER_BUSY: Data transfer is acting */ __weak uint8_t BSP_SD_GetCardState(void) { 800e2d0: b580 push {r7, lr} 800e2d2: af00 add r7, sp, #0 return ((HAL_SD_GetCardState(&hsd1) == HAL_SD_CARD_TRANSFER ) ? SD_TRANSFER_OK : SD_TRANSFER_BUSY); 800e2d4: 4805 ldr r0, [pc, #20] ; (800e2ec ) 800e2d6: f7fc fbd3 bl 800aa80 800e2da: 4603 mov r3, r0 800e2dc: 2b04 cmp r3, #4 800e2de: bf14 ite ne 800e2e0: 2301 movne r3, #1 800e2e2: 2300 moveq r3, #0 800e2e4: b2db uxtb r3, r3 } 800e2e6: 4618 mov r0, r3 800e2e8: bd80 pop {r7, pc} 800e2ea: bf00 nop 800e2ec: 200004a0 .word 0x200004a0 0800e2f0 : * @brief Get SD information about specific SD card. * @param CardInfo: Pointer to HAL_SD_CardInfoTypedef structure * @retval None */ __weak void BSP_SD_GetCardInfo(HAL_SD_CardInfoTypeDef *CardInfo) { 800e2f0: b580 push {r7, lr} 800e2f2: b082 sub sp, #8 800e2f4: af00 add r7, sp, #0 800e2f6: 6078 str r0, [r7, #4] /* Get SD card Information */ HAL_SD_GetCardInfo(&hsd1, CardInfo); 800e2f8: 6879 ldr r1, [r7, #4] 800e2fa: 4803 ldr r0, [pc, #12] ; (800e308 ) 800e2fc: f7fc fa82 bl 800a804 } 800e300: bf00 nop 800e302: 3708 adds r7, #8 800e304: 46bd mov sp, r7 800e306: bd80 pop {r7, pc} 800e308: 200004a0 .word 0x200004a0 0800e30c : * @brief Detects if SD card is correctly plugged in the memory slot or not. * @param None * @retval Returns if SD is detected or not */ __weak uint8_t BSP_SD_IsDetected(void) { 800e30c: b580 push {r7, lr} 800e30e: b082 sub sp, #8 800e310: af00 add r7, sp, #0 __IO uint8_t status = SD_PRESENT; 800e312: 2301 movs r3, #1 800e314: 71fb strb r3, [r7, #7] if (BSP_PlatformIsDetected() == 0x0) 800e316: f000 f80b bl 800e330 800e31a: 4603 mov r3, r0 800e31c: 2b00 cmp r3, #0 800e31e: d101 bne.n 800e324 { status = SD_NOT_PRESENT; 800e320: 2300 movs r3, #0 800e322: 71fb strb r3, [r7, #7] } return status; 800e324: 79fb ldrb r3, [r7, #7] 800e326: b2db uxtb r3, r3 } 800e328: 4618 mov r0, r3 800e32a: 3708 adds r7, #8 800e32c: 46bd mov sp, r7 800e32e: bd80 pop {r7, pc} 0800e330 : ****************************************************************************** */ /* USER CODE END Header */ #include "fatfs_platform.h" uint8_t BSP_PlatformIsDetected(void) { 800e330: b580 push {r7, lr} 800e332: b082 sub sp, #8 800e334: af00 add r7, sp, #0 uint8_t status = SD_PRESENT; 800e336: 2301 movs r3, #1 800e338: 71fb strb r3, [r7, #7] /* Check SD card detect pin */ if(HAL_GPIO_ReadPin(SD_DETECT_GPIO_PORT, SD_DETECT_PIN) != GPIO_PIN_RESET) 800e33a: 2110 movs r1, #16 800e33c: 4806 ldr r0, [pc, #24] ; (800e358 ) 800e33e: f7f6 ff71 bl 8005224 800e342: 4603 mov r3, r0 800e344: 2b00 cmp r3, #0 800e346: d001 beq.n 800e34c { status = SD_NOT_PRESENT; 800e348: 2300 movs r3, #0 800e34a: 71fb strb r3, [r7, #7] } /* USER CODE BEGIN 1 */ /* user code can be inserted here */ /* USER CODE END 1 */ return status; 800e34c: 79fb ldrb r3, [r7, #7] } 800e34e: 4618 mov r0, r3 800e350: 3708 adds r7, #8 800e352: 46bd mov sp, r7 800e354: bd80 pop {r7, pc} 800e356: bf00 nop 800e358: 58020800 .word 0x58020800 0800e35c : /* USER CODE END beforeFunctionSection */ /* Private functions ---------------------------------------------------------*/ static DSTATUS SD_CheckStatus(BYTE lun) { 800e35c: b580 push {r7, lr} 800e35e: b082 sub sp, #8 800e360: af00 add r7, sp, #0 800e362: 4603 mov r3, r0 800e364: 71fb strb r3, [r7, #7] Stat = STA_NOINIT; 800e366: 4b0b ldr r3, [pc, #44] ; (800e394 ) 800e368: 2201 movs r2, #1 800e36a: 701a strb r2, [r3, #0] if(BSP_SD_GetCardState() == MSD_OK) 800e36c: f7ff ffb0 bl 800e2d0 800e370: 4603 mov r3, r0 800e372: 2b00 cmp r3, #0 800e374: d107 bne.n 800e386 { Stat &= ~STA_NOINIT; 800e376: 4b07 ldr r3, [pc, #28] ; (800e394 ) 800e378: 781b ldrb r3, [r3, #0] 800e37a: b2db uxtb r3, r3 800e37c: f023 0301 bic.w r3, r3, #1 800e380: b2da uxtb r2, r3 800e382: 4b04 ldr r3, [pc, #16] ; (800e394 ) 800e384: 701a strb r2, [r3, #0] } return Stat; 800e386: 4b03 ldr r3, [pc, #12] ; (800e394 ) 800e388: 781b ldrb r3, [r3, #0] 800e38a: b2db uxtb r3, r3 } 800e38c: 4618 mov r0, r3 800e38e: 3708 adds r7, #8 800e390: 46bd mov sp, r7 800e392: bd80 pop {r7, pc} 800e394: 2000000d .word 0x2000000d 0800e398 : * @brief Initializes a Drive * @param lun : not used * @retval DSTATUS: Operation status */ DSTATUS SD_initialize(BYTE lun) { 800e398: b580 push {r7, lr} 800e39a: b082 sub sp, #8 800e39c: af00 add r7, sp, #0 800e39e: 4603 mov r3, r0 800e3a0: 71fb strb r3, [r7, #7] Stat = STA_NOINIT; 800e3a2: 4b0b ldr r3, [pc, #44] ; (800e3d0 ) 800e3a4: 2201 movs r2, #1 800e3a6: 701a strb r2, [r3, #0] #if !defined(DISABLE_SD_INIT) if(BSP_SD_Init() == MSD_OK) 800e3a8: f7ff ff30 bl 800e20c 800e3ac: 4603 mov r3, r0 800e3ae: 2b00 cmp r3, #0 800e3b0: d107 bne.n 800e3c2 { Stat = SD_CheckStatus(lun); 800e3b2: 79fb ldrb r3, [r7, #7] 800e3b4: 4618 mov r0, r3 800e3b6: f7ff ffd1 bl 800e35c 800e3ba: 4603 mov r3, r0 800e3bc: 461a mov r2, r3 800e3be: 4b04 ldr r3, [pc, #16] ; (800e3d0 ) 800e3c0: 701a strb r2, [r3, #0] #else Stat = SD_CheckStatus(lun); #endif return Stat; 800e3c2: 4b03 ldr r3, [pc, #12] ; (800e3d0 ) 800e3c4: 781b ldrb r3, [r3, #0] 800e3c6: b2db uxtb r3, r3 } 800e3c8: 4618 mov r0, r3 800e3ca: 3708 adds r7, #8 800e3cc: 46bd mov sp, r7 800e3ce: bd80 pop {r7, pc} 800e3d0: 2000000d .word 0x2000000d 0800e3d4 : * @brief Gets Disk Status * @param lun : not used * @retval DSTATUS: Operation status */ DSTATUS SD_status(BYTE lun) { 800e3d4: b580 push {r7, lr} 800e3d6: b082 sub sp, #8 800e3d8: af00 add r7, sp, #0 800e3da: 4603 mov r3, r0 800e3dc: 71fb strb r3, [r7, #7] return SD_CheckStatus(lun); 800e3de: 79fb ldrb r3, [r7, #7] 800e3e0: 4618 mov r0, r3 800e3e2: f7ff ffbb bl 800e35c 800e3e6: 4603 mov r3, r0 } 800e3e8: 4618 mov r0, r3 800e3ea: 3708 adds r7, #8 800e3ec: 46bd mov sp, r7 800e3ee: bd80 pop {r7, pc} 0800e3f0 : * @param count: Number of sectors to read (1..128) * @retval DRESULT: Operation result */ DRESULT SD_read(BYTE lun, BYTE *buff, DWORD sector, UINT count) { 800e3f0: b580 push {r7, lr} 800e3f2: b086 sub sp, #24 800e3f4: af00 add r7, sp, #0 800e3f6: 60b9 str r1, [r7, #8] 800e3f8: 607a str r2, [r7, #4] 800e3fa: 603b str r3, [r7, #0] 800e3fc: 4603 mov r3, r0 800e3fe: 73fb strb r3, [r7, #15] DRESULT res = RES_ERROR; 800e400: 2301 movs r3, #1 800e402: 75fb strb r3, [r7, #23] if(BSP_SD_ReadBlocks((uint32_t*)buff, 800e404: f04f 33ff mov.w r3, #4294967295 800e408: 683a ldr r2, [r7, #0] 800e40a: 6879 ldr r1, [r7, #4] 800e40c: 68b8 ldr r0, [r7, #8] 800e40e: f7ff ff23 bl 800e258 800e412: 4603 mov r3, r0 800e414: 2b00 cmp r3, #0 800e416: d107 bne.n 800e428 (uint32_t) (sector), count, SD_TIMEOUT) == MSD_OK) { /* wait until the read operation is finished */ while(BSP_SD_GetCardState()!= MSD_OK) 800e418: bf00 nop 800e41a: f7ff ff59 bl 800e2d0 800e41e: 4603 mov r3, r0 800e420: 2b00 cmp r3, #0 800e422: d1fa bne.n 800e41a { } res = RES_OK; 800e424: 2300 movs r3, #0 800e426: 75fb strb r3, [r7, #23] } return res; 800e428: 7dfb ldrb r3, [r7, #23] } 800e42a: 4618 mov r0, r3 800e42c: 3718 adds r7, #24 800e42e: 46bd mov sp, r7 800e430: bd80 pop {r7, pc} 0800e432 : * @retval DRESULT: Operation result */ #if _USE_WRITE == 1 DRESULT SD_write(BYTE lun, const BYTE *buff, DWORD sector, UINT count) { 800e432: b580 push {r7, lr} 800e434: b086 sub sp, #24 800e436: af00 add r7, sp, #0 800e438: 60b9 str r1, [r7, #8] 800e43a: 607a str r2, [r7, #4] 800e43c: 603b str r3, [r7, #0] 800e43e: 4603 mov r3, r0 800e440: 73fb strb r3, [r7, #15] DRESULT res = RES_ERROR; 800e442: 2301 movs r3, #1 800e444: 75fb strb r3, [r7, #23] if(BSP_SD_WriteBlocks((uint32_t*)buff, 800e446: f04f 33ff mov.w r3, #4294967295 800e44a: 683a ldr r2, [r7, #0] 800e44c: 6879 ldr r1, [r7, #4] 800e44e: 68b8 ldr r0, [r7, #8] 800e450: f7ff ff20 bl 800e294 800e454: 4603 mov r3, r0 800e456: 2b00 cmp r3, #0 800e458: d107 bne.n 800e46a (uint32_t)(sector), count, SD_TIMEOUT) == MSD_OK) { /* wait until the Write operation is finished */ while(BSP_SD_GetCardState() != MSD_OK) 800e45a: bf00 nop 800e45c: f7ff ff38 bl 800e2d0 800e460: 4603 mov r3, r0 800e462: 2b00 cmp r3, #0 800e464: d1fa bne.n 800e45c { } res = RES_OK; 800e466: 2300 movs r3, #0 800e468: 75fb strb r3, [r7, #23] } return res; 800e46a: 7dfb ldrb r3, [r7, #23] } 800e46c: 4618 mov r0, r3 800e46e: 3718 adds r7, #24 800e470: 46bd mov sp, r7 800e472: bd80 pop {r7, pc} 0800e474 : * @param *buff: Buffer to send/receive control data * @retval DRESULT: Operation result */ #if _USE_IOCTL == 1 DRESULT SD_ioctl(BYTE lun, BYTE cmd, void *buff) { 800e474: b580 push {r7, lr} 800e476: b08c sub sp, #48 ; 0x30 800e478: af00 add r7, sp, #0 800e47a: 4603 mov r3, r0 800e47c: 603a str r2, [r7, #0] 800e47e: 71fb strb r3, [r7, #7] 800e480: 460b mov r3, r1 800e482: 71bb strb r3, [r7, #6] DRESULT res = RES_ERROR; 800e484: 2301 movs r3, #1 800e486: f887 302f strb.w r3, [r7, #47] ; 0x2f BSP_SD_CardInfo CardInfo; if (Stat & STA_NOINIT) return RES_NOTRDY; 800e48a: 4b25 ldr r3, [pc, #148] ; (800e520 ) 800e48c: 781b ldrb r3, [r3, #0] 800e48e: b2db uxtb r3, r3 800e490: f003 0301 and.w r3, r3, #1 800e494: 2b00 cmp r3, #0 800e496: d001 beq.n 800e49c 800e498: 2303 movs r3, #3 800e49a: e03c b.n 800e516 switch (cmd) 800e49c: 79bb ldrb r3, [r7, #6] 800e49e: 2b03 cmp r3, #3 800e4a0: d834 bhi.n 800e50c 800e4a2: a201 add r2, pc, #4 ; (adr r2, 800e4a8 ) 800e4a4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800e4a8: 0800e4b9 .word 0x0800e4b9 800e4ac: 0800e4c1 .word 0x0800e4c1 800e4b0: 0800e4d9 .word 0x0800e4d9 800e4b4: 0800e4f3 .word 0x0800e4f3 { /* Make sure that no pending write process */ case CTRL_SYNC : res = RES_OK; 800e4b8: 2300 movs r3, #0 800e4ba: f887 302f strb.w r3, [r7, #47] ; 0x2f break; 800e4be: e028 b.n 800e512 /* Get number of sectors on the disk (DWORD) */ case GET_SECTOR_COUNT : BSP_SD_GetCardInfo(&CardInfo); 800e4c0: f107 0308 add.w r3, r7, #8 800e4c4: 4618 mov r0, r3 800e4c6: f7ff ff13 bl 800e2f0 *(DWORD*)buff = CardInfo.LogBlockNbr; 800e4ca: 6a3a ldr r2, [r7, #32] 800e4cc: 683b ldr r3, [r7, #0] 800e4ce: 601a str r2, [r3, #0] res = RES_OK; 800e4d0: 2300 movs r3, #0 800e4d2: f887 302f strb.w r3, [r7, #47] ; 0x2f break; 800e4d6: e01c b.n 800e512 /* Get R/W sector size (WORD) */ case GET_SECTOR_SIZE : BSP_SD_GetCardInfo(&CardInfo); 800e4d8: f107 0308 add.w r3, r7, #8 800e4dc: 4618 mov r0, r3 800e4de: f7ff ff07 bl 800e2f0 *(WORD*)buff = CardInfo.LogBlockSize; 800e4e2: 6a7b ldr r3, [r7, #36] ; 0x24 800e4e4: b29a uxth r2, r3 800e4e6: 683b ldr r3, [r7, #0] 800e4e8: 801a strh r2, [r3, #0] res = RES_OK; 800e4ea: 2300 movs r3, #0 800e4ec: f887 302f strb.w r3, [r7, #47] ; 0x2f break; 800e4f0: e00f b.n 800e512 /* Get erase block size in unit of sector (DWORD) */ case GET_BLOCK_SIZE : BSP_SD_GetCardInfo(&CardInfo); 800e4f2: f107 0308 add.w r3, r7, #8 800e4f6: 4618 mov r0, r3 800e4f8: f7ff fefa bl 800e2f0 *(DWORD*)buff = CardInfo.LogBlockSize / SD_DEFAULT_BLOCK_SIZE; 800e4fc: 6a7b ldr r3, [r7, #36] ; 0x24 800e4fe: 0a5a lsrs r2, r3, #9 800e500: 683b ldr r3, [r7, #0] 800e502: 601a str r2, [r3, #0] res = RES_OK; 800e504: 2300 movs r3, #0 800e506: f887 302f strb.w r3, [r7, #47] ; 0x2f break; 800e50a: e002 b.n 800e512 default: res = RES_PARERR; 800e50c: 2304 movs r3, #4 800e50e: f887 302f strb.w r3, [r7, #47] ; 0x2f } return res; 800e512: f897 302f ldrb.w r3, [r7, #47] ; 0x2f } 800e516: 4618 mov r0, r3 800e518: 3730 adds r7, #48 ; 0x30 800e51a: 46bd mov sp, r7 800e51c: bd80 pop {r7, pc} 800e51e: bf00 nop 800e520: 2000000d .word 0x2000000d 0800e524 : * @param lun : only used for USB Key Disk to add multi-lun management else the parameter must be equal to 0 * @retval Returns 0 in case of success, otherwise 1. */ uint8_t FATFS_LinkDriverEx(const Diskio_drvTypeDef *drv, char *path, uint8_t lun) { 800e524: b480 push {r7} 800e526: b087 sub sp, #28 800e528: af00 add r7, sp, #0 800e52a: 60f8 str r0, [r7, #12] 800e52c: 60b9 str r1, [r7, #8] 800e52e: 4613 mov r3, r2 800e530: 71fb strb r3, [r7, #7] uint8_t ret = 1; 800e532: 2301 movs r3, #1 800e534: 75fb strb r3, [r7, #23] uint8_t DiskNum = 0; 800e536: 2300 movs r3, #0 800e538: 75bb strb r3, [r7, #22] if(disk.nbr < _VOLUMES) 800e53a: 4b1f ldr r3, [pc, #124] ; (800e5b8 ) 800e53c: 7a5b ldrb r3, [r3, #9] 800e53e: b2db uxtb r3, r3 800e540: 2b00 cmp r3, #0 800e542: d131 bne.n 800e5a8 { disk.is_initialized[disk.nbr] = 0; 800e544: 4b1c ldr r3, [pc, #112] ; (800e5b8 ) 800e546: 7a5b ldrb r3, [r3, #9] 800e548: b2db uxtb r3, r3 800e54a: 461a mov r2, r3 800e54c: 4b1a ldr r3, [pc, #104] ; (800e5b8 ) 800e54e: 2100 movs r1, #0 800e550: 5499 strb r1, [r3, r2] disk.drv[disk.nbr] = drv; 800e552: 4b19 ldr r3, [pc, #100] ; (800e5b8 ) 800e554: 7a5b ldrb r3, [r3, #9] 800e556: b2db uxtb r3, r3 800e558: 4a17 ldr r2, [pc, #92] ; (800e5b8 ) 800e55a: 009b lsls r3, r3, #2 800e55c: 4413 add r3, r2 800e55e: 68fa ldr r2, [r7, #12] 800e560: 605a str r2, [r3, #4] disk.lun[disk.nbr] = lun; 800e562: 4b15 ldr r3, [pc, #84] ; (800e5b8 ) 800e564: 7a5b ldrb r3, [r3, #9] 800e566: b2db uxtb r3, r3 800e568: 461a mov r2, r3 800e56a: 4b13 ldr r3, [pc, #76] ; (800e5b8 ) 800e56c: 4413 add r3, r2 800e56e: 79fa ldrb r2, [r7, #7] 800e570: 721a strb r2, [r3, #8] DiskNum = disk.nbr++; 800e572: 4b11 ldr r3, [pc, #68] ; (800e5b8 ) 800e574: 7a5b ldrb r3, [r3, #9] 800e576: b2db uxtb r3, r3 800e578: 1c5a adds r2, r3, #1 800e57a: b2d1 uxtb r1, r2 800e57c: 4a0e ldr r2, [pc, #56] ; (800e5b8 ) 800e57e: 7251 strb r1, [r2, #9] 800e580: 75bb strb r3, [r7, #22] path[0] = DiskNum + '0'; 800e582: 7dbb ldrb r3, [r7, #22] 800e584: 3330 adds r3, #48 ; 0x30 800e586: b2da uxtb r2, r3 800e588: 68bb ldr r3, [r7, #8] 800e58a: 701a strb r2, [r3, #0] path[1] = ':'; 800e58c: 68bb ldr r3, [r7, #8] 800e58e: 3301 adds r3, #1 800e590: 223a movs r2, #58 ; 0x3a 800e592: 701a strb r2, [r3, #0] path[2] = '/'; 800e594: 68bb ldr r3, [r7, #8] 800e596: 3302 adds r3, #2 800e598: 222f movs r2, #47 ; 0x2f 800e59a: 701a strb r2, [r3, #0] path[3] = 0; 800e59c: 68bb ldr r3, [r7, #8] 800e59e: 3303 adds r3, #3 800e5a0: 2200 movs r2, #0 800e5a2: 701a strb r2, [r3, #0] ret = 0; 800e5a4: 2300 movs r3, #0 800e5a6: 75fb strb r3, [r7, #23] } return ret; 800e5a8: 7dfb ldrb r3, [r7, #23] } 800e5aa: 4618 mov r0, r3 800e5ac: 371c adds r7, #28 800e5ae: 46bd mov sp, r7 800e5b0: f85d 7b04 ldr.w r7, [sp], #4 800e5b4: 4770 bx lr 800e5b6: bf00 nop 800e5b8: 20000030 .word 0x20000030 0800e5bc : * @param drv: pointer to the disk IO Driver structure * @param path: pointer to the logical drive path * @retval Returns 0 in case of success, otherwise 1. */ uint8_t FATFS_LinkDriver(const Diskio_drvTypeDef *drv, char *path) { 800e5bc: b580 push {r7, lr} 800e5be: b082 sub sp, #8 800e5c0: af00 add r7, sp, #0 800e5c2: 6078 str r0, [r7, #4] 800e5c4: 6039 str r1, [r7, #0] return FATFS_LinkDriverEx(drv, path, 0); 800e5c6: 2200 movs r2, #0 800e5c8: 6839 ldr r1, [r7, #0] 800e5ca: 6878 ldr r0, [r7, #4] 800e5cc: f7ff ffaa bl 800e524 800e5d0: 4603 mov r3, r0 } 800e5d2: 4618 mov r0, r3 800e5d4: 3708 adds r7, #8 800e5d6: 46bd mov sp, r7 800e5d8: bd80 pop {r7, pc} ... 0800e5dc <__libc_init_array>: 800e5dc: b570 push {r4, r5, r6, lr} 800e5de: 4d0d ldr r5, [pc, #52] ; (800e614 <__libc_init_array+0x38>) 800e5e0: 4c0d ldr r4, [pc, #52] ; (800e618 <__libc_init_array+0x3c>) 800e5e2: 1b64 subs r4, r4, r5 800e5e4: 10a4 asrs r4, r4, #2 800e5e6: 2600 movs r6, #0 800e5e8: 42a6 cmp r6, r4 800e5ea: d109 bne.n 800e600 <__libc_init_array+0x24> 800e5ec: 4d0b ldr r5, [pc, #44] ; (800e61c <__libc_init_array+0x40>) 800e5ee: 4c0c ldr r4, [pc, #48] ; (800e620 <__libc_init_array+0x44>) 800e5f0: f000 f820 bl 800e634 <_init> 800e5f4: 1b64 subs r4, r4, r5 800e5f6: 10a4 asrs r4, r4, #2 800e5f8: 2600 movs r6, #0 800e5fa: 42a6 cmp r6, r4 800e5fc: d105 bne.n 800e60a <__libc_init_array+0x2e> 800e5fe: bd70 pop {r4, r5, r6, pc} 800e600: f855 3b04 ldr.w r3, [r5], #4 800e604: 4798 blx r3 800e606: 3601 adds r6, #1 800e608: e7ee b.n 800e5e8 <__libc_init_array+0xc> 800e60a: f855 3b04 ldr.w r3, [r5], #4 800e60e: 4798 blx r3 800e610: 3601 adds r6, #1 800e612: e7f2 b.n 800e5fa <__libc_init_array+0x1e> 800e614: 0800e6b8 .word 0x0800e6b8 800e618: 0800e6b8 .word 0x0800e6b8 800e61c: 0800e6b8 .word 0x0800e6b8 800e620: 0800e6bc .word 0x0800e6bc 0800e624 : 800e624: 4402 add r2, r0 800e626: 4603 mov r3, r0 800e628: 4293 cmp r3, r2 800e62a: d100 bne.n 800e62e 800e62c: 4770 bx lr 800e62e: f803 1b01 strb.w r1, [r3], #1 800e632: e7f9 b.n 800e628 0800e634 <_init>: 800e634: b5f8 push {r3, r4, r5, r6, r7, lr} 800e636: bf00 nop 800e638: bcf8 pop {r3, r4, r5, r6, r7} 800e63a: bc08 pop {r3} 800e63c: 469e mov lr, r3 800e63e: 4770 bx lr 0800e640 <_fini>: 800e640: b5f8 push {r3, r4, r5, r6, r7, lr} 800e642: bf00 nop 800e644: bcf8 pop {r3, r4, r5, r6, r7} 800e646: bc08 pop {r3} 800e648: 469e mov lr, r3 800e64a: 4770 bx lr