#ifndef __USART_6_REGISTERS_H__
#define __USART_6_REGISTERS_H__

#include "base_addresses.h"
#include "hw_register.h"

namespace USART_6_REGS {
	enum  { SR		= USART6_BASE + 0x00 };
	enum  { DR		= USART6_BASE + 0x04 };
	enum  { BRR		= USART6_BASE + 0x08 };
	enum  { CR1		= USART6_BASE + 0x0C };
	enum  { CR2		= USART6_BASE + 0x10 };
	enum  { CR3		= USART6_BASE + 0x14 };
	enum  { GTPR	= USART6_BASE + 0x18 };

	// Status Register Definitions
	typedef hw_register<SR, 0x1,   9, rw_t> 	CTS;		// CTS Toggled
	typedef hw_register<SR, 0x1,   8, rw_t> 	LBD;		// LIN Break Detected
	typedef hw_register<SR, 0x1,   7, ro_t> 	TXE;		// Transmit Data Register Empty
	typedef hw_register<SR, 0x1,   6, rw_t> 	TC;			// Transmission Complete
	typedef hw_register<SR, 0x1,   5, rw_t> 	RXNE;		// Receive Data Register Not Empty
	typedef hw_register<SR, 0x1,   4, ro_t> 	IDLE;		// IDLE line detected
	typedef hw_register<SR, 0x1,   3, ro_t> 	ORE;		// Overrun Error
	typedef hw_register<SR, 0x1,   2, ro_t> 	NF;			// Noise Detected
	typedef hw_register<SR, 0x1,   1, ro_t> 	FE;			// Framing Error
	typedef hw_register<SR, 0x1,   0, ro_t>		PE;			// Parity Error

	// Data Register Definitions
	typedef hw_register<DR, 0xFF,  0, rw_t> 	Data;

	// Baud Rate Register Register
	typedef hw_register<BRR, 0xFFF,   4, rw_t> 	Integer;	//
	typedef hw_register<BRR, 0xF,     0, rw_t> 	Fraction;	//
	typedef hw_register<BRR, 0xFFFF,  0, rw_t> 	Divider;	//

	// Control Register 1 Definitions
	typedef hw_register<CR1, 0x1, 15, rw_t>		OVER8;		// Oversampling (0=16X, 1=8X)
	typedef hw_register<CR1, 0x1, 13, rw_t>		UE;			// USART Enabled, when UE=1
	typedef hw_register<CR1, 0x1, 12, rw_t> 	M;			// Word Length (0=8 Data Bits, 1=9 Data Bits)
	typedef hw_register<CR1, 0x1, 11, rw_t> 	WAKE;		// Wakeup (0=Line IDLE, 1=Address Mark)
	typedef hw_register<CR1, 0x1, 10, rw_t> 	PCE;		// Parity Control Enable
	typedef hw_register<CR1, 0x1,  9, rw_t> 	PS;			// Parity Selection
	typedef hw_register<CR1, 0x1,  8, rw_t> 	PEIE;		// PE Interrupt Enable
	typedef hw_register<CR1, 0x1,  7, rw_t> 	TXEIE;		// TXE Interrupt Enable
	typedef hw_register<CR1, 0x1,  6, rw_t>		TCIE;		// TC Interrupt Enable
	typedef hw_register<CR1, 0x1,  5, rw_t> 	RXNIE;		// RXNE interrupt Enable
	typedef hw_register<CR1, 0x1,  4, rw_t> 	IDLEIE;		// IDLE Interrupt Enable
	typedef hw_register<CR1, 0x1,  3, rw_t> 	TE;			// Transmitter Enable
	typedef hw_register<CR1, 0x1,  2, rw_t> 	RE;			// Receiver Enable
	typedef hw_register<CR1, 0x1,  1, rw_t> 	RWU;		// Receiver Wakeup
	typedef hw_register<CR1, 0x1,  0, rw_t> 	SBK;		// Send Break

	// Control Register 2 Definitions
	typedef hw_register<CR2, 0x1, 14, rw_t>		LINEN;		// LIN Mode Enable
	typedef hw_register<CR2, 0x3, 12, rw_t> 	STOP;		// Stop Bits (00=1, 01=0.5, 10=2, 11=1.5)
	typedef hw_register<CR2, 0x1, 11, rw_t> 	CLKEN;		// Produce a clock on the SCLK pin(when 1)
	typedef hw_register<CR2, 0x1, 10, rw_t> 	CPOL;		// Clock Polarity
	typedef hw_register<CR2, 0x1,  9, rw_t> 	CPHA;		// Clock Phase
	typedef hw_register<CR2, 0x1,  8, rw_t> 	LBCL;		// Last Bit Clock Pulse
	typedef hw_register<CR2, 0x1,  6, rw_t>		LBDIE;		// LIN Break Detection Interrupt Enable
	typedef hw_register<CR2, 0x1,  5, rw_t> 	LBDL;		// LIN Break Detection Length
	typedef hw_register<CR2, 0xF,  0, rw_t> 	ADD;		// USART Address

	// Control Register 3 Definitions
	typedef hw_register<CR3, 0x1, 11, rw_t> 	ONEBIT;		// Wakeup (0=Line IDLE, 1=Address Mark)
	typedef hw_register<CR3, 0x1, 10, rw_t> 	CTSIE;		// CTS Toggled Interrupt Enable
	typedef hw_register<CR3, 0x1,  9, rw_t> 	CTSE;		// Enable CTS Output
	typedef hw_register<CR3, 0x1,  8, rw_t> 	RTSE;		// RTS Enable
	typedef hw_register<CR3, 0x1,  7, rw_t> 	DMAT;		// Transmitter DMA enable
	typedef hw_register<CR3, 0x1,  6, rw_t>		DMAR;		// Receiver DMA Enable
	typedef hw_register<CR3, 0x1,  5, rw_t> 	SCEN;		// Smartcard Mode Enable
	typedef hw_register<CR3, 0x1,  4, rw_t> 	NACK;		// Smartcard NACK Enable
	typedef hw_register<CR3, 0x1,  3, rw_t> 	HDSEL;		// Transmitter Enable
	typedef hw_register<CR3, 0x1,  2, rw_t> 	IRLP;		// IRDA Low Power
	typedef hw_register<CR3, 0x1,  1, rw_t> 	IREN;		// IRDA Mode Enable
	typedef hw_register<CR3, 0x1,  0, rw_t> 	EIE;		// Error Interrupt Enable

	// Guard Time and Prescaler Register
	typedef hw_register<GTPR, 0xFF, 8, rw_t> 	GT;			// Guard Time Value
	typedef hw_register<GTPR, 0xFF, 0, rw_t> 	PSC;		// Prescaler Value
};

#endif // __USART_6_REGISTERS_H__