#ifndef __CORTEX_M3_H__
#define __CORTEX_M3_H__

#include "types.h"

#define CPU_ICSR            ( ( volatile uint32_t*) 0xE000ED04 )   // Interrupt Control State Register
#define CPU_SYSTICKCSR      ( ( volatile uint32_t*) 0xE000E010 )   // SysTick Control and Status Register
#define CPU_SYSTICKCSR_EINT 0x02                            // Bit for enable/disable SysTick interrupt


// Define SysTick clock frequency and its interrupt rate in Hz.
#define SYSTICKFREQ     72000000
#define SYSTICKINTRATE  1000


class CriticalSection
{
	public:

		CriticalSection() : _statusReg(__get_interrupt_state()) {
			__asm__ __volatile__ ("cpsid i");
		}

		~CriticalSection() {
			__set_interrupt_state(_statusReg);
		}

	private:
		void __set_interrupt_state(uint32_t status) {
			__asm__ __volatile__ (
				"MSR PRIMASK, %0\n"
				: : "r"(status)
				:"memory"
			);
		}

		 uint32_t __get_interrupt_state() {
			uint32_t sr;
			__asm__ __volatile__ ("MRS %0, PRIMASK" : "=r"(sr) );
			return sr;
		}

	private:
		uint32_t	_statusReg;
};

#endif // __CORTEX_M3_H__