// Xilinx Verilog produced by program ngc2hdl G.26
// Command: -ofmt verilog -intstyle silent -w U21.ngc U21.v 
// Input file: U21.ngc
// Output file: U21.v
// Design name: U21
// Xilinx: C:/Xilinx

// The output of ngc2hdl is a simulation model. This file cannot be synthesized,
// or used in any other manner other than simulation. This netlist uses simulation
// primitives which may not represent the true implementation of the device, however
// the netlist is functionally correct. Do not modify this file.

`timescale 1 ns/10 ps

module LPM_XOR2_1 (
  Data_0_, Data_1_, Result
);
  input Data_0_;
  input Data_1_;
  output Result;
  XOR2 Xo_0_1 (
    .I0(Data_0_),
    .I1(Data_1_),
    .O(Result)
  );
endmodule

module NegDetect (
  Line, Mclk, Ndetect
);
  input Line;
  input Mclk;
  output Ndetect;
  wire Line_last;
  wire _n0001;
  wire Ndetectr__n0002;
  wire _n00011;
  FD Ndetectr (
    .D(_n0001),
    .C(Ndetectr__n0002),
    .Q(Ndetect)
  );
  INV _n00011_2 (
    .I(Line),
    .O(_n00011)
  );
  INV Ndetectr__n00021 (
    .I(Mclk),
    .O(Ndetectr__n0002)
  );
  AND2 _n00012 (
    .I0(Line_last),
    .I1(_n00011),
    .O(_n0001)
  );
  FD Line_last_3 (
    .D(Line),
    .C(Ndetectr__n0002),
    .Q(Line_last)
  );
endmodule

module Counter (
  sense, ce, Reset, updown, Zero, Sclk, count
);
  input sense;
  input ce;
  input Reset;
  input updown;
  input Zero;
  input Sclk;
  output [15 : 0] count;
  wire N17478;
  wire _n0000;
  wire _n0002;
  wire location_Madd__n0000__n0056;
  wire location_0_2__n0000;
  wire location_0_4__n0000;
  wire location_0_12__n0000;
  wire location_0_6__n0000;
  wire location_0_13__n0000;
  wire location_0_15__n0001;
  wire location_Madd__n0000__n0055;
  wire location_Madd__n0000__n0054;
  wire location_0_3__n0000;
  wire location_0_5__n0000;
  wire location_0_9__n0000;
  wire location_0_11__n0000;
  wire location_0_0__n0000;
  wire location_0_8__n0000;
  wire location_0_14__n0000;
  wire N13185;
  wire location_0_7__n0000;
  wire location_0_1__n0000;
  wire location_0_15__n0000;
  wire location_0_10__n0000;
  wire _n00001;
  wire _n00002;
  wire location_0_15__n00011;
  wire location_0_15__n00012;
  wire location_Madd__n0000__n00561;
  wire location_Madd__n0000__n00541;
  wire location_Madd__n0000__n0004;
  wire location_Madd__n0000__n00041;
  wire location_Madd__n0000__n00042;
  wire location_Madd__n0000__n00043;
  wire location_Madd__n0000__n00044;
  wire location_Madd__n0000__n00045;
  wire location_Madd__n0000__n00046;
  wire location_Madd__n0000__n0013;
  wire location_Madd__n0000__n00131;
  wire location_Madd__n0000__n00132;
  wire location_Madd__n0000__n00133;
  wire location_Madd__n0000__n00134;
  wire location_Madd__n0000__n00135;
  wire location_Madd__n0000__n00136;
  wire location_Madd__n0000__n0003;
  wire location_Madd__n0000__n00031;
  wire location_Madd__n0000__n00032;
  wire location_Madd__n0000__n00033;
  wire location_Madd__n0000__n00034;
  wire location_Madd__n0000__n00035;
  wire location_Madd__n0000__n00036;
  wire location_Madd__n0000__n0012;
  wire location_Madd__n0000__n00121;
  wire location_Madd__n0000__n00122;
  wire location_Madd__n0000__n00123;
  wire location_Madd__n0000__n00124;
  wire location_Madd__n0000__n00125;
  wire location_Madd__n0000__n00126;
  wire location_Madd__n0000__n0002;
  wire location_Madd__n0000__n00021;
  wire location_Madd__n0000__n00022;
  wire location_Madd__n0000__n00023;
  wire location_Madd__n0000__n00024;
  wire location_Madd__n0000__n00025;
  wire location_Madd__n0000__n00026;
  wire location_Madd__n0000__n0011;
  wire location_Madd__n0000__n00111;
  wire location_Madd__n0000__n00112;
  wire location_Madd__n0000__n00113;
  wire location_Madd__n0000__n00114;
  wire location_Madd__n0000__n00115;
  wire location_Madd__n0000__n00116;
  wire location_Madd__n0000__n0001;
  wire location_Madd__n0000__n00011;
  wire location_Madd__n0000__n00012;
  wire location_Madd__n0000__n00013;
  wire location_Madd__n0000__n00014;
  wire location_Madd__n0000__n00015;
  wire location_Madd__n0000__n00016;
  wire location_Madd__n0000__n0010;
  wire location_Madd__n0000__n00101;
  wire location_Madd__n0000__n00102;
  wire location_Madd__n0000__n00103;
  wire location_Madd__n0000__n00104;
  wire location_Madd__n0000__n00105;
  wire location_Madd__n0000__n00106;
  wire location_Madd__n0000__n0009;
  wire location_Madd__n0000__n00091;
  wire location_Madd__n0000__n00092;
  wire location_Madd__n0000__n00093;
  wire location_Madd__n0000__n00094;
  wire location_Madd__n0000__n00095;
  wire location_Madd__n0000__n00096;
  wire location_Madd__n0000__n0014;
  wire location_Madd__n0000__n00141;
  wire location_Madd__n0000__n00142;
  wire location_Madd__n0000__n00143;
  wire location_Madd__n0000__n0008;
  wire location_Madd__n0000__n00081;
  wire location_Madd__n0000__n00082;
  wire location_Madd__n0000__n00083;
  wire location_Madd__n0000__n00084;
  wire location_Madd__n0000__n00085;
  wire location_Madd__n0000__n00086;
  wire location_Madd__n0000__n0007;
  wire location_Madd__n0000__n00071;
  wire location_Madd__n0000__n00072;
  wire location_Madd__n0000__n00073;
  wire location_Madd__n0000__n00074;
  wire location_Madd__n0000__n00075;
  wire location_Madd__n0000__n00076;
  wire location_Madd__n0000__n0006;
  wire location_Madd__n0000__n00061;
  wire location_Madd__n0000__n00062;
  wire location_Madd__n0000__n00063;
  wire location_Madd__n0000__n00064;
  wire location_Madd__n0000__n00065;
  wire location_Madd__n0000__n00066;
  wire location_Madd__n0000__n0005;
  wire location_Madd__n0000__n00051;
  wire location_Madd__n0000__n00052;
  wire location_Madd__n0000__n00053;
  wire location_Madd__n0000__n00054;
  wire location_Madd__n0000__n00055;
  wire location_Madd__n0000__n00056;
  wire [1 : 1] _n0001;
  wire [0 : 0] location_Madd__n0000__n0085;
  wire [0 : 0] location_Madd__n0000_Mxor_Result_10___n0002;
  wire [15 : 0] NlwRenamedSig_OI_count;
  wire [0 : 0] location_Madd__n0000_Mxor_Result_15___n0002;
  wire [15 : 0] location__n0000;
  wire [0 : 0] location_Madd__n0000_Mxor_Result_1___n0002;
  wire [0 : 0] location_Madd__n0000__n0071;
  wire [0 : 0] location_Madd__n0000__n0079;
  wire [0 : 0] location_Madd__n0000_Mxor_Result_2___n0002;
  wire [0 : 0] location_Madd__n0000__n0081;
  wire [0 : 0] location_Madd__n0000__n0077;
  wire [0 : 0] location_Madd__n0000_Mxor_Result_14___n0002;
  wire [0 : 0] location_Madd__n0000_Mxor_Result_9___n0002;
  wire [0 : 0] location_Madd__n0000_Mxor_Result_4___n0002;
  wire [0 : 0] location_Madd__n0000__n0087;
  wire [0 : 0] location_Madd__n0000__n0065;
  wire [0 : 0] location_Madd__n0000_Mxor_Result_3___n0002;
  wire [0 : 0] location_Madd__n0000__n0083;
  wire [0 : 0] location_Madd__n0000__n0073;
  wire [0 : 0] location_Madd__n0000_Mxor_Result_7___n0002;
  wire [0 : 0] location_Madd__n0000_Mxor_Result_13___n0002;
  wire [0 : 0] location_Madd__n0000_Mxor_Result_8___n0002;
  wire [0 : 0] location_Madd__n0000__n0075;
  wire [0 : 0] location_Madd__n0000__n0061;
  wire [0 : 0] location_Madd__n0000_Mxor_Result_11___n0002;
  wire [0 : 0] location_Madd__n0000__n0063;
  wire [0 : 0] location_Madd__n0000_Mxor_Result_6___n0002;
  wire [0 : 0] location_Madd__n0000_Mxor_Result_12___n0002;
  wire [0 : 0] location_Madd__n0000__n0069;
  wire [0 : 0] location_Madd__n0000__n0067;
  wire [0 : 0] location_Madd__n0000_Mxor_Result_5___n0002;
  assign
    count[15] = NlwRenamedSig_OI_count[15],
    count[14] = NlwRenamedSig_OI_count[14],
    count[13] = NlwRenamedSig_OI_count[13],
    count[12] = NlwRenamedSig_OI_count[12],
    count[11] = NlwRenamedSig_OI_count[11],
    count[10] = NlwRenamedSig_OI_count[10],
    count[9] = NlwRenamedSig_OI_count[9],
    count[8] = NlwRenamedSig_OI_count[8],
    count[7] = NlwRenamedSig_OI_count[7],
    count[6] = NlwRenamedSig_OI_count[6],
    count[5] = NlwRenamedSig_OI_count[5],
    count[4] = NlwRenamedSig_OI_count[4],
    count[3] = NlwRenamedSig_OI_count[3],
    count[2] = NlwRenamedSig_OI_count[2],
    count[1] = NlwRenamedSig_OI_count[1],
    count[0] = NlwRenamedSig_OI_count[0];
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_2__Mxor_Result (
    .Data_0_(location_Madd__n0000_Mxor_Result_2___n0002[0]),
    .Data_1_(location_Madd__n0000__n0061[0]),
    .Result(location__n0000[2])
  );
  XOR2 _n00021 (
    .I0(sense),
    .I1(updown),
    .O(_n0002)
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_3__Mxor__n0000 (
    .Data_0_(NlwRenamedSig_OI_count[3]),
    .Data_1_(_n0001[1]),
    .Result(location_Madd__n0000_Mxor_Result_3___n0002[0])
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_4__Mxor__n0000 (
    .Data_0_(NlwRenamedSig_OI_count[4]),
    .Data_1_(_n0001[1]),
    .Result(location_Madd__n0000_Mxor_Result_4___n0002[0])
  );
  VCC XST_VCC (
    .P(N17478)
  );
  INV _n0001_1_1 (
    .I(_n0002),
    .O(_n0001[1])
  );
  AND2 _n00003 (
    .I0(_n00001),
    .I1(_n00002),
    .O(_n0000)
  );
  AND2 location_0__n00001 (
    .I0(_n0000),
    .I1(location__n0000[0]),
    .O(location_0_0__n0000)
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_1__Mxor_Result (
    .Data_0_(location_Madd__n0000_Mxor_Result_1___n0002[0]),
    .Data_1_(NlwRenamedSig_OI_count[0]),
    .Result(location__n0000[1])
  );
  FDCE location_15 (
    .D(location_0_15__n0000),
    .CE(location_0_15__n0001),
    .CLR(N13185),
    .C(Sclk),
    .Q(NlwRenamedSig_OI_count[15])
  );
  FDCE location_14 (
    .D(location_0_14__n0000),
    .CE(location_0_15__n0001),
    .CLR(N13185),
    .C(Sclk),
    .Q(NlwRenamedSig_OI_count[14])
  );
  FDCE location_0 (
    .D(location_0_0__n0000),
    .CE(location_0_15__n0001),
    .CLR(N13185),
    .C(Sclk),
    .Q(NlwRenamedSig_OI_count[0])
  );
  FDCE location_1 (
    .D(location_0_1__n0000),
    .CE(location_0_15__n0001),
    .CLR(N13185),
    .C(Sclk),
    .Q(NlwRenamedSig_OI_count[1])
  );
  FDCE location_2 (
    .D(location_0_2__n0000),
    .CE(location_0_15__n0001),
    .CLR(N13185),
    .C(Sclk),
    .Q(NlwRenamedSig_OI_count[2])
  );
  FDCE location_3 (
    .D(location_0_3__n0000),
    .CE(location_0_15__n0001),
    .CLR(N13185),
    .C(Sclk),
    .Q(NlwRenamedSig_OI_count[3])
  );
  FDCE location_4 (
    .D(location_0_4__n0000),
    .CE(location_0_15__n0001),
    .CLR(N13185),
    .C(Sclk),
    .Q(NlwRenamedSig_OI_count[4])
  );
  FDCE location_5 (
    .D(location_0_5__n0000),
    .CE(location_0_15__n0001),
    .CLR(N13185),
    .C(Sclk),
    .Q(NlwRenamedSig_OI_count[5])
  );
  FDCE location_6 (
    .D(location_0_6__n0000),
    .CE(location_0_15__n0001),
    .CLR(N13185),
    .C(Sclk),
    .Q(NlwRenamedSig_OI_count[6])
  );
  FDCE location_7 (
    .D(location_0_7__n0000),
    .CE(location_0_15__n0001),
    .CLR(N13185),
    .C(Sclk),
    .Q(NlwRenamedSig_OI_count[7])
  );
  FDCE location_8 (
    .D(location_0_8__n0000),
    .CE(location_0_15__n0001),
    .CLR(N13185),
    .C(Sclk),
    .Q(NlwRenamedSig_OI_count[8])
  );
  FDCE location_9 (
    .D(location_0_9__n0000),
    .CE(location_0_15__n0001),
    .CLR(N13185),
    .C(Sclk),
    .Q(NlwRenamedSig_OI_count[9])
  );
  FDCE location_10 (
    .D(location_0_10__n0000),
    .CE(location_0_15__n0001),
    .CLR(N13185),
    .C(Sclk),
    .Q(NlwRenamedSig_OI_count[10])
  );
  FDCE location_11 (
    .D(location_0_11__n0000),
    .CE(location_0_15__n0001),
    .CLR(N13185),
    .C(Sclk),
    .Q(NlwRenamedSig_OI_count[11])
  );
  FDCE location_12 (
    .D(location_0_12__n0000),
    .CE(location_0_15__n0001),
    .CLR(N13185),
    .C(Sclk),
    .Q(NlwRenamedSig_OI_count[12])
  );
  FDCE location_13 (
    .D(location_0_13__n0000),
    .CE(location_0_15__n0001),
    .CLR(N13185),
    .C(Sclk),
    .Q(NlwRenamedSig_OI_count[13])
  );
  INV location_0_15__n00013 (
    .I(location_0_15__n00012),
    .O(location_0_15__n0001)
  );
  AND2 location_15__n00001 (
    .I0(_n0000),
    .I1(location__n0000[15]),
    .O(location_0_15__n0000)
  );
  GND XST_GND (
    .G(N13185)
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_0_ (
    .Data_0_(N17478),
    .Data_1_(NlwRenamedSig_OI_count[0]),
    .Result(location__n0000[0])
  );
  AND2 location_14__n00001 (
    .I0(_n0000),
    .I1(location__n0000[14]),
    .O(location_0_14__n0000)
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_15__Mxor_Result (
    .Data_0_(location_Madd__n0000_Mxor_Result_15___n0002[0]),
    .Data_1_(location_Madd__n0000__n0087[0]),
    .Result(location__n0000[15])
  );
  AND2 location_13__n00001 (
    .I0(_n0000),
    .I1(location__n0000[13]),
    .O(location_0_13__n0000)
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_14__Mxor_Result (
    .Data_0_(location_Madd__n0000_Mxor_Result_14___n0002[0]),
    .Data_1_(location_Madd__n0000__n0085[0]),
    .Result(location__n0000[14])
  );
  AND2 location_12__n00001 (
    .I0(_n0000),
    .I1(location__n0000[12]),
    .O(location_0_12__n0000)
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_13__Mxor_Result (
    .Data_0_(location_Madd__n0000_Mxor_Result_13___n0002[0]),
    .Data_1_(location_Madd__n0000__n0083[0]),
    .Result(location__n0000[13])
  );
  AND2 location_11__n00001 (
    .I0(_n0000),
    .I1(location__n0000[11]),
    .O(location_0_11__n0000)
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_12__Mxor_Result (
    .Data_0_(location_Madd__n0000_Mxor_Result_12___n0002[0]),
    .Data_1_(location_Madd__n0000__n0081[0]),
    .Result(location__n0000[12])
  );
  AND2 location_10__n00001 (
    .I0(_n0000),
    .I1(location__n0000[10]),
    .O(location_0_10__n0000)
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_11__Mxor_Result (
    .Data_0_(location_Madd__n0000_Mxor_Result_11___n0002[0]),
    .Data_1_(location_Madd__n0000__n0079[0]),
    .Result(location__n0000[11])
  );
  AND2 location_9__n00001 (
    .I0(_n0000),
    .I1(location__n0000[9]),
    .O(location_0_9__n0000)
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_10__Mxor_Result (
    .Data_0_(location_Madd__n0000_Mxor_Result_10___n0002[0]),
    .Data_1_(location_Madd__n0000__n0077[0]),
    .Result(location__n0000[10])
  );
  AND2 location_8__n00001 (
    .I0(_n0000),
    .I1(location__n0000[8]),
    .O(location_0_8__n0000)
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_9__Mxor_Result (
    .Data_0_(location_Madd__n0000_Mxor_Result_9___n0002[0]),
    .Data_1_(location_Madd__n0000__n0075[0]),
    .Result(location__n0000[9])
  );
  AND2 location_7__n00001 (
    .I0(_n0000),
    .I1(location__n0000[7]),
    .O(location_0_7__n0000)
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_8__Mxor_Result (
    .Data_0_(location_Madd__n0000_Mxor_Result_8___n0002[0]),
    .Data_1_(location_Madd__n0000__n0073[0]),
    .Result(location__n0000[8])
  );
  AND2 location_6__n00001 (
    .I0(_n0000),
    .I1(location__n0000[6]),
    .O(location_0_6__n0000)
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_7__Mxor_Result (
    .Data_0_(location_Madd__n0000_Mxor_Result_7___n0002[0]),
    .Data_1_(location_Madd__n0000__n0071[0]),
    .Result(location__n0000[7])
  );
  AND2 location_5__n00001 (
    .I0(_n0000),
    .I1(location__n0000[5]),
    .O(location_0_5__n0000)
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_6__Mxor_Result (
    .Data_0_(location_Madd__n0000_Mxor_Result_6___n0002[0]),
    .Data_1_(location_Madd__n0000__n0069[0]),
    .Result(location__n0000[6])
  );
  AND2 location_4__n00001 (
    .I0(_n0000),
    .I1(location__n0000[4]),
    .O(location_0_4__n0000)
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_5__Mxor_Result (
    .Data_0_(location_Madd__n0000_Mxor_Result_5___n0002[0]),
    .Data_1_(location_Madd__n0000__n0067[0]),
    .Result(location__n0000[5])
  );
  AND2 location_3__n00001 (
    .I0(_n0000),
    .I1(location__n0000[3]),
    .O(location_0_3__n0000)
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_4__Mxor_Result (
    .Data_0_(location_Madd__n0000_Mxor_Result_4___n0002[0]),
    .Data_1_(location_Madd__n0000__n0065[0]),
    .Result(location__n0000[4])
  );
  AND2 location_2__n00001 (
    .I0(_n0000),
    .I1(location__n0000[2]),
    .O(location_0_2__n0000)
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_3__Mxor_Result (
    .Data_0_(location_Madd__n0000_Mxor_Result_3___n0002[0]),
    .Data_1_(location_Madd__n0000__n0063[0]),
    .Result(location__n0000[3])
  );
  AND2 location_1__n00001 (
    .I0(_n0000),
    .I1(location__n0000[1]),
    .O(location_0_1__n0000)
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_1__Mxor__n0000 (
    .Data_0_(NlwRenamedSig_OI_count[1]),
    .Data_1_(_n0001[1]),
    .Result(location_Madd__n0000_Mxor_Result_1___n0002[0])
  );
  AND2 location_Madd__n0000__n00562 (
    .I0(location_Madd__n0000__n0085[0]),
    .I1(location_Madd__n0000__n00561),
    .O(location_Madd__n0000__n0056)
  );
  AND2 location_Madd__n0000__n00551 (
    .I0(NlwRenamedSig_OI_count[14]),
    .I1(location_Madd__n0000__n0085[0]),
    .O(location_Madd__n0000__n0055)
  );
  AND2 location_Madd__n0000__n00542 (
    .I0(NlwRenamedSig_OI_count[14]),
    .I1(location_Madd__n0000__n00541),
    .O(location_Madd__n0000__n0054)
  );
  OR2 location_Madd__n0000__n00048 (
    .I0(location_Madd__n0000__n0004),
    .I1(location_Madd__n0000__n00046),
    .O(location_Madd__n0000__n0067[0])
  );
  OR2 location_Madd__n0000__n00138 (
    .I0(location_Madd__n0000__n0013),
    .I1(location_Madd__n0000__n00136),
    .O(location_Madd__n0000__n0085[0])
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_14__Mxor__n0000 (
    .Data_0_(NlwRenamedSig_OI_count[14]),
    .Data_1_(_n0001[1]),
    .Result(location_Madd__n0000_Mxor_Result_14___n0002[0])
  );
  OR2 location_Madd__n0000__n00038 (
    .I0(location_Madd__n0000__n0003),
    .I1(location_Madd__n0000__n00036),
    .O(location_Madd__n0000__n0065[0])
  );
  OR2 location_Madd__n0000__n00128 (
    .I0(location_Madd__n0000__n0012),
    .I1(location_Madd__n0000__n00126),
    .O(location_Madd__n0000__n0083[0])
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_11__Mxor__n0000 (
    .Data_0_(NlwRenamedSig_OI_count[11]),
    .Data_1_(_n0001[1]),
    .Result(location_Madd__n0000_Mxor_Result_11___n0002[0])
  );
  OR2 location_Madd__n0000__n00028 (
    .I0(location_Madd__n0000__n0002),
    .I1(location_Madd__n0000__n00026),
    .O(location_Madd__n0000__n0063[0])
  );
  OR2 location_Madd__n0000__n00118 (
    .I0(location_Madd__n0000__n0011),
    .I1(location_Madd__n0000__n00116),
    .O(location_Madd__n0000__n0081[0])
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_8__Mxor__n0000 (
    .Data_0_(NlwRenamedSig_OI_count[8]),
    .Data_1_(_n0001[1]),
    .Result(location_Madd__n0000_Mxor_Result_8___n0002[0])
  );
  OR2 location_Madd__n0000__n00018 (
    .I0(location_Madd__n0000__n0001),
    .I1(location_Madd__n0000__n00016),
    .O(location_Madd__n0000__n0061[0])
  );
  OR2 location_Madd__n0000__n00108 (
    .I0(location_Madd__n0000__n0010),
    .I1(location_Madd__n0000__n00106),
    .O(location_Madd__n0000__n0079[0])
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_5__Mxor__n0000 (
    .Data_0_(NlwRenamedSig_OI_count[5]),
    .Data_1_(_n0001[1]),
    .Result(location_Madd__n0000_Mxor_Result_5___n0002[0])
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_10__Mxor__n0000 (
    .Data_0_(NlwRenamedSig_OI_count[10]),
    .Data_1_(_n0001[1]),
    .Result(location_Madd__n0000_Mxor_Result_10___n0002[0])
  );
  OR2 location_Madd__n0000__n00098 (
    .I0(location_Madd__n0000__n0009),
    .I1(location_Madd__n0000__n00096),
    .O(location_Madd__n0000__n0077[0])
  );
  INV location_Madd__n0000__n00145 (
    .I(location_Madd__n0000__n00143),
    .O(location_Madd__n0000__n0087[0])
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_9__Mxor__n0000 (
    .Data_0_(NlwRenamedSig_OI_count[9]),
    .Data_1_(_n0001[1]),
    .Result(location_Madd__n0000_Mxor_Result_9___n0002[0])
  );
  OR2 location_Madd__n0000__n00088 (
    .I0(location_Madd__n0000__n0008),
    .I1(location_Madd__n0000__n00086),
    .O(location_Madd__n0000__n0075[0])
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_12__Mxor__n0000 (
    .Data_0_(NlwRenamedSig_OI_count[12]),
    .Data_1_(_n0001[1]),
    .Result(location_Madd__n0000_Mxor_Result_12___n0002[0])
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_6__Mxor__n0000 (
    .Data_0_(NlwRenamedSig_OI_count[6]),
    .Data_1_(_n0001[1]),
    .Result(location_Madd__n0000_Mxor_Result_6___n0002[0])
  );
  OR2 location_Madd__n0000__n00078 (
    .I0(location_Madd__n0000__n0007),
    .I1(location_Madd__n0000__n00076),
    .O(location_Madd__n0000__n0073[0])
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_15__Mxor__n0000 (
    .Data_0_(NlwRenamedSig_OI_count[15]),
    .Data_1_(_n0001[1]),
    .Result(location_Madd__n0000_Mxor_Result_15___n0002[0])
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_2__Mxor__n0000 (
    .Data_0_(NlwRenamedSig_OI_count[2]),
    .Data_1_(_n0001[1]),
    .Result(location_Madd__n0000_Mxor_Result_2___n0002[0])
  );
  OR2 location_Madd__n0000__n00068 (
    .I0(location_Madd__n0000__n0006),
    .I1(location_Madd__n0000__n00066),
    .O(location_Madd__n0000__n0071[0])
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_13__Mxor__n0000 (
    .Data_0_(NlwRenamedSig_OI_count[13]),
    .Data_1_(_n0001[1]),
    .Result(location_Madd__n0000_Mxor_Result_13___n0002[0])
  );
  LPM_XOR2_1 location_Madd__n0000_Mxor_Result_7__Mxor__n0000 (
    .Data_0_(NlwRenamedSig_OI_count[7]),
    .Data_1_(_n0001[1]),
    .Result(location_Madd__n0000_Mxor_Result_7___n0002[0])
  );
  OR2 location_Madd__n0000__n00058 (
    .I0(location_Madd__n0000__n0005),
    .I1(location_Madd__n0000__n00056),
    .O(location_Madd__n0000__n0069[0])
  );
  INV _n00001_190 (
    .I(Zero),
    .O(_n00001)
  );
  INV _n00002_191 (
    .I(Reset),
    .O(_n00002)
  );
  INV location_0_15__n00011_192 (
    .I(ce),
    .O(location_0_15__n00011)
  );
  AND2 location_0_15__n00012_193 (
    .I0(_n0000),
    .I1(location_0_15__n00011),
    .O(location_0_15__n00012)
  );
  INV location_Madd__n0000__n00561_194 (
    .I(_n0002),
    .O(location_Madd__n0000__n00561)
  );
  INV location_Madd__n0000__n00541_195 (
    .I(_n0002),
    .O(location_Madd__n0000__n00541)
  );
  AND2 location_Madd__n0000__n00041_196 (
    .I0(location_Madd__n0000__n0065[0]),
    .I1(NlwRenamedSig_OI_count[4]),
    .O(location_Madd__n0000__n0004)
  );
  INV location_Madd__n0000__n00042_197 (
    .I(_n0002),
    .O(location_Madd__n0000__n00041)
  );
  INV location_Madd__n0000__n00043_198 (
    .I(location_Madd__n0000__n0065[0]),
    .O(location_Madd__n0000__n00042)
  );
  INV location_Madd__n0000__n00044_199 (
    .I(NlwRenamedSig_OI_count[4]),
    .O(location_Madd__n0000__n00043)
  );
  AND2 location_Madd__n0000__n00045_200 (
    .I0(location_Madd__n0000__n00042),
    .I1(location_Madd__n0000__n00043),
    .O(location_Madd__n0000__n00044)
  );
  INV location_Madd__n0000__n00046_201 (
    .I(location_Madd__n0000__n00044),
    .O(location_Madd__n0000__n00045)
  );
  AND2 location_Madd__n0000__n00047 (
    .I0(location_Madd__n0000__n00041),
    .I1(location_Madd__n0000__n00045),
    .O(location_Madd__n0000__n00046)
  );
  AND2 location_Madd__n0000__n00131_202 (
    .I0(location_Madd__n0000__n0083[0]),
    .I1(NlwRenamedSig_OI_count[13]),
    .O(location_Madd__n0000__n0013)
  );
  INV location_Madd__n0000__n00132_203 (
    .I(_n0002),
    .O(location_Madd__n0000__n00131)
  );
  INV location_Madd__n0000__n00133_204 (
    .I(location_Madd__n0000__n0083[0]),
    .O(location_Madd__n0000__n00132)
  );
  INV location_Madd__n0000__n00134_205 (
    .I(NlwRenamedSig_OI_count[13]),
    .O(location_Madd__n0000__n00133)
  );
  AND2 location_Madd__n0000__n00135_206 (
    .I0(location_Madd__n0000__n00132),
    .I1(location_Madd__n0000__n00133),
    .O(location_Madd__n0000__n00134)
  );
  INV location_Madd__n0000__n00136_207 (
    .I(location_Madd__n0000__n00134),
    .O(location_Madd__n0000__n00135)
  );
  AND2 location_Madd__n0000__n00137 (
    .I0(location_Madd__n0000__n00131),
    .I1(location_Madd__n0000__n00135),
    .O(location_Madd__n0000__n00136)
  );
  AND2 location_Madd__n0000__n00031_208 (
    .I0(location_Madd__n0000__n0063[0]),
    .I1(NlwRenamedSig_OI_count[3]),
    .O(location_Madd__n0000__n0003)
  );
  INV location_Madd__n0000__n00032_209 (
    .I(_n0002),
    .O(location_Madd__n0000__n00031)
  );
  INV location_Madd__n0000__n00033_210 (
    .I(location_Madd__n0000__n0063[0]),
    .O(location_Madd__n0000__n00032)
  );
  INV location_Madd__n0000__n00034_211 (
    .I(NlwRenamedSig_OI_count[3]),
    .O(location_Madd__n0000__n00033)
  );
  AND2 location_Madd__n0000__n00035_212 (
    .I0(location_Madd__n0000__n00032),
    .I1(location_Madd__n0000__n00033),
    .O(location_Madd__n0000__n00034)
  );
  INV location_Madd__n0000__n00036_213 (
    .I(location_Madd__n0000__n00034),
    .O(location_Madd__n0000__n00035)
  );
  AND2 location_Madd__n0000__n00037 (
    .I0(location_Madd__n0000__n00031),
    .I1(location_Madd__n0000__n00035),
    .O(location_Madd__n0000__n00036)
  );
  AND2 location_Madd__n0000__n00121_214 (
    .I0(location_Madd__n0000__n0081[0]),
    .I1(NlwRenamedSig_OI_count[12]),
    .O(location_Madd__n0000__n0012)
  );
  INV location_Madd__n0000__n00122_215 (
    .I(_n0002),
    .O(location_Madd__n0000__n00121)
  );
  INV location_Madd__n0000__n00123_216 (
    .I(location_Madd__n0000__n0081[0]),
    .O(location_Madd__n0000__n00122)
  );
  INV location_Madd__n0000__n00124_217 (
    .I(NlwRenamedSig_OI_count[12]),
    .O(location_Madd__n0000__n00123)
  );
  AND2 location_Madd__n0000__n00125_218 (
    .I0(location_Madd__n0000__n00122),
    .I1(location_Madd__n0000__n00123),
    .O(location_Madd__n0000__n00124)
  );
  INV location_Madd__n0000__n00126_219 (
    .I(location_Madd__n0000__n00124),
    .O(location_Madd__n0000__n00125)
  );
  AND2 location_Madd__n0000__n00127 (
    .I0(location_Madd__n0000__n00121),
    .I1(location_Madd__n0000__n00125),
    .O(location_Madd__n0000__n00126)
  );
  AND2 location_Madd__n0000__n00021_220 (
    .I0(location_Madd__n0000__n0061[0]),
    .I1(NlwRenamedSig_OI_count[2]),
    .O(location_Madd__n0000__n0002)
  );
  INV location_Madd__n0000__n00022_221 (
    .I(_n0002),
    .O(location_Madd__n0000__n00021)
  );
  INV location_Madd__n0000__n00023_222 (
    .I(location_Madd__n0000__n0061[0]),
    .O(location_Madd__n0000__n00022)
  );
  INV location_Madd__n0000__n00024_223 (
    .I(NlwRenamedSig_OI_count[2]),
    .O(location_Madd__n0000__n00023)
  );
  AND2 location_Madd__n0000__n00025_224 (
    .I0(location_Madd__n0000__n00022),
    .I1(location_Madd__n0000__n00023),
    .O(location_Madd__n0000__n00024)
  );
  INV location_Madd__n0000__n00026_225 (
    .I(location_Madd__n0000__n00024),
    .O(location_Madd__n0000__n00025)
  );
  AND2 location_Madd__n0000__n00027 (
    .I0(location_Madd__n0000__n00021),
    .I1(location_Madd__n0000__n00025),
    .O(location_Madd__n0000__n00026)
  );
  AND2 location_Madd__n0000__n00111_226 (
    .I0(location_Madd__n0000__n0079[0]),
    .I1(NlwRenamedSig_OI_count[11]),
    .O(location_Madd__n0000__n0011)
  );
  INV location_Madd__n0000__n00112_227 (
    .I(_n0002),
    .O(location_Madd__n0000__n00111)
  );
  INV location_Madd__n0000__n00113_228 (
    .I(location_Madd__n0000__n0079[0]),
    .O(location_Madd__n0000__n00112)
  );
  INV location_Madd__n0000__n00114_229 (
    .I(NlwRenamedSig_OI_count[11]),
    .O(location_Madd__n0000__n00113)
  );
  AND2 location_Madd__n0000__n00115_230 (
    .I0(location_Madd__n0000__n00112),
    .I1(location_Madd__n0000__n00113),
    .O(location_Madd__n0000__n00114)
  );
  INV location_Madd__n0000__n00116_231 (
    .I(location_Madd__n0000__n00114),
    .O(location_Madd__n0000__n00115)
  );
  AND2 location_Madd__n0000__n00117 (
    .I0(location_Madd__n0000__n00111),
    .I1(location_Madd__n0000__n00115),
    .O(location_Madd__n0000__n00116)
  );
  AND2 location_Madd__n0000__n00011_232 (
    .I0(NlwRenamedSig_OI_count[0]),
    .I1(NlwRenamedSig_OI_count[1]),
    .O(location_Madd__n0000__n0001)
  );
  INV location_Madd__n0000__n00012_233 (
    .I(_n0002),
    .O(location_Madd__n0000__n00011)
  );
  INV location_Madd__n0000__n00013_234 (
    .I(NlwRenamedSig_OI_count[0]),
    .O(location_Madd__n0000__n00012)
  );
  INV location_Madd__n0000__n00014_235 (
    .I(NlwRenamedSig_OI_count[1]),
    .O(location_Madd__n0000__n00013)
  );
  AND2 location_Madd__n0000__n00015_236 (
    .I0(location_Madd__n0000__n00012),
    .I1(location_Madd__n0000__n00013),
    .O(location_Madd__n0000__n00014)
  );
  INV location_Madd__n0000__n00016_237 (
    .I(location_Madd__n0000__n00014),
    .O(location_Madd__n0000__n00015)
  );
  AND2 location_Madd__n0000__n00017 (
    .I0(location_Madd__n0000__n00011),
    .I1(location_Madd__n0000__n00015),
    .O(location_Madd__n0000__n00016)
  );
  AND2 location_Madd__n0000__n00101_238 (
    .I0(location_Madd__n0000__n0077[0]),
    .I1(NlwRenamedSig_OI_count[10]),
    .O(location_Madd__n0000__n0010)
  );
  INV location_Madd__n0000__n00102_239 (
    .I(_n0002),
    .O(location_Madd__n0000__n00101)
  );
  INV location_Madd__n0000__n00103_240 (
    .I(location_Madd__n0000__n0077[0]),
    .O(location_Madd__n0000__n00102)
  );
  INV location_Madd__n0000__n00104_241 (
    .I(NlwRenamedSig_OI_count[10]),
    .O(location_Madd__n0000__n00103)
  );
  AND2 location_Madd__n0000__n00105_242 (
    .I0(location_Madd__n0000__n00102),
    .I1(location_Madd__n0000__n00103),
    .O(location_Madd__n0000__n00104)
  );
  INV location_Madd__n0000__n00106_243 (
    .I(location_Madd__n0000__n00104),
    .O(location_Madd__n0000__n00105)
  );
  AND2 location_Madd__n0000__n00107 (
    .I0(location_Madd__n0000__n00101),
    .I1(location_Madd__n0000__n00105),
    .O(location_Madd__n0000__n00106)
  );
  AND2 location_Madd__n0000__n00091_244 (
    .I0(location_Madd__n0000__n0075[0]),
    .I1(NlwRenamedSig_OI_count[9]),
    .O(location_Madd__n0000__n0009)
  );
  INV location_Madd__n0000__n00092_245 (
    .I(_n0002),
    .O(location_Madd__n0000__n00091)
  );
  INV location_Madd__n0000__n00093_246 (
    .I(location_Madd__n0000__n0075[0]),
    .O(location_Madd__n0000__n00092)
  );
  INV location_Madd__n0000__n00094_247 (
    .I(NlwRenamedSig_OI_count[9]),
    .O(location_Madd__n0000__n00093)
  );
  AND2 location_Madd__n0000__n00095_248 (
    .I0(location_Madd__n0000__n00092),
    .I1(location_Madd__n0000__n00093),
    .O(location_Madd__n0000__n00094)
  );
  INV location_Madd__n0000__n00096_249 (
    .I(location_Madd__n0000__n00094),
    .O(location_Madd__n0000__n00095)
  );
  AND2 location_Madd__n0000__n00097 (
    .I0(location_Madd__n0000__n00091),
    .I1(location_Madd__n0000__n00095),
    .O(location_Madd__n0000__n00096)
  );
  INV location_Madd__n0000__n00141_250 (
    .I(location_Madd__n0000__n0056),
    .O(location_Madd__n0000__n0014)
  );
  INV location_Madd__n0000__n00142_251 (
    .I(location_Madd__n0000__n0055),
    .O(location_Madd__n0000__n00141)
  );
  INV location_Madd__n0000__n00143_252 (
    .I(location_Madd__n0000__n0054),
    .O(location_Madd__n0000__n00142)
  );
  AND3 location_Madd__n0000__n00144 (
    .I0(location_Madd__n0000__n00141),
    .I1(location_Madd__n0000__n0014),
    .I2(location_Madd__n0000__n00142),
    .O(location_Madd__n0000__n00143)
  );
  AND2 location_Madd__n0000__n00081_253 (
    .I0(location_Madd__n0000__n0073[0]),
    .I1(NlwRenamedSig_OI_count[8]),
    .O(location_Madd__n0000__n0008)
  );
  INV location_Madd__n0000__n00082_254 (
    .I(_n0002),
    .O(location_Madd__n0000__n00081)
  );
  INV location_Madd__n0000__n00083_255 (
    .I(location_Madd__n0000__n0073[0]),
    .O(location_Madd__n0000__n00082)
  );
  INV location_Madd__n0000__n00084_256 (
    .I(NlwRenamedSig_OI_count[8]),
    .O(location_Madd__n0000__n00083)
  );
  AND2 location_Madd__n0000__n00085_257 (
    .I0(location_Madd__n0000__n00082),
    .I1(location_Madd__n0000__n00083),
    .O(location_Madd__n0000__n00084)
  );
  INV location_Madd__n0000__n00086_258 (
    .I(location_Madd__n0000__n00084),
    .O(location_Madd__n0000__n00085)
  );
  AND2 location_Madd__n0000__n00087 (
    .I0(location_Madd__n0000__n00081),
    .I1(location_Madd__n0000__n00085),
    .O(location_Madd__n0000__n00086)
  );
  AND2 location_Madd__n0000__n00071_259 (
    .I0(location_Madd__n0000__n0071[0]),
    .I1(NlwRenamedSig_OI_count[7]),
    .O(location_Madd__n0000__n0007)
  );
  INV location_Madd__n0000__n00072_260 (
    .I(_n0002),
    .O(location_Madd__n0000__n00071)
  );
  INV location_Madd__n0000__n00073_261 (
    .I(location_Madd__n0000__n0071[0]),
    .O(location_Madd__n0000__n00072)
  );
  INV location_Madd__n0000__n00074_262 (
    .I(NlwRenamedSig_OI_count[7]),
    .O(location_Madd__n0000__n00073)
  );
  AND2 location_Madd__n0000__n00075_263 (
    .I0(location_Madd__n0000__n00072),
    .I1(location_Madd__n0000__n00073),
    .O(location_Madd__n0000__n00074)
  );
  INV location_Madd__n0000__n00076_264 (
    .I(location_Madd__n0000__n00074),
    .O(location_Madd__n0000__n00075)
  );
  AND2 location_Madd__n0000__n00077 (
    .I0(location_Madd__n0000__n00071),
    .I1(location_Madd__n0000__n00075),
    .O(location_Madd__n0000__n00076)
  );
  AND2 location_Madd__n0000__n00061_265 (
    .I0(location_Madd__n0000__n0069[0]),
    .I1(NlwRenamedSig_OI_count[6]),
    .O(location_Madd__n0000__n0006)
  );
  INV location_Madd__n0000__n00062_266 (
    .I(_n0002),
    .O(location_Madd__n0000__n00061)
  );
  INV location_Madd__n0000__n00063_267 (
    .I(location_Madd__n0000__n0069[0]),
    .O(location_Madd__n0000__n00062)
  );
  INV location_Madd__n0000__n00064_268 (
    .I(NlwRenamedSig_OI_count[6]),
    .O(location_Madd__n0000__n00063)
  );
  AND2 location_Madd__n0000__n00065_269 (
    .I0(location_Madd__n0000__n00062),
    .I1(location_Madd__n0000__n00063),
    .O(location_Madd__n0000__n00064)
  );
  INV location_Madd__n0000__n00066_270 (
    .I(location_Madd__n0000__n00064),
    .O(location_Madd__n0000__n00065)
  );
  AND2 location_Madd__n0000__n00067 (
    .I0(location_Madd__n0000__n00061),
    .I1(location_Madd__n0000__n00065),
    .O(location_Madd__n0000__n00066)
  );
  AND2 location_Madd__n0000__n00051_271 (
    .I0(location_Madd__n0000__n0067[0]),
    .I1(NlwRenamedSig_OI_count[5]),
    .O(location_Madd__n0000__n0005)
  );
  INV location_Madd__n0000__n00052_272 (
    .I(_n0002),
    .O(location_Madd__n0000__n00051)
  );
  INV location_Madd__n0000__n00053_273 (
    .I(location_Madd__n0000__n0067[0]),
    .O(location_Madd__n0000__n00052)
  );
  INV location_Madd__n0000__n00054_274 (
    .I(NlwRenamedSig_OI_count[5]),
    .O(location_Madd__n0000__n00053)
  );
  AND2 location_Madd__n0000__n00055_275 (
    .I0(location_Madd__n0000__n00052),
    .I1(location_Madd__n0000__n00053),
    .O(location_Madd__n0000__n00054)
  );
  INV location_Madd__n0000__n00056_276 (
    .I(location_Madd__n0000__n00054),
    .O(location_Madd__n0000__n00055)
  );
  AND2 location_Madd__n0000__n00057 (
    .I0(location_Madd__n0000__n00051),
    .I1(location_Madd__n0000__n00055),
    .O(location_Madd__n0000__n00056)
  );
endmodule

module HomeConfig (
  DCORENCCTLw, DCOR0THRESLOWr, DCOR0THRESHIGHr, Reset, DCOR1THRESHIGHr, DCORIFGr, DCORIFGw, MotorIn0, MotorIn1, Home_Encoder0, Home_Encoder1, Sclk, 
DCOR1THRESLOWr, Zero0, Zero1, Hfound0, Hfound1, sense0, sense1, Tfound0, Tfound1, inDATA, Channel0, Channel1, outDATA
);
  input DCORENCCTLw;
  input DCOR0THRESLOWr;
  input DCOR0THRESHIGHr;
  input Reset;
  input DCOR1THRESHIGHr;
  input DCORIFGr;
  input DCORIFGw;
  input MotorIn0;
  input MotorIn1;
  input Home_Encoder0;
  input Home_Encoder1;
  input Sclk;
  input DCOR1THRESLOWr;
  output Zero0;
  output Zero1;
  output Hfound0;
  output Hfound1;
  output sense0;
  output sense1;
  output Tfound0;
  output Tfound1;
  input [7 : 0] inDATA;
  input [15 : 0] Channel0;
  input [15 : 0] Channel1;
  output [7 : 0] outDATA;
  wire NlwRenamedSig_OI_Hfound0;
  wire NlwRenamedSig_OI_Hfound1;
  wire NlwRenamedSig_OI_Tfound0;
  wire NlwRenamedSig_OI_Tfound1;
  wire RF0r;
  wire RF1r;
  wire HE1stater;
  wire HE0stater;
  wire Latch1r_0__n0002;
  wire Latch1r_7__n0000;
  wire Latch1r_15__n0000;
  wire _n0011;
  wire _n0012;
  wire _n0007;
  wire Latch1r_3__n0000;
  wire Latch1r_5__n0000;
  wire _n0009;
  wire _n0020;
  wire _n0015;
  wire _n0021;
  wire _n0022;
  wire _n0017;
  wire _n0023;
  wire _n0024;
  wire _n0019;
  wire Latch0r_9__n0000;
  wire Latch0r_13__n0000;
  wire LatchEdge0r__n0000;
  wire sense0r__n0000;
  wire Latch1r_0__n0000;
  wire Latch0r_11__n0000;
  wire Latch0r_10__n0000;
  wire Latch1r_1__n0000;
  wire Latch0r_2__n0000;
  wire Latch0r_7__n0000;
  wire LatchEdge0r;
  wire Latch0r_3__n0000;
  wire RF0r__n0000;
  wire Latch1r_10__n0000;
  wire Latch1r_6__n0000;
  wire _n0051;
  wire E0r__n0000;
  wire _n0052;
  wire Latch1r_11__n0000;
  wire E1r__n0000;
  wire Latch0r_8__n0000;
  wire LatchEdge1r;
  wire Latch0r_4__n0000;
  wire Latch0r_1__n0000;
  wire Latch0r_1__n0002;
  wire RF1r__n0000;
  wire Latch0r_0__n0000;
  wire Latch1r_4__n0000;
  wire _n0070;
  wire Latch1r_12__n0000;
  wire HE0statelastr;
  wire _n0071;
  wire Latch0r_12__n0000;
  wire Latch1r_8__n0000;
  wire Latch1r_14__n0000;
  wire _n0073;
  wire Latch0r_6__n0000;
  wire Latch1r_9__n0000;
  wire _n0069;
  wire InEdge0r;
  wire InEdge1r;
  wire HE1statelastr;
  wire E0r;
  wire E1r;
  wire N1364;
  wire Latch0r_5__n0000;
  wire Zero1r_N1313;
  wire Hfound1r__n0000;
  wire Latch0r_15__n0000;
  wire Hfound1r__n0002;
  wire Hfound0r__n0000;
  wire Latch1r_13__n0000;
  wire Hfound0r__n0002;
  wire sense1r__n0000;
  wire Latch0r_14__n0000;
  wire sense1r__n0002;
  wire LatchEdge1r__n0000;
  wire Latch0r_0__n0003;
  wire Latch1r_2__n0000;
  wire Latch1r_13__n00001;
  wire Latch0r_1__n00001;
  wire Latch0r_11__n00001;
  wire _n00701;
  wire _n00702;
  wire _n00703;
  wire _n00704;
  wire _n00705;
  wire _n00706;
  wire _n00707;
  wire _n00708;
  wire _n00709;
  wire _n007010;
  wire _n007011;
  wire _n007012;
  wire _n00691;
  wire _n00692;
  wire _n00693;
  wire _n00694;
  wire _n00695;
  wire _n00696;
  wire _n00697;
  wire _n00698;
  wire _n00699;
  wire _n006910;
  wire _n006911;
  wire _n006912;
  wire _n00521;
  wire _n00522;
  wire _n00523;
  wire _n00524;
  wire _n00525;
  wire _n00511;
  wire _n00512;
  wire _n00513;
  wire _n00514;
  wire _n00515;
  wire _n00516;
  wire Latch1r_12__n00001;
  wire Latch0r_8__n00001;
  wire Latch0r_12__n00001;
  wire Latch1r_15__n00001;
  wire Latch1r_10__n00001;
  wire Latch0r_6__n00001;
  wire Latch1r_0__n00021;
  wire Latch1r_0__n00022;
  wire Latch1r_0__n00023;
  wire Latch1r_0__n00024;
  wire Latch1r_0__n00025;
  wire Latch1r_0__n00026;
  wire Latch1r_0__n00027;
  wire Latch1r_0__n00028;
  wire Latch1r_0__n00029;
  wire Latch1r_0__n000210;
  wire Latch1r_0__n000211;
  wire Latch1r_0__n000212;
  wire Latch0r_14__n00001;
  wire Latch0r_1__n00021;
  wire Latch0r_1__n00022;
  wire Latch0r_1__n00023;
  wire Latch0r_1__n00024;
  wire Latch0r_1__n00025;
  wire Latch0r_1__n00026;
  wire Latch0r_1__n00027;
  wire Latch0r_1__n00028;
  wire Latch0r_1__n00029;
  wire Latch0r_1__n000210;
  wire Latch0r_1__n000211;
  wire Latch0r_1__n000212;
  wire Hfound1r__n00021;
  wire Hfound1r__n00022;
  wire Hfound1r__n00023;
  wire Hfound1r__n00024;
  wire Hfound1r__n00025;
  wire Hfound1r__n00026;
  wire Hfound1r__n00027;
  wire Hfound1r__n00028;
  wire Hfound1r__n00029;
  wire Hfound1r__n000210;
  wire Hfound1r__n000211;
  wire Hfound1r__n000212;
  wire Latch1r_0__n00001;
  wire Hfound0r__n00021;
  wire Hfound0r__n00022;
  wire Hfound0r__n00023;
  wire Hfound0r__n00024;
  wire Hfound0r__n00025;
  wire Hfound0r__n00026;
  wire Hfound0r__n00027;
  wire Hfound0r__n00028;
  wire Hfound0r__n00029;
  wire Hfound0r__n000210;
  wire Hfound0r__n000211;
  wire Hfound0r__n000212;
  wire _n00241;
  wire _n00242;
  wire _n00243;
  wire _n00244;
  wire _n00245;
  wire _n00246;
  wire _n00247;
  wire _n00248;
  wire _n00249;
  wire _n002410;
  wire _n002411;
  wire _n00231;
  wire _n00232;
  wire _n00233;
  wire _n00234;
  wire _n00235;
  wire _n00236;
  wire _n00237;
  wire _n00238;
  wire _n00239;
  wire _n002310;
  wire _n002311;
  wire _n00221;
  wire _n00222;
  wire _n00223;
  wire _n00224;
  wire _n00225;
  wire _n00226;
  wire _n00227;
  wire _n00228;
  wire _n00229;
  wire _n002210;
  wire _n002211;
  wire _n002212;
  wire _n002213;
  wire _n002214;
  wire _n002215;
  wire _n00211;
  wire _n00212;
  wire _n00213;
  wire _n00214;
  wire _n00215;
  wire _n00216;
  wire _n00217;
  wire _n00218;
  wire _n00219;
  wire _n002110;
  wire _n002111;
  wire _n002112;
  wire _n002113;
  wire _n002114;
  wire _n002115;
  wire _n00201;
  wire _n00202;
  wire _n00203;
  wire _n00204;
  wire _n00205;
  wire _n00206;
  wire _n00207;
  wire _n00208;
  wire _n00209;
  wire _n002010;
  wire _n002011;
  wire _n00191;
  wire _n00192;
  wire _n00193;
  wire _n00194;
  wire _n00195;
  wire _n00196;
  wire _n00197;
  wire _n00198;
  wire _n00199;
  wire _n001910;
  wire _n001911;
  wire _n001912;
  wire _n001913;
  wire _n001914;
  wire _n001915;
  wire _n00171;
  wire _n00172;
  wire _n00173;
  wire _n00174;
  wire _n00175;
  wire _n00176;
  wire _n00177;
  wire _n00178;
  wire _n00179;
  wire _n001710;
  wire _n001711;
  wire _n001712;
  wire _n001713;
  wire _n001714;
  wire _n001715;
  wire _n00151;
  wire _n00152;
  wire _n00153;
  wire _n00154;
  wire _n00155;
  wire _n00156;
  wire _n00157;
  wire _n00158;
  wire _n00159;
  wire _n001510;
  wire _n001511;
  wire _n00121;
  wire _n00122;
  wire _n00123;
  wire _n00124;
  wire _n00125;
  wire _n00126;
  wire _n00127;
  wire _n00128;
  wire _n00111;
  wire _n00112;
  wire _n00113;
  wire _n00114;
  wire _n00115;
  wire _n00116;
  wire _n00117;
  wire _n00118;
  wire Zero1r_N13131;
  wire Zero1r_N13132;
  wire Zero1r_N13133;
  wire Latch1r_8__n00001;
  wire Latch0r_9__n00001;
  wire Latch1r_9__n00001;
  wire Latch1r_3__n00001;
  wire Hfound0r__n00001;
  wire Hfound0r__n00002;
  wire Hfound0r__n00003;
  wire Hfound0r__n00004;
  wire Hfound0r__n00005;
  wire Hfound1r__n00001;
  wire Hfound1r__n00002;
  wire Hfound1r__n00003;
  wire Hfound1r__n00004;
  wire Hfound1r__n00005;
  wire _n00071;
  wire _n00072;
  wire _n00073;
  wire _n00091;
  wire _n00092;
  wire _n00093;
  wire Latch1r_1__n00001;
  wire Latch0r_3__n00001;
  wire Latch0r_15__n00001;
  wire Latch0r_7__n00001;
  wire Latch1r_11__n00001;
  wire Latch0r_2__n00001;
  wire Latch1r_14__n00001;
  wire Latch1r_2__n00001;
  wire sense1r__n00021;
  wire sense1r__n00022;
  wire sense1r__n00023;
  wire sense1r__n00001;
  wire Latch1r_4__n00001;
  wire LatchEdge1r__n00001;
  wire Latch1r_7__n00001;
  wire E1r__n00001;
  wire Latch0r_5__n00001;
  wire RF1r__n00001;
  wire Latch0r_0__n00001;
  wire Latch0r_13__n00001;
  wire sense0r__n00001;
  wire Latch1r_6__n00001;
  wire LatchEdge0r__n00001;
  wire Latch0r_4__n00001;
  wire Latch0r_10__n00001;
  wire E0r__n00001;
  wire Latch1r_5__n00001;
  wire RF0r__n00001;
  wire [15 : 0] Latch1r;
  wire [15 : 0] Latch0r;
  assign
    Hfound0 = NlwRenamedSig_OI_Hfound0,
    Hfound1 = NlwRenamedSig_OI_Hfound1,
    Tfound0 = NlwRenamedSig_OI_Tfound0,
    Tfound1 = NlwRenamedSig_OI_Tfound1;
  INV _n00731 (
    .I(_n0052),
    .O(_n0073)
  );
  INV _n00711 (
    .I(_n0051),
    .O(_n0071)
  );
  AND2 Latch1r_13__n00002 (
    .I0(Channel1[13]),
    .I1(Latch1r_13__n00001),
    .O(Latch1r_13__n0000)
  );
  FDCE Latch0r_15 (
    .D(Latch0r_15__n0000),
    .CE(Latch0r_1__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch0r[15])
  );
  INV Latch0r_0__n00031 (
    .I(Sclk),
    .O(Latch0r_0__n0003)
  );
  AND2 Latch0r_1__n00002 (
    .I0(Channel0[1]),
    .I1(Latch0r_1__n00001),
    .O(Latch0r_1__n0000)
  );
  BUFE I29_0 (
    .E(_n0071),
    .I(_n0024),
    .O(outDATA[0])
  );
  BUFE I28_0 (
    .E(_n0071),
    .I(_n0023),
    .O(outDATA[1])
  );
  BUFE I27_0 (
    .E(_n0073),
    .I(_n0022),
    .O(outDATA[2])
  );
  BUFE I26_0 (
    .E(_n0073),
    .I(_n0021),
    .O(outDATA[3])
  );
  BUFE I25_0 (
    .E(_n0071),
    .I(_n0020),
    .O(outDATA[4])
  );
  BUFE I24_0 (
    .E(_n0073),
    .I(_n0019),
    .O(outDATA[5])
  );
  BUFE I23_0 (
    .E(_n0073),
    .I(_n0017),
    .O(outDATA[6])
  );
  BUFE I22_0 (
    .E(_n0071),
    .I(_n0015),
    .O(outDATA[7])
  );
  FDCE Latch0r_4 (
    .D(Latch0r_4__n0000),
    .CE(Latch0r_1__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch0r[4])
  );
  AND2 Latch0r_11__n00002 (
    .I0(Channel0[11]),
    .I1(Latch0r_11__n00001),
    .O(Latch0r_11__n0000)
  );
  AND3 _n007013 (
    .I0(_n00706),
    .I1(_n007012),
    .I2(_n00707),
    .O(_n0070)
  );
  FDCE Latch1r_13 (
    .D(Latch1r_13__n0000),
    .CE(Latch1r_0__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch1r[13])
  );
  AND3 _n006913 (
    .I0(_n00696),
    .I1(_n006912),
    .I2(_n00697),
    .O(_n0069)
  );
  FDCE Latch1r_11 (
    .D(Latch1r_11__n0000),
    .CE(Latch1r_0__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch1r[11])
  );
  AND5 _n00526 (
    .I0(_n00522),
    .I1(_n00521),
    .I2(_n00523),
    .I3(_n00524),
    .I4(_n00525),
    .O(_n0052)
  );
  FDCE Latch0r_8 (
    .D(Latch0r_8__n0000),
    .CE(Latch0r_1__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch0r[8])
  );
  FDCE Latch0r_6 (
    .D(Latch0r_6__n0000),
    .CE(Latch0r_1__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch0r[6])
  );
  AND2 _n00517 (
    .I0(_n00516),
    .I1(_n00514),
    .O(_n0051)
  );
  AND2 Latch1r_12__n00002 (
    .I0(Channel1[12]),
    .I1(Latch1r_12__n00001),
    .O(Latch1r_12__n0000)
  );
  FDCE Latch1r_12 (
    .D(Latch1r_12__n0000),
    .CE(Latch1r_0__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch1r[12])
  );
  AND2 Latch0r_8__n00002 (
    .I0(Channel0[8]),
    .I1(Latch0r_8__n00001),
    .O(Latch0r_8__n0000)
  );
  FDCE Latch1r_10 (
    .D(Latch1r_10__n0000),
    .CE(Latch1r_0__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch1r[10])
  );
  AND2 Latch0r_12__n00002 (
    .I0(Channel0[12]),
    .I1(Latch0r_12__n00001),
    .O(Latch0r_12__n0000)
  );
  AND2 Latch1r_15__n00002 (
    .I0(Channel1[15]),
    .I1(Latch1r_15__n00001),
    .O(Latch1r_15__n0000)
  );
  AND2 Latch1r_10__n00002 (
    .I0(Channel1[10]),
    .I1(Latch1r_10__n00001),
    .O(Latch1r_10__n0000)
  );
  FDCE Latch0r_11 (
    .D(Latch0r_11__n0000),
    .CE(Latch0r_1__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch0r[11])
  );
  AND2 Latch0r_6__n00002 (
    .I0(Channel0[6]),
    .I1(Latch0r_6__n00001),
    .O(Latch0r_6__n0000)
  );
  OR2 Latch1r_0__n000213 (
    .I0(Reset),
    .I1(Latch1r_0__n000212),
    .O(Latch1r_0__n0002)
  );
  AND2 Latch0r_14__n00002 (
    .I0(Channel0[14]),
    .I1(Latch0r_14__n00001),
    .O(Latch0r_14__n0000)
  );
  OR2 Latch0r_1__n000213 (
    .I0(Reset),
    .I1(Latch0r_1__n000212),
    .O(Latch0r_1__n0002)
  );
  OR2 Hfound1r__n000213 (
    .I0(Reset),
    .I1(Hfound1r__n000212),
    .O(Hfound1r__n0002)
  );
  AND2 Latch1r_0__n00002 (
    .I0(Channel1[0]),
    .I1(Latch1r_0__n00001),
    .O(Latch1r_0__n0000)
  );
  OR2 Hfound0r__n000213 (
    .I0(Reset),
    .I1(Hfound0r__n000212),
    .O(Hfound0r__n0002)
  );
  FDCE Latch0r_3 (
    .D(Latch0r_3__n0000),
    .CE(Latch0r_1__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch0r[3])
  );
  OR2 _n002412 (
    .I0(_n00241),
    .I1(_n002411),
    .O(_n0024)
  );
  OR2 _n002312 (
    .I0(_n00231),
    .I1(_n002311),
    .O(_n0023)
  );
  OR2 _n002216 (
    .I0(_n00221),
    .I1(_n002215),
    .O(_n0022)
  );
  OR2 _n002116 (
    .I0(_n00211),
    .I1(_n002115),
    .O(_n0021)
  );
  OR2 _n002012 (
    .I0(_n00201),
    .I1(_n002011),
    .O(_n0020)
  );
  OR2 _n001916 (
    .I0(_n00191),
    .I1(_n001915),
    .O(_n0019)
  );
  OR2 _n001716 (
    .I0(_n00171),
    .I1(_n001715),
    .O(_n0017)
  );
  OR2 _n001512 (
    .I0(_n00151),
    .I1(_n001511),
    .O(_n0015)
  );
  AND3 _n00129 (
    .I0(_n00128),
    .I1(E1r),
    .I2(_n00125),
    .O(_n0012)
  );
  AND3 _n00119 (
    .I0(_n00118),
    .I1(E0r),
    .I2(_n00115),
    .O(_n0011)
  );
  FDCE Latch0r_5 (
    .D(Latch0r_5__n0000),
    .CE(Latch0r_1__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch0r[5])
  );
  FDCE Latch0r_14 (
    .D(Latch0r_14__n0000),
    .CE(Latch0r_1__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch0r[14])
  );
  AND3 Zero1r_N13134 (
    .I0(Zero1r_N13132),
    .I1(Zero1r_N13131),
    .I2(Zero1r_N13133),
    .O(Zero1r_N1313)
  );
  AND2 Latch1r_8__n00002 (
    .I0(Channel1[8]),
    .I1(Latch1r_8__n00001),
    .O(Latch1r_8__n0000)
  );
  AND2 Latch0r_9__n00002 (
    .I0(Channel0[9]),
    .I1(Latch0r_9__n00001),
    .O(Latch0r_9__n0000)
  );
  AND2 Latch1r_9__n00002 (
    .I0(Channel1[9]),
    .I1(Latch1r_9__n00001),
    .O(Latch1r_9__n0000)
  );
  AND2 Latch1r_3__n00002 (
    .I0(Channel1[3]),
    .I1(Latch1r_3__n00001),
    .O(Latch1r_3__n0000)
  );
  AND2 Hfound0r__n00006 (
    .I0(Hfound0r__n00005),
    .I1(Hfound0r__n00003),
    .O(Hfound0r__n0000)
  );
  AND2 Hfound1r__n00006 (
    .I0(Hfound1r__n00005),
    .I1(Hfound1r__n00003),
    .O(Hfound1r__n0000)
  );
  OR2 _n00074 (
    .I0(_n00073),
    .I1(_n00072),
    .O(_n0007)
  );
  OR2 _n00094 (
    .I0(_n00093),
    .I1(_n00092),
    .O(_n0009)
  );
  FDCE Zero1r (
    .D(_n0012),
    .CE(Zero1r_N1313),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Zero1)
  );
  FDCE Zero0r (
    .D(_n0011),
    .CE(Zero1r_N1313),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Zero0)
  );
  GND XST_GND (
    .G(N1364)
  );
  FDCE Tfound0r (
    .D(_n0007),
    .CE(_n0069),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(NlwRenamedSig_OI_Tfound0)
  );
  FDCE Hfound1r (
    .D(Hfound1r__n0000),
    .CE(Hfound1r__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(NlwRenamedSig_OI_Hfound1)
  );
  FDCE Hfound0r (
    .D(Hfound0r__n0000),
    .CE(Hfound0r__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(NlwRenamedSig_OI_Hfound0)
  );
  AND2 Latch1r_1__n00002 (
    .I0(Channel1[1]),
    .I1(Latch1r_1__n00001),
    .O(Latch1r_1__n0000)
  );
  FDCE Latch0r_13 (
    .D(Latch0r_13__n0000),
    .CE(Latch0r_1__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch0r[13])
  );
  FDCE sense1r (
    .D(sense1r__n0000),
    .CE(sense1r__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(sense1)
  );
  FDCE LatchEdge1r_661 (
    .D(LatchEdge1r__n0000),
    .CE(sense1r__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(LatchEdge1r)
  );
  FDCE E1r_662 (
    .D(E1r__n0000),
    .CE(sense1r__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(E1r)
  );
  FDCE RF1r_663 (
    .D(RF1r__n0000),
    .CE(sense1r__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(RF1r)
  );
  FDCE sense0r (
    .D(sense0r__n0000),
    .CE(sense1r__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(sense0)
  );
  FD HE0stater_664 (
    .D(Home_Encoder0),
    .C(Latch0r_0__n0003),
    .Q(HE0stater)
  );
  FD HE0statelastr_665 (
    .D(HE0stater),
    .C(Latch0r_0__n0003),
    .Q(HE0statelastr)
  );
  FD HE1stater_666 (
    .D(Home_Encoder1),
    .C(Latch0r_0__n0003),
    .Q(HE1stater)
  );
  FD HE1statelastr_667 (
    .D(HE1stater),
    .C(Latch0r_0__n0003),
    .Q(HE1statelastr)
  );
  FD InEdge0r_668 (
    .D(MotorIn0),
    .C(Latch0r_0__n0003),
    .Q(InEdge0r)
  );
  FD InEdge1r_669 (
    .D(MotorIn1),
    .C(Latch0r_0__n0003),
    .Q(InEdge1r)
  );
  FDCE RF0r_670 (
    .D(RF0r__n0000),
    .CE(sense1r__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(RF0r)
  );
  FDCE E0r_671 (
    .D(E0r__n0000),
    .CE(sense1r__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(E0r)
  );
  FDCE LatchEdge0r_672 (
    .D(LatchEdge0r__n0000),
    .CE(sense1r__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(LatchEdge0r)
  );
  AND2 Latch0r_3__n00002 (
    .I0(Channel0[3]),
    .I1(Latch0r_3__n00001),
    .O(Latch0r_3__n0000)
  );
  FDCE Tfound1r (
    .D(_n0009),
    .CE(_n0070),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(NlwRenamedSig_OI_Tfound1)
  );
  FDCE Latch0r_7 (
    .D(Latch0r_7__n0000),
    .CE(Latch0r_1__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch0r[7])
  );
  AND2 Latch0r_15__n00002 (
    .I0(Channel0[15]),
    .I1(Latch0r_15__n00001),
    .O(Latch0r_15__n0000)
  );
  AND2 Latch0r_7__n00002 (
    .I0(Channel0[7]),
    .I1(Latch0r_7__n00001),
    .O(Latch0r_7__n0000)
  );
  AND2 Latch1r_11__n00002 (
    .I0(Channel1[11]),
    .I1(Latch1r_11__n00001),
    .O(Latch1r_11__n0000)
  );
  AND2 Latch0r_2__n00002 (
    .I0(Channel0[2]),
    .I1(Latch0r_2__n00001),
    .O(Latch0r_2__n0000)
  );
  AND2 Latch1r_14__n00002 (
    .I0(Channel1[14]),
    .I1(Latch1r_14__n00001),
    .O(Latch1r_14__n0000)
  );
  AND2 Latch1r_2__n00002 (
    .I0(Channel1[2]),
    .I1(Latch1r_2__n00001),
    .O(Latch1r_2__n0000)
  );
  FDCE Latch0r_0 (
    .D(Latch0r_0__n0000),
    .CE(Latch0r_1__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch0r[0])
  );
  INV sense1r__n00024 (
    .I(sense1r__n00023),
    .O(sense1r__n0002)
  );
  AND2 sense1r__n00002 (
    .I0(inDATA[7]),
    .I1(sense1r__n00001),
    .O(sense1r__n0000)
  );
  FDCE Latch0r_9 (
    .D(Latch0r_9__n0000),
    .CE(Latch0r_1__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch0r[9])
  );
  AND2 Latch1r_4__n00002 (
    .I0(Channel1[4]),
    .I1(Latch1r_4__n00001),
    .O(Latch1r_4__n0000)
  );
  AND2 LatchEdge1r__n00002 (
    .I0(inDATA[6]),
    .I1(LatchEdge1r__n00001),
    .O(LatchEdge1r__n0000)
  );
  FDCE Latch0r_2 (
    .D(Latch0r_2__n0000),
    .CE(Latch0r_1__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch0r[2])
  );
  AND2 Latch1r_7__n00002 (
    .I0(Channel1[7]),
    .I1(Latch1r_7__n00001),
    .O(Latch1r_7__n0000)
  );
  AND2 E1r__n00002 (
    .I0(inDATA[5]),
    .I1(E1r__n00001),
    .O(E1r__n0000)
  );
  AND2 Latch0r_5__n00002 (
    .I0(Channel0[5]),
    .I1(Latch0r_5__n00001),
    .O(Latch0r_5__n0000)
  );
  FDCE Latch0r_10 (
    .D(Latch0r_10__n0000),
    .CE(Latch0r_1__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch0r[10])
  );
  AND2 RF1r__n00002 (
    .I0(inDATA[4]),
    .I1(RF1r__n00001),
    .O(RF1r__n0000)
  );
  AND2 Latch0r_0__n00002 (
    .I0(Channel0[0]),
    .I1(Latch0r_0__n00001),
    .O(Latch0r_0__n0000)
  );
  AND2 Latch0r_13__n00002 (
    .I0(Channel0[13]),
    .I1(Latch0r_13__n00001),
    .O(Latch0r_13__n0000)
  );
  AND2 sense0r__n00002 (
    .I0(inDATA[3]),
    .I1(sense0r__n00001),
    .O(sense0r__n0000)
  );
  FDCE Latch0r_1 (
    .D(Latch0r_1__n0000),
    .CE(Latch0r_1__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch0r[1])
  );
  AND2 Latch1r_6__n00002 (
    .I0(Channel1[6]),
    .I1(Latch1r_6__n00001),
    .O(Latch1r_6__n0000)
  );
  AND2 LatchEdge0r__n00002 (
    .I0(inDATA[2]),
    .I1(LatchEdge0r__n00001),
    .O(LatchEdge0r__n0000)
  );
  AND2 Latch0r_4__n00002 (
    .I0(Channel0[4]),
    .I1(Latch0r_4__n00001),
    .O(Latch0r_4__n0000)
  );
  AND2 Latch0r_10__n00002 (
    .I0(Channel0[10]),
    .I1(Latch0r_10__n00001),
    .O(Latch0r_10__n0000)
  );
  AND2 E0r__n00002 (
    .I0(inDATA[1]),
    .I1(E0r__n00001),
    .O(E0r__n0000)
  );
  FDCE Latch0r_12 (
    .D(Latch0r_12__n0000),
    .CE(Latch0r_1__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch0r[12])
  );
  AND2 Latch1r_5__n00002 (
    .I0(Channel1[5]),
    .I1(Latch1r_5__n00001),
    .O(Latch1r_5__n0000)
  );
  AND2 RF0r__n00002 (
    .I0(inDATA[0]),
    .I1(RF0r__n00001),
    .O(RF0r__n0000)
  );
  FDCE Latch1r_15 (
    .D(Latch1r_15__n0000),
    .CE(Latch1r_0__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch1r[15])
  );
  FDCE Latch1r_14 (
    .D(Latch1r_14__n0000),
    .CE(Latch1r_0__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch1r[14])
  );
  FDCE Latch1r_0 (
    .D(Latch1r_0__n0000),
    .CE(Latch1r_0__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch1r[0])
  );
  FDCE Latch1r_1 (
    .D(Latch1r_1__n0000),
    .CE(Latch1r_0__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch1r[1])
  );
  FDCE Latch1r_2 (
    .D(Latch1r_2__n0000),
    .CE(Latch1r_0__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch1r[2])
  );
  FDCE Latch1r_3 (
    .D(Latch1r_3__n0000),
    .CE(Latch1r_0__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch1r[3])
  );
  FDCE Latch1r_4 (
    .D(Latch1r_4__n0000),
    .CE(Latch1r_0__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch1r[4])
  );
  FDCE Latch1r_5 (
    .D(Latch1r_5__n0000),
    .CE(Latch1r_0__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch1r[5])
  );
  FDCE Latch1r_6 (
    .D(Latch1r_6__n0000),
    .CE(Latch1r_0__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch1r[6])
  );
  FDCE Latch1r_7 (
    .D(Latch1r_7__n0000),
    .CE(Latch1r_0__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch1r[7])
  );
  FDCE Latch1r_8 (
    .D(Latch1r_8__n0000),
    .CE(Latch1r_0__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch1r[8])
  );
  FDCE Latch1r_9 (
    .D(Latch1r_9__n0000),
    .CE(Latch1r_0__n0002),
    .CLR(N1364),
    .C(Latch0r_0__n0003),
    .Q(Latch1r[9])
  );
  INV Latch1r_13__n00001_673 (
    .I(Reset),
    .O(Latch1r_13__n00001)
  );
  INV Latch0r_1__n00001_674 (
    .I(Reset),
    .O(Latch0r_1__n00001)
  );
  INV Latch0r_11__n00001_675 (
    .I(Reset),
    .O(Latch0r_11__n00001)
  );
  AND2 _n00701_676 (
    .I0(MotorIn1),
    .I1(LatchEdge1r),
    .O(_n00701)
  );
  INV _n00702_677 (
    .I(InEdge1r),
    .O(_n00702)
  );
  INV _n00703_678 (
    .I(MotorIn1),
    .O(_n00703)
  );
  INV _n00704_679 (
    .I(LatchEdge1r),
    .O(_n00704)
  );
  INV _n00705_680 (
    .I(NlwRenamedSig_OI_Tfound1),
    .O(_n00705)
  );
  INV _n00706_681 (
    .I(Reset),
    .O(_n00706)
  );
  INV _n00707_682 (
    .I(DCORENCCTLw),
    .O(_n00707)
  );
  AND2 _n00708_683 (
    .I0(_n00701),
    .I1(_n00702),
    .O(_n00708)
  );
  AND3 _n00709_684 (
    .I0(_n00703),
    .I1(InEdge1r),
    .I2(_n00704),
    .O(_n00709)
  );
  OR2 _n007010_685 (
    .I0(_n00708),
    .I1(_n00709),
    .O(_n007010)
  );
  AND2 _n007011_686 (
    .I0(_n007010),
    .I1(_n00705),
    .O(_n007011)
  );
  OR2 _n007012_687 (
    .I0(DCORIFGw),
    .I1(_n007011),
    .O(_n007012)
  );
  AND2 _n00691_688 (
    .I0(MotorIn0),
    .I1(LatchEdge0r),
    .O(_n00691)
  );
  INV _n00692_689 (
    .I(InEdge0r),
    .O(_n00692)
  );
  INV _n00693_690 (
    .I(MotorIn0),
    .O(_n00693)
  );
  INV _n00694_691 (
    .I(LatchEdge0r),
    .O(_n00694)
  );
  INV _n00695_692 (
    .I(NlwRenamedSig_OI_Tfound0),
    .O(_n00695)
  );
  INV _n00696_693 (
    .I(Reset),
    .O(_n00696)
  );
  INV _n00697_694 (
    .I(DCORENCCTLw),
    .O(_n00697)
  );
  AND2 _n00698_695 (
    .I0(_n00691),
    .I1(_n00692),
    .O(_n00698)
  );
  AND3 _n00699_696 (
    .I0(_n00693),
    .I1(InEdge0r),
    .I2(_n00694),
    .O(_n00699)
  );
  OR2 _n006910_697 (
    .I0(_n00698),
    .I1(_n00699),
    .O(_n006910)
  );
  AND2 _n006911_698 (
    .I0(_n006910),
    .I1(_n00695),
    .O(_n006911)
  );
  OR2 _n006912_699 (
    .I0(DCORIFGw),
    .I1(_n006911),
    .O(_n006912)
  );
  INV _n00521_700 (
    .I(DCOR1THRESLOWr),
    .O(_n00521)
  );
  INV _n00522_701 (
    .I(DCOR1THRESHIGHr),
    .O(_n00522)
  );
  INV _n00523_702 (
    .I(DCOR0THRESHIGHr),
    .O(_n00523)
  );
  INV _n00524_703 (
    .I(DCORIFGr),
    .O(_n00524)
  );
  INV _n00525_704 (
    .I(DCOR0THRESLOWr),
    .O(_n00525)
  );
  INV _n00511_705 (
    .I(DCOR1THRESLOWr),
    .O(_n00511)
  );
  INV _n00512_706 (
    .I(DCOR1THRESHIGHr),
    .O(_n00512)
  );
  INV _n00513_707 (
    .I(DCOR0THRESHIGHr),
    .O(_n00513)
  );
  INV _n00514_708 (
    .I(DCOR0THRESLOWr),
    .O(_n00514)
  );
  AND3 _n00515_709 (
    .I0(_n00512),
    .I1(_n00511),
    .I2(_n00513),
    .O(_n00515)
  );
  OR2 _n00516_710 (
    .I0(DCORIFGr),
    .I1(_n00515),
    .O(_n00516)
  );
  INV Latch1r_12__n00001_711 (
    .I(Reset),
    .O(Latch1r_12__n00001)
  );
  INV Latch0r_8__n00001_712 (
    .I(Reset),
    .O(Latch0r_8__n00001)
  );
  INV Latch0r_12__n00001_713 (
    .I(Reset),
    .O(Latch0r_12__n00001)
  );
  INV Latch1r_15__n00001_714 (
    .I(Reset),
    .O(Latch1r_15__n00001)
  );
  INV Latch1r_10__n00001_715 (
    .I(Reset),
    .O(Latch1r_10__n00001)
  );
  INV Latch0r_6__n00001_716 (
    .I(Reset),
    .O(Latch0r_6__n00001)
  );
  AND2 Latch1r_0__n00021_717 (
    .I0(MotorIn1),
    .I1(LatchEdge1r),
    .O(Latch1r_0__n00021)
  );
  INV Latch1r_0__n00022_718 (
    .I(InEdge1r),
    .O(Latch1r_0__n00022)
  );
  INV Latch1r_0__n00023_719 (
    .I(MotorIn1),
    .O(Latch1r_0__n00023)
  );
  INV Latch1r_0__n00024_720 (
    .I(LatchEdge1r),
    .O(Latch1r_0__n00024)
  );
  INV Latch1r_0__n00025_721 (
    .I(DCORENCCTLw),
    .O(Latch1r_0__n00025)
  );
  INV Latch1r_0__n00026_722 (
    .I(DCORIFGw),
    .O(Latch1r_0__n00026)
  );
  INV Latch1r_0__n00027_723 (
    .I(NlwRenamedSig_OI_Tfound1),
    .O(Latch1r_0__n00027)
  );
  AND2 Latch1r_0__n00028_724 (
    .I0(Latch1r_0__n00021),
    .I1(Latch1r_0__n00022),
    .O(Latch1r_0__n00028)
  );
  AND3 Latch1r_0__n00029_725 (
    .I0(Latch1r_0__n00023),
    .I1(InEdge1r),
    .I2(Latch1r_0__n00024),
    .O(Latch1r_0__n00029)
  );
  AND2 Latch1r_0__n000210_726 (
    .I0(Latch1r_0__n00026),
    .I1(Latch1r_0__n00027),
    .O(Latch1r_0__n000210)
  );
  OR2 Latch1r_0__n000211_727 (
    .I0(Latch1r_0__n00028),
    .I1(Latch1r_0__n00029),
    .O(Latch1r_0__n000211)
  );
  AND3 Latch1r_0__n000212_728 (
    .I0(Latch1r_0__n00025),
    .I1(Latch1r_0__n000211),
    .I2(Latch1r_0__n000210),
    .O(Latch1r_0__n000212)
  );
  INV Latch0r_14__n00001_729 (
    .I(Reset),
    .O(Latch0r_14__n00001)
  );
  AND2 Latch0r_1__n00021_730 (
    .I0(MotorIn0),
    .I1(LatchEdge0r),
    .O(Latch0r_1__n00021)
  );
  INV Latch0r_1__n00022_731 (
    .I(InEdge0r),
    .O(Latch0r_1__n00022)
  );
  INV Latch0r_1__n00023_732 (
    .I(MotorIn0),
    .O(Latch0r_1__n00023)
  );
  INV Latch0r_1__n00024_733 (
    .I(LatchEdge0r),
    .O(Latch0r_1__n00024)
  );
  INV Latch0r_1__n00025_734 (
    .I(DCORENCCTLw),
    .O(Latch0r_1__n00025)
  );
  INV Latch0r_1__n00026_735 (
    .I(DCORIFGw),
    .O(Latch0r_1__n00026)
  );
  INV Latch0r_1__n00027_736 (
    .I(NlwRenamedSig_OI_Tfound0),
    .O(Latch0r_1__n00027)
  );
  AND2 Latch0r_1__n00028_737 (
    .I0(Latch0r_1__n00021),
    .I1(Latch0r_1__n00022),
    .O(Latch0r_1__n00028)
  );
  AND3 Latch0r_1__n00029_738 (
    .I0(Latch0r_1__n00023),
    .I1(InEdge0r),
    .I2(Latch0r_1__n00024),
    .O(Latch0r_1__n00029)
  );
  AND2 Latch0r_1__n000210_739 (
    .I0(Latch0r_1__n00026),
    .I1(Latch0r_1__n00027),
    .O(Latch0r_1__n000210)
  );
  OR2 Latch0r_1__n000211_740 (
    .I0(Latch0r_1__n00028),
    .I1(Latch0r_1__n00029),
    .O(Latch0r_1__n000211)
  );
  AND3 Latch0r_1__n000212_741 (
    .I0(Latch0r_1__n00025),
    .I1(Latch0r_1__n000211),
    .I2(Latch0r_1__n000210),
    .O(Latch0r_1__n000212)
  );
  AND2 Hfound1r__n00021_742 (
    .I0(HE1stater),
    .I1(RF1r),
    .O(Hfound1r__n00021)
  );
  INV Hfound1r__n00022_743 (
    .I(HE1statelastr),
    .O(Hfound1r__n00022)
  );
  INV Hfound1r__n00023_744 (
    .I(HE1stater),
    .O(Hfound1r__n00023)
  );
  INV Hfound1r__n00024_745 (
    .I(RF1r),
    .O(Hfound1r__n00024)
  );
  INV Hfound1r__n00025_746 (
    .I(NlwRenamedSig_OI_Hfound1),
    .O(Hfound1r__n00025)
  );
  INV Hfound1r__n00026_747 (
    .I(DCORENCCTLw),
    .O(Hfound1r__n00026)
  );
  AND2 Hfound1r__n00027_748 (
    .I0(Hfound1r__n00021),
    .I1(Hfound1r__n00022),
    .O(Hfound1r__n00027)
  );
  AND3 Hfound1r__n00028_749 (
    .I0(Hfound1r__n00023),
    .I1(HE1statelastr),
    .I2(Hfound1r__n00024),
    .O(Hfound1r__n00028)
  );
  OR2 Hfound1r__n00029_750 (
    .I0(Hfound1r__n00027),
    .I1(Hfound1r__n00028),
    .O(Hfound1r__n00029)
  );
  AND3 Hfound1r__n000210_751 (
    .I0(Hfound1r__n00029),
    .I1(E1r),
    .I2(Hfound1r__n00025),
    .O(Hfound1r__n000210)
  );
  OR2 Hfound1r__n000211_752 (
    .I0(DCORIFGw),
    .I1(Hfound1r__n000210),
    .O(Hfound1r__n000211)
  );
  AND2 Hfound1r__n000212_753 (
    .I0(Hfound1r__n000211),
    .I1(Hfound1r__n00026),
    .O(Hfound1r__n000212)
  );
  INV Latch1r_0__n00001_754 (
    .I(Reset),
    .O(Latch1r_0__n00001)
  );
  AND2 Hfound0r__n00021_755 (
    .I0(HE0stater),
    .I1(RF0r),
    .O(Hfound0r__n00021)
  );
  INV Hfound0r__n00022_756 (
    .I(HE0statelastr),
    .O(Hfound0r__n00022)
  );
  INV Hfound0r__n00023_757 (
    .I(HE0stater),
    .O(Hfound0r__n00023)
  );
  INV Hfound0r__n00024_758 (
    .I(RF0r),
    .O(Hfound0r__n00024)
  );
  INV Hfound0r__n00025_759 (
    .I(NlwRenamedSig_OI_Hfound0),
    .O(Hfound0r__n00025)
  );
  INV Hfound0r__n00026_760 (
    .I(DCORENCCTLw),
    .O(Hfound0r__n00026)
  );
  AND2 Hfound0r__n00027_761 (
    .I0(Hfound0r__n00021),
    .I1(Hfound0r__n00022),
    .O(Hfound0r__n00027)
  );
  AND3 Hfound0r__n00028_762 (
    .I0(Hfound0r__n00023),
    .I1(HE0statelastr),
    .I2(Hfound0r__n00024),
    .O(Hfound0r__n00028)
  );
  OR2 Hfound0r__n00029_763 (
    .I0(Hfound0r__n00027),
    .I1(Hfound0r__n00028),
    .O(Hfound0r__n00029)
  );
  AND3 Hfound0r__n000210_764 (
    .I0(Hfound0r__n00029),
    .I1(E0r),
    .I2(Hfound0r__n00025),
    .O(Hfound0r__n000210)
  );
  OR2 Hfound0r__n000211_765 (
    .I0(DCORIFGw),
    .I1(Hfound0r__n000210),
    .O(Hfound0r__n000211)
  );
  AND2 Hfound0r__n000212_766 (
    .I0(Hfound0r__n000211),
    .I1(Hfound0r__n00026),
    .O(Hfound0r__n000212)
  );
  AND2 _n00241_767 (
    .I0(DCOR0THRESLOWr),
    .I1(Latch0r[0]),
    .O(_n00241)
  );
  AND2 _n00242_768 (
    .I0(DCOR0THRESHIGHr),
    .I1(Latch0r[8]),
    .O(_n00242)
  );
  AND2 _n00243_769 (
    .I0(DCOR1THRESLOWr),
    .I1(Latch1r[0]),
    .O(_n00243)
  );
  INV _n00244_770 (
    .I(DCOR1THRESLOWr),
    .O(_n00244)
  );
  INV _n00245_771 (
    .I(DCOR0THRESHIGHr),
    .O(_n00245)
  );
  INV _n00246_772 (
    .I(DCOR0THRESLOWr),
    .O(_n00246)
  );
  AND2 _n00247_773 (
    .I0(Latch1r[8]),
    .I1(_n00244),
    .O(_n00247)
  );
  OR2 _n00248_774 (
    .I0(_n00243),
    .I1(_n00247),
    .O(_n00248)
  );
  AND2 _n00249_775 (
    .I0(_n00248),
    .I1(_n00245),
    .O(_n00249)
  );
  OR2 _n002410_776 (
    .I0(_n00242),
    .I1(_n00249),
    .O(_n002410)
  );
  AND2 _n002411_777 (
    .I0(_n002410),
    .I1(_n00246),
    .O(_n002411)
  );
  AND2 _n00231_778 (
    .I0(DCOR0THRESLOWr),
    .I1(Latch0r[1]),
    .O(_n00231)
  );
  AND2 _n00232_779 (
    .I0(DCOR0THRESHIGHr),
    .I1(Latch0r[9]),
    .O(_n00232)
  );
  AND2 _n00233_780 (
    .I0(DCOR1THRESLOWr),
    .I1(Latch1r[1]),
    .O(_n00233)
  );
  INV _n00234_781 (
    .I(DCOR1THRESLOWr),
    .O(_n00234)
  );
  INV _n00235_782 (
    .I(DCOR0THRESHIGHr),
    .O(_n00235)
  );
  INV _n00236_783 (
    .I(DCOR0THRESLOWr),
    .O(_n00236)
  );
  AND2 _n00237_784 (
    .I0(Latch1r[9]),
    .I1(_n00234),
    .O(_n00237)
  );
  OR2 _n00238_785 (
    .I0(_n00233),
    .I1(_n00237),
    .O(_n00238)
  );
  AND2 _n00239_786 (
    .I0(_n00238),
    .I1(_n00235),
    .O(_n00239)
  );
  OR2 _n002310_787 (
    .I0(_n00232),
    .I1(_n00239),
    .O(_n002310)
  );
  AND2 _n002311_788 (
    .I0(_n002310),
    .I1(_n00236),
    .O(_n002311)
  );
  AND2 _n00221_789 (
    .I0(DCOR0THRESLOWr),
    .I1(Latch0r[2]),
    .O(_n00221)
  );
  AND2 _n00222_790 (
    .I0(DCORIFGr),
    .I1(NlwRenamedSig_OI_Hfound0),
    .O(_n00222)
  );
  AND2 _n00223_791 (
    .I0(DCOR0THRESHIGHr),
    .I1(Latch0r[10]),
    .O(_n00223)
  );
  AND2 _n00224_792 (
    .I0(DCOR1THRESLOWr),
    .I1(Latch1r[2]),
    .O(_n00224)
  );
  INV _n00225_793 (
    .I(DCOR1THRESLOWr),
    .O(_n00225)
  );
  INV _n00226_794 (
    .I(DCOR0THRESHIGHr),
    .O(_n00226)
  );
  INV _n00227_795 (
    .I(DCORIFGr),
    .O(_n00227)
  );
  INV _n00228_796 (
    .I(DCOR0THRESLOWr),
    .O(_n00228)
  );
  AND2 _n00229_797 (
    .I0(Latch1r[10]),
    .I1(_n00225),
    .O(_n00229)
  );
  OR2 _n002210_798 (
    .I0(_n00224),
    .I1(_n00229),
    .O(_n002210)
  );
  AND2 _n002211_799 (
    .I0(_n002210),
    .I1(_n00226),
    .O(_n002211)
  );
  OR2 _n002212_800 (
    .I0(_n00223),
    .I1(_n002211),
    .O(_n002212)
  );
  AND2 _n002213_801 (
    .I0(_n002212),
    .I1(_n00227),
    .O(_n002213)
  );
  OR2 _n002214_802 (
    .I0(_n00222),
    .I1(_n002213),
    .O(_n002214)
  );
  AND2 _n002215_803 (
    .I0(_n002214),
    .I1(_n00228),
    .O(_n002215)
  );
  AND2 _n00211_804 (
    .I0(DCOR0THRESLOWr),
    .I1(Latch0r[3]),
    .O(_n00211)
  );
  AND2 _n00212_805 (
    .I0(DCORIFGr),
    .I1(NlwRenamedSig_OI_Hfound1),
    .O(_n00212)
  );
  AND2 _n00213_806 (
    .I0(DCOR0THRESHIGHr),
    .I1(Latch0r[11]),
    .O(_n00213)
  );
  AND2 _n00214_807 (
    .I0(DCOR1THRESLOWr),
    .I1(Latch1r[3]),
    .O(_n00214)
  );
  INV _n00215_808 (
    .I(DCOR1THRESLOWr),
    .O(_n00215)
  );
  INV _n00216_809 (
    .I(DCOR0THRESHIGHr),
    .O(_n00216)
  );
  INV _n00217_810 (
    .I(DCORIFGr),
    .O(_n00217)
  );
  INV _n00218_811 (
    .I(DCOR0THRESLOWr),
    .O(_n00218)
  );
  AND2 _n00219_812 (
    .I0(Latch1r[11]),
    .I1(_n00215),
    .O(_n00219)
  );
  OR2 _n002110_813 (
    .I0(_n00214),
    .I1(_n00219),
    .O(_n002110)
  );
  AND2 _n002111_814 (
    .I0(_n002110),
    .I1(_n00216),
    .O(_n002111)
  );
  OR2 _n002112_815 (
    .I0(_n00213),
    .I1(_n002111),
    .O(_n002112)
  );
  AND2 _n002113_816 (
    .I0(_n002112),
    .I1(_n00217),
    .O(_n002113)
  );
  OR2 _n002114_817 (
    .I0(_n00212),
    .I1(_n002113),
    .O(_n002114)
  );
  AND2 _n002115_818 (
    .I0(_n002114),
    .I1(_n00218),
    .O(_n002115)
  );
  AND2 _n00201_819 (
    .I0(DCOR0THRESLOWr),
    .I1(Latch0r[4]),
    .O(_n00201)
  );
  AND2 _n00202_820 (
    .I0(DCOR0THRESHIGHr),
    .I1(Latch0r[12]),
    .O(_n00202)
  );
  AND2 _n00203_821 (
    .I0(DCOR1THRESLOWr),
    .I1(Latch1r[4]),
    .O(_n00203)
  );
  INV _n00204_822 (
    .I(DCOR1THRESLOWr),
    .O(_n00204)
  );
  INV _n00205_823 (
    .I(DCOR0THRESHIGHr),
    .O(_n00205)
  );
  INV _n00206_824 (
    .I(DCOR0THRESLOWr),
    .O(_n00206)
  );
  AND2 _n00207_825 (
    .I0(Latch1r[12]),
    .I1(_n00204),
    .O(_n00207)
  );
  OR2 _n00208_826 (
    .I0(_n00203),
    .I1(_n00207),
    .O(_n00208)
  );
  AND2 _n00209_827 (
    .I0(_n00208),
    .I1(_n00205),
    .O(_n00209)
  );
  OR2 _n002010_828 (
    .I0(_n00202),
    .I1(_n00209),
    .O(_n002010)
  );
  AND2 _n002011_829 (
    .I0(_n002010),
    .I1(_n00206),
    .O(_n002011)
  );
  AND2 _n00191_830 (
    .I0(DCOR0THRESLOWr),
    .I1(Latch0r[5]),
    .O(_n00191)
  );
  AND2 _n00192_831 (
    .I0(DCORIFGr),
    .I1(NlwRenamedSig_OI_Tfound0),
    .O(_n00192)
  );
  AND2 _n00193_832 (
    .I0(DCOR0THRESHIGHr),
    .I1(Latch0r[13]),
    .O(_n00193)
  );
  AND2 _n00194_833 (
    .I0(DCOR1THRESLOWr),
    .I1(Latch1r[5]),
    .O(_n00194)
  );
  INV _n00195_834 (
    .I(DCOR1THRESLOWr),
    .O(_n00195)
  );
  INV _n00196_835 (
    .I(DCOR0THRESHIGHr),
    .O(_n00196)
  );
  INV _n00197_836 (
    .I(DCORIFGr),
    .O(_n00197)
  );
  INV _n00198_837 (
    .I(DCOR0THRESLOWr),
    .O(_n00198)
  );
  AND2 _n00199_838 (
    .I0(Latch1r[13]),
    .I1(_n00195),
    .O(_n00199)
  );
  OR2 _n001910_839 (
    .I0(_n00194),
    .I1(_n00199),
    .O(_n001910)
  );
  AND2 _n001911_840 (
    .I0(_n001910),
    .I1(_n00196),
    .O(_n001911)
  );
  OR2 _n001912_841 (
    .I0(_n00193),
    .I1(_n001911),
    .O(_n001912)
  );
  AND2 _n001913_842 (
    .I0(_n001912),
    .I1(_n00197),
    .O(_n001913)
  );
  OR2 _n001914_843 (
    .I0(_n00192),
    .I1(_n001913),
    .O(_n001914)
  );
  AND2 _n001915_844 (
    .I0(_n001914),
    .I1(_n00198),
    .O(_n001915)
  );
  AND2 _n00171_845 (
    .I0(DCOR0THRESLOWr),
    .I1(Latch0r[6]),
    .O(_n00171)
  );
  AND2 _n00172_846 (
    .I0(DCORIFGr),
    .I1(NlwRenamedSig_OI_Tfound1),
    .O(_n00172)
  );
  AND2 _n00173_847 (
    .I0(DCOR0THRESHIGHr),
    .I1(Latch0r[14]),
    .O(_n00173)
  );
  AND2 _n00174_848 (
    .I0(DCOR1THRESLOWr),
    .I1(Latch1r[6]),
    .O(_n00174)
  );
  INV _n00175_849 (
    .I(DCOR1THRESLOWr),
    .O(_n00175)
  );
  INV _n00176_850 (
    .I(DCOR0THRESHIGHr),
    .O(_n00176)
  );
  INV _n00177_851 (
    .I(DCORIFGr),
    .O(_n00177)
  );
  INV _n00178_852 (
    .I(DCOR0THRESLOWr),
    .O(_n00178)
  );
  AND2 _n00179_853 (
    .I0(Latch1r[14]),
    .I1(_n00175),
    .O(_n00179)
  );
  OR2 _n001710_854 (
    .I0(_n00174),
    .I1(_n00179),
    .O(_n001710)
  );
  AND2 _n001711_855 (
    .I0(_n001710),
    .I1(_n00176),
    .O(_n001711)
  );
  OR2 _n001712_856 (
    .I0(_n00173),
    .I1(_n001711),
    .O(_n001712)
  );
  AND2 _n001713_857 (
    .I0(_n001712),
    .I1(_n00177),
    .O(_n001713)
  );
  OR2 _n001714_858 (
    .I0(_n00172),
    .I1(_n001713),
    .O(_n001714)
  );
  AND2 _n001715_859 (
    .I0(_n001714),
    .I1(_n00178),
    .O(_n001715)
  );
  AND2 _n00151_860 (
    .I0(DCOR0THRESLOWr),
    .I1(Latch0r[7]),
    .O(_n00151)
  );
  AND2 _n00152_861 (
    .I0(DCOR0THRESHIGHr),
    .I1(Latch0r[15]),
    .O(_n00152)
  );
  AND2 _n00153_862 (
    .I0(DCOR1THRESLOWr),
    .I1(Latch1r[7]),
    .O(_n00153)
  );
  INV _n00154_863 (
    .I(DCOR1THRESLOWr),
    .O(_n00154)
  );
  INV _n00155_864 (
    .I(DCOR0THRESHIGHr),
    .O(_n00155)
  );
  INV _n00156_865 (
    .I(DCOR0THRESLOWr),
    .O(_n00156)
  );
  AND2 _n00157_866 (
    .I0(Latch1r[15]),
    .I1(_n00154),
    .O(_n00157)
  );
  OR2 _n00158_867 (
    .I0(_n00153),
    .I1(_n00157),
    .O(_n00158)
  );
  AND2 _n00159_868 (
    .I0(_n00158),
    .I1(_n00155),
    .O(_n00159)
  );
  OR2 _n001510_869 (
    .I0(_n00152),
    .I1(_n00159),
    .O(_n001510)
  );
  AND2 _n001511_870 (
    .I0(_n001510),
    .I1(_n00156),
    .O(_n001511)
  );
  AND2 _n00121_871 (
    .I0(HE1stater),
    .I1(RF1r),
    .O(_n00121)
  );
  INV _n00122_872 (
    .I(HE1statelastr),
    .O(_n00122)
  );
  INV _n00123_873 (
    .I(HE1stater),
    .O(_n00123)
  );
  INV _n00124_874 (
    .I(RF1r),
    .O(_n00124)
  );
  INV _n00125_875 (
    .I(NlwRenamedSig_OI_Hfound1),
    .O(_n00125)
  );
  AND2 _n00126_876 (
    .I0(_n00121),
    .I1(_n00122),
    .O(_n00126)
  );
  AND3 _n00127_877 (
    .I0(_n00123),
    .I1(HE1statelastr),
    .I2(_n00124),
    .O(_n00127)
  );
  OR2 _n00128_878 (
    .I0(_n00126),
    .I1(_n00127),
    .O(_n00128)
  );
  AND2 _n00111_879 (
    .I0(HE0stater),
    .I1(RF0r),
    .O(_n00111)
  );
  INV _n00112_880 (
    .I(HE0statelastr),
    .O(_n00112)
  );
  INV _n00113_881 (
    .I(HE0stater),
    .O(_n00113)
  );
  INV _n00114_882 (
    .I(RF0r),
    .O(_n00114)
  );
  INV _n00115_883 (
    .I(NlwRenamedSig_OI_Hfound0),
    .O(_n00115)
  );
  AND2 _n00116_884 (
    .I0(_n00111),
    .I1(_n00112),
    .O(_n00116)
  );
  AND3 _n00117_885 (
    .I0(_n00113),
    .I1(HE0statelastr),
    .I2(_n00114),
    .O(_n00117)
  );
  OR2 _n00118_886 (
    .I0(_n00116),
    .I1(_n00117),
    .O(_n00118)
  );
  INV Zero1r_N13131_887 (
    .I(DCORIFGw),
    .O(Zero1r_N13131)
  );
  INV Zero1r_N13132_888 (
    .I(DCORENCCTLw),
    .O(Zero1r_N13132)
  );
  INV Zero1r_N13133_889 (
    .I(Reset),
    .O(Zero1r_N13133)
  );
  INV Latch1r_8__n00001_890 (
    .I(Reset),
    .O(Latch1r_8__n00001)
  );
  INV Latch0r_9__n00001_891 (
    .I(Reset),
    .O(Latch0r_9__n00001)
  );
  INV Latch1r_9__n00001_892 (
    .I(Reset),
    .O(Latch1r_9__n00001)
  );
  INV Latch1r_3__n00001_893 (
    .I(Reset),
    .O(Latch1r_3__n00001)
  );
  INV Hfound0r__n00001_894 (
    .I(inDATA[2]),
    .O(Hfound0r__n00001)
  );
  INV Hfound0r__n00002_895 (
    .I(DCORIFGw),
    .O(Hfound0r__n00002)
  );
  INV Hfound0r__n00003_896 (
    .I(Reset),
    .O(Hfound0r__n00003)
  );
  AND2 Hfound0r__n00004_897 (
    .I0(NlwRenamedSig_OI_Hfound0),
    .I1(Hfound0r__n00001),
    .O(Hfound0r__n00004)
  );
  OR2 Hfound0r__n00005_898 (
    .I0(Hfound0r__n00004),
    .I1(Hfound0r__n00002),
    .O(Hfound0r__n00005)
  );
  INV Hfound1r__n00001_899 (
    .I(inDATA[3]),
    .O(Hfound1r__n00001)
  );
  INV Hfound1r__n00002_900 (
    .I(DCORIFGw),
    .O(Hfound1r__n00002)
  );
  INV Hfound1r__n00003_901 (
    .I(Reset),
    .O(Hfound1r__n00003)
  );
  AND2 Hfound1r__n00004_902 (
    .I0(NlwRenamedSig_OI_Hfound1),
    .I1(Hfound1r__n00001),
    .O(Hfound1r__n00004)
  );
  OR2 Hfound1r__n00005_903 (
    .I0(Hfound1r__n00004),
    .I1(Hfound1r__n00002),
    .O(Hfound1r__n00005)
  );
  INV _n00071_904 (
    .I(inDATA[5]),
    .O(_n00071)
  );
  INV _n00072_905 (
    .I(DCORIFGw),
    .O(_n00072)
  );
  AND2 _n00073_906 (
    .I0(NlwRenamedSig_OI_Tfound0),
    .I1(_n00071),
    .O(_n00073)
  );
  INV _n00091_907 (
    .I(inDATA[6]),
    .O(_n00091)
  );
  INV _n00092_908 (
    .I(DCORIFGw),
    .O(_n00092)
  );
  AND2 _n00093_909 (
    .I0(NlwRenamedSig_OI_Tfound1),
    .I1(_n00091),
    .O(_n00093)
  );
  INV Latch1r_1__n00001_910 (
    .I(Reset),
    .O(Latch1r_1__n00001)
  );
  INV Latch0r_3__n00001_911 (
    .I(Reset),
    .O(Latch0r_3__n00001)
  );
  INV Latch0r_15__n00001_912 (
    .I(Reset),
    .O(Latch0r_15__n00001)
  );
  INV Latch0r_7__n00001_913 (
    .I(Reset),
    .O(Latch0r_7__n00001)
  );
  INV Latch1r_11__n00001_914 (
    .I(Reset),
    .O(Latch1r_11__n00001)
  );
  INV Latch0r_2__n00001_915 (
    .I(Reset),
    .O(Latch0r_2__n00001)
  );
  INV Latch1r_14__n00001_916 (
    .I(Reset),
    .O(Latch1r_14__n00001)
  );
  INV Latch1r_2__n00001_917 (
    .I(Reset),
    .O(Latch1r_2__n00001)
  );
  INV sense1r__n00021_918 (
    .I(DCORENCCTLw),
    .O(sense1r__n00021)
  );
  INV sense1r__n00022_919 (
    .I(Reset),
    .O(sense1r__n00022)
  );
  AND2 sense1r__n00023_920 (
    .I0(sense1r__n00021),
    .I1(sense1r__n00022),
    .O(sense1r__n00023)
  );
  INV sense1r__n00001_921 (
    .I(Reset),
    .O(sense1r__n00001)
  );
  INV Latch1r_4__n00001_922 (
    .I(Reset),
    .O(Latch1r_4__n00001)
  );
  INV LatchEdge1r__n00001_923 (
    .I(Reset),
    .O(LatchEdge1r__n00001)
  );
  INV Latch1r_7__n00001_924 (
    .I(Reset),
    .O(Latch1r_7__n00001)
  );
  INV E1r__n00001_925 (
    .I(Reset),
    .O(E1r__n00001)
  );
  INV Latch0r_5__n00001_926 (
    .I(Reset),
    .O(Latch0r_5__n00001)
  );
  INV RF1r__n00001_927 (
    .I(Reset),
    .O(RF1r__n00001)
  );
  INV Latch0r_0__n00001_928 (
    .I(Reset),
    .O(Latch0r_0__n00001)
  );
  INV Latch0r_13__n00001_929 (
    .I(Reset),
    .O(Latch0r_13__n00001)
  );
  INV sense0r__n00001_930 (
    .I(Reset),
    .O(sense0r__n00001)
  );
  INV Latch1r_6__n00001_931 (
    .I(Reset),
    .O(Latch1r_6__n00001)
  );
  INV LatchEdge0r__n00001_932 (
    .I(Reset),
    .O(LatchEdge0r__n00001)
  );
  INV Latch0r_4__n00001_933 (
    .I(Reset),
    .O(Latch0r_4__n00001)
  );
  INV Latch0r_10__n00001_934 (
    .I(Reset),
    .O(Latch0r_10__n00001)
  );
  INV E0r__n00001_935 (
    .I(Reset),
    .O(E0r__n00001)
  );
  INV Latch1r_5__n00001_936 (
    .I(Reset),
    .O(Latch1r_5__n00001)
  );
  INV RF0r__n00001_937 (
    .I(Reset),
    .O(RF0r__n00001)
  );
endmodule

module Holdreg (
  DCOR0CNTLOWr, DCOR1CNTHIGHr, Reset, DCOR0CNTHIGHr, Sclk, DCOR1CNTLOWr, ASleading, ch0in, ch1in, outDATA
);
  input DCOR0CNTLOWr;
  input DCOR1CNTHIGHr;
  input Reset;
  input DCOR0CNTHIGHr;
  input Sclk;
  input DCOR1CNTLOWr;
  input ASleading;
  input [15 : 0] ch0in;
  input [15 : 0] ch1in;
  output [7 : 0] outDATA;
  wire _n0002;
  wire _n0003;
  wire holdingreg0_12__n0000;
  wire N12334;
  wire holdingreg1_5__n0000;
  wire holdingreg0_11__n0000;
  wire holdingreg1_0__n0000;
  wire holdingreg0_2__n0000;
  wire holdingreg1_10__n0000;
  wire holdingreg0_1__n0000;
  wire holdingreg0_9__n0000;
  wire holdingreg1_12__n0000;
  wire holdingreg1_15__n0003;
  wire holdingreg0_14__n0000;
  wire holdingreg1_11__n0000;
  wire holdingreg1_14__n0000;
  wire holdingreg0_0__n0002;
  wire holdingreg0_6__n0000;
  wire holdingreg0_10__n0000;
  wire holdingreg1_1__n0000;
  wire holdingreg1_2__n0000;
  wire holdingreg1_6__n0000;
  wire holdingreg1_3__n0000;
  wire holdingreg1_7__n0000;
  wire holdingreg1_8__n0000;
  wire holdingreg0_8__n0000;
  wire holdingreg0_4__n0000;
  wire holdingreg1_15__n0000;
  wire holdingreg0_15__n0000;
  wire holdingreg0_5__n0000;
  wire holdingreg0_7__n0000;
  wire holdingreg0_13__n0000;
  wire holdingreg0_0__n0000;
  wire holdingreg0_3__n0000;
  wire holdingreg1_13__n0000;
  wire holdingreg1_4__n0000;
  wire holdingreg1_9__n0000;
  wire _n00021;
  wire _n00022;
  wire _n00023;
  wire _n00024;
  wire _n0000_0_1;
  wire _n0000_0_2;
  wire _n0000_0_3;
  wire _n0000_0_4;
  wire _n0000_0_5;
  wire _n0000_0_6;
  wire _n0000_0_7;
  wire _n0000_0_8;
  wire _n0000_0_9;
  wire _n0000_0_10;
  wire _n0000_0_11;
  wire _n0000_1_1;
  wire _n0000_1_2;
  wire _n0000_1_3;
  wire _n0000_1_4;
  wire _n0000_1_5;
  wire _n0000_1_6;
  wire _n0000_1_7;
  wire _n0000_1_8;
  wire _n0000_1_9;
  wire _n0000_1_10;
  wire _n0000_1_11;
  wire _n0000_2_1;
  wire _n0000_2_2;
  wire _n0000_2_3;
  wire _n0000_2_4;
  wire _n0000_2_5;
  wire _n0000_2_6;
  wire _n0000_2_7;
  wire _n0000_2_8;
  wire _n0000_2_9;
  wire _n0000_2_10;
  wire _n0000_2_11;
  wire holdingreg0_0__n00021;
  wire holdingreg0_0__n00022;
  wire holdingreg0_0__n00023;
  wire holdingreg1_0__n00001;
  wire _n0000_7_1;
  wire _n0000_7_2;
  wire _n0000_7_3;
  wire _n0000_7_4;
  wire _n0000_7_5;
  wire _n0000_7_6;
  wire _n0000_7_7;
  wire _n0000_7_8;
  wire _n0000_7_9;
  wire _n0000_7_10;
  wire _n0000_7_11;
  wire _n0000_6_1;
  wire _n0000_6_2;
  wire _n0000_6_3;
  wire _n0000_6_4;
  wire _n0000_6_5;
  wire _n0000_6_6;
  wire _n0000_6_7;
  wire _n0000_6_8;
  wire _n0000_6_9;
  wire _n0000_6_10;
  wire _n0000_6_11;
  wire _n0000_5_1;
  wire _n0000_5_2;
  wire _n0000_5_3;
  wire _n0000_5_4;
  wire _n0000_5_5;
  wire _n0000_5_6;
  wire _n0000_5_7;
  wire _n0000_5_8;
  wire _n0000_5_9;
  wire _n0000_5_10;
  wire _n0000_5_11;
  wire _n0000_4_1;
  wire _n0000_4_2;
  wire _n0000_4_3;
  wire _n0000_4_4;
  wire _n0000_4_5;
  wire _n0000_4_6;
  wire _n0000_4_7;
  wire _n0000_4_8;
  wire _n0000_4_9;
  wire _n0000_4_10;
  wire _n0000_4_11;
  wire _n0000_3_1;
  wire _n0000_3_2;
  wire _n0000_3_3;
  wire _n0000_3_4;
  wire _n0000_3_5;
  wire _n0000_3_6;
  wire _n0000_3_7;
  wire _n0000_3_8;
  wire _n0000_3_9;
  wire _n0000_3_10;
  wire _n0000_3_11;
  wire holdingreg1_15__n00001;
  wire holdingreg0_12__n00001;
  wire holdingreg0_2__n00001;
  wire holdingreg1_14__n00001;
  wire holdingreg0_9__n00001;
  wire holdingreg1_13__n00001;
  wire holdingreg1_12__n00001;
  wire holdingreg0_13__n00001;
  wire holdingreg0_3__n00001;
  wire holdingreg1_11__n00001;
  wire holdingreg0_7__n00001;
  wire holdingreg0_8__n00001;
  wire holdingreg1_10__n00001;
  wire holdingreg1_9__n00001;
  wire holdingreg0_14__n00001;
  wire holdingreg0_4__n00001;
  wire holdingreg1_8__n00001;
  wire holdingreg0_10__n00001;
  wire holdingreg1_7__n00001;
  wire holdingreg1_6__n00001;
  wire holdingreg0_0__n00001;
  wire holdingreg0_5__n00001;
  wire holdingreg1_5__n00001;
  wire holdingreg0_15__n00001;
  wire holdingreg1_4__n00001;
  wire holdingreg1_3__n00001;
  wire holdingreg0_11__n00001;
  wire holdingreg1_2__n00001;
  wire holdingreg0_1__n00001;
  wire holdingreg1_1__n00001;
  wire holdingreg0_6__n00001;
  wire [15 : 0] holdingreg0;
  wire [15 : 0] holdingreg1;
  wire [7 : 0] interDATA;
  wire [7 : 0] _n0000;
  assign
    outDATA[7] = interDATA[7],
    outDATA[6] = interDATA[6],
    outDATA[5] = interDATA[5],
    outDATA[4] = interDATA[4],
    outDATA[3] = interDATA[3],
    outDATA[2] = interDATA[2],
    outDATA[1] = interDATA[1],
    outDATA[0] = interDATA[0];
  BUFE I2_7 (
    .E(_n0003),
    .I(_n0000[7]),
    .O(interDATA[7])
  );
  INV _n00031 (
    .I(_n0002),
    .O(_n0003)
  );
  AND4 _n00025 (
    .I0(_n00021),
    .I1(_n00022),
    .I2(_n00023),
    .I3(_n00024),
    .O(_n0002)
  );
  OR2 _n0000_0_12 (
    .I0(_n0000_0_1),
    .I1(_n0000_0_11),
    .O(_n0000[0])
  );
  OR2 _n0000_1_12 (
    .I0(_n0000_1_1),
    .I1(_n0000_1_11),
    .O(_n0000[1])
  );
  OR2 _n0000_2_12 (
    .I0(_n0000_2_1),
    .I1(_n0000_2_11),
    .O(_n0000[2])
  );
  INV holdingreg0_0__n00024 (
    .I(holdingreg0_0__n00023),
    .O(holdingreg0_0__n0002)
  );
  AND2 holdingreg1_0__n00002 (
    .I0(ch1in[0]),
    .I1(holdingreg1_0__n00001),
    .O(holdingreg1_0__n0000)
  );
  OR2 _n0000_7_12 (
    .I0(_n0000_7_1),
    .I1(_n0000_7_11),
    .O(_n0000[7])
  );
  OR2 _n0000_6_12 (
    .I0(_n0000_6_1),
    .I1(_n0000_6_11),
    .O(_n0000[6])
  );
  OR2 _n0000_5_12 (
    .I0(_n0000_5_1),
    .I1(_n0000_5_11),
    .O(_n0000[5])
  );
  OR2 _n0000_4_12 (
    .I0(_n0000_4_1),
    .I1(_n0000_4_11),
    .O(_n0000[4])
  );
  OR2 _n0000_3_12 (
    .I0(_n0000_3_1),
    .I1(_n0000_3_11),
    .O(_n0000[3])
  );
  BUFE I2_0 (
    .E(_n0003),
    .I(_n0000[0]),
    .O(interDATA[0])
  );
  BUFE I2_1 (
    .E(_n0003),
    .I(_n0000[1]),
    .O(interDATA[1])
  );
  BUFE I2_2 (
    .E(_n0003),
    .I(_n0000[2]),
    .O(interDATA[2])
  );
  BUFE I2_3 (
    .E(_n0003),
    .I(_n0000[3]),
    .O(interDATA[3])
  );
  BUFE I2_4 (
    .E(_n0003),
    .I(_n0000[4]),
    .O(interDATA[4])
  );
  BUFE I2_5 (
    .E(_n0003),
    .I(_n0000[5]),
    .O(interDATA[5])
  );
  BUFE I2_6 (
    .E(_n0003),
    .I(_n0000[6]),
    .O(interDATA[6])
  );
  FDCE holdingreg1_15 (
    .D(holdingreg1_15__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg1[15])
  );
  FDCE holdingreg1_14 (
    .D(holdingreg1_14__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg1[14])
  );
  FDCE holdingreg1_0 (
    .D(holdingreg1_0__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg1[0])
  );
  FDCE holdingreg1_1 (
    .D(holdingreg1_1__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg1[1])
  );
  FDCE holdingreg1_2 (
    .D(holdingreg1_2__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg1[2])
  );
  FDCE holdingreg1_3 (
    .D(holdingreg1_3__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg1[3])
  );
  FDCE holdingreg1_4 (
    .D(holdingreg1_4__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg1[4])
  );
  FDCE holdingreg1_5 (
    .D(holdingreg1_5__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg1[5])
  );
  FDCE holdingreg1_6 (
    .D(holdingreg1_6__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg1[6])
  );
  FDCE holdingreg1_7 (
    .D(holdingreg1_7__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg1[7])
  );
  FDCE holdingreg1_8 (
    .D(holdingreg1_8__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg1[8])
  );
  FDCE holdingreg1_9 (
    .D(holdingreg1_9__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg1[9])
  );
  FDCE holdingreg1_10 (
    .D(holdingreg1_10__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg1[10])
  );
  FDCE holdingreg1_11 (
    .D(holdingreg1_11__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg1[11])
  );
  FDCE holdingreg1_12 (
    .D(holdingreg1_12__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg1[12])
  );
  FDCE holdingreg1_13 (
    .D(holdingreg1_13__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg1[13])
  );
  INV holdingreg1_15__n00031 (
    .I(Sclk),
    .O(holdingreg1_15__n0003)
  );
  FDCE holdingreg0_12 (
    .D(holdingreg0_12__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg0[12])
  );
  AND2 holdingreg1_15__n00002 (
    .I0(ch1in[15]),
    .I1(holdingreg1_15__n00001),
    .O(holdingreg1_15__n0000)
  );
  GND XST_GND (
    .G(N12334)
  );
  AND2 holdingreg0_12__n00002 (
    .I0(ch0in[12]),
    .I1(holdingreg0_12__n00001),
    .O(holdingreg0_12__n0000)
  );
  AND2 holdingreg0_2__n00002 (
    .I0(ch0in[2]),
    .I1(holdingreg0_2__n00001),
    .O(holdingreg0_2__n0000)
  );
  AND2 holdingreg1_14__n00002 (
    .I0(ch1in[14]),
    .I1(holdingreg1_14__n00001),
    .O(holdingreg1_14__n0000)
  );
  AND2 holdingreg0_9__n00002 (
    .I0(ch0in[9]),
    .I1(holdingreg0_9__n00001),
    .O(holdingreg0_9__n0000)
  );
  FDCE holdingreg0_7 (
    .D(holdingreg0_7__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg0[7])
  );
  AND2 holdingreg1_13__n00002 (
    .I0(ch1in[13]),
    .I1(holdingreg1_13__n00001),
    .O(holdingreg1_13__n0000)
  );
  FDCE holdingreg0_9 (
    .D(holdingreg0_9__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg0[9])
  );
  FDCE holdingreg0_14 (
    .D(holdingreg0_14__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg0[14])
  );
  AND2 holdingreg1_12__n00002 (
    .I0(ch1in[12]),
    .I1(holdingreg1_12__n00001),
    .O(holdingreg1_12__n0000)
  );
  AND2 holdingreg0_13__n00002 (
    .I0(ch0in[13]),
    .I1(holdingreg0_13__n00001),
    .O(holdingreg0_13__n0000)
  );
  AND2 holdingreg0_3__n00002 (
    .I0(ch0in[3]),
    .I1(holdingreg0_3__n00001),
    .O(holdingreg0_3__n0000)
  );
  AND2 holdingreg1_11__n00002 (
    .I0(ch1in[11]),
    .I1(holdingreg1_11__n00001),
    .O(holdingreg1_11__n0000)
  );
  AND2 holdingreg0_7__n00002 (
    .I0(ch0in[7]),
    .I1(holdingreg0_7__n00001),
    .O(holdingreg0_7__n0000)
  );
  AND2 holdingreg0_8__n00002 (
    .I0(ch0in[8]),
    .I1(holdingreg0_8__n00001),
    .O(holdingreg0_8__n0000)
  );
  AND2 holdingreg1_10__n00002 (
    .I0(ch1in[10]),
    .I1(holdingreg1_10__n00001),
    .O(holdingreg1_10__n0000)
  );
  FDCE holdingreg0_10 (
    .D(holdingreg0_10__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg0[10])
  );
  FDCE holdingreg0_0 (
    .D(holdingreg0_0__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg0[0])
  );
  AND2 holdingreg1_9__n00002 (
    .I0(ch1in[9]),
    .I1(holdingreg1_9__n00001),
    .O(holdingreg1_9__n0000)
  );
  AND2 holdingreg0_14__n00002 (
    .I0(ch0in[14]),
    .I1(holdingreg0_14__n00001),
    .O(holdingreg0_14__n0000)
  );
  AND2 holdingreg0_4__n00002 (
    .I0(ch0in[4]),
    .I1(holdingreg0_4__n00001),
    .O(holdingreg0_4__n0000)
  );
  AND2 holdingreg1_8__n00002 (
    .I0(ch1in[8]),
    .I1(holdingreg1_8__n00001),
    .O(holdingreg1_8__n0000)
  );
  FDCE holdingreg0_3 (
    .D(holdingreg0_3__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg0[3])
  );
  AND2 holdingreg0_10__n00002 (
    .I0(ch0in[10]),
    .I1(holdingreg0_10__n00001),
    .O(holdingreg0_10__n0000)
  );
  AND2 holdingreg1_7__n00002 (
    .I0(ch1in[7]),
    .I1(holdingreg1_7__n00001),
    .O(holdingreg1_7__n0000)
  );
  FDCE holdingreg0_11 (
    .D(holdingreg0_11__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg0[11])
  );
  FDCE holdingreg0_1 (
    .D(holdingreg0_1__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg0[1])
  );
  AND2 holdingreg1_6__n00002 (
    .I0(ch1in[6]),
    .I1(holdingreg1_6__n00001),
    .O(holdingreg1_6__n0000)
  );
  AND2 holdingreg0_0__n00002 (
    .I0(ch0in[0]),
    .I1(holdingreg0_0__n00001),
    .O(holdingreg0_0__n0000)
  );
  AND2 holdingreg0_5__n00002 (
    .I0(ch0in[5]),
    .I1(holdingreg0_5__n00001),
    .O(holdingreg0_5__n0000)
  );
  AND2 holdingreg1_5__n00002 (
    .I0(ch1in[5]),
    .I1(holdingreg1_5__n00001),
    .O(holdingreg1_5__n0000)
  );
  AND2 holdingreg0_15__n00002 (
    .I0(ch0in[15]),
    .I1(holdingreg0_15__n00001),
    .O(holdingreg0_15__n0000)
  );
  FDCE holdingreg0_6 (
    .D(holdingreg0_6__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg0[6])
  );
  AND2 holdingreg1_4__n00002 (
    .I0(ch1in[4]),
    .I1(holdingreg1_4__n00001),
    .O(holdingreg1_4__n0000)
  );
  FDCE holdingreg0_5 (
    .D(holdingreg0_5__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg0[5])
  );
  FDCE holdingreg0_2 (
    .D(holdingreg0_2__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg0[2])
  );
  AND2 holdingreg1_3__n00002 (
    .I0(ch1in[3]),
    .I1(holdingreg1_3__n00001),
    .O(holdingreg1_3__n0000)
  );
  AND2 holdingreg0_11__n00002 (
    .I0(ch0in[11]),
    .I1(holdingreg0_11__n00001),
    .O(holdingreg0_11__n0000)
  );
  FDCE holdingreg0_13 (
    .D(holdingreg0_13__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg0[13])
  );
  AND2 holdingreg1_2__n00002 (
    .I0(ch1in[2]),
    .I1(holdingreg1_2__n00001),
    .O(holdingreg1_2__n0000)
  );
  FDCE holdingreg0_4 (
    .D(holdingreg0_4__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg0[4])
  );
  AND2 holdingreg0_1__n00002 (
    .I0(ch0in[1]),
    .I1(holdingreg0_1__n00001),
    .O(holdingreg0_1__n0000)
  );
  AND2 holdingreg1_1__n00002 (
    .I0(ch1in[1]),
    .I1(holdingreg1_1__n00001),
    .O(holdingreg1_1__n0000)
  );
  FDCE holdingreg0_8 (
    .D(holdingreg0_8__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg0[8])
  );
  AND2 holdingreg0_6__n00002 (
    .I0(ch0in[6]),
    .I1(holdingreg0_6__n00001),
    .O(holdingreg0_6__n0000)
  );
  FDCE holdingreg0_15 (
    .D(holdingreg0_15__n0000),
    .CE(holdingreg0_0__n0002),
    .CLR(N12334),
    .C(holdingreg1_15__n0003),
    .Q(holdingreg0[15])
  );
  INV _n00021_1143 (
    .I(DCOR1CNTHIGHr),
    .O(_n00021)
  );
  INV _n00022_1144 (
    .I(DCOR0CNTHIGHr),
    .O(_n00022)
  );
  INV _n00023_1145 (
    .I(DCOR1CNTLOWr),
    .O(_n00023)
  );
  INV _n00024_1146 (
    .I(DCOR0CNTLOWr),
    .O(_n00024)
  );
  AND2 _n0000_0_1_1147 (
    .I0(DCOR0CNTLOWr),
    .I1(holdingreg0[0]),
    .O(_n0000_0_1)
  );
  AND2 _n0000_0_2_1148 (
    .I0(DCOR1CNTLOWr),
    .I1(holdingreg1[0]),
    .O(_n0000_0_2)
  );
  AND2 _n0000_0_3_1149 (
    .I0(DCOR0CNTHIGHr),
    .I1(holdingreg0[8]),
    .O(_n0000_0_3)
  );
  INV _n0000_0_4_1150 (
    .I(DCOR0CNTHIGHr),
    .O(_n0000_0_4)
  );
  INV _n0000_0_5_1151 (
    .I(DCOR1CNTLOWr),
    .O(_n0000_0_5)
  );
  INV _n0000_0_6_1152 (
    .I(DCOR0CNTLOWr),
    .O(_n0000_0_6)
  );
  AND2 _n0000_0_7_1153 (
    .I0(holdingreg1[8]),
    .I1(_n0000_0_4),
    .O(_n0000_0_7)
  );
  OR2 _n0000_0_8_1154 (
    .I0(_n0000_0_3),
    .I1(_n0000_0_7),
    .O(_n0000_0_8)
  );
  AND2 _n0000_0_9_1155 (
    .I0(_n0000_0_8),
    .I1(_n0000_0_5),
    .O(_n0000_0_9)
  );
  OR2 _n0000_0_10_1156 (
    .I0(_n0000_0_2),
    .I1(_n0000_0_9),
    .O(_n0000_0_10)
  );
  AND2 _n0000_0_11_1157 (
    .I0(_n0000_0_10),
    .I1(_n0000_0_6),
    .O(_n0000_0_11)
  );
  AND2 _n0000_1_1_1158 (
    .I0(DCOR0CNTLOWr),
    .I1(holdingreg0[1]),
    .O(_n0000_1_1)
  );
  AND2 _n0000_1_2_1159 (
    .I0(DCOR1CNTLOWr),
    .I1(holdingreg1[1]),
    .O(_n0000_1_2)
  );
  AND2 _n0000_1_3_1160 (
    .I0(DCOR0CNTHIGHr),
    .I1(holdingreg0[9]),
    .O(_n0000_1_3)
  );
  INV _n0000_1_4_1161 (
    .I(DCOR0CNTHIGHr),
    .O(_n0000_1_4)
  );
  INV _n0000_1_5_1162 (
    .I(DCOR1CNTLOWr),
    .O(_n0000_1_5)
  );
  INV _n0000_1_6_1163 (
    .I(DCOR0CNTLOWr),
    .O(_n0000_1_6)
  );
  AND2 _n0000_1_7_1164 (
    .I0(holdingreg1[9]),
    .I1(_n0000_1_4),
    .O(_n0000_1_7)
  );
  OR2 _n0000_1_8_1165 (
    .I0(_n0000_1_3),
    .I1(_n0000_1_7),
    .O(_n0000_1_8)
  );
  AND2 _n0000_1_9_1166 (
    .I0(_n0000_1_8),
    .I1(_n0000_1_5),
    .O(_n0000_1_9)
  );
  OR2 _n0000_1_10_1167 (
    .I0(_n0000_1_2),
    .I1(_n0000_1_9),
    .O(_n0000_1_10)
  );
  AND2 _n0000_1_11_1168 (
    .I0(_n0000_1_10),
    .I1(_n0000_1_6),
    .O(_n0000_1_11)
  );
  AND2 _n0000_2_1_1169 (
    .I0(DCOR0CNTLOWr),
    .I1(holdingreg0[2]),
    .O(_n0000_2_1)
  );
  AND2 _n0000_2_2_1170 (
    .I0(DCOR1CNTLOWr),
    .I1(holdingreg1[2]),
    .O(_n0000_2_2)
  );
  AND2 _n0000_2_3_1171 (
    .I0(DCOR0CNTHIGHr),
    .I1(holdingreg0[10]),
    .O(_n0000_2_3)
  );
  INV _n0000_2_4_1172 (
    .I(DCOR0CNTHIGHr),
    .O(_n0000_2_4)
  );
  INV _n0000_2_5_1173 (
    .I(DCOR1CNTLOWr),
    .O(_n0000_2_5)
  );
  INV _n0000_2_6_1174 (
    .I(DCOR0CNTLOWr),
    .O(_n0000_2_6)
  );
  AND2 _n0000_2_7_1175 (
    .I0(holdingreg1[10]),
    .I1(_n0000_2_4),
    .O(_n0000_2_7)
  );
  OR2 _n0000_2_8_1176 (
    .I0(_n0000_2_3),
    .I1(_n0000_2_7),
    .O(_n0000_2_8)
  );
  AND2 _n0000_2_9_1177 (
    .I0(_n0000_2_8),
    .I1(_n0000_2_5),
    .O(_n0000_2_9)
  );
  OR2 _n0000_2_10_1178 (
    .I0(_n0000_2_2),
    .I1(_n0000_2_9),
    .O(_n0000_2_10)
  );
  AND2 _n0000_2_11_1179 (
    .I0(_n0000_2_10),
    .I1(_n0000_2_6),
    .O(_n0000_2_11)
  );
  INV holdingreg0_0__n00021_1180 (
    .I(ASleading),
    .O(holdingreg0_0__n00021)
  );
  INV holdingreg0_0__n00022_1181 (
    .I(Reset),
    .O(holdingreg0_0__n00022)
  );
  AND2 holdingreg0_0__n00023_1182 (
    .I0(holdingreg0_0__n00021),
    .I1(holdingreg0_0__n00022),
    .O(holdingreg0_0__n00023)
  );
  INV holdingreg1_0__n00001_1183 (
    .I(Reset),
    .O(holdingreg1_0__n00001)
  );
  AND2 _n0000_7_1_1184 (
    .I0(DCOR0CNTLOWr),
    .I1(holdingreg0[7]),
    .O(_n0000_7_1)
  );
  AND2 _n0000_7_2_1185 (
    .I0(DCOR1CNTLOWr),
    .I1(holdingreg1[7]),
    .O(_n0000_7_2)
  );
  AND2 _n0000_7_3_1186 (
    .I0(DCOR0CNTHIGHr),
    .I1(holdingreg0[15]),
    .O(_n0000_7_3)
  );
  INV _n0000_7_4_1187 (
    .I(DCOR0CNTHIGHr),
    .O(_n0000_7_4)
  );
  INV _n0000_7_5_1188 (
    .I(DCOR1CNTLOWr),
    .O(_n0000_7_5)
  );
  INV _n0000_7_6_1189 (
    .I(DCOR0CNTLOWr),
    .O(_n0000_7_6)
  );
  AND2 _n0000_7_7_1190 (
    .I0(holdingreg1[15]),
    .I1(_n0000_7_4),
    .O(_n0000_7_7)
  );
  OR2 _n0000_7_8_1191 (
    .I0(_n0000_7_3),
    .I1(_n0000_7_7),
    .O(_n0000_7_8)
  );
  AND2 _n0000_7_9_1192 (
    .I0(_n0000_7_8),
    .I1(_n0000_7_5),
    .O(_n0000_7_9)
  );
  OR2 _n0000_7_10_1193 (
    .I0(_n0000_7_2),
    .I1(_n0000_7_9),
    .O(_n0000_7_10)
  );
  AND2 _n0000_7_11_1194 (
    .I0(_n0000_7_10),
    .I1(_n0000_7_6),
    .O(_n0000_7_11)
  );
  AND2 _n0000_6_1_1195 (
    .I0(DCOR0CNTLOWr),
    .I1(holdingreg0[6]),
    .O(_n0000_6_1)
  );
  AND2 _n0000_6_2_1196 (
    .I0(DCOR1CNTLOWr),
    .I1(holdingreg1[6]),
    .O(_n0000_6_2)
  );
  AND2 _n0000_6_3_1197 (
    .I0(DCOR0CNTHIGHr),
    .I1(holdingreg0[14]),
    .O(_n0000_6_3)
  );
  INV _n0000_6_4_1198 (
    .I(DCOR0CNTHIGHr),
    .O(_n0000_6_4)
  );
  INV _n0000_6_5_1199 (
    .I(DCOR1CNTLOWr),
    .O(_n0000_6_5)
  );
  INV _n0000_6_6_1200 (
    .I(DCOR0CNTLOWr),
    .O(_n0000_6_6)
  );
  AND2 _n0000_6_7_1201 (
    .I0(holdingreg1[14]),
    .I1(_n0000_6_4),
    .O(_n0000_6_7)
  );
  OR2 _n0000_6_8_1202 (
    .I0(_n0000_6_3),
    .I1(_n0000_6_7),
    .O(_n0000_6_8)
  );
  AND2 _n0000_6_9_1203 (
    .I0(_n0000_6_8),
    .I1(_n0000_6_5),
    .O(_n0000_6_9)
  );
  OR2 _n0000_6_10_1204 (
    .I0(_n0000_6_2),
    .I1(_n0000_6_9),
    .O(_n0000_6_10)
  );
  AND2 _n0000_6_11_1205 (
    .I0(_n0000_6_10),
    .I1(_n0000_6_6),
    .O(_n0000_6_11)
  );
  AND2 _n0000_5_1_1206 (
    .I0(DCOR0CNTLOWr),
    .I1(holdingreg0[5]),
    .O(_n0000_5_1)
  );
  AND2 _n0000_5_2_1207 (
    .I0(DCOR1CNTLOWr),
    .I1(holdingreg1[5]),
    .O(_n0000_5_2)
  );
  AND2 _n0000_5_3_1208 (
    .I0(DCOR0CNTHIGHr),
    .I1(holdingreg0[13]),
    .O(_n0000_5_3)
  );
  INV _n0000_5_4_1209 (
    .I(DCOR0CNTHIGHr),
    .O(_n0000_5_4)
  );
  INV _n0000_5_5_1210 (
    .I(DCOR1CNTLOWr),
    .O(_n0000_5_5)
  );
  INV _n0000_5_6_1211 (
    .I(DCOR0CNTLOWr),
    .O(_n0000_5_6)
  );
  AND2 _n0000_5_7_1212 (
    .I0(holdingreg1[13]),
    .I1(_n0000_5_4),
    .O(_n0000_5_7)
  );
  OR2 _n0000_5_8_1213 (
    .I0(_n0000_5_3),
    .I1(_n0000_5_7),
    .O(_n0000_5_8)
  );
  AND2 _n0000_5_9_1214 (
    .I0(_n0000_5_8),
    .I1(_n0000_5_5),
    .O(_n0000_5_9)
  );
  OR2 _n0000_5_10_1215 (
    .I0(_n0000_5_2),
    .I1(_n0000_5_9),
    .O(_n0000_5_10)
  );
  AND2 _n0000_5_11_1216 (
    .I0(_n0000_5_10),
    .I1(_n0000_5_6),
    .O(_n0000_5_11)
  );
  AND2 _n0000_4_1_1217 (
    .I0(DCOR0CNTLOWr),
    .I1(holdingreg0[4]),
    .O(_n0000_4_1)
  );
  AND2 _n0000_4_2_1218 (
    .I0(DCOR1CNTLOWr),
    .I1(holdingreg1[4]),
    .O(_n0000_4_2)
  );
  AND2 _n0000_4_3_1219 (
    .I0(DCOR0CNTHIGHr),
    .I1(holdingreg0[12]),
    .O(_n0000_4_3)
  );
  INV _n0000_4_4_1220 (
    .I(DCOR0CNTHIGHr),
    .O(_n0000_4_4)
  );
  INV _n0000_4_5_1221 (
    .I(DCOR1CNTLOWr),
    .O(_n0000_4_5)
  );
  INV _n0000_4_6_1222 (
    .I(DCOR0CNTLOWr),
    .O(_n0000_4_6)
  );
  AND2 _n0000_4_7_1223 (
    .I0(holdingreg1[12]),
    .I1(_n0000_4_4),
    .O(_n0000_4_7)
  );
  OR2 _n0000_4_8_1224 (
    .I0(_n0000_4_3),
    .I1(_n0000_4_7),
    .O(_n0000_4_8)
  );
  AND2 _n0000_4_9_1225 (
    .I0(_n0000_4_8),
    .I1(_n0000_4_5),
    .O(_n0000_4_9)
  );
  OR2 _n0000_4_10_1226 (
    .I0(_n0000_4_2),
    .I1(_n0000_4_9),
    .O(_n0000_4_10)
  );
  AND2 _n0000_4_11_1227 (
    .I0(_n0000_4_10),
    .I1(_n0000_4_6),
    .O(_n0000_4_11)
  );
  AND2 _n0000_3_1_1228 (
    .I0(DCOR0CNTLOWr),
    .I1(holdingreg0[3]),
    .O(_n0000_3_1)
  );
  AND2 _n0000_3_2_1229 (
    .I0(DCOR1CNTLOWr),
    .I1(holdingreg1[3]),
    .O(_n0000_3_2)
  );
  AND2 _n0000_3_3_1230 (
    .I0(DCOR0CNTHIGHr),
    .I1(holdingreg0[11]),
    .O(_n0000_3_3)
  );
  INV _n0000_3_4_1231 (
    .I(DCOR0CNTHIGHr),
    .O(_n0000_3_4)
  );
  INV _n0000_3_5_1232 (
    .I(DCOR1CNTLOWr),
    .O(_n0000_3_5)
  );
  INV _n0000_3_6_1233 (
    .I(DCOR0CNTLOWr),
    .O(_n0000_3_6)
  );
  AND2 _n0000_3_7_1234 (
    .I0(holdingreg1[11]),
    .I1(_n0000_3_4),
    .O(_n0000_3_7)
  );
  OR2 _n0000_3_8_1235 (
    .I0(_n0000_3_3),
    .I1(_n0000_3_7),
    .O(_n0000_3_8)
  );
  AND2 _n0000_3_9_1236 (
    .I0(_n0000_3_8),
    .I1(_n0000_3_5),
    .O(_n0000_3_9)
  );
  OR2 _n0000_3_10_1237 (
    .I0(_n0000_3_2),
    .I1(_n0000_3_9),
    .O(_n0000_3_10)
  );
  AND2 _n0000_3_11_1238 (
    .I0(_n0000_3_10),
    .I1(_n0000_3_6),
    .O(_n0000_3_11)
  );
  INV holdingreg1_15__n00001_1239 (
    .I(Reset),
    .O(holdingreg1_15__n00001)
  );
  INV holdingreg0_12__n00001_1240 (
    .I(Reset),
    .O(holdingreg0_12__n00001)
  );
  INV holdingreg0_2__n00001_1241 (
    .I(Reset),
    .O(holdingreg0_2__n00001)
  );
  INV holdingreg1_14__n00001_1242 (
    .I(Reset),
    .O(holdingreg1_14__n00001)
  );
  INV holdingreg0_9__n00001_1243 (
    .I(Reset),
    .O(holdingreg0_9__n00001)
  );
  INV holdingreg1_13__n00001_1244 (
    .I(Reset),
    .O(holdingreg1_13__n00001)
  );
  INV holdingreg1_12__n00001_1245 (
    .I(Reset),
    .O(holdingreg1_12__n00001)
  );
  INV holdingreg0_13__n00001_1246 (
    .I(Reset),
    .O(holdingreg0_13__n00001)
  );
  INV holdingreg0_3__n00001_1247 (
    .I(Reset),
    .O(holdingreg0_3__n00001)
  );
  INV holdingreg1_11__n00001_1248 (
    .I(Reset),
    .O(holdingreg1_11__n00001)
  );
  INV holdingreg0_7__n00001_1249 (
    .I(Reset),
    .O(holdingreg0_7__n00001)
  );
  INV holdingreg0_8__n00001_1250 (
    .I(Reset),
    .O(holdingreg0_8__n00001)
  );
  INV holdingreg1_10__n00001_1251 (
    .I(Reset),
    .O(holdingreg1_10__n00001)
  );
  INV holdingreg1_9__n00001_1252 (
    .I(Reset),
    .O(holdingreg1_9__n00001)
  );
  INV holdingreg0_14__n00001_1253 (
    .I(Reset),
    .O(holdingreg0_14__n00001)
  );
  INV holdingreg0_4__n00001_1254 (
    .I(Reset),
    .O(holdingreg0_4__n00001)
  );
  INV holdingreg1_8__n00001_1255 (
    .I(Reset),
    .O(holdingreg1_8__n00001)
  );
  INV holdingreg0_10__n00001_1256 (
    .I(Reset),
    .O(holdingreg0_10__n00001)
  );
  INV holdingreg1_7__n00001_1257 (
    .I(Reset),
    .O(holdingreg1_7__n00001)
  );
  INV holdingreg1_6__n00001_1258 (
    .I(Reset),
    .O(holdingreg1_6__n00001)
  );
  INV holdingreg0_0__n00001_1259 (
    .I(Reset),
    .O(holdingreg0_0__n00001)
  );
  INV holdingreg0_5__n00001_1260 (
    .I(Reset),
    .O(holdingreg0_5__n00001)
  );
  INV holdingreg1_5__n00001_1261 (
    .I(Reset),
    .O(holdingreg1_5__n00001)
  );
  INV holdingreg0_15__n00001_1262 (
    .I(Reset),
    .O(holdingreg0_15__n00001)
  );
  INV holdingreg1_4__n00001_1263 (
    .I(Reset),
    .O(holdingreg1_4__n00001)
  );
  INV holdingreg1_3__n00001_1264 (
    .I(Reset),
    .O(holdingreg1_3__n00001)
  );
  INV holdingreg0_11__n00001_1265 (
    .I(Reset),
    .O(holdingreg0_11__n00001)
  );
  INV holdingreg1_2__n00001_1266 (
    .I(Reset),
    .O(holdingreg1_2__n00001)
  );
  INV holdingreg0_1__n00001_1267 (
    .I(Reset),
    .O(holdingreg0_1__n00001)
  );
  INV holdingreg1_1__n00001_1268 (
    .I(Reset),
    .O(holdingreg1_1__n00001)
  );
  INV holdingreg0_6__n00001_1269 (
    .I(Reset),
    .O(holdingreg0_6__n00001)
  );
endmodule

module Decode (
  Reset, phaseA, phaseB, Sclk, ce, updown
);
  input Reset;
  input phaseA;
  input phaseB;
  input Sclk;
  output ce;
  output updown;
  wire _n0003;
  wire _n0000;
  wire _n0001;
  wire _n0004;
  wire _n0002;
  wire CurrState_Sreg0_FFD2_N1338;
  wire CurrState_Sreg0_FFD1_N1333;
  wire CurrState_Sreg0_FFD3_N1328;
  wire CurrState_Sreg0_FFD4_N1323;
  wire CurrState_Sreg0_XX_FFD1;
  wire CurrState_Sreg0_XX_FFD2;
  wire CurrState_Sreg0_XX_FFD3;
  wire CurrState_Sreg0_XX_FFD4;
  wire CurrState_Sreg0_FFD1;
  wire CurrState_Sreg0_FFD4;
  wire CurrState_Sreg0_FFD3;
  wire CurrState_Sreg0_FFD2;
  wire updown1;
  wire updown2;
  wire updown3;
  wire updown4;
  wire updown5;
  wire ce1;
  wire ce2;
  wire ce3;
  wire CurrState_Sreg0_Out0;
  wire CurrState_Sreg0_Out01;
  wire CurrState_Sreg0_Out02;
  wire CurrState_Sreg0_Out03;
  wire CurrState_Sreg0_Out1;
  wire CurrState_Sreg0_Out11;
  wire CurrState_Sreg0_Out12;
  wire CurrState_Sreg0_Out13;
  wire CurrState_Sreg0_Out2;
  wire CurrState_Sreg0_Out21;
  wire CurrState_Sreg0_Out22;
  wire CurrState_Sreg0_Out3;
  wire CurrState_Sreg0_Out31;
  wire CurrState_Sreg0_Out32;
  wire CurrState_Sreg0_Out33;
  wire CurrState_Sreg0_Out4;
  wire CurrState_Sreg0_Out41;
  wire CurrState_Sreg0_Out42;
  wire CurrState_Sreg0_XX_FFD41;
  wire CurrState_Sreg0_XX_FFD42;
  wire CurrState_Sreg0_XX_FFD43;
  wire CurrState_Sreg0_XX_FFD44;
  wire CurrState_Sreg0_XX_FFD45;
  wire CurrState_Sreg0_XX_FFD31;
  wire CurrState_Sreg0_XX_FFD32;
  wire CurrState_Sreg0_XX_FFD33;
  wire CurrState_Sreg0_XX_FFD34;
  wire CurrState_Sreg0_XX_FFD35;
  wire CurrState_Sreg0_XX_FFD36;
  wire CurrState_Sreg0_XX_FFD37;
  wire CurrState_Sreg0_XX_FFD38;
  wire CurrState_Sreg0_XX_FFD39;
  wire CurrState_Sreg0_XX_FFD310;
  wire CurrState_Sreg0_XX_FFD311;
  wire CurrState_Sreg0_XX_FFD21;
  wire CurrState_Sreg0_XX_FFD22;
  wire CurrState_Sreg0_XX_FFD23;
  wire CurrState_Sreg0_XX_FFD24;
  wire CurrState_Sreg0_XX_FFD25;
  wire CurrState_Sreg0_XX_FFD26;
  wire CurrState_Sreg0_XX_FFD27;
  wire CurrState_Sreg0_XX_FFD28;
  wire CurrState_Sreg0_XX_FFD29;
  wire CurrState_Sreg0_XX_FFD210;
  wire CurrState_Sreg0_XX_FFD211;
  wire CurrState_Sreg0_XX_FFD212;
  wire CurrState_Sreg0_XX_FFD213;
  wire CurrState_Sreg0_XX_FFD214;
  wire CurrState_Sreg0_XX_FFD215;
  wire CurrState_Sreg0_XX_FFD216;
  wire CurrState_Sreg0_XX_FFD217;
  wire CurrState_Sreg0_XX_FFD218;
  wire CurrState_Sreg0_XX_FFD219;
  wire CurrState_Sreg0_XX_FFD220;
  wire CurrState_Sreg0_XX_FFD11;
  wire CurrState_Sreg0_XX_FFD12;
  wire CurrState_Sreg0_XX_FFD13;
  wire CurrState_Sreg0_XX_FFD14;
  wire CurrState_Sreg0_XX_FFD15;
  wire CurrState_Sreg0_XX_FFD16;
  wire CurrState_Sreg0_XX_FFD17;
  wire CurrState_Sreg0_XX_FFD18;
  wire CurrState_Sreg0_XX_FFD19;
  wire CurrState_Sreg0_XX_FFD110;
  wire CurrState_Sreg0_FFD4_0_SClr;
  wire CurrState_Sreg0_FFD3_0_SClr;
  wire CurrState_Sreg0_FFD1_0_SClr;
  wire CurrState_Sreg0_FFD2_0_SClr;
  INV updown6 (
    .I(updown5),
    .O(updown)
  );
  INV ce4 (
    .I(ce3),
    .O(ce)
  );
  FD CurrState_Sreg0_FFD2_1621 (
    .D(CurrState_Sreg0_FFD2_N1338),
    .C(Sclk),
    .Q(CurrState_Sreg0_FFD2)
  );
  AND2 CurrState_Sreg0_Out05 (
    .I0(CurrState_Sreg0_Out0),
    .I1(CurrState_Sreg0_Out03),
    .O(_n0000)
  );
  AND2 CurrState_Sreg0_Out15 (
    .I0(CurrState_Sreg0_Out1),
    .I1(CurrState_Sreg0_Out13),
    .O(_n0001)
  );
  AND4 CurrState_Sreg0_Out24 (
    .I0(CurrState_Sreg0_FFD2),
    .I1(CurrState_Sreg0_Out2),
    .I2(CurrState_Sreg0_Out21),
    .I3(CurrState_Sreg0_Out22),
    .O(_n0002)
  );
  AND2 CurrState_Sreg0_Out35 (
    .I0(CurrState_Sreg0_Out3),
    .I1(CurrState_Sreg0_Out33),
    .O(_n0003)
  );
  AND4 CurrState_Sreg0_Out44 (
    .I0(CurrState_Sreg0_FFD3),
    .I1(CurrState_Sreg0_Out4),
    .I2(CurrState_Sreg0_Out41),
    .I3(CurrState_Sreg0_Out42),
    .O(_n0004)
  );
  AND6 CurrState_Sreg0_XX_FFD46 (
    .I0(CurrState_Sreg0_XX_FFD41),
    .I1(CurrState_Sreg0_FFD3),
    .I2(CurrState_Sreg0_XX_FFD42),
    .I3(CurrState_Sreg0_XX_FFD44),
    .I4(CurrState_Sreg0_XX_FFD43),
    .I5(CurrState_Sreg0_XX_FFD45),
    .O(CurrState_Sreg0_XX_FFD4)
  );
  AND2 CurrState_Sreg0_XX_FFD312 (
    .I0(CurrState_Sreg0_XX_FFD311),
    .I1(CurrState_Sreg0_XX_FFD35),
    .O(CurrState_Sreg0_XX_FFD3)
  );
  AND2 CurrState_Sreg0_XX_FFD221 (
    .I0(CurrState_Sreg0_XX_FFD220),
    .I1(CurrState_Sreg0_XX_FFD211),
    .O(CurrState_Sreg0_XX_FFD2)
  );
  AND2 CurrState_Sreg0_XX_FFD111 (
    .I0(CurrState_Sreg0_XX_FFD110),
    .I1(CurrState_Sreg0_XX_FFD16),
    .O(CurrState_Sreg0_XX_FFD1)
  );
  AND2 CurrState_Sreg0_FFD4_0_SClr2 (
    .I0(CurrState_Sreg0_XX_FFD4),
    .I1(CurrState_Sreg0_FFD4_0_SClr),
    .O(CurrState_Sreg0_FFD4_N1323)
  );
  AND2 CurrState_Sreg0_FFD3_0_SClr2 (
    .I0(CurrState_Sreg0_XX_FFD3),
    .I1(CurrState_Sreg0_FFD3_0_SClr),
    .O(CurrState_Sreg0_FFD3_N1328)
  );
  AND2 CurrState_Sreg0_FFD1_0_SClr2 (
    .I0(CurrState_Sreg0_XX_FFD1),
    .I1(CurrState_Sreg0_FFD1_0_SClr),
    .O(CurrState_Sreg0_FFD1_N1333)
  );
  AND2 CurrState_Sreg0_FFD2_0_SClr2 (
    .I0(CurrState_Sreg0_XX_FFD2),
    .I1(CurrState_Sreg0_FFD2_0_SClr),
    .O(CurrState_Sreg0_FFD2_N1338)
  );
  FD CurrState_Sreg0_FFD4_1622 (
    .D(CurrState_Sreg0_FFD4_N1323),
    .C(Sclk),
    .Q(CurrState_Sreg0_FFD4)
  );
  FD CurrState_Sreg0_FFD3_1623 (
    .D(CurrState_Sreg0_FFD3_N1328),
    .C(Sclk),
    .Q(CurrState_Sreg0_FFD3)
  );
  FD CurrState_Sreg0_FFD1_1624 (
    .D(CurrState_Sreg0_FFD1_N1333),
    .C(Sclk),
    .Q(CurrState_Sreg0_FFD1)
  );
  INV updown1_1625 (
    .I(_n0003),
    .O(updown1)
  );
  INV updown2_1626 (
    .I(_n0004),
    .O(updown2)
  );
  INV updown3_1627 (
    .I(_n0000),
    .O(updown3)
  );
  INV updown4_1628 (
    .I(_n0002),
    .O(updown4)
  );
  AND4 updown5_1629 (
    .I0(updown1),
    .I1(updown2),
    .I2(updown3),
    .I3(updown4),
    .O(updown5)
  );
  INV ce1_1630 (
    .I(_n0001),
    .O(ce1)
  );
  INV ce2_1631 (
    .I(_n0000),
    .O(ce2)
  );
  AND2 ce3_1632 (
    .I0(ce1),
    .I1(ce2),
    .O(ce3)
  );
  AND2 CurrState_Sreg0_Out01_1633 (
    .I0(CurrState_Sreg0_FFD4),
    .I1(CurrState_Sreg0_FFD3),
    .O(CurrState_Sreg0_Out0)
  );
  INV CurrState_Sreg0_Out02_1634 (
    .I(CurrState_Sreg0_FFD2),
    .O(CurrState_Sreg0_Out01)
  );
  INV CurrState_Sreg0_Out03_1635 (
    .I(CurrState_Sreg0_FFD1),
    .O(CurrState_Sreg0_Out02)
  );
  AND2 CurrState_Sreg0_Out04 (
    .I0(CurrState_Sreg0_Out01),
    .I1(CurrState_Sreg0_Out02),
    .O(CurrState_Sreg0_Out03)
  );
  AND2 CurrState_Sreg0_Out11_1636 (
    .I0(CurrState_Sreg0_FFD3),
    .I1(CurrState_Sreg0_FFD1),
    .O(CurrState_Sreg0_Out1)
  );
  INV CurrState_Sreg0_Out12_1637 (
    .I(CurrState_Sreg0_FFD4),
    .O(CurrState_Sreg0_Out11)
  );
  INV CurrState_Sreg0_Out13_1638 (
    .I(CurrState_Sreg0_FFD2),
    .O(CurrState_Sreg0_Out12)
  );
  AND2 CurrState_Sreg0_Out14 (
    .I0(CurrState_Sreg0_Out11),
    .I1(CurrState_Sreg0_Out12),
    .O(CurrState_Sreg0_Out13)
  );
  INV CurrState_Sreg0_Out21_1639 (
    .I(CurrState_Sreg0_FFD4),
    .O(CurrState_Sreg0_Out2)
  );
  INV CurrState_Sreg0_Out22_1640 (
    .I(CurrState_Sreg0_FFD3),
    .O(CurrState_Sreg0_Out21)
  );
  INV CurrState_Sreg0_Out23 (
    .I(CurrState_Sreg0_FFD1),
    .O(CurrState_Sreg0_Out22)
  );
  AND2 CurrState_Sreg0_Out31_1641 (
    .I0(CurrState_Sreg0_FFD3),
    .I1(CurrState_Sreg0_FFD2),
    .O(CurrState_Sreg0_Out3)
  );
  INV CurrState_Sreg0_Out32_1642 (
    .I(CurrState_Sreg0_FFD4),
    .O(CurrState_Sreg0_Out31)
  );
  INV CurrState_Sreg0_Out33_1643 (
    .I(CurrState_Sreg0_FFD1),
    .O(CurrState_Sreg0_Out32)
  );
  AND2 CurrState_Sreg0_Out34 (
    .I0(CurrState_Sreg0_Out31),
    .I1(CurrState_Sreg0_Out32),
    .O(CurrState_Sreg0_Out33)
  );
  INV CurrState_Sreg0_Out41_1644 (
    .I(CurrState_Sreg0_FFD4),
    .O(CurrState_Sreg0_Out4)
  );
  INV CurrState_Sreg0_Out42_1645 (
    .I(CurrState_Sreg0_FFD2),
    .O(CurrState_Sreg0_Out41)
  );
  INV CurrState_Sreg0_Out43 (
    .I(CurrState_Sreg0_FFD1),
    .O(CurrState_Sreg0_Out42)
  );
  INV CurrState_Sreg0_XX_FFD41_1646 (
    .I(phaseB),
    .O(CurrState_Sreg0_XX_FFD41)
  );
  INV CurrState_Sreg0_XX_FFD42_1647 (
    .I(phaseA),
    .O(CurrState_Sreg0_XX_FFD42)
  );
  INV CurrState_Sreg0_XX_FFD43_1648 (
    .I(CurrState_Sreg0_FFD4),
    .O(CurrState_Sreg0_XX_FFD43)
  );
  INV CurrState_Sreg0_XX_FFD44_1649 (
    .I(CurrState_Sreg0_FFD2),
    .O(CurrState_Sreg0_XX_FFD44)
  );
  INV CurrState_Sreg0_XX_FFD45_1650 (
    .I(CurrState_Sreg0_FFD1),
    .O(CurrState_Sreg0_XX_FFD45)
  );
  XOR2 CurrState_Sreg0_XX_FFD31_1651 (
    .I0(CurrState_Sreg0_FFD1),
    .I1(phaseB),
    .O(CurrState_Sreg0_XX_FFD31)
  );
  INV CurrState_Sreg0_XX_FFD32_1652 (
    .I(phaseA),
    .O(CurrState_Sreg0_XX_FFD32)
  );
  INV CurrState_Sreg0_XX_FFD33_1653 (
    .I(CurrState_Sreg0_FFD1),
    .O(CurrState_Sreg0_XX_FFD33)
  );
  INV CurrState_Sreg0_XX_FFD34_1654 (
    .I(CurrState_Sreg0_FFD2),
    .O(CurrState_Sreg0_XX_FFD34)
  );
  INV CurrState_Sreg0_XX_FFD35_1655 (
    .I(CurrState_Sreg0_FFD4),
    .O(CurrState_Sreg0_XX_FFD35)
  );
  AND2 CurrState_Sreg0_XX_FFD36_1656 (
    .I0(phaseA),
    .I1(CurrState_Sreg0_XX_FFD31),
    .O(CurrState_Sreg0_XX_FFD36)
  );
  AND2 CurrState_Sreg0_XX_FFD37_1657 (
    .I0(CurrState_Sreg0_FFD3),
    .I1(CurrState_Sreg0_XX_FFD32),
    .O(CurrState_Sreg0_XX_FFD37)
  );
  AND3 CurrState_Sreg0_XX_FFD38_1658 (
    .I0(CurrState_Sreg0_XX_FFD33),
    .I1(CurrState_Sreg0_FFD3),
    .I2(CurrState_Sreg0_XX_FFD34),
    .O(CurrState_Sreg0_XX_FFD38)
  );
  OR2 CurrState_Sreg0_XX_FFD39_1659 (
    .I0(CurrState_Sreg0_XX_FFD36),
    .I1(CurrState_Sreg0_XX_FFD37),
    .O(CurrState_Sreg0_XX_FFD39)
  );
  AND2 CurrState_Sreg0_XX_FFD310_1660 (
    .I0(CurrState_Sreg0_FFD2),
    .I1(CurrState_Sreg0_XX_FFD39),
    .O(CurrState_Sreg0_XX_FFD310)
  );
  OR2 CurrState_Sreg0_XX_FFD311_1661 (
    .I0(CurrState_Sreg0_XX_FFD310),
    .I1(CurrState_Sreg0_XX_FFD38),
    .O(CurrState_Sreg0_XX_FFD311)
  );
  AND2 CurrState_Sreg0_XX_FFD21_1662 (
    .I0(CurrState_Sreg0_FFD3),
    .I1(CurrState_Sreg0_FFD1),
    .O(CurrState_Sreg0_XX_FFD21)
  );
  INV CurrState_Sreg0_XX_FFD22_1663 (
    .I(CurrState_Sreg0_FFD3),
    .O(CurrState_Sreg0_XX_FFD22)
  );
  INV CurrState_Sreg0_XX_FFD23_1664 (
    .I(CurrState_Sreg0_FFD1),
    .O(CurrState_Sreg0_XX_FFD23)
  );
  XOR2 CurrState_Sreg0_XX_FFD24_1665 (
    .I0(CurrState_Sreg0_FFD1),
    .I1(CurrState_Sreg0_FFD3),
    .O(CurrState_Sreg0_XX_FFD24)
  );
  INV CurrState_Sreg0_XX_FFD25_1666 (
    .I(phaseB),
    .O(CurrState_Sreg0_XX_FFD25)
  );
  AND2 CurrState_Sreg0_XX_FFD26_1667 (
    .I0(phaseB),
    .I1(phaseA),
    .O(CurrState_Sreg0_XX_FFD26)
  );
  XOR2 CurrState_Sreg0_XX_FFD27_1668 (
    .I0(CurrState_Sreg0_FFD1),
    .I1(CurrState_Sreg0_FFD3),
    .O(CurrState_Sreg0_XX_FFD27)
  );
  INV CurrState_Sreg0_XX_FFD28_1669 (
    .I(phaseB),
    .O(CurrState_Sreg0_XX_FFD28)
  );
  INV CurrState_Sreg0_XX_FFD29_1670 (
    .I(CurrState_Sreg0_FFD3),
    .O(CurrState_Sreg0_XX_FFD29)
  );
  INV CurrState_Sreg0_XX_FFD210_1671 (
    .I(CurrState_Sreg0_FFD1),
    .O(CurrState_Sreg0_XX_FFD210)
  );
  INV CurrState_Sreg0_XX_FFD211_1672 (
    .I(CurrState_Sreg0_FFD4),
    .O(CurrState_Sreg0_XX_FFD211)
  );
  AND2 CurrState_Sreg0_XX_FFD212_1673 (
    .I0(CurrState_Sreg0_XX_FFD22),
    .I1(CurrState_Sreg0_XX_FFD23),
    .O(CurrState_Sreg0_XX_FFD212)
  );
  AND2 CurrState_Sreg0_XX_FFD213_1674 (
    .I0(CurrState_Sreg0_XX_FFD24),
    .I1(CurrState_Sreg0_XX_FFD25),
    .O(CurrState_Sreg0_XX_FFD213)
  );
  AND2 CurrState_Sreg0_XX_FFD214_1675 (
    .I0(CurrState_Sreg0_XX_FFD26),
    .I1(CurrState_Sreg0_XX_FFD27),
    .O(CurrState_Sreg0_XX_FFD214)
  );
  AND4 CurrState_Sreg0_XX_FFD215_1676 (
    .I0(phaseA),
    .I1(CurrState_Sreg0_XX_FFD28),
    .I2(CurrState_Sreg0_XX_FFD29),
    .I3(CurrState_Sreg0_XX_FFD210),
    .O(CurrState_Sreg0_XX_FFD215)
  );
  OR2 CurrState_Sreg0_XX_FFD216_1677 (
    .I0(CurrState_Sreg0_XX_FFD21),
    .I1(CurrState_Sreg0_XX_FFD212),
    .O(CurrState_Sreg0_XX_FFD216)
  );
  AND2 CurrState_Sreg0_XX_FFD217_1678 (
    .I0(phaseB),
    .I1(CurrState_Sreg0_XX_FFD216),
    .O(CurrState_Sreg0_XX_FFD217)
  );
  OR3 CurrState_Sreg0_XX_FFD218_1679 (
    .I0(CurrState_Sreg0_XX_FFD217),
    .I1(phaseA),
    .I2(CurrState_Sreg0_XX_FFD213),
    .O(CurrState_Sreg0_XX_FFD218)
  );
  AND2 CurrState_Sreg0_XX_FFD219_1680 (
    .I0(CurrState_Sreg0_FFD2),
    .I1(CurrState_Sreg0_XX_FFD218),
    .O(CurrState_Sreg0_XX_FFD219)
  );
  OR3 CurrState_Sreg0_XX_FFD220_1681 (
    .I0(CurrState_Sreg0_XX_FFD214),
    .I1(CurrState_Sreg0_XX_FFD219),
    .I2(CurrState_Sreg0_XX_FFD215),
    .O(CurrState_Sreg0_XX_FFD220)
  );
  AND2 CurrState_Sreg0_XX_FFD11_1682 (
    .I0(CurrState_Sreg0_FFD1),
    .I1(CurrState_Sreg0_FFD2),
    .O(CurrState_Sreg0_XX_FFD11)
  );
  AND2 CurrState_Sreg0_XX_FFD12_1683 (
    .I0(CurrState_Sreg0_FFD1),
    .I1(phaseA),
    .O(CurrState_Sreg0_XX_FFD12)
  );
  INV CurrState_Sreg0_XX_FFD13_1684 (
    .I(phaseA),
    .O(CurrState_Sreg0_XX_FFD13)
  );
  INV CurrState_Sreg0_XX_FFD14_1685 (
    .I(CurrState_Sreg0_FFD2),
    .O(CurrState_Sreg0_XX_FFD14)
  );
  INV CurrState_Sreg0_XX_FFD15_1686 (
    .I(CurrState_Sreg0_FFD3),
    .O(CurrState_Sreg0_XX_FFD15)
  );
  INV CurrState_Sreg0_XX_FFD16_1687 (
    .I(CurrState_Sreg0_FFD4),
    .O(CurrState_Sreg0_XX_FFD16)
  );
  AND3 CurrState_Sreg0_XX_FFD17_1688 (
    .I0(CurrState_Sreg0_XX_FFD13),
    .I1(phaseB),
    .I2(CurrState_Sreg0_XX_FFD14),
    .O(CurrState_Sreg0_XX_FFD17)
  );
  OR2 CurrState_Sreg0_XX_FFD18_1689 (
    .I0(CurrState_Sreg0_XX_FFD12),
    .I1(CurrState_Sreg0_XX_FFD17),
    .O(CurrState_Sreg0_XX_FFD18)
  );
  AND2 CurrState_Sreg0_XX_FFD19_1690 (
    .I0(CurrState_Sreg0_XX_FFD18),
    .I1(CurrState_Sreg0_XX_FFD15),
    .O(CurrState_Sreg0_XX_FFD19)
  );
  OR2 CurrState_Sreg0_XX_FFD110_1691 (
    .I0(CurrState_Sreg0_XX_FFD11),
    .I1(CurrState_Sreg0_XX_FFD19),
    .O(CurrState_Sreg0_XX_FFD110)
  );
  INV CurrState_Sreg0_FFD4_0_SClr1 (
    .I(Reset),
    .O(CurrState_Sreg0_FFD4_0_SClr)
  );
  INV CurrState_Sreg0_FFD3_0_SClr1 (
    .I(Reset),
    .O(CurrState_Sreg0_FFD3_0_SClr)
  );
  INV CurrState_Sreg0_FFD1_0_SClr1 (
    .I(Reset),
    .O(CurrState_Sreg0_FFD1_0_SClr)
  );
  INV CurrState_Sreg0_FFD2_0_SClr1 (
    .I(Reset),
    .O(CurrState_Sreg0_FFD2_0_SClr)
  );
endmodule

module Servos (
  DCOR0CNTLOWr, DCORENCCTLw, DCOR0THRESLOWr, PhaseB_Encoder0, PhaseB_Encoder1, DCOR0THRESHIGHr, DCOR1CNTHIGHr, Reset, DCOR0CNTHIGHr, DCOR1THRESHIGHr, 
PhaseA_Encoder0, PhaseA_Encoder1, DCORIFGr, DCORIFGw, MotorIn0, Motorin1, Home_Encoder0, Home_Encoder1, DCOR1CNTLOWr, ASleading, Mclk, DCOR1THRESLOWr
, Hfound0, Hfound1, TP, Tfound0, Tfound1, inDATA, outDATA
);
  input DCOR0CNTLOWr;
  input DCORENCCTLw;
  input DCOR0THRESLOWr;
  input PhaseB_Encoder0;
  input PhaseB_Encoder1;
  input DCOR0THRESHIGHr;
  input DCOR1CNTHIGHr;
  input Reset;
  input DCOR0CNTHIGHr;
  input DCOR1THRESHIGHr;
  input PhaseA_Encoder0;
  input PhaseA_Encoder1;
  input DCORIFGr;
  input DCORIFGw;
  input MotorIn0;
  input Motorin1;
  input Home_Encoder0;
  input Home_Encoder1;
  input DCOR1CNTLOWr;
  input ASleading;
  input Mclk;
  input DCOR1THRESLOWr;
  output Hfound0;
  output Hfound1;
  output TP;
  output Tfound0;
  output Tfound1;
  input [7 : 0] inDATA;
  output [7 : 0] outDATA;
  wire NlwRenamedSig_OI_TP;
  wire Zero0;
  wire Zero1;
  wire NET3720;
  wire ce0;
  wire ce1;
  wire updown0;
  wire updown1;
  wire [15 : 0] Channel1;
  wire [15 : 0] Channel0;
  assign
    TP = NlwRenamedSig_OI_TP;
  Decode U6 (
    .Reset(Reset),
    .phaseA(PhaseA_Encoder1),
    .phaseB(PhaseB_Encoder1),
    .Sclk(Mclk),
    .ce(ce1),
    .updown(updown1)
  );
  Decode U1 (
    .Reset(Reset),
    .phaseA(PhaseA_Encoder0),
    .phaseB(PhaseB_Encoder0),
    .Sclk(Mclk),
    .ce(ce0),
    .updown(updown0)
  );
  Counter U2 (
    .sense(NlwRenamedSig_OI_TP),
    .ce(ce0),
    .Reset(Reset),
    .updown(updown0),
    .Zero(Zero0),
    .Sclk(Mclk),
    .count({Channel0[15], Channel0[14], Channel0[13], Channel0[12], Channel0[11], Channel0[10], Channel0[9], Channel0[8], Channel0[7], Channel0[6], 
Channel0[5], Channel0[4], Channel0[3], Channel0[2], Channel0[1], Channel0[0]})
  );
  Holdreg U3 (
    .DCOR0CNTLOWr(DCOR0CNTLOWr),
    .DCOR1CNTHIGHr(DCOR1CNTHIGHr),
    .Reset(Reset),
    .DCOR0CNTHIGHr(DCOR0CNTHIGHr),
    .Sclk(Mclk),
    .DCOR1CNTLOWr(DCOR1CNTLOWr),
    .ASleading(ASleading),
    .ch0in({Channel0[15], Channel0[14], Channel0[13], Channel0[12], Channel0[11], Channel0[10], Channel0[9], Channel0[8], Channel0[7], Channel0[6], 
Channel0[5], Channel0[4], Channel0[3], Channel0[2], Channel0[1], Channel0[0]}),
    .ch1in({Channel1[15], Channel1[14], Channel1[13], Channel1[12], Channel1[11], Channel1[10], Channel1[9], Channel1[8], Channel1[7], Channel1[6], 
Channel1[5], Channel1[4], Channel1[3], Channel1[2], Channel1[1], Channel1[0]}),
    .outDATA({outDATA[7], outDATA[6], outDATA[5], outDATA[4], outDATA[3], outDATA[2], outDATA[1], outDATA[0]})
  );
  HomeConfig U4 (
    .DCORENCCTLw(DCORENCCTLw),
    .DCOR0THRESLOWr(DCOR0THRESLOWr),
    .DCOR0THRESHIGHr(DCOR0THRESHIGHr),
    .Reset(Reset),
    .DCOR1THRESHIGHr(DCOR1THRESHIGHr),
    .DCORIFGr(DCORIFGr),
    .DCORIFGw(DCORIFGw),
    .MotorIn0(MotorIn0),
    .MotorIn1(Motorin1),
    .Home_Encoder0(Home_Encoder0),
    .Home_Encoder1(Home_Encoder1),
    .Sclk(Mclk),
    .DCOR1THRESLOWr(DCOR1THRESLOWr),
    .Zero0(Zero0),
    .Zero1(Zero1),
    .Hfound0(Hfound0),
    .Hfound1(Hfound1),
    .sense0(NlwRenamedSig_OI_TP),
    .sense1(NET3720),
    .Tfound0(Tfound0),
    .Tfound1(Tfound1),
    .inDATA({inDATA[7], inDATA[6], inDATA[5], inDATA[4], inDATA[3], inDATA[2], inDATA[1], inDATA[0]}),
    .Channel0({Channel0[15], Channel0[14], Channel0[13], Channel0[12], Channel0[11], Channel0[10], Channel0[9], Channel0[8], Channel0[7], Channel0[6]
, Channel0[5], Channel0[4], Channel0[3], Channel0[2], Channel0[1], Channel0[0]}),
    .Channel1({Channel1[15], Channel1[14], Channel1[13], Channel1[12], Channel1[11], Channel1[10], Channel1[9], Channel1[8], Channel1[7], Channel1[6]
, Channel1[5], Channel1[4], Channel1[3], Channel1[2], Channel1[1], Channel1[0]}),
    .outDATA({outDATA[7], outDATA[6], outDATA[5], outDATA[4], outDATA[3], outDATA[2], outDATA[1], outDATA[0]})
  );
  Counter U5 (
    .sense(NET3720),
    .ce(ce1),
    .Reset(Reset),
    .updown(updown1),
    .Zero(Zero1),
    .Sclk(Mclk),
    .count({Channel1[15], Channel1[14], Channel1[13], Channel1[12], Channel1[11], Channel1[10], Channel1[9], Channel1[8], Channel1[7], Channel1[6], 
Channel1[5], Channel1[4], Channel1[3], Channel1[2], Channel1[1], Channel1[0]})
  );
endmodule

module U21AddDecode (
  AS, RD, WR, DCORENCPWRr, DCOR0CNTLOWr, DCORENCPWRw, DCORENCCTLw, DCOR0THRESLOWr, DCOR0THRESHIGHr, DCOR1CNTHIGHr, DCORLINTr, DCOR0CNTHIGHr, 
DCOR1THRESHIGHr, DCORLIMITSr, DCORSENSORw, DCORCONFIGr, DCORIFGr, DCORIFGw, DCOROUTw, DCORIEw, DCOR1CNTLOWr, DCOR1THRESLOWr, DCORI2CCNTr, ADDR
);
  input AS;
  input RD;
  input WR;
  output DCORENCPWRr;
  output DCOR0CNTLOWr;
  output DCORENCPWRw;
  output DCORENCCTLw;
  output DCOR0THRESLOWr;
  output DCOR0THRESHIGHr;
  output DCOR1CNTHIGHr;
  output DCORLINTr;
  output DCOR0CNTHIGHr;
  output DCOR1THRESHIGHr;
  output DCORLIMITSr;
  output DCORSENSORw;
  output DCORCONFIGr;
  output DCORIFGr;
  output DCORIFGw;
  output DCOROUTw;
  output DCORIEw;
  output DCOR1CNTLOWr;
  output DCOR1THRESLOWr;
  output DCORI2CCNTr;
  input [7 : 0] ADDR;
  wire SF14762;
  wire SF14775;
  wire SF14788;
  wire SF14781;
  wire SF14785;
  wire SF14770;
  wire SF14766;
  wire SF14814;
  wire SF14809;
  wire SF14804;
  wire Select_16_Select;
  wire Select_16_Select1;
  wire Select_17_Select;
  wire Select_17_Select1;
  wire SF148141;
  wire SF148142;
  wire SF148091;
  wire SF148092;
  wire Select_1_Select;
  wire Select_1_Select1;
  wire Select_6_Select;
  wire Select_6_Select1;
  wire Select_2_Select;
  wire Select_2_Select1;
  wire Select_10_Select;
  wire Select_10_Select1;
  wire Select_10_Select2;
  wire Select_10_Select3;
  wire Select_5_Select;
  wire Select_5_Select1;
  wire SF147851;
  wire SF147852;
  wire Select_3_Select;
  wire Select_3_Select1;
  wire Select_20_Select;
  wire Select_20_Select1;
  wire Select_20_Select2;
  wire Select_20_Select3;
  wire Select_15_Select;
  wire Select_15_Select1;
  wire Select_15_Select2;
  wire Select_15_Select3;
  wire Select_15_Select4;
  wire Select_12_Select;
  wire Select_12_Select1;
  wire Select_12_Select2;
  wire Select_12_Select3;
  wire Select_19_Select;
  wire Select_19_Select1;
  wire Select_8_Select;
  wire Select_8_Select1;
  wire SF147881;
  wire SF147882;
  wire SF147621;
  wire SF147622;
  wire SF147623;
  wire SF147624;
  wire Select_14_Select;
  wire Select_14_Select1;
  wire Select_9_Select;
  wire Select_9_Select1;
  wire Select_9_Select2;
  wire Select_9_Select3;
  wire Select_7_Select;
  wire Select_7_Select1;
  wire Select_7_Select2;
  wire Select_7_Select3;
  wire Select_11_Select;
  wire Select_11_Select1;
  wire Select_11_Select2;
  wire Select_11_Select3;
  wire Select_11_Select4;
  wire SF147811;
  wire SF147812;
  wire Select_18_Select;
  wire Select_18_Select1;
  wire Select_4_Select;
  wire Select_4_Select1;
  wire SF147701;
  wire SF147702;
  wire SF147751;
  wire SF147752;
  wire Select_13_Select;
  wire Select_13_Select1;
  wire Select_13_Select2;
  wire Select_13_Select3;
  wire Select_13_Select4;
  AND2 Select_16_Select3 (
    .I0(Select_16_Select),
    .I1(Select_16_Select1),
    .O(DCORLIMITSr)
  );
  AND2 Select_17_Select3 (
    .I0(Select_17_Select),
    .I1(Select_17_Select1),
    .O(DCORIFGr)
  );
  AND3 SF148143 (
    .I0(SF148141),
    .I1(SF14788),
    .I2(SF148142),
    .O(SF14814)
  );
  AND2 SF148093 (
    .I0(SF148091),
    .I1(SF148092),
    .O(SF14809)
  );
  AND2 Select_1_Select3 (
    .I0(Select_1_Select),
    .I1(Select_1_Select1),
    .O(DCORI2CCNTr)
  );
  AND2 Select_6_Select3 (
    .I0(Select_6_Select),
    .I1(Select_6_Select1),
    .O(DCOR1THRESHIGHr)
  );
  AND2 Select_2_Select3 (
    .I0(Select_2_Select),
    .I1(Select_2_Select1),
    .O(DCOROUTw)
  );
  AND3 Select_10_Select5 (
    .I0(Select_10_Select3),
    .I1(Select_10_Select),
    .I2(Select_10_Select2),
    .O(DCOR1CNTHIGHr)
  );
  AND2 Select_5_Select3 (
    .I0(Select_5_Select),
    .I1(Select_5_Select1),
    .O(DCORENCPWRr)
  );
  AND2 SF147853 (
    .I0(SF147851),
    .I1(SF147852),
    .O(SF14785)
  );
  AND2 Select_3_Select3 (
    .I0(Select_3_Select),
    .I1(Select_3_Select1),
    .O(DCORCONFIGr)
  );
  AND3 SF147661 (
    .I0(ADDR[2]),
    .I1(ADDR[1]),
    .I2(SF14762),
    .O(SF14766)
  );
  AND3 Select_20_Select5 (
    .I0(Select_20_Select3),
    .I1(Select_20_Select),
    .I2(Select_20_Select2),
    .O(DCORSENSORw)
  );
  AND3 Select_15_Select6 (
    .I0(Select_15_Select4),
    .I1(Select_15_Select),
    .I2(Select_15_Select3),
    .O(DCORLINTr)
  );
  AND3 Select_12_Select5 (
    .I0(Select_12_Select3),
    .I1(Select_12_Select),
    .I2(Select_12_Select2),
    .O(DCOR0CNTHIGHr)
  );
  AND2 Select_19_Select3 (
    .I0(Select_19_Select),
    .I1(Select_19_Select1),
    .O(DCORIEw)
  );
  AND2 Select_8_Select3 (
    .I0(Select_8_Select),
    .I1(Select_8_Select1),
    .O(DCOR0THRESHIGHr)
  );
  AND3 SF148041 (
    .I0(ADDR[0]),
    .I1(ADDR[3]),
    .I2(SF14766),
    .O(SF14804)
  );
  AND3 SF147883 (
    .I0(SF147881),
    .I1(SF14762),
    .I2(SF147882),
    .O(SF14788)
  );
  AND4 SF147625 (
    .I0(SF147621),
    .I1(SF147622),
    .I2(SF147623),
    .I3(SF147624),
    .O(SF14762)
  );
  AND2 Select_14_Select3 (
    .I0(Select_14_Select),
    .I1(Select_14_Select1),
    .O(DCORENCCTLw)
  );
  AND3 Select_9_Select5 (
    .I0(Select_9_Select3),
    .I1(Select_9_Select),
    .I2(Select_9_Select2),
    .O(DCOR0THRESLOWr)
  );
  AND3 Select_7_Select5 (
    .I0(Select_7_Select3),
    .I1(Select_7_Select),
    .I2(Select_7_Select2),
    .O(DCOR1THRESLOWr)
  );
  AND3 Select_11_Select6 (
    .I0(Select_11_Select4),
    .I1(Select_11_Select),
    .I2(Select_11_Select3),
    .O(DCOR1CNTLOWr)
  );
  AND2 SF147813 (
    .I0(SF147811),
    .I1(SF147812),
    .O(SF14781)
  );
  AND2 Select_18_Select3 (
    .I0(Select_18_Select),
    .I1(Select_18_Select1),
    .O(DCORIFGw)
  );
  AND2 Select_4_Select3 (
    .I0(Select_4_Select),
    .I1(Select_4_Select1),
    .O(DCORENCPWRw)
  );
  AND2 SF147703 (
    .I0(SF147701),
    .I1(SF147702),
    .O(SF14770)
  );
  AND2 SF147753 (
    .I0(SF147751),
    .I1(SF147752),
    .O(SF14775)
  );
  AND3 Select_13_Select6 (
    .I0(Select_13_Select4),
    .I1(Select_13_Select),
    .I2(Select_13_Select3),
    .O(DCOR0CNTLOWr)
  );
  AND2 Select_16_Select1_1954 (
    .I0(WR),
    .I1(SF14785),
    .O(Select_16_Select)
  );
  INV Select_16_Select2 (
    .I(RD),
    .O(Select_16_Select1)
  );
  AND2 Select_17_Select1_1955 (
    .I0(WR),
    .I1(SF14809),
    .O(Select_17_Select)
  );
  INV Select_17_Select2 (
    .I(RD),
    .O(Select_17_Select1)
  );
  INV SF148141_1956 (
    .I(ADDR[3]),
    .O(SF148141)
  );
  INV SF148142_1957 (
    .I(ADDR[0]),
    .O(SF148142)
  );
  AND2 SF148091_1958 (
    .I0(SF14788),
    .I1(ADDR[0]),
    .O(SF148091)
  );
  INV SF148092_1959 (
    .I(ADDR[3]),
    .O(SF148092)
  );
  AND2 Select_1_Select1_1960 (
    .I0(WR),
    .I1(SF14814),
    .O(Select_1_Select)
  );
  INV Select_1_Select2 (
    .I(RD),
    .O(Select_1_Select1)
  );
  AND4 Select_6_Select1_1961 (
    .I0(WR),
    .I1(ADDR[0]),
    .I2(ADDR[3]),
    .I3(SF14781),
    .O(Select_6_Select)
  );
  INV Select_6_Select2 (
    .I(RD),
    .O(Select_6_Select1)
  );
  AND2 Select_2_Select1_1962 (
    .I0(SF14804),
    .I1(RD),
    .O(Select_2_Select)
  );
  INV Select_2_Select2 (
    .I(WR),
    .O(Select_2_Select1)
  );
  AND2 Select_10_Select1_1963 (
    .I0(WR),
    .I1(ADDR[0]),
    .O(Select_10_Select)
  );
  INV Select_10_Select2_1964 (
    .I(RD),
    .O(Select_10_Select1)
  );
  INV Select_10_Select3_1965 (
    .I(ADDR[3]),
    .O(Select_10_Select2)
  );
  AND2 Select_10_Select4 (
    .I0(SF14766),
    .I1(Select_10_Select1),
    .O(Select_10_Select3)
  );
  AND2 Select_5_Select1_1966 (
    .I0(WR),
    .I1(SF14770),
    .O(Select_5_Select)
  );
  INV Select_5_Select2 (
    .I(RD),
    .O(Select_5_Select1)
  );
  AND2 SF147851_1967 (
    .I0(SF14781),
    .I1(ADDR[0]),
    .O(SF147851)
  );
  INV SF147852_1968 (
    .I(ADDR[3]),
    .O(SF147852)
  );
  AND2 Select_3_Select1_1969 (
    .I0(WR),
    .I1(SF14804),
    .O(Select_3_Select)
  );
  INV Select_3_Select2 (
    .I(RD),
    .O(Select_3_Select1)
  );
  AND2 Select_20_Select1_1970 (
    .I0(RD),
    .I1(ADDR[3]),
    .O(Select_20_Select)
  );
  INV Select_20_Select2_1971 (
    .I(WR),
    .O(Select_20_Select1)
  );
  INV Select_20_Select3_1972 (
    .I(ADDR[0]),
    .O(Select_20_Select2)
  );
  AND2 Select_20_Select4 (
    .I0(SF14775),
    .I1(Select_20_Select1),
    .O(Select_20_Select3)
  );
  AND2 Select_15_Select1_1973 (
    .I0(WR),
    .I1(SF14781),
    .O(Select_15_Select)
  );
  INV Select_15_Select2_1974 (
    .I(RD),
    .O(Select_15_Select1)
  );
  INV Select_15_Select3_1975 (
    .I(ADDR[0]),
    .O(Select_15_Select2)
  );
  INV Select_15_Select4_1976 (
    .I(ADDR[3]),
    .O(Select_15_Select3)
  );
  AND2 Select_15_Select5 (
    .I0(Select_15_Select1),
    .I1(Select_15_Select2),
    .O(Select_15_Select4)
  );
  AND2 Select_12_Select1_1977 (
    .I0(WR),
    .I1(ADDR[0]),
    .O(Select_12_Select)
  );
  INV Select_12_Select2_1978 (
    .I(RD),
    .O(Select_12_Select1)
  );
  INV Select_12_Select3_1979 (
    .I(ADDR[3]),
    .O(Select_12_Select2)
  );
  AND2 Select_12_Select4 (
    .I0(SF14775),
    .I1(Select_12_Select1),
    .O(Select_12_Select3)
  );
  AND2 Select_19_Select1_1980 (
    .I0(SF14814),
    .I1(RD),
    .O(Select_19_Select)
  );
  INV Select_19_Select2 (
    .I(WR),
    .O(Select_19_Select1)
  );
  AND4 Select_8_Select1_1981 (
    .I0(WR),
    .I1(ADDR[0]),
    .I2(ADDR[3]),
    .I3(SF14788),
    .O(Select_8_Select)
  );
  INV Select_8_Select2 (
    .I(RD),
    .O(Select_8_Select1)
  );
  INV SF147881_1982 (
    .I(ADDR[1]),
    .O(SF147881)
  );
  INV SF147882_1983 (
    .I(ADDR[2]),
    .O(SF147882)
  );
  INV SF147621_1984 (
    .I(ADDR[7]),
    .O(SF147621)
  );
  INV SF147622_1985 (
    .I(ADDR[6]),
    .O(SF147622)
  );
  INV SF147623_1986 (
    .I(ADDR[5]),
    .O(SF147623)
  );
  INV SF147624_1987 (
    .I(ADDR[4]),
    .O(SF147624)
  );
  AND2 Select_14_Select1_1988 (
    .I0(SF14785),
    .I1(RD),
    .O(Select_14_Select)
  );
  INV Select_14_Select2 (
    .I(WR),
    .O(Select_14_Select1)
  );
  AND2 Select_9_Select1_1989 (
    .I0(WR),
    .I1(ADDR[3]),
    .O(Select_9_Select)
  );
  INV Select_9_Select2_1990 (
    .I(RD),
    .O(Select_9_Select1)
  );
  INV Select_9_Select3_1991 (
    .I(ADDR[0]),
    .O(Select_9_Select2)
  );
  AND2 Select_9_Select4 (
    .I0(SF14788),
    .I1(Select_9_Select1),
    .O(Select_9_Select3)
  );
  AND2 Select_7_Select1_1992 (
    .I0(WR),
    .I1(ADDR[3]),
    .O(Select_7_Select)
  );
  INV Select_7_Select2_1993 (
    .I(RD),
    .O(Select_7_Select1)
  );
  INV Select_7_Select3_1994 (
    .I(ADDR[0]),
    .O(Select_7_Select2)
  );
  AND2 Select_7_Select4 (
    .I0(SF14781),
    .I1(Select_7_Select1),
    .O(Select_7_Select3)
  );
  AND2 Select_11_Select1_1995 (
    .I0(WR),
    .I1(SF14766),
    .O(Select_11_Select)
  );
  INV Select_11_Select2_1996 (
    .I(RD),
    .O(Select_11_Select1)
  );
  INV Select_11_Select3_1997 (
    .I(ADDR[0]),
    .O(Select_11_Select2)
  );
  INV Select_11_Select4_1998 (
    .I(ADDR[3]),
    .O(Select_11_Select3)
  );
  AND2 Select_11_Select5 (
    .I0(Select_11_Select1),
    .I1(Select_11_Select2),
    .O(Select_11_Select4)
  );
  AND2 SF147811_1999 (
    .I0(ADDR[1]),
    .I1(SF14762),
    .O(SF147811)
  );
  INV SF147812_2000 (
    .I(ADDR[2]),
    .O(SF147812)
  );
  AND2 Select_18_Select1_2001 (
    .I0(SF14809),
    .I1(RD),
    .O(Select_18_Select)
  );
  INV Select_18_Select2 (
    .I(WR),
    .O(Select_18_Select1)
  );
  AND2 Select_4_Select1_2002 (
    .I0(SF14770),
    .I1(RD),
    .O(Select_4_Select)
  );
  INV Select_4_Select2 (
    .I(WR),
    .O(Select_4_Select1)
  );
  AND2 SF147701_2003 (
    .I0(ADDR[3]),
    .I1(SF14766),
    .O(SF147701)
  );
  INV SF147702_2004 (
    .I(ADDR[0]),
    .O(SF147702)
  );
  AND2 SF147751_2005 (
    .I0(SF14762),
    .I1(ADDR[2]),
    .O(SF147751)
  );
  INV SF147752_2006 (
    .I(ADDR[1]),
    .O(SF147752)
  );
  AND2 Select_13_Select1_2007 (
    .I0(WR),
    .I1(SF14775),
    .O(Select_13_Select)
  );
  INV Select_13_Select2_2008 (
    .I(RD),
    .O(Select_13_Select1)
  );
  INV Select_13_Select3_2009 (
    .I(ADDR[0]),
    .O(Select_13_Select2)
  );
  INV Select_13_Select4_2010 (
    .I(ADDR[3]),
    .O(Select_13_Select3)
  );
  AND2 Select_13_Select5 (
    .I0(Select_13_Select1),
    .I1(Select_13_Select2),
    .O(Select_13_Select4)
  );
endmodule

module Interrupt (
  PWRint, Reset, I2Cint, DCORIFGr, Homed0, Homed1, BusInt, DCORIEw, Thres0, Thres1, LSwitchInt, Mclk, INT, inDATA, outDATA
);
  input PWRint;
  input Reset;
  input I2Cint;
  input DCORIFGr;
  input Homed0;
  input Homed1;
  input BusInt;
  input DCORIEw;
  input Thres0;
  input Thres1;
  input LSwitchInt;
  input Mclk;
  output INT;
  input [7 : 0] inDATA;
  output [7 : 0] outDATA;
  wire _n0000;
  wire _n0001;
  wire _n0002;
  wire _n0003;
  wire _n0004;
  wire _n0005;
  wire _n0006;
  wire _n0007;
  wire N1246;
  wire DCORIE_0__n0002;
  wire DCORIE_3__n0000;
  wire DCORIE_2__n0000;
  wire DCORIE_7__n0003;
  wire DCORIE_0__n0000;
  wire DCORIE_5__n0000;
  wire DCORIE_4__n0000;
  wire DCORIE_7__n0000;
  wire DCORIE_1__n0000;
  wire DCORIE_6__n0000;
  wire _n00071;
  wire INT1;
  wire INT2;
  wire INT3;
  wire INT4;
  wire INT5;
  wire INT6;
  wire INT7;
  wire INT8;
  wire INT9;
  wire DCORIE_0__n00021;
  wire DCORIE_0__n00022;
  wire DCORIE_0__n00023;
  wire DCORIE_1__n00001;
  wire DCORIE_7__n00001;
  wire DCORIE_0__n00001;
  wire DCORIE_2__n00001;
  wire DCORIE_5__n00001;
  wire DCORIE_6__n00001;
  wire DCORIE_4__n00001;
  wire DCORIE_3__n00001;
  wire [7 : 0] DCORIE;
  GND XST_GND (
    .G(N1246)
  );
  AND2 _n00072 (
    .I0(DCORIE[0]),
    .I1(_n00071),
    .O(_n0007)
  );
  AND2 _n00061 (
    .I0(DCORIE[1]),
    .I1(PWRint),
    .O(_n0006)
  );
  AND2 _n00051 (
    .I0(DCORIE[2]),
    .I1(Homed0),
    .O(_n0005)
  );
  AND2 _n00041 (
    .I0(DCORIE[3]),
    .I1(Homed1),
    .O(_n0004)
  );
  AND2 _n00031 (
    .I0(DCORIE[4]),
    .I1(LSwitchInt),
    .O(_n0003)
  );
  AND2 _n00021 (
    .I0(DCORIE[5]),
    .I1(Thres0),
    .O(_n0002)
  );
  AND2 _n00011 (
    .I0(DCORIE[6]),
    .I1(Thres1),
    .O(_n0001)
  );
  AND2 _n00001 (
    .I0(DCORIE[7]),
    .I1(I2Cint),
    .O(_n0000)
  );
  INV INT10 (
    .I(INT9),
    .O(INT)
  );
  BUFE I8_0 (
    .E(DCORIFGr),
    .I(BusInt),
    .O(outDATA[0])
  );
  BUFE I7_0 (
    .E(N1246),
    .I(N1246),
    .O(outDATA[1])
  );
  INV DCORIE_0__n00024 (
    .I(DCORIE_0__n00023),
    .O(DCORIE_0__n0002)
  );
  BUFE I1_0 (
    .E(DCORIFGr),
    .I(I2Cint),
    .O(outDATA[7])
  );
  BUFE I2_0 (
    .E(N1246),
    .I(N1246),
    .O(outDATA[6])
  );
  BUFE I3_0 (
    .E(N1246),
    .I(N1246),
    .O(outDATA[5])
  );
  BUFE I4_0 (
    .E(DCORIFGr),
    .I(LSwitchInt),
    .O(outDATA[4])
  );
  BUFE I5_0 (
    .E(N1246),
    .I(N1246),
    .O(outDATA[3])
  );
  BUFE I6_0 (
    .E(N1246),
    .I(N1246),
    .O(outDATA[2])
  );
  FDCE DCORIE_7 (
    .D(DCORIE_7__n0000),
    .CE(DCORIE_0__n0002),
    .CLR(N1246),
    .C(DCORIE_7__n0003),
    .Q(DCORIE[7])
  );
  FDCE DCORIE_6 (
    .D(DCORIE_6__n0000),
    .CE(DCORIE_0__n0002),
    .CLR(N1246),
    .C(DCORIE_7__n0003),
    .Q(DCORIE[6])
  );
  FDCE DCORIE_0 (
    .D(DCORIE_0__n0000),
    .CE(DCORIE_0__n0002),
    .CLR(N1246),
    .C(DCORIE_7__n0003),
    .Q(DCORIE[0])
  );
  FDCE DCORIE_1 (
    .D(DCORIE_1__n0000),
    .CE(DCORIE_0__n0002),
    .CLR(N1246),
    .C(DCORIE_7__n0003),
    .Q(DCORIE[1])
  );
  FDCE DCORIE_2 (
    .D(DCORIE_2__n0000),
    .CE(DCORIE_0__n0002),
    .CLR(N1246),
    .C(DCORIE_7__n0003),
    .Q(DCORIE[2])
  );
  FDCE DCORIE_3 (
    .D(DCORIE_3__n0000),
    .CE(DCORIE_0__n0002),
    .CLR(N1246),
    .C(DCORIE_7__n0003),
    .Q(DCORIE[3])
  );
  FDCE DCORIE_4 (
    .D(DCORIE_4__n0000),
    .CE(DCORIE_0__n0002),
    .CLR(N1246),
    .C(DCORIE_7__n0003),
    .Q(DCORIE[4])
  );
  FDCE DCORIE_5 (
    .D(DCORIE_5__n0000),
    .CE(DCORIE_0__n0002),
    .CLR(N1246),
    .C(DCORIE_7__n0003),
    .Q(DCORIE[5])
  );
  INV DCORIE_7__n00031 (
    .I(Mclk),
    .O(DCORIE_7__n0003)
  );
  AND2 DCORIE_1__n00002 (
    .I0(inDATA[1]),
    .I1(DCORIE_1__n00001),
    .O(DCORIE_1__n0000)
  );
  AND2 DCORIE_7__n00002 (
    .I0(inDATA[7]),
    .I1(DCORIE_7__n00001),
    .O(DCORIE_7__n0000)
  );
  AND2 DCORIE_0__n00002 (
    .I0(inDATA[0]),
    .I1(DCORIE_0__n00001),
    .O(DCORIE_0__n0000)
  );
  AND2 DCORIE_2__n00002 (
    .I0(inDATA[2]),
    .I1(DCORIE_2__n00001),
    .O(DCORIE_2__n0000)
  );
  AND2 DCORIE_5__n00002 (
    .I0(inDATA[5]),
    .I1(DCORIE_5__n00001),
    .O(DCORIE_5__n0000)
  );
  AND2 DCORIE_6__n00002 (
    .I0(inDATA[6]),
    .I1(DCORIE_6__n00001),
    .O(DCORIE_6__n0000)
  );
  AND2 DCORIE_4__n00002 (
    .I0(inDATA[4]),
    .I1(DCORIE_4__n00001),
    .O(DCORIE_4__n0000)
  );
  AND2 DCORIE_3__n00002 (
    .I0(inDATA[3]),
    .I1(DCORIE_3__n00001),
    .O(DCORIE_3__n0000)
  );
  INV _n00071_2062 (
    .I(BusInt),
    .O(_n00071)
  );
  INV INT1_2063 (
    .I(_n0001),
    .O(INT1)
  );
  INV INT2_2064 (
    .I(_n0002),
    .O(INT2)
  );
  INV INT3_2065 (
    .I(_n0003),
    .O(INT3)
  );
  INV INT4_2066 (
    .I(_n0004),
    .O(INT4)
  );
  INV INT5_2067 (
    .I(_n0005),
    .O(INT5)
  );
  INV INT6_2068 (
    .I(_n0006),
    .O(INT6)
  );
  INV INT7_2069 (
    .I(_n0007),
    .O(INT7)
  );
  INV INT8_2070 (
    .I(_n0000),
    .O(INT8)
  );
  AND8 INT9_2071 (
    .I0(INT1),
    .I1(INT2),
    .I2(INT3),
    .I3(INT4),
    .I4(INT5),
    .I5(INT6),
    .I6(INT7),
    .I7(INT8),
    .O(INT9)
  );
  INV DCORIE_0__n00021_2072 (
    .I(DCORIEw),
    .O(DCORIE_0__n00021)
  );
  INV DCORIE_0__n00022_2073 (
    .I(Reset),
    .O(DCORIE_0__n00022)
  );
  AND2 DCORIE_0__n00023_2074 (
    .I0(DCORIE_0__n00021),
    .I1(DCORIE_0__n00022),
    .O(DCORIE_0__n00023)
  );
  INV DCORIE_1__n00001_2075 (
    .I(Reset),
    .O(DCORIE_1__n00001)
  );
  INV DCORIE_7__n00001_2076 (
    .I(Reset),
    .O(DCORIE_7__n00001)
  );
  INV DCORIE_0__n00001_2077 (
    .I(Reset),
    .O(DCORIE_0__n00001)
  );
  INV DCORIE_2__n00001_2078 (
    .I(Reset),
    .O(DCORIE_2__n00001)
  );
  INV DCORIE_5__n00001_2079 (
    .I(Reset),
    .O(DCORIE_5__n00001)
  );
  INV DCORIE_6__n00001_2080 (
    .I(Reset),
    .O(DCORIE_6__n00001)
  );
  INV DCORIE_4__n00001_2081 (
    .I(Reset),
    .O(DCORIE_4__n00001)
  );
  INV DCORIE_3__n00001_2082 (
    .I(Reset),
    .O(DCORIE_3__n00001)
  );
endmodule

module PWRreg (
  DCORENCPWRr, DCORENCPWRw, Reset, Hme05flg, Enc033flg, Hme033flg, DCORIFGr, DCORIFGw, Enc05flg, Hme15flg, Enc133flg, Hme133flg, Enc15flg, Mclk, 
PWRint, Hme05ctl, Enc033ctl, Hme033ctl, Enc05ctl, Hme15ctl, Enc133ctl, Hme133ctl, Enc15ctl, inDATA, outDATA
);
  input DCORENCPWRr;
  input DCORENCPWRw;
  input Reset;
  input Hme05flg;
  input Enc033flg;
  input Hme033flg;
  input DCORIFGr;
  input DCORIFGw;
  input Enc05flg;
  input Hme15flg;
  input Enc133flg;
  input Hme133flg;
  input Enc15flg;
  input Mclk;
  output PWRint;
  output Hme05ctl;
  output Enc033ctl;
  output Hme033ctl;
  output Enc05ctl;
  output Hme15ctl;
  output Enc133ctl;
  output Hme133ctl;
  output Enc15ctl;
  input [7 : 0] inDATA;
  output [7 : 0] outDATA;
  wire NlwRenamedSig_OI_PWRint;
  wire orFLGs;
  wire _n0002;
  wire _n0003;
  wire _n0004;
  wire _n0005;
  wire _n0011;
  wire _n0006;
  wire _n0007;
  wire _n0008;
  wire _n0009;
  wire _n0020;
  wire DCORIFG__n0002;
  wire N11185;
  wire DCORIFG__n0000;
  wire Flgreg_7_N1267;
  wire _n0032;
  wire _n00321;
  wire _n00322;
  wire _n00323;
  wire DCORIFG__n00001;
  wire DCORIFG__n00002;
  wire DCORIFG__n00003;
  wire DCORIFG__n00004;
  wire DCORIFG__n00005;
  wire _n00201;
  wire Enc15ctl1;
  wire Enc15ctl2;
  wire Enc133ctl1;
  wire Enc05ctl1;
  wire Enc05ctl2;
  wire Mmux__n0011_Result;
  wire Mmux__n0011_Result1;
  wire Mmux__n0011_Result2;
  wire Enc033ctl1;
  wire Enc033ctl2;
  wire _n00091;
  wire _n00092;
  wire _n00093;
  wire _n00094;
  wire _n00095;
  wire _n00096;
  wire _n00097;
  wire _n00021;
  wire _n00022;
  wire Mmux__n0008_Result;
  wire Mmux__n0008_Result1;
  wire Mmux__n0008_Result2;
  wire Mmux__n0007_Result;
  wire Mmux__n0007_Result1;
  wire Mmux__n0007_Result2;
  wire Mmux__n0006_Result;
  wire Mmux__n0006_Result1;
  wire Mmux__n0006_Result2;
  wire Mmux__n0005_Result;
  wire Mmux__n0005_Result1;
  wire Mmux__n0005_Result2;
  wire Mmux__n0004_Result;
  wire Mmux__n0004_Result1;
  wire Mmux__n0004_Result2;
  wire Mmux__n0003_Result;
  wire Mmux__n0003_Result1;
  wire Mmux__n0003_Result2;
  wire DCORIFG__n00021;
  wire DCORIFG__n00022;
  wire [7 : 0] Flgreg;
  wire [7 : 0] ctrlr;
  assign
    PWRint = NlwRenamedSig_OI_PWRint;
  FDCE ctrlr_2 (
    .D(inDATA[2]),
    .CE(DCORENCPWRw),
    .CLR(Reset),
    .C(Flgreg_7_N1267),
    .Q(ctrlr[2])
  );
  FDCE ctrlr_5 (
    .D(inDATA[5]),
    .CE(DCORENCPWRw),
    .CLR(Reset),
    .C(Flgreg_7_N1267),
    .Q(ctrlr[5])
  );
  INV _n00324 (
    .I(_n00323),
    .O(_n0032)
  );
  FDCE Flgreg_4 (
    .D(Hme133flg),
    .CE(_n0002),
    .CLR(N11185),
    .C(Flgreg_7_N1267),
    .Q(Flgreg[4])
  );
  AND2 DCORIFG__n00006 (
    .I0(DCORIFG__n00005),
    .I1(DCORIFG__n00003),
    .O(DCORIFG__n0000)
  );
  AND2 _n00202 (
    .I0(orFLGs),
    .I1(_n00201),
    .O(_n0020)
  );
  INV Enc15ctl3 (
    .I(Enc15ctl2),
    .O(Enc15ctl)
  );
  INV Enc133ctl2 (
    .I(Enc133ctl1),
    .O(Enc133ctl)
  );
  INV Enc05ctl3 (
    .I(Enc05ctl2),
    .O(Enc05ctl)
  );
  OR2 Mmux__n0011_Result4 (
    .I0(Mmux__n0011_Result),
    .I1(Mmux__n0011_Result2),
    .O(_n0011)
  );
  INV Enc033ctl3 (
    .I(Enc033ctl2),
    .O(Enc033ctl)
  );
  FDCE Flgreg_1 (
    .D(Hme05flg),
    .CE(_n0002),
    .CLR(N11185),
    .C(Flgreg_7_N1267),
    .Q(Flgreg[1])
  );
  FDCE Flgreg_5 (
    .D(Hme15flg),
    .CE(_n0002),
    .CLR(N11185),
    .C(Flgreg_7_N1267),
    .Q(Flgreg[5])
  );
  OR2 _n00098 (
    .I0(_n00097),
    .I1(_n00095),
    .O(_n0009)
  );
  FDCE Flgreg_0 (
    .D(Hme033flg),
    .CE(_n0002),
    .CLR(N11185),
    .C(Flgreg_7_N1267),
    .Q(Flgreg[0])
  );
  FDCE Flgreg_6 (
    .D(Enc133flg),
    .CE(_n0002),
    .CLR(N11185),
    .C(Flgreg_7_N1267),
    .Q(Flgreg[6])
  );
  AND2 _n00023 (
    .I0(_n00021),
    .I1(_n00022),
    .O(_n0002)
  );
  FDCE Flgreg_3 (
    .D(Enc05flg),
    .CE(_n0002),
    .CLR(N11185),
    .C(Flgreg_7_N1267),
    .Q(Flgreg[3])
  );
  AND8 orFLGs1 (
    .I0(Enc133flg),
    .I1(Hme15flg),
    .I2(Hme133flg),
    .I3(Enc05flg),
    .I4(Enc033flg),
    .I5(Hme05flg),
    .I6(Hme033flg),
    .I7(Enc15flg),
    .O(orFLGs)
  );
  FDCE ctrlr_1 (
    .D(inDATA[1]),
    .CE(DCORENCPWRw),
    .CLR(Reset),
    .C(Flgreg_7_N1267),
    .Q(ctrlr[1])
  );
  FDCE ctrlr_0 (
    .D(inDATA[0]),
    .CE(DCORENCPWRw),
    .CLR(Reset),
    .C(Flgreg_7_N1267),
    .Q(ctrlr[0])
  );
  INV Hme15ctl1 (
    .I(ctrlr[5]),
    .O(Hme15ctl)
  );
  INV Hme133ctl1 (
    .I(ctrlr[4]),
    .O(Hme133ctl)
  );
  FDCE ctrlr_6 (
    .D(inDATA[6]),
    .CE(DCORENCPWRw),
    .CLR(Reset),
    .C(Flgreg_7_N1267),
    .Q(ctrlr[6])
  );
  FDCE ctrlr_7 (
    .D(inDATA[7]),
    .CE(DCORENCPWRw),
    .CLR(Reset),
    .C(Flgreg_7_N1267),
    .Q(ctrlr[7])
  );
  INV Hme05ctl1 (
    .I(ctrlr[1]),
    .O(Hme05ctl)
  );
  INV Hme033ctl1 (
    .I(ctrlr[0]),
    .O(Hme033ctl)
  );
  OR2 Mmux__n0008_Result4 (
    .I0(Mmux__n0008_Result),
    .I1(Mmux__n0008_Result2),
    .O(_n0008)
  );
  OR2 Mmux__n0007_Result4 (
    .I0(Mmux__n0007_Result),
    .I1(Mmux__n0007_Result2),
    .O(_n0007)
  );
  OR2 Mmux__n0006_Result4 (
    .I0(Mmux__n0006_Result),
    .I1(Mmux__n0006_Result2),
    .O(_n0006)
  );
  OR2 Mmux__n0005_Result4 (
    .I0(Mmux__n0005_Result),
    .I1(Mmux__n0005_Result2),
    .O(_n0005)
  );
  OR2 Mmux__n0004_Result4 (
    .I0(Mmux__n0004_Result),
    .I1(Mmux__n0004_Result2),
    .O(_n0004)
  );
  OR2 Mmux__n0003_Result4 (
    .I0(Mmux__n0003_Result),
    .I1(Mmux__n0003_Result2),
    .O(_n0003)
  );
  BUFE I10_0 (
    .E(DCORENCPWRr),
    .I(_n0011),
    .O(outDATA[0])
  );
  BUFE I9_0 (
    .E(_n0032),
    .I(_n0009),
    .O(outDATA[1])
  );
  BUFE I8_0 (
    .E(DCORENCPWRr),
    .I(_n0008),
    .O(outDATA[2])
  );
  BUFE I7_0 (
    .E(DCORENCPWRr),
    .I(_n0007),
    .O(outDATA[3])
  );
  BUFE I6_0 (
    .E(DCORENCPWRr),
    .I(_n0006),
    .O(outDATA[4])
  );
  BUFE I5_0 (
    .E(DCORENCPWRr),
    .I(_n0005),
    .O(outDATA[5])
  );
  FDCE DCORIFG (
    .D(DCORIFG__n0000),
    .CE(DCORIFG__n0002),
    .CLR(N11185),
    .C(Flgreg_7_N1267),
    .Q(NlwRenamedSig_OI_PWRint)
  );
  INV Flgreg_7_N12671 (
    .I(Mclk),
    .O(Flgreg_7_N1267)
  );
  FDCE ctrlr_3 (
    .D(inDATA[3]),
    .CE(DCORENCPWRw),
    .CLR(Reset),
    .C(Flgreg_7_N1267),
    .Q(ctrlr[3])
  );
  BUFE I3_0 (
    .E(DCORENCPWRr),
    .I(_n0003),
    .O(outDATA[7])
  );
  BUFE I4_0 (
    .E(DCORENCPWRr),
    .I(_n0004),
    .O(outDATA[6])
  );
  FDCE ctrlr_4 (
    .D(inDATA[4]),
    .CE(DCORENCPWRw),
    .CLR(Reset),
    .C(Flgreg_7_N1267),
    .Q(ctrlr[4])
  );
  INV DCORIFG__n00023 (
    .I(DCORIFG__n00022),
    .O(DCORIFG__n0002)
  );
  FDCE Flgreg_2 (
    .D(Enc033flg),
    .CE(_n0002),
    .CLR(N11185),
    .C(Flgreg_7_N1267),
    .Q(Flgreg[2])
  );
  GND XST_GND (
    .G(N11185)
  );
  FDCE Flgreg_7 (
    .D(Enc15flg),
    .CE(_n0002),
    .CLR(N11185),
    .C(Flgreg_7_N1267),
    .Q(Flgreg[7])
  );
  INV _n00321_2173 (
    .I(DCORENCPWRr),
    .O(_n00321)
  );
  INV _n00322_2174 (
    .I(DCORIFGr),
    .O(_n00322)
  );
  AND2 _n00323_2175 (
    .I0(_n00321),
    .I1(_n00322),
    .O(_n00323)
  );
  INV DCORIFG__n00001_2176 (
    .I(inDATA[1]),
    .O(DCORIFG__n00001)
  );
  INV DCORIFG__n00002_2177 (
    .I(DCORIFGw),
    .O(DCORIFG__n00002)
  );
  INV DCORIFG__n00003_2178 (
    .I(Reset),
    .O(DCORIFG__n00003)
  );
  AND2 DCORIFG__n00004_2179 (
    .I0(NlwRenamedSig_OI_PWRint),
    .I1(DCORIFG__n00001),
    .O(DCORIFG__n00004)
  );
  OR2 DCORIFG__n00005_2180 (
    .I0(DCORIFG__n00004),
    .I1(DCORIFG__n00002),
    .O(DCORIFG__n00005)
  );
  INV _n00201_2181 (
    .I(DCORIFGw),
    .O(_n00201)
  );
  INV Enc15ctl1_2182 (
    .I(ctrlr[6]),
    .O(Enc15ctl1)
  );
  AND2 Enc15ctl2_2183 (
    .I0(ctrlr[7]),
    .I1(Enc15ctl1),
    .O(Enc15ctl2)
  );
  AND2 Enc133ctl1_2184 (
    .I0(ctrlr[7]),
    .I1(ctrlr[6]),
    .O(Enc133ctl1)
  );
  INV Enc05ctl1_2185 (
    .I(ctrlr[2]),
    .O(Enc05ctl1)
  );
  AND2 Enc05ctl2_2186 (
    .I0(ctrlr[3]),
    .I1(Enc05ctl1),
    .O(Enc05ctl2)
  );
  AND2 Mmux__n0011_Result1_2187 (
    .I0(NlwRenamedSig_OI_PWRint),
    .I1(Flgreg[0]),
    .O(Mmux__n0011_Result)
  );
  INV Mmux__n0011_Result2_2188 (
    .I(NlwRenamedSig_OI_PWRint),
    .O(Mmux__n0011_Result1)
  );
  AND2 Mmux__n0011_Result3 (
    .I0(Hme033flg),
    .I1(Mmux__n0011_Result1),
    .O(Mmux__n0011_Result2)
  );
  INV Enc033ctl1_2189 (
    .I(ctrlr[3]),
    .O(Enc033ctl1)
  );
  AND2 Enc033ctl2_2190 (
    .I0(ctrlr[2]),
    .I1(Enc033ctl1),
    .O(Enc033ctl2)
  );
  INV _n00091_2191 (
    .I(Flgreg[1]),
    .O(_n00091)
  );
  AND2 _n00092_2192 (
    .I0(DCORENCPWRr),
    .I1(Hme05flg),
    .O(_n00092)
  );
  INV _n00093_2193 (
    .I(NlwRenamedSig_OI_PWRint),
    .O(_n00093)
  );
  AND2 _n00094_2194 (
    .I0(DCORENCPWRr),
    .I1(_n00091),
    .O(_n00094)
  );
  AND2 _n00095_2195 (
    .I0(_n00092),
    .I1(_n00093),
    .O(_n00095)
  );
  INV _n00096_2196 (
    .I(_n00094),
    .O(_n00096)
  );
  AND2 _n00097_2197 (
    .I0(NlwRenamedSig_OI_PWRint),
    .I1(_n00096),
    .O(_n00097)
  );
  INV _n00021_2198 (
    .I(orFLGs),
    .O(_n00021)
  );
  INV _n00022_2199 (
    .I(NlwRenamedSig_OI_PWRint),
    .O(_n00022)
  );
  AND2 Mmux__n0008_Result1_2200 (
    .I0(NlwRenamedSig_OI_PWRint),
    .I1(Flgreg[2]),
    .O(Mmux__n0008_Result)
  );
  INV Mmux__n0008_Result2_2201 (
    .I(NlwRenamedSig_OI_PWRint),
    .O(Mmux__n0008_Result1)
  );
  AND2 Mmux__n0008_Result3 (
    .I0(Enc033flg),
    .I1(Mmux__n0008_Result1),
    .O(Mmux__n0008_Result2)
  );
  AND2 Mmux__n0007_Result1_2202 (
    .I0(NlwRenamedSig_OI_PWRint),
    .I1(Flgreg[3]),
    .O(Mmux__n0007_Result)
  );
  INV Mmux__n0007_Result2_2203 (
    .I(NlwRenamedSig_OI_PWRint),
    .O(Mmux__n0007_Result1)
  );
  AND2 Mmux__n0007_Result3 (
    .I0(Enc05flg),
    .I1(Mmux__n0007_Result1),
    .O(Mmux__n0007_Result2)
  );
  AND2 Mmux__n0006_Result1_2204 (
    .I0(NlwRenamedSig_OI_PWRint),
    .I1(Flgreg[4]),
    .O(Mmux__n0006_Result)
  );
  INV Mmux__n0006_Result2_2205 (
    .I(NlwRenamedSig_OI_PWRint),
    .O(Mmux__n0006_Result1)
  );
  AND2 Mmux__n0006_Result3 (
    .I0(Hme133flg),
    .I1(Mmux__n0006_Result1),
    .O(Mmux__n0006_Result2)
  );
  AND2 Mmux__n0005_Result1_2206 (
    .I0(NlwRenamedSig_OI_PWRint),
    .I1(Flgreg[5]),
    .O(Mmux__n0005_Result)
  );
  INV Mmux__n0005_Result2_2207 (
    .I(NlwRenamedSig_OI_PWRint),
    .O(Mmux__n0005_Result1)
  );
  AND2 Mmux__n0005_Result3 (
    .I0(Hme15flg),
    .I1(Mmux__n0005_Result1),
    .O(Mmux__n0005_Result2)
  );
  AND2 Mmux__n0004_Result1_2208 (
    .I0(NlwRenamedSig_OI_PWRint),
    .I1(Flgreg[6]),
    .O(Mmux__n0004_Result)
  );
  INV Mmux__n0004_Result2_2209 (
    .I(NlwRenamedSig_OI_PWRint),
    .O(Mmux__n0004_Result1)
  );
  AND2 Mmux__n0004_Result3 (
    .I0(Enc133flg),
    .I1(Mmux__n0004_Result1),
    .O(Mmux__n0004_Result2)
  );
  AND2 Mmux__n0003_Result1_2210 (
    .I0(NlwRenamedSig_OI_PWRint),
    .I1(Flgreg[7]),
    .O(Mmux__n0003_Result)
  );
  INV Mmux__n0003_Result2_2211 (
    .I(NlwRenamedSig_OI_PWRint),
    .O(Mmux__n0003_Result1)
  );
  AND2 Mmux__n0003_Result3 (
    .I0(Enc15flg),
    .I1(Mmux__n0003_Result1),
    .O(Mmux__n0003_Result2)
  );
  INV DCORIFG__n00021_2212 (
    .I(Reset),
    .O(DCORIFG__n00021)
  );
  AND2 DCORIFG__n00022_2213 (
    .I0(_n0020),
    .I1(DCORIFG__n00021),
    .O(DCORIFG__n00022)
  );
endmodule

module Lswitch (
  Brake0, Brake1, DCORLINTr, Reset, DCORLIMITSr, Home0, Home1, RLS0, RLS1, DCORIFGw, FLS0, FLS1, LIFG, DIR0, DIR1, Mclk, fBRK0, fBRK1, LSwitchInt, 
outDATA
);
  input Brake0;
  input Brake1;
  input DCORLINTr;
  input Reset;
  input DCORLIMITSr;
  input Home0;
  input Home1;
  input RLS0;
  input RLS1;
  input DCORIFGw;
  input FLS0;
  input FLS1;
  input LIFG;
  input DIR0;
  input DIR1;
  input Mclk;
  output fBRK0;
  output fBRK1;
  output LSwitchInt;
  output [7 : 0] outDATA;
  wire _n0011_4_;
  wire NlwRenamedSig_OI_fBRK0;
  wire NlwRenamedSig_OI_fBRK1;
  wire NlwRenamedSig_OI_LSwitchInt;
  wire RLS0fr;
  wire RLS1fr;
  wire RLS0r;
  wire RLS1r;
  wire DCORIFG__n0002;
  wire _n0011_5_;
  wire _n0011_0_;
  wire _n0006;
  wire FLS0r;
  wire Ftrip0;
  wire _n0013;
  wire _n0011_6_;
  wire Ftrip1;
  wire _n0014;
  wire _n0011_2_;
  wire FLS1r__n0000;
  wire FLS0fr__n0002;
  wire FLS1r;
  wire fBRK1r_N1267;
  wire _n0018;
  wire DCORIFG__n0000;
  wire _n0030;
  wire _n0031;
  wire FLS0r__n0000;
  wire RLS1fr__n0002;
  wire RLS0r__n0000;
  wire N1248;
  wire Rtrip12;
  wire RLS0fr__n0002;
  wire _n0029;
  wire FLS1fr__n0002;
  wire RLS1r__n0000;
  wire _n0011_1_;
  wire FLS1fr;
  wire Rtrip0;
  wire Rtrip1;
  wire FLS0fr;
  wire FLS1r__n00001;
  wire Mmux__n0011_I2_Result;
  wire Mmux__n0011_I2_Result1;
  wire Mmux__n0011_I2_Result2;
  wire Mmux__n0011_I2_Result3;
  wire Mmux__n0011_I3_Result;
  wire Mmux__n0011_I3_Result1;
  wire Mmux__n0011_I3_Result2;
  wire Mmux__n0011_I3_Result3;
  wire DCORIFG__n00021;
  wire DCORIFG__n00022;
  wire RLS1fr__n00021;
  wire RLS1fr__n00022;
  wire FLS0r__n00001;
  wire FLS0fr__n00021;
  wire FLS0fr__n00022;
  wire _n00311;
  wire _n00312;
  wire _n00313;
  wire RLS0fr__n00021;
  wire RLS0fr__n00022;
  wire Mmux__n0011_I7_Result;
  wire Mmux__n0011_I7_Result1;
  wire Mmux__n0011_I7_Result2;
  wire Mmux__n0011_I7_Result3;
  wire _n00301;
  wire _n00302;
  wire _n00303;
  wire _n00304;
  wire _n00305;
  wire _n00306;
  wire _n00307;
  wire _n00308;
  wire _n00309;
  wire _n003010;
  wire RLS1r__n00001;
  wire FLS1fr__n00021;
  wire FLS1fr__n00022;
  wire _n00291;
  wire _n00292;
  wire _n00293;
  wire _n00294;
  wire _n00295;
  wire _n00296;
  wire _n00297;
  wire _n00298;
  wire _n00299;
  wire _n002910;
  wire DCORIFG__n00001;
  wire DCORIFG__n00002;
  wire DCORIFG__n00003;
  wire DCORIFG__n00004;
  wire DCORIFG__n00005;
  wire Mmux__n0011_I6_Result;
  wire Mmux__n0011_I6_Result1;
  wire Mmux__n0011_I6_Result2;
  wire Mmux__n0011_I6_Result3;
  wire _n00181;
  wire _n00182;
  wire _n00183;
  wire _n00184;
  wire _n00185;
  wire _n00141;
  wire _n00142;
  wire _n00143;
  wire _n00144;
  wire _n00145;
  wire _n00146;
  wire _n00131;
  wire _n00132;
  wire _n00133;
  wire _n00134;
  wire _n00135;
  wire _n00136;
  wire _n00061;
  wire _n00062;
  wire RLS0r__n00001;
  wire Ftrip01;
  wire Ftrip02;
  wire Rtrip01;
  wire Rtrip02;
  wire Ftrip11;
  wire Ftrip12;
  wire Rtrip11;
  assign
    fBRK0 = NlwRenamedSig_OI_fBRK0,
    fBRK1 = NlwRenamedSig_OI_fBRK1,
    LSwitchInt = NlwRenamedSig_OI_LSwitchInt;
  AND2 FLS1r__n00002 (
    .I0(FLS1),
    .I1(FLS1r__n00001),
    .O(FLS1r__n0000)
  );
  BUFE I11_7 (
    .E(_n0031),
    .I(NlwRenamedSig_OI_fBRK1),
    .O(outDATA[7])
  );
  FDCE fBRK1r (
    .D(_n0014),
    .CE(_n0030),
    .CLR(N1248),
    .C(fBRK1r_N1267),
    .Q(NlwRenamedSig_OI_fBRK1)
  );
  GND XST_GND (
    .G(N1248)
  );
  AND2 Mmux__n0011_I1_Result1 (
    .I0(DCORLIMITSr),
    .I1(Home1),
    .O(_n0011_6_)
  );
  OR2 Mmux__n0011_I2_Result5 (
    .I0(Mmux__n0011_I2_Result2),
    .I1(Mmux__n0011_I2_Result3),
    .O(_n0011_5_)
  );
  OR2 Mmux__n0011_I3_Result5 (
    .I0(Mmux__n0011_I3_Result2),
    .I1(Mmux__n0011_I3_Result3),
    .O(_n0011_4_)
  );
  INV DCORIFG__n00023 (
    .I(DCORIFG__n00022),
    .O(DCORIFG__n0002)
  );
  INV RLS1fr__n00023 (
    .I(RLS1fr__n00022),
    .O(RLS1fr__n0002)
  );
  AND2 FLS0r__n00002 (
    .I0(FLS0),
    .I1(FLS0r__n00001),
    .O(FLS0r__n0000)
  );
  INV FLS0fr__n00023 (
    .I(FLS0fr__n00022),
    .O(FLS0fr__n0002)
  );
  INV Rtrip12_2338 (
    .I(DIR1),
    .O(Rtrip12)
  );
  AND2 Mmux__n0011_I5_Result1 (
    .I0(DCORLIMITSr),
    .I1(Home0),
    .O(_n0011_2_)
  );
  INV _n00314 (
    .I(_n00313),
    .O(_n0031)
  );
  INV RLS0fr__n00023 (
    .I(RLS0fr__n00022),
    .O(RLS0fr__n0002)
  );
  OR2 Mmux__n0011_I7_Result5 (
    .I0(Mmux__n0011_I7_Result2),
    .I1(Mmux__n0011_I7_Result3),
    .O(_n0011_0_)
  );
  AND3 _n003011 (
    .I0(_n00305),
    .I1(_n003010),
    .I2(_n00306),
    .O(_n0030)
  );
  AND2 RLS1r__n00002 (
    .I0(RLS1),
    .I1(RLS1r__n00001),
    .O(RLS1r__n0000)
  );
  INV FLS1fr__n00023 (
    .I(FLS1fr__n00022),
    .O(FLS1fr__n0002)
  );
  AND3 _n002911 (
    .I0(_n00295),
    .I1(_n002910),
    .I2(_n00296),
    .O(_n0029)
  );
  AND2 DCORIFG__n00006 (
    .I0(DCORIFG__n00005),
    .I1(DCORIFG__n00003),
    .O(DCORIFG__n0000)
  );
  OR2 Mmux__n0011_I6_Result5 (
    .I0(Mmux__n0011_I6_Result2),
    .I1(Mmux__n0011_I6_Result3),
    .O(_n0011_1_)
  );
  AND5 _n00186 (
    .I0(_n00182),
    .I1(_n00181),
    .I2(_n00183),
    .I3(_n00184),
    .I4(_n00185),
    .O(_n0018)
  );
  OR2 _n00147 (
    .I0(_n00145),
    .I1(_n00146),
    .O(_n0014)
  );
  OR2 _n00137 (
    .I0(_n00135),
    .I1(_n00136),
    .O(_n0013)
  );
  FDCE FLS0fr_2339 (
    .D(_n0006),
    .CE(FLS0fr__n0002),
    .CLR(N1248),
    .C(fBRK1r_N1267),
    .Q(FLS0fr)
  );
  FDCE RLS0fr_2340 (
    .D(_n0006),
    .CE(RLS0fr__n0002),
    .CLR(N1248),
    .C(fBRK1r_N1267),
    .Q(RLS0fr)
  );
  AND2 _n00063 (
    .I0(_n00061),
    .I1(_n00062),
    .O(_n0006)
  );
  AND2 RLS0r__n00002 (
    .I0(RLS0),
    .I1(RLS0r__n00001),
    .O(RLS0r__n0000)
  );
  AND2 Ftrip03 (
    .I0(Ftrip01),
    .I1(Ftrip02),
    .O(Ftrip0)
  );
  AND3 Rtrip03 (
    .I0(Rtrip01),
    .I1(RLS0r),
    .I2(Rtrip02),
    .O(Rtrip0)
  );
  AND2 Ftrip13 (
    .I0(Ftrip11),
    .I1(Ftrip12),
    .O(Ftrip1)
  );
  AND3 Rtrip13 (
    .I0(Rtrip11),
    .I1(RLS1r),
    .I2(Rtrip12),
    .O(Rtrip1)
  );
  FDCE fBRK0r (
    .D(_n0013),
    .CE(_n0029),
    .CLR(N1248),
    .C(fBRK1r_N1267),
    .Q(NlwRenamedSig_OI_fBRK0)
  );
  FD FLS0r_2341 (
    .D(FLS0r__n0000),
    .C(fBRK1r_N1267),
    .Q(FLS0r)
  );
  FD RLS0r_2342 (
    .D(RLS0r__n0000),
    .C(fBRK1r_N1267),
    .Q(RLS0r)
  );
  FDCE DCORIFG (
    .D(DCORIFG__n0000),
    .CE(DCORIFG__n0002),
    .CLR(N1248),
    .C(fBRK1r_N1267),
    .Q(NlwRenamedSig_OI_LSwitchInt)
  );
  FDCE RLS1fr_2343 (
    .D(_n0006),
    .CE(RLS1fr__n0002),
    .CLR(N1248),
    .C(fBRK1r_N1267),
    .Q(RLS1fr)
  );
  FDCE FLS1fr_2344 (
    .D(_n0006),
    .CE(FLS1fr__n0002),
    .CLR(N1248),
    .C(fBRK1r_N1267),
    .Q(FLS1fr)
  );
  FD RLS1r_2345 (
    .D(RLS1r__n0000),
    .C(fBRK1r_N1267),
    .Q(RLS1r)
  );
  FD FLS1r_2346 (
    .D(FLS1r__n0000),
    .C(fBRK1r_N1267),
    .Q(FLS1r)
  );
  INV fBRK1r_N12671 (
    .I(Mclk),
    .O(fBRK1r_N1267)
  );
  BUFE I11_6 (
    .E(_n0031),
    .I(_n0011_6_),
    .O(outDATA[6])
  );
  BUFE I11_0 (
    .E(_n0031),
    .I(_n0011_0_),
    .O(outDATA[0])
  );
  BUFE I11_1 (
    .E(_n0031),
    .I(_n0011_1_),
    .O(outDATA[1])
  );
  BUFE I11_2 (
    .E(_n0031),
    .I(_n0011_2_),
    .O(outDATA[2])
  );
  BUFE I11_3 (
    .E(_n0031),
    .I(NlwRenamedSig_OI_fBRK0),
    .O(outDATA[3])
  );
  BUFE I11_4 (
    .E(_n0031),
    .I(_n0011_4_),
    .O(outDATA[4])
  );
  BUFE I11_5 (
    .E(_n0031),
    .I(_n0011_5_),
    .O(outDATA[5])
  );
  INV FLS1r__n00001_2347 (
    .I(Reset),
    .O(FLS1r__n00001)
  );
  INV Mmux__n0011_I2_Result1_2348 (
    .I(DCORLIMITSr),
    .O(Mmux__n0011_I2_Result)
  );
  INV Mmux__n0011_I2_Result2_2349 (
    .I(FLS1),
    .O(Mmux__n0011_I2_Result1)
  );
  AND2 Mmux__n0011_I2_Result3_2350 (
    .I0(FLS1fr),
    .I1(Mmux__n0011_I2_Result),
    .O(Mmux__n0011_I2_Result2)
  );
  AND2 Mmux__n0011_I2_Result4 (
    .I0(DCORLIMITSr),
    .I1(Mmux__n0011_I2_Result1),
    .O(Mmux__n0011_I2_Result3)
  );
  INV Mmux__n0011_I3_Result1_2351 (
    .I(DCORLIMITSr),
    .O(Mmux__n0011_I3_Result)
  );
  INV Mmux__n0011_I3_Result2_2352 (
    .I(RLS1),
    .O(Mmux__n0011_I3_Result1)
  );
  AND2 Mmux__n0011_I3_Result3_2353 (
    .I0(RLS1fr),
    .I1(Mmux__n0011_I3_Result),
    .O(Mmux__n0011_I3_Result2)
  );
  AND2 Mmux__n0011_I3_Result4 (
    .I0(DCORLIMITSr),
    .I1(Mmux__n0011_I3_Result1),
    .O(Mmux__n0011_I3_Result3)
  );
  INV DCORIFG__n00021_2354 (
    .I(Reset),
    .O(DCORIFG__n00021)
  );
  AND2 DCORIFG__n00022_2355 (
    .I0(_n0018),
    .I1(DCORIFG__n00021),
    .O(DCORIFG__n00022)
  );
  INV RLS1fr__n00021_2356 (
    .I(Rtrip1),
    .O(RLS1fr__n00021)
  );
  AND2 RLS1fr__n00022_2357 (
    .I0(_n0006),
    .I1(RLS1fr__n00021),
    .O(RLS1fr__n00022)
  );
  INV FLS0r__n00001_2358 (
    .I(Reset),
    .O(FLS0r__n00001)
  );
  INV FLS0fr__n00021_2359 (
    .I(Ftrip0),
    .O(FLS0fr__n00021)
  );
  AND2 FLS0fr__n00022_2360 (
    .I0(_n0006),
    .I1(FLS0fr__n00021),
    .O(FLS0fr__n00022)
  );
  INV _n00311_2361 (
    .I(DCORLIMITSr),
    .O(_n00311)
  );
  INV _n00312_2362 (
    .I(DCORLINTr),
    .O(_n00312)
  );
  AND2 _n00313_2363 (
    .I0(_n00311),
    .I1(_n00312),
    .O(_n00313)
  );
  INV RLS0fr__n00021_2364 (
    .I(Rtrip0),
    .O(RLS0fr__n00021)
  );
  AND2 RLS0fr__n00022_2365 (
    .I0(_n0006),
    .I1(RLS0fr__n00021),
    .O(RLS0fr__n00022)
  );
  INV Mmux__n0011_I7_Result1_2366 (
    .I(DCORLIMITSr),
    .O(Mmux__n0011_I7_Result)
  );
  INV Mmux__n0011_I7_Result2_2367 (
    .I(RLS0),
    .O(Mmux__n0011_I7_Result1)
  );
  AND2 Mmux__n0011_I7_Result3_2368 (
    .I0(RLS0fr),
    .I1(Mmux__n0011_I7_Result),
    .O(Mmux__n0011_I7_Result2)
  );
  AND2 Mmux__n0011_I7_Result4 (
    .I0(DCORLIMITSr),
    .I1(Mmux__n0011_I7_Result1),
    .O(Mmux__n0011_I7_Result3)
  );
  INV _n00301_2369 (
    .I(RLS1fr),
    .O(_n00301)
  );
  INV _n00302_2370 (
    .I(FLS1fr),
    .O(_n00302)
  );
  INV _n00303_2371 (
    .I(Rtrip1),
    .O(_n00303)
  );
  INV _n00304_2372 (
    .I(Ftrip1),
    .O(_n00304)
  );
  INV _n00305_2373 (
    .I(Reset),
    .O(_n00305)
  );
  INV _n00306_2374 (
    .I(DCORLINTr),
    .O(_n00306)
  );
  AND3 _n00307_2375 (
    .I0(_n00301),
    .I1(Brake1),
    .I2(_n00302),
    .O(_n00307)
  );
  AND2 _n00308_2376 (
    .I0(_n00303),
    .I1(_n00304),
    .O(_n00308)
  );
  INV _n00309_2377 (
    .I(_n00308),
    .O(_n00309)
  );
  OR2 _n003010_2378 (
    .I0(_n00307),
    .I1(_n00309),
    .O(_n003010)
  );
  INV RLS1r__n00001_2379 (
    .I(Reset),
    .O(RLS1r__n00001)
  );
  INV FLS1fr__n00021_2380 (
    .I(Ftrip1),
    .O(FLS1fr__n00021)
  );
  AND2 FLS1fr__n00022_2381 (
    .I0(_n0006),
    .I1(FLS1fr__n00021),
    .O(FLS1fr__n00022)
  );
  INV _n00291_2382 (
    .I(RLS0fr),
    .O(_n00291)
  );
  INV _n00292_2383 (
    .I(FLS0fr),
    .O(_n00292)
  );
  INV _n00293_2384 (
    .I(Rtrip0),
    .O(_n00293)
  );
  INV _n00294_2385 (
    .I(Ftrip0),
    .O(_n00294)
  );
  INV _n00295_2386 (
    .I(Reset),
    .O(_n00295)
  );
  INV _n00296_2387 (
    .I(DCORLINTr),
    .O(_n00296)
  );
  AND3 _n00297_2388 (
    .I0(_n00291),
    .I1(Brake0),
    .I2(_n00292),
    .O(_n00297)
  );
  AND2 _n00298_2389 (
    .I0(_n00293),
    .I1(_n00294),
    .O(_n00298)
  );
  INV _n00299_2390 (
    .I(_n00298),
    .O(_n00299)
  );
  OR2 _n002910_2391 (
    .I0(_n00297),
    .I1(_n00299),
    .O(_n002910)
  );
  INV DCORIFG__n00001_2392 (
    .I(LIFG),
    .O(DCORIFG__n00001)
  );
  INV DCORIFG__n00002_2393 (
    .I(DCORIFGw),
    .O(DCORIFG__n00002)
  );
  INV DCORIFG__n00003_2394 (
    .I(Reset),
    .O(DCORIFG__n00003)
  );
  AND2 DCORIFG__n00004_2395 (
    .I0(NlwRenamedSig_OI_LSwitchInt),
    .I1(DCORIFG__n00001),
    .O(DCORIFG__n00004)
  );
  OR2 DCORIFG__n00005_2396 (
    .I0(DCORIFG__n00004),
    .I1(DCORIFG__n00002),
    .O(DCORIFG__n00005)
  );
  INV Mmux__n0011_I6_Result1_2397 (
    .I(DCORLIMITSr),
    .O(Mmux__n0011_I6_Result)
  );
  INV Mmux__n0011_I6_Result2_2398 (
    .I(FLS0),
    .O(Mmux__n0011_I6_Result1)
  );
  AND2 Mmux__n0011_I6_Result3_2399 (
    .I0(FLS0fr),
    .I1(Mmux__n0011_I6_Result),
    .O(Mmux__n0011_I6_Result2)
  );
  AND2 Mmux__n0011_I6_Result4 (
    .I0(DCORLIMITSr),
    .I1(Mmux__n0011_I6_Result1),
    .O(Mmux__n0011_I6_Result3)
  );
  INV _n00181_2400 (
    .I(RLS0fr),
    .O(_n00181)
  );
  INV _n00182_2401 (
    .I(DCORIFGw),
    .O(_n00182)
  );
  INV _n00183_2402 (
    .I(FLS1fr),
    .O(_n00183)
  );
  INV _n00184_2403 (
    .I(RLS1fr),
    .O(_n00184)
  );
  INV _n00185_2404 (
    .I(FLS0fr),
    .O(_n00185)
  );
  AND2 _n00141_2405 (
    .I0(FLS1r),
    .I1(DIR1),
    .O(_n00141)
  );
  INV _n00142_2406 (
    .I(FLS1),
    .O(_n00142)
  );
  INV _n00143_2407 (
    .I(RLS1),
    .O(_n00143)
  );
  INV _n00144_2408 (
    .I(DIR1),
    .O(_n00144)
  );
  AND2 _n00145_2409 (
    .I0(_n00141),
    .I1(_n00142),
    .O(_n00145)
  );
  AND3 _n00146_2410 (
    .I0(_n00143),
    .I1(RLS1r),
    .I2(_n00144),
    .O(_n00146)
  );
  AND2 _n00131_2411 (
    .I0(FLS0r),
    .I1(DIR0),
    .O(_n00131)
  );
  INV _n00132_2412 (
    .I(FLS0),
    .O(_n00132)
  );
  INV _n00133_2413 (
    .I(RLS0),
    .O(_n00133)
  );
  INV _n00134_2414 (
    .I(DIR0),
    .O(_n00134)
  );
  AND2 _n00135_2415 (
    .I0(_n00131),
    .I1(_n00132),
    .O(_n00135)
  );
  AND3 _n00136_2416 (
    .I0(_n00133),
    .I1(RLS0r),
    .I2(_n00134),
    .O(_n00136)
  );
  INV _n00061_2417 (
    .I(DCORLINTr),
    .O(_n00061)
  );
  INV _n00062_2418 (
    .I(Reset),
    .O(_n00062)
  );
  INV RLS0r__n00001_2419 (
    .I(Reset),
    .O(RLS0r__n00001)
  );
  AND2 Ftrip01_2420 (
    .I0(FLS0r),
    .I1(DIR0),
    .O(Ftrip01)
  );
  INV Ftrip02_2421 (
    .I(FLS0),
    .O(Ftrip02)
  );
  INV Rtrip01_2422 (
    .I(RLS0),
    .O(Rtrip01)
  );
  INV Rtrip02_2423 (
    .I(DIR0),
    .O(Rtrip02)
  );
  AND2 Ftrip11_2424 (
    .I0(FLS1r),
    .I1(DIR1),
    .O(Ftrip11)
  );
  INV Ftrip12_2425 (
    .I(FLS1),
    .O(Ftrip12)
  );
  INV Rtrip11_2426 (
    .I(RLS1),
    .O(Rtrip11)
  );
endmodule

module I2CAddress (
  DCORCONFIGr, MotorIn0, MotorIn1, I2CS, outDATA
);
  input DCORCONFIGr;
  input MotorIn0;
  input MotorIn1;
  input [5 : 0] I2CS;
  output [7 : 0] outDATA;
  BUFE I7_0 (
    .E(DCORCONFIGr),
    .I(I2CS[0]),
    .O(outDATA[0])
  );
  BUFE I6_0 (
    .E(DCORCONFIGr),
    .I(I2CS[1]),
    .O(outDATA[1])
  );
  BUFE I0_0 (
    .E(DCORCONFIGr),
    .I(MotorIn1),
    .O(outDATA[7])
  );
  BUFE I1_0 (
    .E(DCORCONFIGr),
    .I(MotorIn0),
    .O(outDATA[6])
  );
  BUFE I2_0 (
    .E(DCORCONFIGr),
    .I(I2CS[5]),
    .O(outDATA[5])
  );
  BUFE I3_0 (
    .E(DCORCONFIGr),
    .I(I2CS[4]),
    .O(outDATA[4])
  );
  BUFE I4_0 (
    .E(DCORCONFIGr),
    .I(I2CS[3]),
    .O(outDATA[3])
  );
  BUFE I5_0 (
    .E(DCORCONFIGr),
    .I(I2CS[2]),
    .O(outDATA[2])
  );
endmodule

module PWMtranslator (
  PWM, RLS, DIR, fBRK, FLS, Brake, HBRK, MTRpwr, PAH, PAL, PBH, PBL
);
  input PWM;
  input RLS;
  input DIR;
  input fBRK;
  input FLS;
  input Brake;
  input HBRK;
  input MTRpwr;
  output PAH;
  output PAL;
  output PBH;
  output PBL;
  wire BRK;
  wire PAL1;
  wire PAL2;
  wire BRK1;
  wire BRK2;
  wire BRK3;
  wire PAH1;
  wire PAH2;
  wire PBL1;
  wire PBL2;
  wire PBL3;
  wire PBL4;
  wire PBL5;
  wire PBL6;
  AND5 PBH1 (
    .I0(PWM),
    .I1(DIR),
    .I2(BRK),
    .I3(FLS),
    .I4(MTRpwr),
    .O(PBH)
  );
  AND2 PAL3 (
    .I0(PAL1),
    .I1(PAL2),
    .O(PAL)
  );
  AND3 BRK4 (
    .I0(BRK2),
    .I1(BRK1),
    .I2(BRK3),
    .O(BRK)
  );
  AND2 PAH3 (
    .I0(PAH1),
    .I1(PAH2),
    .O(PAH)
  );
  AND2 PBL7 (
    .I0(PBL1),
    .I1(PBL6),
    .O(PBL)
  );
  AND2 PAL1_2445 (
    .I0(BRK),
    .I1(MTRpwr),
    .O(PAL1)
  );
  XOR2 PAL2_2446 (
    .I0(PWM),
    .I1(DIR),
    .O(PAL2)
  );
  INV BRK1_2447 (
    .I(HBRK),
    .O(BRK1)
  );
  INV BRK2_2448 (
    .I(Brake),
    .O(BRK2)
  );
  INV BRK3_2449 (
    .I(fBRK),
    .O(BRK3)
  );
  AND4 PAH1_2450 (
    .I0(BRK),
    .I1(PWM),
    .I2(RLS),
    .I3(MTRpwr),
    .O(PAH1)
  );
  INV PAH2_2451 (
    .I(DIR),
    .O(PAH2)
  );
  AND2 PBL1_2452 (
    .I0(BRK),
    .I1(MTRpwr),
    .O(PBL1)
  );
  AND2 PBL2_2453 (
    .I0(PWM),
    .I1(DIR),
    .O(PBL2)
  );
  INV PBL3_2454 (
    .I(PWM),
    .O(PBL3)
  );
  INV PBL4_2455 (
    .I(DIR),
    .O(PBL4)
  );
  AND2 PBL5_2456 (
    .I0(PBL3),
    .I1(PBL4),
    .O(PBL5)
  );
  OR2 PBL6_2457 (
    .I0(PBL2),
    .I1(PBL5),
    .O(PBL6)
  );
endmodule

module PWMcontrol (
  Brake1, Brake2, fBRK1, fBRK2, PWM1, PWM2, RLS0, RLS1, FLS0, FLS1, HBRK1, HBRK2, DIR1, DIR2, MTRpwr, PAH1, PAH2, PAL1, PAL2, PBH1, PBH2, PBL1, PBL2
);
  input Brake1;
  input Brake2;
  input fBRK1;
  input fBRK2;
  input PWM1;
  input PWM2;
  input RLS0;
  input RLS1;
  input FLS0;
  input FLS1;
  input HBRK1;
  input HBRK2;
  input DIR1;
  input DIR2;
  input MTRpwr;
  output PAH1;
  output PAH2;
  output PAL1;
  output PAL2;
  output PBH1;
  output PBH2;
  output PBL1;
  output PBL2;
  PWMtranslator U1 (
    .PWM(PWM1),
    .RLS(RLS0),
    .DIR(DIR1),
    .fBRK(fBRK1),
    .FLS(FLS0),
    .Brake(Brake1),
    .HBRK(HBRK1),
    .MTRpwr(MTRpwr),
    .PAH(PAH1),
    .PAL(PAL1),
    .PBH(PBH1),
    .PBL(PBL1)
  );
  PWMtranslator U2 (
    .PWM(PWM2),
    .RLS(RLS1),
    .DIR(DIR2),
    .fBRK(fBRK2),
    .FLS(FLS1),
    .Brake(Brake2),
    .HBRK(HBRK2),
    .MTRpwr(MTRpwr),
    .PAH(PAH2),
    .PAL(PAL2),
    .PBH(PBH2),
    .PBL(PBL2)
  );
endmodule

module Sensor (
  Reset, DCORSENSORw, Mclk, MReset, TmpSlct, TmpEn, PresEn, PresSlct, inDATA
);
  input Reset;
  input DCORSENSORw;
  input Mclk;
  input MReset;
  output TmpSlct;
  output TmpEn;
  output PresEn;
  output PresSlct;
  input [3 : 0] inDATA;
  wire sensorr_2_;
  wire _n0002;
  wire _n0003;
  wire sensorr_0_;
  wire sensorr_3_N1274;
  wire _n00021;
  wire _n00022;
  wire _n0001_0_1;
  wire _n0001_1_1;
  wire _n0001_2_1;
  wire _n0001_3_1;
  wire [3 : 0] _n0001;
  INV _n00031 (
    .I(_n0002),
    .O(_n0003)
  );
  AND2 _n00023 (
    .I0(_n00021),
    .I1(_n00022),
    .O(_n0002)
  );
  AND2 _n0001_0_2 (
    .I0(inDATA[0]),
    .I1(_n0001_0_1),
    .O(_n0001[0])
  );
  AND2 _n0001_1_2 (
    .I0(inDATA[1]),
    .I1(_n0001_1_1),
    .O(_n0001[1])
  );
  AND2 _n0001_2_2 (
    .I0(inDATA[2]),
    .I1(_n0001_2_1),
    .O(_n0001[2])
  );
  AND2 _n0001_3_2 (
    .I0(inDATA[3]),
    .I1(_n0001_3_1),
    .O(_n0001[3])
  );
  INV sensorr_3_N12741 (
    .I(Mclk),
    .O(sensorr_3_N1274)
  );
  INV TmpEn1 (
    .I(sensorr_2_),
    .O(TmpEn)
  );
  INV PresEn1 (
    .I(sensorr_0_),
    .O(PresEn)
  );
  FDCE sensorr_3 (
    .D(_n0001[3]),
    .CE(_n0003),
    .CLR(MReset),
    .C(sensorr_3_N1274),
    .Q(TmpSlct)
  );
  FDCE sensorr_2 (
    .D(_n0001[2]),
    .CE(_n0003),
    .CLR(MReset),
    .C(sensorr_3_N1274),
    .Q(sensorr_2_)
  );
  FDCE sensorr_0 (
    .D(_n0001[0]),
    .CE(_n0003),
    .CLR(MReset),
    .C(sensorr_3_N1274),
    .Q(sensorr_0_)
  );
  FDCE sensorr_1 (
    .D(_n0001[1]),
    .CE(_n0003),
    .CLR(MReset),
    .C(sensorr_3_N1274),
    .Q(PresSlct)
  );
  INV _n00021_2499 (
    .I(DCORSENSORw),
    .O(_n00021)
  );
  INV _n00022_2500 (
    .I(Reset),
    .O(_n00022)
  );
  INV _n0001_0_1_2501 (
    .I(Reset),
    .O(_n0001_0_1)
  );
  INV _n0001_1_1_2502 (
    .I(Reset),
    .O(_n0001_1_1)
  );
  INV _n0001_2_1_2503 (
    .I(Reset),
    .O(_n0001_2_1)
  );
  INV _n0001_3_1_2504 (
    .I(Reset),
    .O(_n0001_3_1)
  );
endmodule

module MISCouts (
  LightSense, Reset, DCOROUTw, Mclk, MReset, MTRpwrn, LED1, LED2, LED3, LED4, LED5, GP_Motor0_1, GP_Motor1_1, MTRpwr, inDATA
);
  input LightSense;
  input Reset;
  input DCOROUTw;
  input Mclk;
  input MReset;
  output MTRpwrn;
  output LED1;
  output LED2;
  output LED3;
  output LED4;
  output LED5;
  output GP_Motor0_1;
  output GP_Motor1_1;
  output MTRpwr;
  input [7 : 0] inDATA;
  wire NlwRenamedSig_OI_MTRpwr;
  wire _n0002;
  wire _n0003;
  wire MISCr_7_N1274;
  wire _n00021;
  wire _n00022;
  wire _n0001_0_1;
  wire _n0001_1_1;
  wire _n0001_2_1;
  wire _n0001_3_1;
  wire _n0001_4_1;
  wire _n0001_5_1;
  wire _n0001_6_1;
  wire _n0001_7_1;
  wire LED51;
  wire LED52;
  wire LED41;
  wire LED42;
  wire LED31;
  wire LED32;
  wire LED21;
  wire LED22;
  wire LED11;
  wire LED12;
  wire [7 : 0] _n0001;
  wire [4 : 0] MISCr;
  assign
    MTRpwr = NlwRenamedSig_OI_MTRpwr;
  INV _n00031 (
    .I(_n0002),
    .O(_n0003)
  );
  AND2 _n00023 (
    .I0(_n00021),
    .I1(_n00022),
    .O(_n0002)
  );
  AND2 _n0001_0_2 (
    .I0(inDATA[0]),
    .I1(_n0001_0_1),
    .O(_n0001[0])
  );
  AND2 _n0001_1_2 (
    .I0(inDATA[1]),
    .I1(_n0001_1_1),
    .O(_n0001[1])
  );
  AND2 _n0001_2_2 (
    .I0(inDATA[2]),
    .I1(_n0001_2_1),
    .O(_n0001[2])
  );
  AND2 _n0001_3_2 (
    .I0(inDATA[3]),
    .I1(_n0001_3_1),
    .O(_n0001[3])
  );
  AND2 _n0001_4_2 (
    .I0(inDATA[4]),
    .I1(_n0001_4_1),
    .O(_n0001[4])
  );
  AND2 _n0001_5_2 (
    .I0(inDATA[5]),
    .I1(_n0001_5_1),
    .O(_n0001[5])
  );
  AND2 _n0001_6_2 (
    .I0(inDATA[6]),
    .I1(_n0001_6_1),
    .O(_n0001[6])
  );
  AND2 _n0001_7_2 (
    .I0(inDATA[7]),
    .I1(_n0001_7_1),
    .O(_n0001[7])
  );
  INV MISCr_7_N12741 (
    .I(Mclk),
    .O(MISCr_7_N1274)
  );
  INV MTRpwrn1 (
    .I(NlwRenamedSig_OI_MTRpwr),
    .O(MTRpwrn)
  );
  INV LED53 (
    .I(LED52),
    .O(LED5)
  );
  INV LED43 (
    .I(LED42),
    .O(LED4)
  );
  INV LED33 (
    .I(LED32),
    .O(LED3)
  );
  INV LED23 (
    .I(LED22),
    .O(LED2)
  );
  INV LED13 (
    .I(LED12),
    .O(LED1)
  );
  FDCE MISCr_7 (
    .D(_n0001[7]),
    .CE(_n0003),
    .CLR(MReset),
    .C(MISCr_7_N1274),
    .Q(GP_Motor1_1)
  );
  FDCE MISCr_6 (
    .D(_n0001[6]),
    .CE(_n0003),
    .CLR(MReset),
    .C(MISCr_7_N1274),
    .Q(GP_Motor0_1)
  );
  FDCE MISCr_0 (
    .D(_n0001[0]),
    .CE(_n0003),
    .CLR(MReset),
    .C(MISCr_7_N1274),
    .Q(MISCr[0])
  );
  FDCE MISCr_1 (
    .D(_n0001[1]),
    .CE(_n0003),
    .CLR(MReset),
    .C(MISCr_7_N1274),
    .Q(MISCr[1])
  );
  FDCE MISCr_2 (
    .D(_n0001[2]),
    .CE(_n0003),
    .CLR(MReset),
    .C(MISCr_7_N1274),
    .Q(MISCr[2])
  );
  FDCE MISCr_3 (
    .D(_n0001[3]),
    .CE(_n0003),
    .CLR(MReset),
    .C(MISCr_7_N1274),
    .Q(MISCr[3])
  );
  FDCE MISCr_4 (
    .D(_n0001[4]),
    .CE(_n0003),
    .CLR(MReset),
    .C(MISCr_7_N1274),
    .Q(MISCr[4])
  );
  FDCE MISCr_5 (
    .D(_n0001[5]),
    .CE(_n0003),
    .CLR(MReset),
    .C(MISCr_7_N1274),
    .Q(NlwRenamedSig_OI_MTRpwr)
  );
  INV _n00021_2547 (
    .I(DCOROUTw),
    .O(_n00021)
  );
  INV _n00022_2548 (
    .I(Reset),
    .O(_n00022)
  );
  INV _n0001_0_1_2549 (
    .I(Reset),
    .O(_n0001_0_1)
  );
  INV _n0001_1_1_2550 (
    .I(Reset),
    .O(_n0001_1_1)
  );
  INV _n0001_2_1_2551 (
    .I(Reset),
    .O(_n0001_2_1)
  );
  INV _n0001_3_1_2552 (
    .I(Reset),
    .O(_n0001_3_1)
  );
  INV _n0001_4_1_2553 (
    .I(Reset),
    .O(_n0001_4_1)
  );
  INV _n0001_5_1_2554 (
    .I(Reset),
    .O(_n0001_5_1)
  );
  INV _n0001_6_1_2555 (
    .I(Reset),
    .O(_n0001_6_1)
  );
  INV _n0001_7_1_2556 (
    .I(Reset),
    .O(_n0001_7_1)
  );
  INV LED51_2557 (
    .I(MISCr[4]),
    .O(LED51)
  );
  AND2 LED52_2558 (
    .I0(LightSense),
    .I1(LED51),
    .O(LED52)
  );
  INV LED41_2559 (
    .I(MISCr[3]),
    .O(LED41)
  );
  AND2 LED42_2560 (
    .I0(LightSense),
    .I1(LED41),
    .O(LED42)
  );
  INV LED31_2561 (
    .I(MISCr[2]),
    .O(LED31)
  );
  AND2 LED32_2562 (
    .I0(LightSense),
    .I1(LED31),
    .O(LED32)
  );
  INV LED21_2563 (
    .I(MISCr[1]),
    .O(LED21)
  );
  AND2 LED22_2564 (
    .I0(LightSense),
    .I1(LED21),
    .O(LED22)
  );
  INV LED11_2565 (
    .I(MISCr[0]),
    .O(LED11)
  );
  AND2 LED12_2566 (
    .I0(LightSense),
    .I1(LED11),
    .O(LED12)
  );
endmodule

module U21 (
  Brake0, Home033FLG, Brake1, LightSense, AS, PhaseB_Encoder0, PhaseB_Encoder1, MSPReset, INTbus, Home05FLG, Home133FLG, PhaseA_Encoder0, 
PhaseA_Encoder1, PWM1, PWM2, Home0, PWM3, Home1, PWM4, Enc033FLG, RLS0, PWM5, RLS1, GP_Motor0_0, Home15FLG, RD, Enc05FLG, GP_Motor1_0, TXI, Enc133FLG
, FLS0, FLS1, WR, Enc15FLG, MHSO, SCLreset, HSI, DIR0, DIR1, Mclk, SCLinc, MReset, SCL, Home033ctrl, MTRpwrn, Home15ctrl, TmpSlct, LED1, LED2, 
Enc05ctrl, LED3, LED4, LED5, TP10, TP12, PAH0, PAH1, Enc15ctrl, MTXI, GP_Motor0_1, TmpEn, PAL0, PAL1, Enc133ctrl, PBH0, PBH1, Enc033ctrl, PresEn, 
GPIO8, GPIO9, GP_Motor1_1, PBL0, PBL1, GPIO10, MHSI, PresSlct, Home05ctrl, HSO, INT, MTRpwr, SCLout, Home133ctrl, I2CS, AD
);
  input Brake0;
  input Home033FLG;
  input Brake1;
  input LightSense;
  input AS;
  input PhaseB_Encoder0;
  input PhaseB_Encoder1;
  input MSPReset;
  input INTbus;
  input Home05FLG;
  input Home133FLG;
  input PhaseA_Encoder0;
  input PhaseA_Encoder1;
  input PWM1;
  input PWM2;
  input Home0;
  input PWM3;
  input Home1;
  input PWM4;
  input Enc033FLG;
  input RLS0;
  input PWM5;
  input RLS1;
  input GP_Motor0_0;
  input Home15FLG;
  input RD;
  input Enc05FLG;
  input GP_Motor1_0;
  input TXI;
  input Enc133FLG;
  input FLS0;
  input FLS1;
  input WR;
  input Enc15FLG;
  input MHSO;
  input SCLreset;
  input HSI;
  input DIR0;
  input DIR1;
  input Mclk;
  input SCLinc;
  input MReset;
  inout SCL;
  output Home033ctrl;
  output MTRpwrn;
  output Home15ctrl;
  output TmpSlct;
  output LED1;
  output LED2;
  output Enc05ctrl;
  output LED3;
  output LED4;
  output LED5;
  output TP10;
  output TP12;
  output PAH0;
  output PAH1;
  output Enc15ctrl;
  output MTXI;
  output GP_Motor0_1;
  output TmpEn;
  output PAL0;
  output PAL1;
  output Enc133ctrl;
  output PBH0;
  output PBH1;
  output Enc033ctrl;
  output PresEn;
  output GPIO8;
  output GPIO9;
  output GP_Motor1_1;
  output PBL0;
  output PBL1;
  output GPIO10;
  output MHSI;
  output PresSlct;
  output Home05ctrl;
  output HSO;
  output INT;
  output MTRpwr;
  output SCLout;
  output Home133ctrl;
  input [5 : 0] I2CS;
  inout [7 : 0] AD;
  wire NET2575;
  wire Home033ctrl_OBUF;
  wire Brake0_IBUF;
  wire Home033FLG_IBUF;
  wire Brake1_IBUF;
  wire LightSense_IBUF;
  wire MTRpwrn_OBUF;
  wire Home15ctrl_OBUF;
  wire AS_IBUF;
  wire TmpSlct_OBUF;
  wire PhaseB_Encoder0_IBUF;
  wire PhaseB_Encoder1_IBUF;
  wire MSPReset_IBUF;
  wire INTbus_IBUF;
  wire LED1_OBUF;
  wire LED2_OBUF;
  wire Enc05ctrl_OBUF;
  wire LED3_OBUF;
  wire LED4_OBUF;
  wire LED5_OBUF;
  wire Home05FLG_IBUF;
  wire Home133FLG_IBUF;
  wire TP10_OBUF;
  wire TP12_OBUF;
  wire PhaseA_Encoder0_IBUF;
  wire PhaseA_Encoder1_IBUF;
  wire PWM1_IBUF;
  wire PWM2_IBUF;
  wire Home0_IBUF;
  wire PWM3_IBUF;
  wire Home1_IBUF;
  wire PAH0_OBUF;
  wire PWM4_IBUF;
  wire Enc033FLG_IBUF;
  wire PAH1_OBUF;
  wire RLS0_IBUF;
  wire NET2501;
  wire RLS1_IBUF;
  wire Enc15ctrl_OBUF;
  wire GP_Motor0_0_IBUF;
  wire MTXI_OBUF;
  wire GP_Motor0_1_OBUF;
  wire TmpEn_OBUF;
  wire PAL0_OBUF;
  wire PAL1_OBUF;
  wire Home15FLG_IBUF;
  wire Enc133ctrl_OBUF;
  wire PBH0_OBUF;
  wire RD_IBUF;
  wire PBH1_OBUF;
  wire Enc05FLG_IBUF;
  wire Enc033ctrl_OBUF;
  wire PresEn_OBUF;
  wire GPIO8_OBUF;
  wire GPIO9_OBUF;
  wire GP_Motor1_0_IBUF;
  wire GP_Motor1_1_OBUF;
  wire NET2482;
  wire Enc133FLG_IBUF;
  wire PBL0_OBUF;
  wire FLS0_IBUF;
  wire PBL1_OBUF;
  wire FLS1_IBUF;
  wire WR_IBUF;
  wire GPIO10_OBUF;
  wire Enc15FLG_IBUF;
  wire MHSI_OBUF;
  wire NET2512;
  wire SCLreset_IBUF;
  wire PresSlct_OBUF;
  wire DCOR1CNTLOWr;
  wire DIR0_IBUF;
  wire DIR1_IBUF;
  wire Home05ctrl_OBUF;
  wire HSO_OBUF;
  wire Mclk_IBUF;
  wire INT_OBUF;
  wire SCLinc_IBUF;
  wire MTRpwr_OBUF;
  wire MReset_IBUF;
  wire Home133ctrl_OBUF;
  wire DCORENCPWRr;
  wire NET2528;
  wire DCOR0CNTLOWr;
  wire DCORENCPWRw;
  wire DCORENCCTLw;
  wire DCOR0THRESLOWr;
  wire DCOR0THRESHIGHr;
  wire NET3248;
  wire NET3253;
  wire DCOR1CNTHIGHr;
  wire DCORLINTr;
  wire Reset;
  wire DCOR0CNTHIGHr;
  wire DCOR1THRESHIGHr;
  wire DCORLIMITSr;
  wire DCORSENSORw;
  wire NET2493;
  wire DCORCONFIGr;
  wire DCOR1THRESLOWr;
  wire DCORI2CCNTr;
  wire DCORIFGr;
  wire DCORIFGw;
  wire NET4826;
  wire DCOROUTw;
  wire DCORIEw;
  wire I2CS_5_IBUF;
  wire I2CS_4_IBUF;
  wire I2CS_3_IBUF;
  wire I2CS_2_IBUF;
  wire I2CS_1_IBUF;
  wire I2CS_0_IBUF;
  wire U2_ADDR_reg_0__n0002;
  wire U2_ADDR_reg_0__n0000;
  wire U11_U3_Maddsub__n0002__n0017;
  wire N13655;
  wire U2_ADDR_reg_6__n0000;
  wire U2_ADDR_reg_7__n0000;
  wire U2_WRRDedge;
  wire U2__n0000;
  wire U11_U3_Maddsub__n0002__n0020;
  wire U2__n0003;
  wire U2__n0005;
  wire U2__n0006;
  wire U11_U3__n0006;
  wire U11_U3__n0041;
  wire U2__n0018;
  wire U2_Enable_AD;
  wire U2_ASedge;
  wire U2_AutoInc;
  wire U2_ADDR_in_Range;
  wire U11_U3_Maddsub__n0002__n0018;
  wire SCL_IOBUFE;
  wire U2_ADDR_reg_3__n0000;
  wire U2_ADDR_reg_4__n0000;
  wire U2_ADDR_reg_5__n0000;
  wire U2_ADDR_reg_0__n0003;
  wire U11_U3_Maddsub__n0002__n0019;
  wire U2_ADDR_reg_2__n0000;
  wire U2_ADDR_reg_1__n0000;
  wire U11_U3__n0042;
  wire U11_ResetDetect;
  wire U11_Incdetect;
  wire U11_SCLdetect;
  wire GPIO91;
  wire GPIO101;
  wire U2_ADDR_reg_1__n00001;
  wire U2_ADDR_reg_1__n00002;
  wire U2_ADDR_reg_1__n00003;
  wire U2_ADDR_reg_1__n00004;
  wire U2_ADDR_reg_1__n00005;
  wire U2_ADDR_reg_2__n00001;
  wire U2_ADDR_reg_2__n00002;
  wire U2_ADDR_reg_2__n00003;
  wire U2_ADDR_reg_2__n00004;
  wire U2_ADDR_reg_2__n00005;
  wire U2_ADDR_reg_3__n00001;
  wire U2_ADDR_reg_3__n00002;
  wire U2_ADDR_reg_3__n00003;
  wire U2_ADDR_reg_3__n00004;
  wire U2_ADDR_reg_3__n00005;
  wire U2_ADDR_reg_4__n00001;
  wire U2_ADDR_reg_4__n00002;
  wire U2_ADDR_reg_4__n00003;
  wire U2_ADDR_reg_4__n00004;
  wire U2_ADDR_reg_4__n00005;
  wire U2_ADDR_reg_5__n00001;
  wire U2_ADDR_reg_5__n00002;
  wire U2_ADDR_reg_5__n00003;
  wire U2_ADDR_reg_5__n00004;
  wire U2_ADDR_reg_5__n00005;
  wire U2_ADDR_reg_6__n00001;
  wire U2_ADDR_reg_6__n00002;
  wire U2_ADDR_reg_6__n00003;
  wire U2_ADDR_reg_6__n00004;
  wire U2_ADDR_reg_6__n00005;
  wire U2_ADDR_reg_7__n00001;
  wire U2_ADDR_reg_7__n00002;
  wire U2_ADDR_reg_7__n00003;
  wire U2_ADDR_reg_7__n00004;
  wire U2_ADDR_reg_7__n00005;
  wire U2_Mcompar__n0006_ALB;
  wire U2_Mcompar__n0006_ALB1;
  wire U2_Mcompar__n0006_ALB2;
  wire U2_Mcompar__n0006_ALB3;
  wire U2_Mcompar__n0006_ALB4;
  wire U2_Mcompar__n0006_ALB5;
  wire U2_Mcompar__n0006_ALB6;
  wire U11_U3_Maddsub__n0002__n0000;
  wire U11_U3_Maddsub__n0002__n00001;
  wire U11_U3_Maddsub__n0002__n00002;
  wire U11_U3_Maddsub__n0002__n00003;
  wire U11_U3_Maddsub__n0002__n00004;
  wire U11_U3_Maddsub__n0002__n00005;
  wire U2_ADDR_reg_0__n00021;
  wire U2_ADDR_reg_0__n00022;
  wire U2_ADDR_reg_0__n00023;
  wire U2_ADDR_reg_0__n00024;
  wire U2_ADDR_reg_0__n00025;
  wire U2_ADDR_reg_0__n00026;
  wire U2_ADDR_reg_0__n00027;
  wire U2_ADDR_reg_0__n00001;
  wire U2_ADDR_reg_0__n00002;
  wire U2_ADDR_reg_0__n00003;
  wire U2_ADDR_reg_0__n00004;
  wire U2_ADDR_reg_0__n00005;
  wire U2_ADDR_reg_0__n00006;
  wire U2_ADDR_reg_0__n00007;
  wire U2_ADDR_reg_0__n00008;
  wire U2_ADDR_reg_0__n00009;
  wire U2__n00031;
  wire U2_Mcompar_ADDR_in_Range_ALEB;
  wire U2_Mcompar_ADDR_in_Range_ALEB1;
  wire U2_Mcompar_ADDR_in_Range_ALEB2;
  wire U2_Mcompar_ADDR_in_Range_ALEB3;
  wire U2_ASleading;
  wire U2_Enable_AD1;
  wire U2_Enable_AD2;
  wire U11_U3_Maddsub__n0002__n0002;
  wire U11_U3_Maddsub__n0002__n00021;
  wire U11_U3_Maddsub__n0002__n00022;
  wire U11_U3_Maddsub__n0002__n00023;
  wire U11_U3_Maddsub__n0002__n00024;
  wire U11_U3_Maddsub__n0002__n00025;
  wire U11_U3_Maddsub__n0002__n0001;
  wire U11_U3_Maddsub__n0002__n00011;
  wire U11_U3_Maddsub__n0002__n00012;
  wire U11_U3_Maddsub__n0002__n00013;
  wire U11_U3_Maddsub__n0002__n00014;
  wire U11_U3_Maddsub__n0002__n00015;
  wire U11_U3__n0000_3_1;
  wire U11_U3__n0000_3_2;
  wire U11_U3__n0000_3_3;
  wire U11_U3__n0000_3_4;
  wire U11_U3__n0000_3_5;
  wire U11_U3__n0000_3_6;
  wire U11_U3__n0000_3_7;
  wire U11_U3__n0000_3_8;
  wire U11_U3__n0000_3_9;
  wire U11_U3__n0000_3_10;
  wire U11_U3_Maddsub__n0002__n0004;
  wire U11_U3_Maddsub__n0002__n00041;
  wire U11_U3_Maddsub__n0002__n00042;
  wire U11_U3_Maddsub__n0002__n00043;
  wire U11_U3__n0000_4_1;
  wire U11_U3__n0000_4_2;
  wire U11_U3__n0000_4_3;
  wire U11_U3__n0000_4_4;
  wire U11_U3__n0000_4_5;
  wire U11_U3__n0000_4_6;
  wire U11_U3__n0000_4_7;
  wire U11_U3__n0000_4_8;
  wire U11_U3__n0000_4_9;
  wire U11_U3__n0000_5_1;
  wire U11_U3__n0000_5_2;
  wire U11_U3__n0000_5_3;
  wire U11_U3__n0000_5_4;
  wire U11_U3__n0000_5_5;
  wire U11_U3__n0000_5_6;
  wire U11_U3__n0000_5_7;
  wire U11_U3__n0000_5_8;
  wire U11_U3__n0000_5_9;
  wire U11_U3__n00411;
  wire U11_U3__n00412;
  wire U11_U3__n00413;
  wire U11_U3__n00414;
  wire U11_U3__n00415;
  wire U11_U3__n00416;
  wire U11_U3__n00421;
  wire U11_U3__n00422;
  wire U11_U3__n00423;
  wire U11_U3__n00424;
  wire U11_U3__n00425;
  wire U11_U3__n00426;
  wire U11_U3__n00427;
  wire U11_U3__n0000_2_1;
  wire U11_U3__n0000_2_2;
  wire U11_U3__n0000_2_3;
  wire U11_U3__n0000_2_4;
  wire U11_U3__n0000_2_5;
  wire U11_U3__n0000_2_6;
  wire U11_U3__n0000_2_7;
  wire U11_U3__n0000_2_8;
  wire U11_U3__n0000_2_9;
  wire U11_U3__n0000_2_10;
  wire U11_U3__n0000_0_1;
  wire U11_U3__n0000_0_2;
  wire U11_U3__n0000_0_3;
  wire U11_U3__n0000_0_4;
  wire U11_U3__n0000_0_5;
  wire U11_U3__n0000_0_6;
  wire U11_U3__n0000_0_7;
  wire U11_U3__n0000_0_8;
  wire U11_U3__n0000_0_9;
  wire U11_U3__n0000_0_10;
  wire U11_U3__n0000_0_11;
  wire U11_U3__n0000_0_12;
  wire U11_U3__n0000_0_13;
  wire U11_U3__n0000_0_14;
  wire U11_U3__n0000_0_15;
  wire U11_U3__n0000_0_16;
  wire U11_U3__n0005;
  wire U11_U3__n00051;
  wire U11_U3__n00052;
  wire U11_U3__n00053;
  wire U11_U3__n00054;
  wire U11_U3__n00055;
  wire U11_U3_Maddsub__n0002__n0003;
  wire U11_U3_Maddsub__n0002__n00031;
  wire U11_U3_Maddsub__n0002__n00032;
  wire U11_U3_Maddsub__n0002__n00033;
  wire U11_U3_Maddsub__n0002__n00034;
  wire U11_U3_Maddsub__n0002__n00035;
  wire U11_U3__n0000_1_1;
  wire U11_U3__n0000_1_2;
  wire U11_U3__n0000_1_3;
  wire U11_U3__n0000_1_4;
  wire U11_U3__n0000_1_5;
  wire U11_U3__n0000_1_6;
  wire U11_U3__n0000_1_7;
  wire U11_U3__n0000_1_8;
  wire U11_U3__n0000_1_9;
  wire U11_U3__n0000_1_10;
  wire U11_U3__n0000_1_11;
  wire U11_U3__n0000_1_12;
  wire U11_U3__n00061;
  wire U11_U3__n00062;
  wire N21761;
  wire N21763;
  wire N21765;
  wire N21767;
  wire SCLout_OBUF;
  wire N21771;
  wire N21773;
  wire N21775;
  wire N21777;
  wire [7 : 0] U2_ADDR_reg;
  wire [5 : 4] U11_U3__n0049;
  wire [3 : 3] U11_U3__n0003;
  wire [5 : 0] U11_U3__n0002;
  wire [0 : 0] U2_Madd__n0011__n0016;
  wire [0 : 0] U2_Madd__n0011__n0014;
  wire [5 : 0] U11_U3_counterr;
  wire [7 : 0] outDATA;
  wire [7 : 1] U2__n0011;
  wire [1 : 0] U11_U3_Maddsub__n0002__n0026;
  wire [0 : 0] U11_U3_Maddsub__n0002_Mxor_Result_1___n0002;
  wire [5 : 0] U11_U3__n0000;
  wire [0 : 0] U2_Madd__n0011__n0008;
  wire [0 : 0] U11_U3_Maddsub__n0002__n0034;
  wire [0 : 0] U11_U3_Madd__n0001__n0003;
  wire [0 : 0] U11_U3_Maddsub__n0002__n0032;
  wire [0 : 0] U2_Madd__n0011__n0018;
  wire [0 : 0] U2_Madd__n0011__n0010;
  wire [0 : 0] U2_Madd__n0011__n0012;
  wire [0 : 0] U11_U3_Maddsub__n0002_Mxor_Result_3___n0002;
  wire [1 : 0] U11_U3_Maddsub__n0002__n0028;
  wire [1 : 0] U11_U3_Maddsub__n0002__n0030;
  wire [0 : 0] U11_U3_Maddsub__n0002_Mxor_Result_5___n0002;
  wire [0 : 0] U11_U3_Maddsub__n0002_Mxor_Result_4___n0002;
  wire [0 : 0] U11_U3_Maddsub__n0002_Mxor_Result_2___n0002;
  MISCouts U9 (
    .LightSense(LightSense_IBUF),
    .Reset(Reset),
    .DCOROUTw(DCOROUTw),
    .Mclk(Mclk_IBUF),
    .MReset(MReset_IBUF),
    .MTRpwrn(MTRpwrn_OBUF),
    .LED1(LED1_OBUF),
    .LED2(LED2_OBUF),
    .LED3(LED3_OBUF),
    .LED4(LED4_OBUF),
    .LED5(LED5_OBUF),
    .GP_Motor0_1(GP_Motor0_1_OBUF),
    .GP_Motor1_1(GP_Motor1_1_OBUF),
    .MTRpwr(MTRpwr_OBUF),
    .inDATA({N21765, N21763, N21761, N21777, N21775, N21773, N21771, N21767})
  );
  Sensor U8 (
    .Reset(Reset),
    .DCORSENSORw(DCORSENSORw),
    .Mclk(Mclk_IBUF),
    .MReset(MReset_IBUF),
    .TmpSlct(TmpSlct_OBUF),
    .TmpEn(TmpEn_OBUF),
    .PresEn(PresEn_OBUF),
    .PresSlct(PresSlct_OBUF),
    .inDATA({N21775, N21773, N21771, N21767})
  );
  PWMcontrol U7 (
    .Brake1(Brake0_IBUF),
    .Brake2(Brake1_IBUF),
    .fBRK1(NET3248),
    .fBRK2(NET3253),
    .PWM1(PWM1_IBUF),
    .PWM2(PWM2_IBUF),
    .RLS0(RLS0_IBUF),
    .RLS1(RLS1_IBUF),
    .FLS0(FLS0_IBUF),
    .FLS1(FLS1_IBUF),
    .HBRK1(NET3248),
    .HBRK2(NET3253),
    .DIR1(DIR0_IBUF),
    .DIR2(DIR1_IBUF),
    .MTRpwr(MTRpwr_OBUF),
    .PAH1(PAH0_OBUF),
    .PAH2(PAH1_OBUF),
    .PAL1(PAL0_OBUF),
    .PAL2(PAL1_OBUF),
    .PBH1(PBH0_OBUF),
    .PBH2(PBH1_OBUF),
    .PBL1(PBL0_OBUF),
    .PBL2(PBL1_OBUF)
  );
  I2CAddress U6 (
    .DCORCONFIGr(DCORCONFIGr),
    .MotorIn0(GP_Motor0_0_IBUF),
    .MotorIn1(GP_Motor1_0_IBUF),
    .I2CS({I2CS_5_IBUF, I2CS_4_IBUF, I2CS_3_IBUF, I2CS_2_IBUF, I2CS_1_IBUF, I2CS_0_IBUF}),
    .outDATA({outDATA[7], outDATA[6], outDATA[5], outDATA[4], outDATA[3], outDATA[2], outDATA[1], outDATA[0]})
  );
  Lswitch U5 (
    .Brake0(Brake0_IBUF),
    .Brake1(Brake1_IBUF),
    .DCORLINTr(DCORLINTr),
    .Reset(Reset),
    .DCORLIMITSr(DCORLIMITSr),
    .Home0(Home0_IBUF),
    .Home1(Home1_IBUF),
    .RLS0(RLS0_IBUF),
    .RLS1(RLS1_IBUF),
    .DCORIFGw(DCORIFGw),
    .FLS0(FLS0_IBUF),
    .FLS1(FLS1_IBUF),
    .LIFG(N21777),
    .DIR0(DIR0_IBUF),
    .DIR1(DIR1_IBUF),
    .Mclk(Mclk_IBUF),
    .fBRK0(NET3248),
    .fBRK1(NET3253),
    .LSwitchInt(NET2575),
    .outDATA({outDATA[7], outDATA[6], outDATA[5], outDATA[4], outDATA[3], outDATA[2], outDATA[1], outDATA[0]})
  );
  PWRreg U4 (
    .DCORENCPWRr(DCORENCPWRr),
    .DCORENCPWRw(DCORENCPWRw),
    .Reset(Reset),
    .Hme05flg(Home05FLG_IBUF),
    .Enc033flg(Enc033FLG_IBUF),
    .Hme033flg(Home033FLG_IBUF),
    .DCORIFGr(DCORIFGr),
    .DCORIFGw(DCORIFGw),
    .Enc05flg(Enc05FLG_IBUF),
    .Hme15flg(Home15FLG_IBUF),
    .Enc133flg(Enc133FLG_IBUF),
    .Hme133flg(Home133FLG_IBUF),
    .Enc15flg(Enc15FLG_IBUF),
    .Mclk(Mclk_IBUF),
    .PWRint(NET2528),
    .Hme05ctl(Home05ctrl_OBUF),
    .Enc033ctl(Enc033ctrl_OBUF),
    .Hme033ctl(Home033ctrl_OBUF),
    .Enc05ctl(Enc05ctrl_OBUF),
    .Hme15ctl(Home15ctrl_OBUF),
    .Enc133ctl(Enc133ctrl_OBUF),
    .Hme133ctl(Home133ctrl_OBUF),
    .Enc15ctl(Enc15ctrl_OBUF),
    .inDATA({N21765, N21763, N21761, N21777, N21775, N21773, N21771, N21767}),
    .outDATA({outDATA[7], outDATA[6], outDATA[5], outDATA[4], outDATA[3], outDATA[2], outDATA[1], outDATA[0]})
  );
  Interrupt U3 (
    .PWRint(NET2528),
    .Reset(Reset),
    .I2Cint(TP12_OBUF),
    .DCORIFGr(DCORIFGr),
    .Homed0(NET2482),
    .Homed1(NET2493),
    .BusInt(INTbus_IBUF),
    .DCORIEw(DCORIEw),
    .Thres0(NET2501),
    .Thres1(NET2512),
    .LSwitchInt(NET2575),
    .Mclk(Mclk_IBUF),
    .INT(INT_OBUF),
    .inDATA({N21765, N21763, N21761, N21777, N21775, N21773, N21771, N21767}),
    .outDATA({outDATA[7], outDATA[6], outDATA[5], outDATA[4], outDATA[3], outDATA[2], outDATA[1], outDATA[0]})
  );
  INV U2_ADDR_reg_0__n00031 (
    .I(Mclk_IBUF),
    .O(U2_ADDR_reg_0__n0003)
  );
  U21AddDecode U12 (
    .AS(AS_IBUF),
    .RD(RD_IBUF),
    .WR(WR_IBUF),
    .DCORENCPWRr(DCORENCPWRr),
    .DCOR0CNTLOWr(DCOR0CNTLOWr),
    .DCORENCPWRw(DCORENCPWRw),
    .DCORENCCTLw(DCORENCCTLw),
    .DCOR0THRESLOWr(DCOR0THRESLOWr),
    .DCOR0THRESHIGHr(DCOR0THRESHIGHr),
    .DCOR1CNTHIGHr(DCOR1CNTHIGHr),
    .DCORLINTr(DCORLINTr),
    .DCOR0CNTHIGHr(DCOR0CNTHIGHr),
    .DCOR1THRESHIGHr(DCOR1THRESHIGHr),
    .DCORLIMITSr(DCORLIMITSr),
    .DCORSENSORw(DCORSENSORw),
    .DCORCONFIGr(DCORCONFIGr),
    .DCORIFGr(DCORIFGr),
    .DCORIFGw(DCORIFGw),
    .DCOROUTw(DCOROUTw),
    .DCORIEw(DCORIEw),
    .DCOR1CNTLOWr(DCOR1CNTLOWr),
    .DCOR1THRESLOWr(DCOR1THRESLOWr),
    .DCORI2CCNTr(DCORI2CCNTr),
    .ADDR({U2_ADDR_reg[7], U2_ADDR_reg[6], U2_ADDR_reg[5], U2_ADDR_reg[4], U2_ADDR_reg[3], U2_ADDR_reg[2], U2_ADDR_reg[1], U2_ADDR_reg[0]})
  );
  INV Reset1 (
    .I(MSPReset_IBUF),
    .O(Reset)
  );
  AND2 GPIO92 (
    .I0(PWM3_IBUF),
    .I1(GPIO91),
    .O(GPIO9_OBUF)
  );
  AND2 GPIO102 (
    .I0(PWM4_IBUF),
    .I1(GPIO101),
    .O(GPIO10_OBUF)
  );
  LPM_XOR2_1 U11_U3_Maddsub__n0002_Mxor_Result_4__Mxor_Result (
    .Data_0_(U11_U3_Maddsub__n0002_Mxor_Result_4___n0002[0]),
    .Data_1_(U11_U3_Maddsub__n0002__n0032[0]),
    .Result(U11_U3__n0002[4])
  );
  Servos U1 (
    .DCOR0CNTLOWr(DCOR0CNTLOWr),
    .DCORENCCTLw(DCORENCCTLw),
    .DCOR0THRESLOWr(DCOR0THRESLOWr),
    .PhaseB_Encoder0(PhaseB_Encoder0_IBUF),
    .PhaseB_Encoder1(PhaseB_Encoder1_IBUF),
    .DCOR0THRESHIGHr(DCOR0THRESHIGHr),
    .DCOR1CNTHIGHr(DCOR1CNTHIGHr),
    .Reset(Reset),
    .DCOR0CNTHIGHr(DCOR0CNTHIGHr),
    .DCOR1THRESHIGHr(DCOR1THRESHIGHr),
    .PhaseA_Encoder0(PhaseA_Encoder0_IBUF),
    .PhaseA_Encoder1(PhaseA_Encoder1_IBUF),
    .DCORIFGr(DCORIFGr),
    .DCORIFGw(DCORIFGw),
    .MotorIn0(GP_Motor0_0_IBUF),
    .Motorin1(GP_Motor1_0_IBUF),
    .Home_Encoder0(Home0_IBUF),
    .Home_Encoder1(Home1_IBUF),
    .DCOR1CNTLOWr(DCOR1CNTLOWr),
    .ASleading(NET4826),
    .Mclk(Mclk_IBUF),
    .DCOR1THRESLOWr(DCOR1THRESLOWr),
    .Hfound0(NET2482),
    .Hfound1(NET2493),
    .TP(TP10_OBUF),
    .Tfound0(NET2501),
    .Tfound1(NET2512),
    .inDATA({N21765, N21763, N21761, N21777, N21775, N21773, N21771, N21767}),
    .outDATA({outDATA[7], outDATA[6], outDATA[5], outDATA[4], outDATA[3], outDATA[2], outDATA[1], outDATA[0]})
  );
  AND2 U2_ADDR_reg_1__n00006 (
    .I0(MSPReset_IBUF),
    .I1(U2_ADDR_reg_1__n00005),
    .O(U2_ADDR_reg_1__n0000)
  );
  AND2 U2_ADDR_reg_2__n00006 (
    .I0(MSPReset_IBUF),
    .I1(U2_ADDR_reg_2__n00005),
    .O(U2_ADDR_reg_2__n0000)
  );
  AND2 U2_ADDR_reg_3__n00006 (
    .I0(MSPReset_IBUF),
    .I1(U2_ADDR_reg_3__n00005),
    .O(U2_ADDR_reg_3__n0000)
  );
  LPM_XOR2_1 U2_Madd__n0011_Mxor_Result_1_ (
    .Data_0_(U2_ADDR_reg[0]),
    .Data_1_(U2_ADDR_reg[1]),
    .Result(U2__n0011[1])
  );
  AND2 U2_ADDR_reg_4__n00006 (
    .I0(MSPReset_IBUF),
    .I1(U2_ADDR_reg_4__n00005),
    .O(U2_ADDR_reg_4__n0000)
  );
  AND2 U2_ADDR_reg_5__n00006 (
    .I0(MSPReset_IBUF),
    .I1(U2_ADDR_reg_5__n00005),
    .O(U2_ADDR_reg_5__n0000)
  );
  AND2 U2_ADDR_reg_6__n00006 (
    .I0(MSPReset_IBUF),
    .I1(U2_ADDR_reg_6__n00005),
    .O(U2_ADDR_reg_6__n0000)
  );
  AND2 U2_ADDR_reg_7__n00006 (
    .I0(MSPReset_IBUF),
    .I1(U2_ADDR_reg_7__n00005),
    .O(U2_ADDR_reg_7__n0000)
  );
  INV U2__n00181 (
    .I(AS_IBUF),
    .O(U2__n0018)
  );
  AND2 U2_Mcompar__n0006_ALB8 (
    .I0(U2_Mcompar__n0006_ALB5),
    .I1(U2_Mcompar__n0006_ALB6),
    .O(U2__n0006)
  );
  OR2 U11_U3_Maddsub__n0002__n00007 (
    .I0(U11_U3_Maddsub__n0002__n0000),
    .I1(U11_U3_Maddsub__n0002__n00005),
    .O(U11_U3_Maddsub__n0002__n0026[1])
  );
  AND2 U11_U3_Maddsub__n0002__n00191 (
    .I0(U11_U3__n0006),
    .I1(U11_U3_Maddsub__n0002__n0032[0]),
    .O(U11_U3_Maddsub__n0002__n0019)
  );
  OR2 U2_ADDR_reg_0__n00028 (
    .I0(U2_ADDR_reg_0__n00027),
    .I1(U2_ADDR_reg_0__n00024),
    .O(U2_ADDR_reg_0__n0002)
  );
  LPM_XOR2_1 U11_U3_Maddsub__n0002_Mxor_Result_1__Mxor_Result (
    .Data_0_(U11_U3_Maddsub__n0002_Mxor_Result_1___n0002[0]),
    .Data_1_(U11_U3_Maddsub__n0002__n0026[0]),
    .Result(U11_U3__n0002[1])
  );
  AND2 U2_ADDR_reg_0__n000010 (
    .I0(MSPReset_IBUF),
    .I1(U2_ADDR_reg_0__n00009),
    .O(U2_ADDR_reg_0__n0000)
  );
  BUFE U11_U3_I1_2 (
    .E(DCORI2CCNTr),
    .I(U11_U3_counterr[2]),
    .O(outDATA[2])
  );
  LPM_XOR2_1 U11_U3_Madd__n0001_Mxor_Result_1_ (
    .Data_0_(U11_U3_counterr[3]),
    .Data_1_(U11_U3_counterr[4]),
    .Result(U11_U3__n0049[4])
  );
  AND3 U2__n00051 (
    .I0(NET4826),
    .I1(RD_IBUF),
    .I2(WR_IBUF),
    .O(U2__n0005)
  );
  AND2 U2__n00032 (
    .I0(U2_WRRDedge),
    .I1(U2__n00031),
    .O(U2__n0003)
  );
  BUFE U11_U3_I1_1 (
    .E(DCORI2CCNTr),
    .I(U11_U3_counterr[1]),
    .O(outDATA[1])
  );
  FD U2_ASedge_2930 (
    .D(AS_IBUF),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U2_ASedge)
  );
  FD U2_WRRDedge_2931 (
    .D(U2__n0000),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U2_WRRDedge)
  );
  IOBUFE SCL_IOBUFE_2932 (
    .I(SCL_IOBUFE),
    .E(TP12_OBUF),
    .O(SCLout_OBUF),
    .IO(SCL)
  );
  GND XST_GND (
    .G(SCL_IOBUFE)
  );
  IOBUFE AD_7_IOBUFE (
    .I(outDATA[7]),
    .E(U2_Enable_AD),
    .O(N21765),
    .IO(AD[7])
  );
  AND4 U2_Mcompar_ADDR_in_Range_ALEB5 (
    .I0(U2_Mcompar_ADDR_in_Range_ALEB),
    .I1(U2_Mcompar_ADDR_in_Range_ALEB1),
    .I2(U2_Mcompar_ADDR_in_Range_ALEB2),
    .I3(U2_Mcompar_ADDR_in_Range_ALEB3),
    .O(U2_ADDR_in_Range)
  );
  FD U11_U3_counterr_0 (
    .D(U11_U3__n0000[0]),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U11_U3_counterr[0])
  );
  BUFE U11_U3_I1_3 (
    .E(DCORI2CCNTr),
    .I(U11_U3_counterr[3]),
    .O(outDATA[3])
  );
  AND2 U2_ASleading2 (
    .I0(U2_ASedge),
    .I1(U2_ASleading),
    .O(NET4826)
  );
  AND2 U2_Enable_AD3 (
    .I0(U2_Enable_AD1),
    .I1(U2_Enable_AD2),
    .O(U2_Enable_AD)
  );
  AND2 U2__n00001 (
    .I0(WR_IBUF),
    .I1(RD_IBUF),
    .O(U2__n0000)
  );
  LPM_XOR2_1 U11_U3_Maddsub__n0002_Mxor_Result_1__Mxor__n0000 (
    .Data_0_(U11_U3_counterr[1]),
    .Data_1_(U11_U3_Maddsub__n0002__n0026[1]),
    .Result(U11_U3_Maddsub__n0002_Mxor_Result_1___n0002[0])
  );
  FDCE U2_AutoInc_2933 (
    .D(U2__n0018),
    .CE(U2__n0003),
    .CLR(SCL_IOBUFE),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U2_AutoInc)
  );
  IOBUFE AD_6_IOBUFE (
    .I(outDATA[6]),
    .E(U2_Enable_AD),
    .O(N21763),
    .IO(AD[6])
  );
  IOBUFE AD_5_IOBUFE (
    .I(outDATA[5]),
    .E(U2_Enable_AD),
    .O(N21761),
    .IO(AD[5])
  );
  IOBUFE AD_0_IOBUFE (
    .I(outDATA[0]),
    .E(U2_Enable_AD),
    .O(N21767),
    .IO(AD[0])
  );
  IOBUFE AD_1_IOBUFE (
    .I(outDATA[1]),
    .E(U2_Enable_AD),
    .O(N21771),
    .IO(AD[1])
  );
  IOBUFE AD_2_IOBUFE (
    .I(outDATA[2]),
    .E(U2_Enable_AD),
    .O(N21773),
    .IO(AD[2])
  );
  IOBUFE AD_3_IOBUFE (
    .I(outDATA[3]),
    .E(U2_Enable_AD),
    .O(N21775),
    .IO(AD[3])
  );
  IOBUFE AD_4_IOBUFE (
    .I(outDATA[4]),
    .E(U2_Enable_AD),
    .O(N21777),
    .IO(AD[4])
  );
  VCC XST_VCC (
    .P(N13655)
  );
  AND2 U2_Madd__n0011__n00051 (
    .I0(U2_ADDR_reg[6]),
    .I1(U2_Madd__n0011__n0016[0]),
    .O(U2_Madd__n0011__n0018[0])
  );
  AND2 U2_Madd__n0011__n00041 (
    .I0(U2_ADDR_reg[5]),
    .I1(U2_Madd__n0011__n0014[0]),
    .O(U2_Madd__n0011__n0016[0])
  );
  AND2 U2_Madd__n0011__n00031 (
    .I0(U2_ADDR_reg[4]),
    .I1(U2_Madd__n0011__n0012[0]),
    .O(U2_Madd__n0011__n0014[0])
  );
  AND2 U2_Madd__n0011__n00021 (
    .I0(U2_ADDR_reg[3]),
    .I1(U2_Madd__n0011__n0010[0]),
    .O(U2_Madd__n0011__n0012[0])
  );
  AND2 U2_Madd__n0011__n00011 (
    .I0(U2_ADDR_reg[2]),
    .I1(U2_Madd__n0011__n0008[0]),
    .O(U2_Madd__n0011__n0010[0])
  );
  AND2 U2_Madd__n0011__n00001 (
    .I0(U2_ADDR_reg[1]),
    .I1(U2_ADDR_reg[0]),
    .O(U2_Madd__n0011__n0008[0])
  );
  LPM_XOR2_1 U2_Madd__n0011_Mxor_Result_7_ (
    .Data_0_(U2_Madd__n0011__n0018[0]),
    .Data_1_(U2_ADDR_reg[7]),
    .Result(U2__n0011[7])
  );
  LPM_XOR2_1 U2_Madd__n0011_Mxor_Result_6_ (
    .Data_0_(U2_Madd__n0011__n0016[0]),
    .Data_1_(U2_ADDR_reg[6]),
    .Result(U2__n0011[6])
  );
  LPM_XOR2_1 U2_Madd__n0011_Mxor_Result_5_ (
    .Data_0_(U2_Madd__n0011__n0014[0]),
    .Data_1_(U2_ADDR_reg[5]),
    .Result(U2__n0011[5])
  );
  LPM_XOR2_1 U2_Madd__n0011_Mxor_Result_4_ (
    .Data_0_(U2_Madd__n0011__n0012[0]),
    .Data_1_(U2_ADDR_reg[4]),
    .Result(U2__n0011[4])
  );
  LPM_XOR2_1 U2_Madd__n0011_Mxor_Result_3_ (
    .Data_0_(U2_Madd__n0011__n0010[0]),
    .Data_1_(U2_ADDR_reg[3]),
    .Result(U2__n0011[3])
  );
  LPM_XOR2_1 U2_Madd__n0011_Mxor_Result_2_ (
    .Data_0_(U2_Madd__n0011__n0008[0]),
    .Data_1_(U2_ADDR_reg[2]),
    .Result(U2__n0011[2])
  );
  FDCE U2_ADDR_reg_7 (
    .D(U2_ADDR_reg_7__n0000),
    .CE(U2_ADDR_reg_0__n0002),
    .CLR(SCL_IOBUFE),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U2_ADDR_reg[7])
  );
  FDCE U2_ADDR_reg_6 (
    .D(U2_ADDR_reg_6__n0000),
    .CE(U2_ADDR_reg_0__n0002),
    .CLR(SCL_IOBUFE),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U2_ADDR_reg[6])
  );
  FDCE U2_ADDR_reg_0 (
    .D(U2_ADDR_reg_0__n0000),
    .CE(U2_ADDR_reg_0__n0002),
    .CLR(SCL_IOBUFE),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U2_ADDR_reg[0])
  );
  FDCE U2_ADDR_reg_1 (
    .D(U2_ADDR_reg_1__n0000),
    .CE(U2_ADDR_reg_0__n0002),
    .CLR(SCL_IOBUFE),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U2_ADDR_reg[1])
  );
  FDCE U2_ADDR_reg_2 (
    .D(U2_ADDR_reg_2__n0000),
    .CE(U2_ADDR_reg_0__n0002),
    .CLR(SCL_IOBUFE),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U2_ADDR_reg[2])
  );
  FDCE U2_ADDR_reg_3 (
    .D(U2_ADDR_reg_3__n0000),
    .CE(U2_ADDR_reg_0__n0002),
    .CLR(SCL_IOBUFE),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U2_ADDR_reg[3])
  );
  FDCE U2_ADDR_reg_4 (
    .D(U2_ADDR_reg_4__n0000),
    .CE(U2_ADDR_reg_0__n0002),
    .CLR(SCL_IOBUFE),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U2_ADDR_reg[4])
  );
  FDCE U2_ADDR_reg_5 (
    .D(U2_ADDR_reg_5__n0000),
    .CE(U2_ADDR_reg_0__n0002),
    .CLR(SCL_IOBUFE),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U2_ADDR_reg[5])
  );
  LPM_XOR2_1 U11_U3_Maddsub__n0002_Mxor__n0021 (
    .Data_0_(U11_U3__n0006),
    .Data_1_(SCL_IOBUFE),
    .Result(U11_U3_Maddsub__n0002__n0026[0])
  );
  BUFE U11_U3_I1_6 (
    .E(DCORI2CCNTr),
    .I(SCL_IOBUFE),
    .O(outDATA[6])
  );
  BUFE U11_U3_I1_0 (
    .E(DCORI2CCNTr),
    .I(U11_U3_counterr[0]),
    .O(outDATA[0])
  );
  BUFE U11_U3_I1_7 (
    .E(DCORI2CCNTr),
    .I(SCL_IOBUFE),
    .O(outDATA[7])
  );
  LPM_XOR2_1 U11_U3_Maddsub__n0002_Mxor__n0020 (
    .Data_0_(U11_U3__n0006),
    .Data_1_(N13655),
    .Result(U11_U3_Maddsub__n0002__n0020)
  );
  OR2 U11_U3_Maddsub__n0002__n00027 (
    .I0(U11_U3_Maddsub__n0002__n0002),
    .I1(U11_U3_Maddsub__n0002__n00025),
    .O(U11_U3_Maddsub__n0002__n0030[1])
  );
  LPM_XOR2_1 U11_U3_Maddsub__n0002_Mxor__n0022 (
    .Data_0_(U11_U3__n0006),
    .Data_1_(SCL_IOBUFE),
    .Result(U11_U3_Maddsub__n0002__n0028[0])
  );
  LPM_XOR2_1 U11_U3_Maddsub__n0002_Mxor_Result_5__Mxor__n0000 (
    .Data_0_(U11_U3_counterr[5]),
    .Data_1_(U11_U3__n0006),
    .Result(U11_U3_Maddsub__n0002_Mxor_Result_5___n0002[0])
  );
  OR2 U11_U3_Maddsub__n0002__n00017 (
    .I0(U11_U3_Maddsub__n0002__n0001),
    .I1(U11_U3_Maddsub__n0002__n00015),
    .O(U11_U3_Maddsub__n0002__n0028[1])
  );
  OR3 U11_U3__n0000_3_11 (
    .I0(U11_U3__n0000_3_10),
    .I1(SCLreset_IBUF),
    .I2(U11_U3__n0000_3_9),
    .O(U11_U3__n0000[3])
  );
  LPM_XOR2_1 U11_U3_Maddsub__n0002_Mxor_Result_4__Mxor__n0000 (
    .Data_0_(U11_U3_counterr[4]),
    .Data_1_(U11_U3__n0006),
    .Result(U11_U3_Maddsub__n0002_Mxor_Result_4___n0002[0])
  );
  INV U11_U3_Maddsub__n0002__n00045 (
    .I(U11_U3_Maddsub__n0002__n00043),
    .O(U11_U3_Maddsub__n0002__n0034[0])
  );
  FD U11_U3_counterr_4 (
    .D(U11_U3__n0000[4]),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U11_U3_counterr[4])
  );
  LPM_XOR2_1 U11_U3_Maddsub__n0002_Mxor_Result_3__Mxor__n0000 (
    .Data_0_(U11_U3_counterr[3]),
    .Data_1_(U11_U3_Maddsub__n0002__n0030[1]),
    .Result(U11_U3_Maddsub__n0002_Mxor_Result_3___n0002[0])
  );
  FD U11_U3_counterr_1 (
    .D(U11_U3__n0000[1]),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U11_U3_counterr[1])
  );
  BUFE U11_U3_I1_5 (
    .E(DCORI2CCNTr),
    .I(U11_U3_counterr[5]),
    .O(outDATA[5])
  );
  LPM_XOR2_1 U11_U3_Maddsub__n0002_Mxor_Result_2__Mxor__n0000 (
    .Data_0_(U11_U3_counterr[2]),
    .Data_1_(U11_U3_Maddsub__n0002__n0028[1]),
    .Result(U11_U3_Maddsub__n0002_Mxor_Result_2___n0002[0])
  );
  LPM_XOR2_1 U11_U3_Maddsub__n0002_Mxor__n0023 (
    .Data_0_(U11_U3__n0006),
    .Data_1_(U11_U3__n0003[3]),
    .Result(U11_U3_Maddsub__n0002__n0030[0])
  );
  FD U11_U3_counterr_5 (
    .D(U11_U3__n0000[5]),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U11_U3_counterr[5])
  );
  LPM_XOR2_1 U11_U3_Maddsub__n0002_Mxor_Result_0_ (
    .Data_0_(U11_U3_counterr[0]),
    .Data_1_(N13655),
    .Result(U11_U3__n0002[0])
  );
  INV U11_U3__n0003_3_1 (
    .I(U11_U3__n0006),
    .O(U11_U3__n0003[3])
  );
  LPM_XOR2_1 U11_U3_Madd__n0001_Mxor_Result_2_ (
    .Data_0_(U11_U3_Madd__n0001__n0003[0]),
    .Data_1_(U11_U3_counterr[5]),
    .Result(U11_U3__n0049[5])
  );
  NegDetect U11_U1 (
    .Line(SCLinc_IBUF),
    .Mclk(Mclk_IBUF),
    .Ndetect(U11_Incdetect)
  );
  NegDetect U11_U2 (
    .Line(SCLout_OBUF),
    .Mclk(Mclk_IBUF),
    .Ndetect(U11_SCLdetect)
  );
  LPM_XOR2_1 U11_U3_Maddsub__n0002_Mxor_Result_2__Mxor_Result (
    .Data_0_(U11_U3_Maddsub__n0002_Mxor_Result_2___n0002[0]),
    .Data_1_(U11_U3_Maddsub__n0002__n0028[0]),
    .Result(U11_U3__n0002[2])
  );
  NegDetect U11_U4 (
    .Line(SCLreset_IBUF),
    .Mclk(Mclk_IBUF),
    .Ndetect(U11_ResetDetect)
  );
  LPM_XOR2_1 U11_U3_Maddsub__n0002_Mxor_Result_3__Mxor_Result (
    .Data_0_(U11_U3_Maddsub__n0002_Mxor_Result_3___n0002[0]),
    .Data_1_(U11_U3_Maddsub__n0002__n0030[0]),
    .Result(U11_U3__n0002[3])
  );
  OR3 U11_U3__n0000_4_10 (
    .I0(U11_U3__n0000_4_9),
    .I1(U11_U3__n0000_4_1),
    .I2(U11_U3__n0000_4_7),
    .O(U11_U3__n0000[4])
  );
  OR3 U11_U3__n0000_5_10 (
    .I0(U11_U3__n0000_5_9),
    .I1(U11_U3__n0000_5_1),
    .I2(U11_U3__n0000_5_7),
    .O(U11_U3__n0000[5])
  );
  LPM_XOR2_1 U11_U3_Maddsub__n0002_Mxor_Result_5__Mxor_Result (
    .Data_0_(U11_U3_Maddsub__n0002_Mxor_Result_5___n0002[0]),
    .Data_1_(U11_U3_Maddsub__n0002__n0034[0]),
    .Result(U11_U3__n0002[5])
  );
  AND2 U11_U3_Maddsub__n0002__n00181 (
    .I0(U11_U3_counterr[4]),
    .I1(U11_U3_Maddsub__n0002__n0032[0]),
    .O(U11_U3_Maddsub__n0002__n0018)
  );
  AND2 U11_U3__n00417 (
    .I0(U11_U3__n00411),
    .I1(U11_U3__n00416),
    .O(U11_U3__n0041)
  );
  AND2 U11_U3__n00428 (
    .I0(U11_U3__n00424),
    .I1(U11_U3__n00427),
    .O(U11_U3__n0042)
  );
  BUFE U11_U3_I1_4 (
    .E(DCORI2CCNTr),
    .I(U11_U3_counterr[4]),
    .O(outDATA[4])
  );
  OR2 U11_U3__n0000_2_11 (
    .I0(U11_U3__n0000_2_9),
    .I1(U11_U3__n0000_2_10),
    .O(U11_U3__n0000[2])
  );
  OR4 U11_U3__n0000_0_17 (
    .I3(U11_U3__n0000_0_14),
    .I0(U11_U3__n0000_0_1),
    .I1(U11_U3__n0000_0_15),
    .I2(U11_U3__n0000_0_16),
    .O(U11_U3__n0000[0])
  );
  AND6 U11_U3__n00057 (
    .I0(U11_U3__n00051),
    .I1(U11_U3__n0005),
    .I2(U11_U3__n00052),
    .I3(U11_U3__n00054),
    .I4(U11_U3__n00053),
    .I5(U11_U3__n00055),
    .O(TP12_OBUF)
  );
  AND2 U11_U3_Madd__n0001__n00001 (
    .I0(U11_U3_counterr[4]),
    .I1(U11_U3_counterr[3]),
    .O(U11_U3_Madd__n0001__n0003[0])
  );
  OR2 U11_U3_Maddsub__n0002__n00037 (
    .I0(U11_U3_Maddsub__n0002__n0003),
    .I1(U11_U3_Maddsub__n0002__n00035),
    .O(U11_U3_Maddsub__n0002__n0032[0])
  );
  OR3 U11_U3__n0000_1_13 (
    .I0(U11_U3__n0000_1_12),
    .I1(U11_U3__n0000_1_11),
    .I2(U11_U3__n0000_1_8),
    .O(U11_U3__n0000[1])
  );
  AND2 U11_U3_Maddsub__n0002__n00171 (
    .I0(U11_U3_counterr[4]),
    .I1(U11_U3__n0006),
    .O(U11_U3_Maddsub__n0002__n0017)
  );
  FD U11_U3_counterr_2 (
    .D(U11_U3__n0000[2]),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U11_U3_counterr[2])
  );
  FD U11_U3_counterr_3 (
    .D(U11_U3__n0000[3]),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U11_U3_counterr[3])
  );
  AND3 U11_U3__n00063 (
    .I0(U11_U3__n00061),
    .I1(U11_SCLdetect),
    .I2(U11_U3__n00062),
    .O(U11_U3__n0006)
  );
  INV GPIO91_2934 (
    .I(TmpEn_OBUF),
    .O(GPIO91)
  );
  INV GPIO101_2935 (
    .I(TmpEn_OBUF),
    .O(GPIO101)
  );
  AND2 U2_ADDR_reg_1__n00001_2936 (
    .I0(U2__n0005),
    .I1(N21771),
    .O(U2_ADDR_reg_1__n00001)
  );
  AND2 U2_ADDR_reg_1__n00002_2937 (
    .I0(U2__n0011[1]),
    .I1(U2__n0006),
    .O(U2_ADDR_reg_1__n00002)
  );
  INV U2_ADDR_reg_1__n00003_2938 (
    .I(U2__n0005),
    .O(U2_ADDR_reg_1__n00003)
  );
  AND2 U2_ADDR_reg_1__n00004_2939 (
    .I0(U2_ADDR_reg_1__n00002),
    .I1(U2_ADDR_reg_1__n00003),
    .O(U2_ADDR_reg_1__n00004)
  );
  OR2 U2_ADDR_reg_1__n00005_2940 (
    .I0(U2_ADDR_reg_1__n00001),
    .I1(U2_ADDR_reg_1__n00004),
    .O(U2_ADDR_reg_1__n00005)
  );
  AND2 U2_ADDR_reg_2__n00001_2941 (
    .I0(U2__n0005),
    .I1(N21773),
    .O(U2_ADDR_reg_2__n00001)
  );
  AND2 U2_ADDR_reg_2__n00002_2942 (
    .I0(U2__n0011[2]),
    .I1(U2__n0006),
    .O(U2_ADDR_reg_2__n00002)
  );
  INV U2_ADDR_reg_2__n00003_2943 (
    .I(U2__n0005),
    .O(U2_ADDR_reg_2__n00003)
  );
  AND2 U2_ADDR_reg_2__n00004_2944 (
    .I0(U2_ADDR_reg_2__n00002),
    .I1(U2_ADDR_reg_2__n00003),
    .O(U2_ADDR_reg_2__n00004)
  );
  OR2 U2_ADDR_reg_2__n00005_2945 (
    .I0(U2_ADDR_reg_2__n00001),
    .I1(U2_ADDR_reg_2__n00004),
    .O(U2_ADDR_reg_2__n00005)
  );
  AND2 U2_ADDR_reg_3__n00001_2946 (
    .I0(U2__n0005),
    .I1(N21775),
    .O(U2_ADDR_reg_3__n00001)
  );
  AND2 U2_ADDR_reg_3__n00002_2947 (
    .I0(U2__n0011[3]),
    .I1(U2__n0006),
    .O(U2_ADDR_reg_3__n00002)
  );
  INV U2_ADDR_reg_3__n00003_2948 (
    .I(U2__n0005),
    .O(U2_ADDR_reg_3__n00003)
  );
  AND2 U2_ADDR_reg_3__n00004_2949 (
    .I0(U2_ADDR_reg_3__n00002),
    .I1(U2_ADDR_reg_3__n00003),
    .O(U2_ADDR_reg_3__n00004)
  );
  OR2 U2_ADDR_reg_3__n00005_2950 (
    .I0(U2_ADDR_reg_3__n00001),
    .I1(U2_ADDR_reg_3__n00004),
    .O(U2_ADDR_reg_3__n00005)
  );
  AND2 U2_ADDR_reg_4__n00001_2951 (
    .I0(U2__n0005),
    .I1(N21777),
    .O(U2_ADDR_reg_4__n00001)
  );
  AND2 U2_ADDR_reg_4__n00002_2952 (
    .I0(U2__n0011[4]),
    .I1(U2__n0006),
    .O(U2_ADDR_reg_4__n00002)
  );
  INV U2_ADDR_reg_4__n00003_2953 (
    .I(U2__n0005),
    .O(U2_ADDR_reg_4__n00003)
  );
  AND2 U2_ADDR_reg_4__n00004_2954 (
    .I0(U2_ADDR_reg_4__n00002),
    .I1(U2_ADDR_reg_4__n00003),
    .O(U2_ADDR_reg_4__n00004)
  );
  OR2 U2_ADDR_reg_4__n00005_2955 (
    .I0(U2_ADDR_reg_4__n00001),
    .I1(U2_ADDR_reg_4__n00004),
    .O(U2_ADDR_reg_4__n00005)
  );
  AND2 U2_ADDR_reg_5__n00001_2956 (
    .I0(U2__n0005),
    .I1(N21761),
    .O(U2_ADDR_reg_5__n00001)
  );
  AND2 U2_ADDR_reg_5__n00002_2957 (
    .I0(U2__n0011[5]),
    .I1(U2__n0006),
    .O(U2_ADDR_reg_5__n00002)
  );
  INV U2_ADDR_reg_5__n00003_2958 (
    .I(U2__n0005),
    .O(U2_ADDR_reg_5__n00003)
  );
  AND2 U2_ADDR_reg_5__n00004_2959 (
    .I0(U2_ADDR_reg_5__n00002),
    .I1(U2_ADDR_reg_5__n00003),
    .O(U2_ADDR_reg_5__n00004)
  );
  OR2 U2_ADDR_reg_5__n00005_2960 (
    .I0(U2_ADDR_reg_5__n00001),
    .I1(U2_ADDR_reg_5__n00004),
    .O(U2_ADDR_reg_5__n00005)
  );
  AND2 U2_ADDR_reg_6__n00001_2961 (
    .I0(U2__n0005),
    .I1(N21763),
    .O(U2_ADDR_reg_6__n00001)
  );
  AND2 U2_ADDR_reg_6__n00002_2962 (
    .I0(U2__n0011[6]),
    .I1(U2__n0006),
    .O(U2_ADDR_reg_6__n00002)
  );
  INV U2_ADDR_reg_6__n00003_2963 (
    .I(U2__n0005),
    .O(U2_ADDR_reg_6__n00003)
  );
  AND2 U2_ADDR_reg_6__n00004_2964 (
    .I0(U2_ADDR_reg_6__n00002),
    .I1(U2_ADDR_reg_6__n00003),
    .O(U2_ADDR_reg_6__n00004)
  );
  OR2 U2_ADDR_reg_6__n00005_2965 (
    .I0(U2_ADDR_reg_6__n00001),
    .I1(U2_ADDR_reg_6__n00004),
    .O(U2_ADDR_reg_6__n00005)
  );
  AND2 U2_ADDR_reg_7__n00001_2966 (
    .I0(U2__n0005),
    .I1(N21765),
    .O(U2_ADDR_reg_7__n00001)
  );
  AND2 U2_ADDR_reg_7__n00002_2967 (
    .I0(U2__n0011[7]),
    .I1(U2__n0006),
    .O(U2_ADDR_reg_7__n00002)
  );
  INV U2_ADDR_reg_7__n00003_2968 (
    .I(U2__n0005),
    .O(U2_ADDR_reg_7__n00003)
  );
  AND2 U2_ADDR_reg_7__n00004_2969 (
    .I0(U2_ADDR_reg_7__n00002),
    .I1(U2_ADDR_reg_7__n00003),
    .O(U2_ADDR_reg_7__n00004)
  );
  OR2 U2_ADDR_reg_7__n00005_2970 (
    .I0(U2_ADDR_reg_7__n00001),
    .I1(U2_ADDR_reg_7__n00004),
    .O(U2_ADDR_reg_7__n00005)
  );
  INV U2_Mcompar__n0006_ALB1_2971 (
    .I(U2_ADDR_reg[4]),
    .O(U2_Mcompar__n0006_ALB)
  );
  INV U2_Mcompar__n0006_ALB2_2972 (
    .I(U2_ADDR_reg[5]),
    .O(U2_Mcompar__n0006_ALB1)
  );
  INV U2_Mcompar__n0006_ALB3_2973 (
    .I(U2_ADDR_reg[6]),
    .O(U2_Mcompar__n0006_ALB2)
  );
  INV U2_Mcompar__n0006_ALB4_2974 (
    .I(U2_ADDR_reg[7]),
    .O(U2_Mcompar__n0006_ALB3)
  );
  AND4 U2_Mcompar__n0006_ALB5_2975 (
    .I0(U2_ADDR_reg[2]),
    .I1(U2_ADDR_reg[3]),
    .I2(U2_ADDR_reg[0]),
    .I3(U2_ADDR_reg[1]),
    .O(U2_Mcompar__n0006_ALB4)
  );
  AND4 U2_Mcompar__n0006_ALB6_2976 (
    .I0(U2_Mcompar__n0006_ALB),
    .I1(U2_Mcompar__n0006_ALB1),
    .I2(U2_Mcompar__n0006_ALB2),
    .I3(U2_Mcompar__n0006_ALB3),
    .O(U2_Mcompar__n0006_ALB5)
  );
  INV U2_Mcompar__n0006_ALB7 (
    .I(U2_Mcompar__n0006_ALB4),
    .O(U2_Mcompar__n0006_ALB6)
  );
  AND2 U11_U3_Maddsub__n0002__n00001_2977 (
    .I0(U11_U3__n0006),
    .I1(U11_U3_counterr[0]),
    .O(U11_U3_Maddsub__n0002__n0000)
  );
  INV U11_U3_Maddsub__n0002__n00002_2978 (
    .I(U11_U3__n0006),
    .O(U11_U3_Maddsub__n0002__n00001)
  );
  INV U11_U3_Maddsub__n0002__n00003_2979 (
    .I(U11_U3_counterr[0]),
    .O(U11_U3_Maddsub__n0002__n00002)
  );
  AND2 U11_U3_Maddsub__n0002__n00004_2980 (
    .I0(U11_U3_Maddsub__n0002__n00001),
    .I1(U11_U3_Maddsub__n0002__n00002),
    .O(U11_U3_Maddsub__n0002__n00003)
  );
  INV U11_U3_Maddsub__n0002__n00005_2981 (
    .I(U11_U3_Maddsub__n0002__n00003),
    .O(U11_U3_Maddsub__n0002__n00004)
  );
  AND2 U11_U3_Maddsub__n0002__n00006 (
    .I0(U11_U3_Maddsub__n0002__n0020),
    .I1(U11_U3_Maddsub__n0002__n00004),
    .O(U11_U3_Maddsub__n0002__n00005)
  );
  AND2 U2_ADDR_reg_0__n00021_2982 (
    .I0(RD_IBUF),
    .I1(WR_IBUF),
    .O(U2_ADDR_reg_0__n00021)
  );
  AND2 U2_ADDR_reg_0__n00022_2983 (
    .I0(U2_AutoInc),
    .I1(U2_ADDR_in_Range),
    .O(U2_ADDR_reg_0__n00022)
  );
  INV U2_ADDR_reg_0__n00023_2984 (
    .I(U2_WRRDedge),
    .O(U2_ADDR_reg_0__n00023)
  );
  INV U2_ADDR_reg_0__n00024_2985 (
    .I(MSPReset_IBUF),
    .O(U2_ADDR_reg_0__n00024)
  );
  AND2 U2_ADDR_reg_0__n00025_2986 (
    .I0(U2_ADDR_reg_0__n00022),
    .I1(U2_ADDR_reg_0__n00023),
    .O(U2_ADDR_reg_0__n00025)
  );
  OR2 U2_ADDR_reg_0__n00026_2987 (
    .I0(NET4826),
    .I1(U2_ADDR_reg_0__n00025),
    .O(U2_ADDR_reg_0__n00026)
  );
  AND2 U2_ADDR_reg_0__n00027_2988 (
    .I0(U2_ADDR_reg_0__n00021),
    .I1(U2_ADDR_reg_0__n00026),
    .O(U2_ADDR_reg_0__n00027)
  );
  AND2 U2_ADDR_reg_0__n00001_2989 (
    .I0(U2__n0005),
    .I1(N21767),
    .O(U2_ADDR_reg_0__n00001)
  );
  INV U2_ADDR_reg_0__n00002_2990 (
    .I(U2_ADDR_reg[0]),
    .O(U2_ADDR_reg_0__n00002)
  );
  INV U2_ADDR_reg_0__n00003_2991 (
    .I(U2__n0005),
    .O(U2_ADDR_reg_0__n00003)
  );
  INV U2_ADDR_reg_0__n00004_2992 (
    .I(U2_ADDR_reg[4]),
    .O(U2_ADDR_reg_0__n00004)
  );
  INV U2_ADDR_reg_0__n00005_2993 (
    .I(U2_ADDR_reg[6]),
    .O(U2_ADDR_reg_0__n00005)
  );
  INV U2_ADDR_reg_0__n00006_2994 (
    .I(U2_ADDR_reg[5]),
    .O(U2_ADDR_reg_0__n00006)
  );
  INV U2_ADDR_reg_0__n00007_2995 (
    .I(U2_ADDR_reg[7]),
    .O(U2_ADDR_reg_0__n00007)
  );
  AND6 U2_ADDR_reg_0__n00008_2996 (
    .I0(U2_ADDR_reg_0__n00003),
    .I1(U2_ADDR_reg_0__n00002),
    .I2(U2_ADDR_reg_0__n00004),
    .I3(U2_ADDR_reg_0__n00006),
    .I4(U2_ADDR_reg_0__n00005),
    .I5(U2_ADDR_reg_0__n00007),
    .O(U2_ADDR_reg_0__n00008)
  );
  OR2 U2_ADDR_reg_0__n00009_2997 (
    .I0(U2_ADDR_reg_0__n00001),
    .I1(U2_ADDR_reg_0__n00008),
    .O(U2_ADDR_reg_0__n00009)
  );
  INV U2__n00031_2998 (
    .I(U2__n0000),
    .O(U2__n00031)
  );
  INV U2_Mcompar_ADDR_in_Range_ALEB1_2999 (
    .I(U2_ADDR_reg[4]),
    .O(U2_Mcompar_ADDR_in_Range_ALEB)
  );
  INV U2_Mcompar_ADDR_in_Range_ALEB2_3000 (
    .I(U2_ADDR_reg[5]),
    .O(U2_Mcompar_ADDR_in_Range_ALEB1)
  );
  INV U2_Mcompar_ADDR_in_Range_ALEB3_3001 (
    .I(U2_ADDR_reg[6]),
    .O(U2_Mcompar_ADDR_in_Range_ALEB2)
  );
  INV U2_Mcompar_ADDR_in_Range_ALEB4 (
    .I(U2_ADDR_reg[7]),
    .O(U2_Mcompar_ADDR_in_Range_ALEB3)
  );
  INV U2_ASleading1 (
    .I(AS_IBUF),
    .O(U2_ASleading)
  );
  AND2 U2_Enable_AD1_3002 (
    .I0(U2_ADDR_in_Range),
    .I1(WR_IBUF),
    .O(U2_Enable_AD1)
  );
  INV U2_Enable_AD2_3003 (
    .I(RD_IBUF),
    .O(U2_Enable_AD2)
  );
  AND2 U11_U3_Maddsub__n0002__n00021_3004 (
    .I0(U11_U3_Maddsub__n0002__n0028[1]),
    .I1(U11_U3_counterr[2]),
    .O(U11_U3_Maddsub__n0002__n0002)
  );
  INV U11_U3_Maddsub__n0002__n00022_3005 (
    .I(U11_U3_Maddsub__n0002__n0028[1]),
    .O(U11_U3_Maddsub__n0002__n00021)
  );
  INV U11_U3_Maddsub__n0002__n00023_3006 (
    .I(U11_U3_counterr[2]),
    .O(U11_U3_Maddsub__n0002__n00022)
  );
  AND2 U11_U3_Maddsub__n0002__n00024_3007 (
    .I0(U11_U3_Maddsub__n0002__n00021),
    .I1(U11_U3_Maddsub__n0002__n00022),
    .O(U11_U3_Maddsub__n0002__n00023)
  );
  INV U11_U3_Maddsub__n0002__n00025_3008 (
    .I(U11_U3_Maddsub__n0002__n00023),
    .O(U11_U3_Maddsub__n0002__n00024)
  );
  AND2 U11_U3_Maddsub__n0002__n00026 (
    .I0(U11_U3_Maddsub__n0002__n0028[0]),
    .I1(U11_U3_Maddsub__n0002__n00024),
    .O(U11_U3_Maddsub__n0002__n00025)
  );
  AND2 U11_U3_Maddsub__n0002__n00011_3009 (
    .I0(U11_U3_Maddsub__n0002__n0026[1]),
    .I1(U11_U3_counterr[1]),
    .O(U11_U3_Maddsub__n0002__n0001)
  );
  INV U11_U3_Maddsub__n0002__n00012_3010 (
    .I(U11_U3_Maddsub__n0002__n0026[1]),
    .O(U11_U3_Maddsub__n0002__n00011)
  );
  INV U11_U3_Maddsub__n0002__n00013_3011 (
    .I(U11_U3_counterr[1]),
    .O(U11_U3_Maddsub__n0002__n00012)
  );
  AND2 U11_U3_Maddsub__n0002__n00014_3012 (
    .I0(U11_U3_Maddsub__n0002__n00011),
    .I1(U11_U3_Maddsub__n0002__n00012),
    .O(U11_U3_Maddsub__n0002__n00013)
  );
  INV U11_U3_Maddsub__n0002__n00015_3013 (
    .I(U11_U3_Maddsub__n0002__n00013),
    .O(U11_U3_Maddsub__n0002__n00014)
  );
  AND2 U11_U3_Maddsub__n0002__n00016 (
    .I0(U11_U3_Maddsub__n0002__n0026[0]),
    .I1(U11_U3_Maddsub__n0002__n00014),
    .O(U11_U3_Maddsub__n0002__n00015)
  );
  INV U11_U3__n0000_3_1_3014 (
    .I(TP12_OBUF),
    .O(U11_U3__n0000_3_1)
  );
  INV U11_U3__n0000_3_2_3015 (
    .I(U11_U3_counterr[3]),
    .O(U11_U3__n0000_3_2)
  );
  INV U11_U3__n0000_3_3_3016 (
    .I(U11_SCLdetect),
    .O(U11_U3__n0000_3_3)
  );
  INV U11_U3__n0000_3_4_3017 (
    .I(U11_Incdetect),
    .O(U11_U3__n0000_3_4)
  );
  AND2 U11_U3__n0000_3_5_3018 (
    .I0(U11_U3__n0006),
    .I1(U11_U3__n0000_3_1),
    .O(U11_U3__n0000_3_5)
  );
  AND2 U11_U3__n0000_3_6_3019 (
    .I0(U11_U3__n0041),
    .I1(U11_U3__n0000_3_2),
    .O(U11_U3__n0000_3_6)
  );
  AND3 U11_U3__n0000_3_7_3020 (
    .I0(U11_U3__n0000_3_3),
    .I1(U11_U3_counterr[3]),
    .I2(U11_U3__n0000_3_4),
    .O(U11_U3__n0000_3_7)
  );
  OR2 U11_U3__n0000_3_8_3021 (
    .I0(U11_U3__n0042),
    .I1(U11_U3__n0000_3_5),
    .O(U11_U3__n0000_3_8)
  );
  OR2 U11_U3__n0000_3_9_3022 (
    .I0(U11_U3__n0000_3_6),
    .I1(U11_U3__n0000_3_7),
    .O(U11_U3__n0000_3_9)
  );
  AND2 U11_U3__n0000_3_10_3023 (
    .I0(U11_U3__n0002[3]),
    .I1(U11_U3__n0000_3_8),
    .O(U11_U3__n0000_3_10)
  );
  INV U11_U3_Maddsub__n0002__n00041_3024 (
    .I(U11_U3_Maddsub__n0002__n0019),
    .O(U11_U3_Maddsub__n0002__n0004)
  );
  INV U11_U3_Maddsub__n0002__n00042_3025 (
    .I(U11_U3_Maddsub__n0002__n0018),
    .O(U11_U3_Maddsub__n0002__n00041)
  );
  INV U11_U3_Maddsub__n0002__n00043_3026 (
    .I(U11_U3_Maddsub__n0002__n0017),
    .O(U11_U3_Maddsub__n0002__n00042)
  );
  AND3 U11_U3_Maddsub__n0002__n00044 (
    .I0(U11_U3_Maddsub__n0002__n00041),
    .I1(U11_U3_Maddsub__n0002__n0004),
    .I2(U11_U3_Maddsub__n0002__n00042),
    .O(U11_U3_Maddsub__n0002__n00043)
  );
  AND2 U11_U3__n0000_4_1_3027 (
    .I0(U11_U3__n0041),
    .I1(U11_U3__n0049[4]),
    .O(U11_U3__n0000_4_1)
  );
  INV U11_U3__n0000_4_2_3028 (
    .I(TP12_OBUF),
    .O(U11_U3__n0000_4_2)
  );
  INV U11_U3__n0000_4_3_3029 (
    .I(U11_SCLdetect),
    .O(U11_U3__n0000_4_3)
  );
  INV U11_U3__n0000_4_4_3030 (
    .I(U11_Incdetect),
    .O(U11_U3__n0000_4_4)
  );
  INV U11_U3__n0000_4_5_3031 (
    .I(SCLreset_IBUF),
    .O(U11_U3__n0000_4_5)
  );
  AND2 U11_U3__n0000_4_6_3032 (
    .I0(U11_U3__n0006),
    .I1(U11_U3__n0000_4_2),
    .O(U11_U3__n0000_4_6)
  );
  AND4 U11_U3__n0000_4_7_3033 (
    .I0(U11_U3_counterr[4]),
    .I1(U11_U3__n0000_4_3),
    .I2(U11_U3__n0000_4_4),
    .I3(U11_U3__n0000_4_5),
    .O(U11_U3__n0000_4_7)
  );
  OR2 U11_U3__n0000_4_8_3034 (
    .I0(U11_U3__n0042),
    .I1(U11_U3__n0000_4_6),
    .O(U11_U3__n0000_4_8)
  );
  AND2 U11_U3__n0000_4_9_3035 (
    .I0(U11_U3__n0002[4]),
    .I1(U11_U3__n0000_4_8),
    .O(U11_U3__n0000_4_9)
  );
  AND2 U11_U3__n0000_5_1_3036 (
    .I0(U11_U3__n0041),
    .I1(U11_U3__n0049[5]),
    .O(U11_U3__n0000_5_1)
  );
  INV U11_U3__n0000_5_2_3037 (
    .I(TP12_OBUF),
    .O(U11_U3__n0000_5_2)
  );
  INV U11_U3__n0000_5_3_3038 (
    .I(U11_SCLdetect),
    .O(U11_U3__n0000_5_3)
  );
  INV U11_U3__n0000_5_4_3039 (
    .I(U11_Incdetect),
    .O(U11_U3__n0000_5_4)
  );
  INV U11_U3__n0000_5_5_3040 (
    .I(SCLreset_IBUF),
    .O(U11_U3__n0000_5_5)
  );
  AND2 U11_U3__n0000_5_6_3041 (
    .I0(U11_U3__n0006),
    .I1(U11_U3__n0000_5_2),
    .O(U11_U3__n0000_5_6)
  );
  AND4 U11_U3__n0000_5_7_3042 (
    .I0(U11_U3_counterr[5]),
    .I1(U11_U3__n0000_5_3),
    .I2(U11_U3__n0000_5_4),
    .I3(U11_U3__n0000_5_5),
    .O(U11_U3__n0000_5_7)
  );
  OR2 U11_U3__n0000_5_8_3043 (
    .I0(U11_U3__n0042),
    .I1(U11_U3__n0000_5_6),
    .O(U11_U3__n0000_5_8)
  );
  AND2 U11_U3__n0000_5_9_3044 (
    .I0(U11_U3__n0002[5]),
    .I1(U11_U3__n0000_5_8),
    .O(U11_U3__n0000_5_9)
  );
  AND2 U11_U3__n00411_3045 (
    .I0(U11_SCLdetect),
    .I1(U11_Incdetect),
    .O(U11_U3__n00411)
  );
  INV U11_U3__n00412_3046 (
    .I(SCLreset_IBUF),
    .O(U11_U3__n00412)
  );
  INV U11_U3__n00413_3047 (
    .I(SCLinc_IBUF),
    .O(U11_U3__n00413)
  );
  AND2 U11_U3__n00414_3048 (
    .I0(U11_ResetDetect),
    .I1(U11_U3__n00413),
    .O(U11_U3__n00414)
  );
  INV U11_U3__n00415_3049 (
    .I(U11_U3__n00414),
    .O(U11_U3__n00415)
  );
  AND2 U11_U3__n00416_3050 (
    .I0(U11_U3__n00412),
    .I1(U11_U3__n00415),
    .O(U11_U3__n00416)
  );
  INV U11_U3__n00421_3051 (
    .I(U11_SCLdetect),
    .O(U11_U3__n00421)
  );
  INV U11_U3__n00422_3052 (
    .I(SCLreset_IBUF),
    .O(U11_U3__n00422)
  );
  INV U11_U3__n00423_3053 (
    .I(SCLinc_IBUF),
    .O(U11_U3__n00423)
  );
  AND2 U11_U3__n00424_3054 (
    .I0(U11_Incdetect),
    .I1(U11_U3__n00421),
    .O(U11_U3__n00424)
  );
  AND2 U11_U3__n00425_3055 (
    .I0(U11_ResetDetect),
    .I1(U11_U3__n00423),
    .O(U11_U3__n00425)
  );
  INV U11_U3__n00426_3056 (
    .I(U11_U3__n00425),
    .O(U11_U3__n00426)
  );
  AND2 U11_U3__n00427_3057 (
    .I0(U11_U3__n00422),
    .I1(U11_U3__n00426),
    .O(U11_U3__n00427)
  );
  INV U11_U3__n0000_2_1_3058 (
    .I(TP12_OBUF),
    .O(U11_U3__n0000_2_1)
  );
  INV U11_U3__n0000_2_2_3059 (
    .I(U11_Incdetect),
    .O(U11_U3__n0000_2_2)
  );
  INV U11_U3__n0000_2_3_3060 (
    .I(U11_SCLdetect),
    .O(U11_U3__n0000_2_3)
  );
  INV U11_U3__n0000_2_4_3061 (
    .I(SCLreset_IBUF),
    .O(U11_U3__n0000_2_4)
  );
  AND2 U11_U3__n0000_2_5_3062 (
    .I0(U11_U3__n0006),
    .I1(U11_U3__n0000_2_1),
    .O(U11_U3__n0000_2_5)
  );
  AND3 U11_U3__n0000_2_6_3063 (
    .I0(U11_U3__n0000_2_3),
    .I1(U11_U3__n0000_2_2),
    .I2(U11_U3__n0000_2_4),
    .O(U11_U3__n0000_2_6)
  );
  OR2 U11_U3__n0000_2_7_3064 (
    .I0(U11_U3__n0042),
    .I1(U11_U3__n0000_2_5),
    .O(U11_U3__n0000_2_7)
  );
  OR2 U11_U3__n0000_2_8_3065 (
    .I0(U11_U3__n0041),
    .I1(U11_U3__n0000_2_6),
    .O(U11_U3__n0000_2_8)
  );
  AND2 U11_U3__n0000_2_9_3066 (
    .I0(U11_U3__n0002[2]),
    .I1(U11_U3__n0000_2_7),
    .O(U11_U3__n0000_2_9)
  );
  AND2 U11_U3__n0000_2_10_3067 (
    .I0(U11_U3_counterr[2]),
    .I1(U11_U3__n0000_2_8),
    .O(U11_U3__n0000_2_10)
  );
  AND2 U11_U3__n0000_0_1_3068 (
    .I0(SCLreset_IBUF),
    .I1(SCLinc_IBUF),
    .O(U11_U3__n0000_0_1)
  );
  INV U11_U3__n0000_0_2_3069 (
    .I(TP12_OBUF),
    .O(U11_U3__n0000_0_2)
  );
  INV U11_U3__n0000_0_3_3070 (
    .I(U11_Incdetect),
    .O(U11_U3__n0000_0_3)
  );
  INV U11_U3__n0000_0_4_3071 (
    .I(U11_SCLdetect),
    .O(U11_U3__n0000_0_4)
  );
  INV U11_U3__n0000_0_5_3072 (
    .I(SCLreset_IBUF),
    .O(U11_U3__n0000_0_5)
  );
  AND2 U11_U3__n0000_0_6_3073 (
    .I0(U11_Incdetect),
    .I1(U11_ResetDetect),
    .O(U11_U3__n0000_0_6)
  );
  INV U11_U3__n0000_0_7_3074 (
    .I(SCLreset_IBUF),
    .O(U11_U3__n0000_0_7)
  );
  INV U11_U3__n0000_0_8_3075 (
    .I(SCLinc_IBUF),
    .O(U11_U3__n0000_0_8)
  );
  AND2 U11_U3__n0000_0_9_3076 (
    .I0(U11_U3__n0006),
    .I1(U11_U3__n0000_0_2),
    .O(U11_U3__n0000_0_9)
  );
  AND3 U11_U3__n0000_0_10_3077 (
    .I0(U11_U3__n0000_0_4),
    .I1(U11_U3__n0000_0_3),
    .I2(U11_U3__n0000_0_5),
    .O(U11_U3__n0000_0_10)
  );
  AND2 U11_U3__n0000_0_11_3078 (
    .I0(U11_U3__n0000_0_7),
    .I1(U11_U3__n0000_0_8),
    .O(U11_U3__n0000_0_11)
  );
  OR2 U11_U3__n0000_0_12_3079 (
    .I0(U11_U3__n0042),
    .I1(U11_U3__n0000_0_9),
    .O(U11_U3__n0000_0_12)
  );
  OR2 U11_U3__n0000_0_13_3080 (
    .I0(U11_U3__n0041),
    .I1(U11_U3__n0000_0_10),
    .O(U11_U3__n0000_0_13)
  );
  AND2 U11_U3__n0000_0_14_3081 (
    .I0(U11_U3__n0000_0_6),
    .I1(U11_U3__n0000_0_11),
    .O(U11_U3__n0000_0_14)
  );
  AND2 U11_U3__n0000_0_15_3082 (
    .I0(U11_U3__n0002[0]),
    .I1(U11_U3__n0000_0_12),
    .O(U11_U3__n0000_0_15)
  );
  AND2 U11_U3__n0000_0_16_3083 (
    .I0(U11_U3_counterr[0]),
    .I1(U11_U3__n0000_0_13),
    .O(U11_U3__n0000_0_16)
  );
  INV U11_U3__n00051_3084 (
    .I(U11_U3_counterr[1]),
    .O(U11_U3__n0005)
  );
  INV U11_U3__n00052_3085 (
    .I(U11_U3_counterr[0]),
    .O(U11_U3__n00051)
  );
  INV U11_U3__n00053_3086 (
    .I(U11_U3_counterr[2]),
    .O(U11_U3__n00052)
  );
  INV U11_U3__n00054_3087 (
    .I(U11_U3_counterr[4]),
    .O(U11_U3__n00053)
  );
  INV U11_U3__n00055_3088 (
    .I(U11_U3_counterr[3]),
    .O(U11_U3__n00054)
  );
  INV U11_U3__n00056 (
    .I(U11_U3_counterr[5]),
    .O(U11_U3__n00055)
  );
  AND2 U11_U3_Maddsub__n0002__n00031_3089 (
    .I0(U11_U3_Maddsub__n0002__n0030[1]),
    .I1(U11_U3_counterr[3]),
    .O(U11_U3_Maddsub__n0002__n0003)
  );
  INV U11_U3_Maddsub__n0002__n00032_3090 (
    .I(U11_U3_Maddsub__n0002__n0030[1]),
    .O(U11_U3_Maddsub__n0002__n00031)
  );
  INV U11_U3_Maddsub__n0002__n00033_3091 (
    .I(U11_U3_counterr[3]),
    .O(U11_U3_Maddsub__n0002__n00032)
  );
  AND2 U11_U3_Maddsub__n0002__n00034_3092 (
    .I0(U11_U3_Maddsub__n0002__n00031),
    .I1(U11_U3_Maddsub__n0002__n00032),
    .O(U11_U3_Maddsub__n0002__n00033)
  );
  INV U11_U3_Maddsub__n0002__n00035_3093 (
    .I(U11_U3_Maddsub__n0002__n00033),
    .O(U11_U3_Maddsub__n0002__n00034)
  );
  AND2 U11_U3_Maddsub__n0002__n00036 (
    .I0(U11_U3_Maddsub__n0002__n0030[0]),
    .I1(U11_U3_Maddsub__n0002__n00034),
    .O(U11_U3_Maddsub__n0002__n00035)
  );
  INV U11_U3__n0000_1_1_3094 (
    .I(TP12_OBUF),
    .O(U11_U3__n0000_1_1)
  );
  INV U11_U3__n0000_1_2_3095 (
    .I(U11_Incdetect),
    .O(U11_U3__n0000_1_2)
  );
  INV U11_U3__n0000_1_3_3096 (
    .I(U11_SCLdetect),
    .O(U11_U3__n0000_1_3)
  );
  INV U11_U3__n0000_1_4_3097 (
    .I(SCLreset_IBUF),
    .O(U11_U3__n0000_1_4)
  );
  INV U11_U3__n0000_1_5_3098 (
    .I(SCLinc_IBUF),
    .O(U11_U3__n0000_1_5)
  );
  AND2 U11_U3__n0000_1_6_3099 (
    .I0(U11_U3__n0006),
    .I1(U11_U3__n0000_1_1),
    .O(U11_U3__n0000_1_6)
  );
  AND3 U11_U3__n0000_1_7_3100 (
    .I0(U11_U3__n0000_1_3),
    .I1(U11_U3__n0000_1_2),
    .I2(U11_U3__n0000_1_4),
    .O(U11_U3__n0000_1_7)
  );
  AND2 U11_U3__n0000_1_8_3101 (
    .I0(SCLreset_IBUF),
    .I1(U11_U3__n0000_1_5),
    .O(U11_U3__n0000_1_8)
  );
  OR2 U11_U3__n0000_1_9_3102 (
    .I0(U11_U3__n0042),
    .I1(U11_U3__n0000_1_6),
    .O(U11_U3__n0000_1_9)
  );
  OR2 U11_U3__n0000_1_10_3103 (
    .I0(U11_U3__n0041),
    .I1(U11_U3__n0000_1_7),
    .O(U11_U3__n0000_1_10)
  );
  AND2 U11_U3__n0000_1_11_3104 (
    .I0(U11_U3__n0002[1]),
    .I1(U11_U3__n0000_1_9),
    .O(U11_U3__n0000_1_11)
  );
  AND2 U11_U3__n0000_1_12_3105 (
    .I0(U11_U3_counterr[1]),
    .I1(U11_U3__n0000_1_10),
    .O(U11_U3__n0000_1_12)
  );
  INV U11_U3__n00061_3106 (
    .I(U11_Incdetect),
    .O(U11_U3__n00061)
  );
  INV U11_U3__n00062_3107 (
    .I(SCLreset_IBUF),
    .O(U11_U3__n00062)
  );
  IBUF Mclk_IBUF_3108 (
    .I(Mclk),
    .O(Mclk_IBUF)
  );
  IBUF Brake0_IBUF_3109 (
    .I(Brake0),
    .O(Brake0_IBUF)
  );
  IBUF Home033FLG_IBUF_3110 (
    .I(Home033FLG),
    .O(Home033FLG_IBUF)
  );
  IBUF Brake1_IBUF_3111 (
    .I(Brake1),
    .O(Brake1_IBUF)
  );
  IBUF LightSense_IBUF_3112 (
    .I(LightSense),
    .O(LightSense_IBUF)
  );
  IBUF AS_IBUF_3113 (
    .I(AS),
    .O(AS_IBUF)
  );
  IBUF PhaseB_Encoder0_IBUF_3114 (
    .I(PhaseB_Encoder0),
    .O(PhaseB_Encoder0_IBUF)
  );
  IBUF PhaseB_Encoder1_IBUF_3115 (
    .I(PhaseB_Encoder1),
    .O(PhaseB_Encoder1_IBUF)
  );
  IBUF MSPReset_IBUF_3116 (
    .I(MSPReset),
    .O(MSPReset_IBUF)
  );
  IBUF INTbus_IBUF_3117 (
    .I(INTbus),
    .O(INTbus_IBUF)
  );
  IBUF Home05FLG_IBUF_3118 (
    .I(Home05FLG),
    .O(Home05FLG_IBUF)
  );
  IBUF Home133FLG_IBUF_3119 (
    .I(Home133FLG),
    .O(Home133FLG_IBUF)
  );
  IBUF PhaseA_Encoder0_IBUF_3120 (
    .I(PhaseA_Encoder0),
    .O(PhaseA_Encoder0_IBUF)
  );
  IBUF PhaseA_Encoder1_IBUF_3121 (
    .I(PhaseA_Encoder1),
    .O(PhaseA_Encoder1_IBUF)
  );
  IBUF PWM1_IBUF_3122 (
    .I(PWM1),
    .O(PWM1_IBUF)
  );
  IBUF PWM2_IBUF_3123 (
    .I(PWM2),
    .O(PWM2_IBUF)
  );
  IBUF Home0_IBUF_3124 (
    .I(Home0),
    .O(Home0_IBUF)
  );
  IBUF PWM3_IBUF_3125 (
    .I(PWM3),
    .O(PWM3_IBUF)
  );
  IBUF Home1_IBUF_3126 (
    .I(Home1),
    .O(Home1_IBUF)
  );
  IBUF PWM4_IBUF_3127 (
    .I(PWM4),
    .O(PWM4_IBUF)
  );
  IBUF Enc033FLG_IBUF_3128 (
    .I(Enc033FLG),
    .O(Enc033FLG_IBUF)
  );
  IBUF RLS0_IBUF_3129 (
    .I(RLS0),
    .O(RLS0_IBUF)
  );
  IBUF PWM5_IBUF (
    .I(PWM5),
    .O(GPIO8_OBUF)
  );
  IBUF RLS1_IBUF_3130 (
    .I(RLS1),
    .O(RLS1_IBUF)
  );
  IBUF GP_Motor0_0_IBUF_3131 (
    .I(GP_Motor0_0),
    .O(GP_Motor0_0_IBUF)
  );
  IBUF Home15FLG_IBUF_3132 (
    .I(Home15FLG),
    .O(Home15FLG_IBUF)
  );
  IBUF RD_IBUF_3133 (
    .I(RD),
    .O(RD_IBUF)
  );
  IBUF Enc05FLG_IBUF_3134 (
    .I(Enc05FLG),
    .O(Enc05FLG_IBUF)
  );
  IBUF GP_Motor1_0_IBUF_3135 (
    .I(GP_Motor1_0),
    .O(GP_Motor1_0_IBUF)
  );
  IBUF TXI_IBUF (
    .I(TXI),
    .O(MTXI_OBUF)
  );
  IBUF Enc133FLG_IBUF_3136 (
    .I(Enc133FLG),
    .O(Enc133FLG_IBUF)
  );
  IBUF FLS0_IBUF_3137 (
    .I(FLS0),
    .O(FLS0_IBUF)
  );
  IBUF FLS1_IBUF_3138 (
    .I(FLS1),
    .O(FLS1_IBUF)
  );
  IBUF WR_IBUF_3139 (
    .I(WR),
    .O(WR_IBUF)
  );
  IBUF Enc15FLG_IBUF_3140 (
    .I(Enc15FLG),
    .O(Enc15FLG_IBUF)
  );
  IBUF MHSO_IBUF (
    .I(MHSO),
    .O(HSO_OBUF)
  );
  IBUF SCLreset_IBUF_3141 (
    .I(SCLreset),
    .O(SCLreset_IBUF)
  );
  IBUF HSI_IBUF (
    .I(HSI),
    .O(MHSI_OBUF)
  );
  IBUF DIR0_IBUF_3142 (
    .I(DIR0),
    .O(DIR0_IBUF)
  );
  IBUF DIR1_IBUF_3143 (
    .I(DIR1),
    .O(DIR1_IBUF)
  );
  IBUF SCLinc_IBUF_3144 (
    .I(SCLinc),
    .O(SCLinc_IBUF)
  );
  IBUF MReset_IBUF_3145 (
    .I(MReset),
    .O(MReset_IBUF)
  );
  IBUF I2CS_5_IBUF_3146 (
    .I(I2CS[5]),
    .O(I2CS_5_IBUF)
  );
  IBUF I2CS_4_IBUF_3147 (
    .I(I2CS[4]),
    .O(I2CS_4_IBUF)
  );
  IBUF I2CS_3_IBUF_3148 (
    .I(I2CS[3]),
    .O(I2CS_3_IBUF)
  );
  IBUF I2CS_2_IBUF_3149 (
    .I(I2CS[2]),
    .O(I2CS_2_IBUF)
  );
  IBUF I2CS_1_IBUF_3150 (
    .I(I2CS[1]),
    .O(I2CS_1_IBUF)
  );
  IBUF I2CS_0_IBUF_3151 (
    .I(I2CS[0]),
    .O(I2CS_0_IBUF)
  );
  OBUF Home033ctrl_OBUF_3152 (
    .I(Home033ctrl_OBUF),
    .O(Home033ctrl)
  );
  OBUF MTRpwrn_OBUF_3153 (
    .I(MTRpwrn_OBUF),
    .O(MTRpwrn)
  );
  OBUF Home15ctrl_OBUF_3154 (
    .I(Home15ctrl_OBUF),
    .O(Home15ctrl)
  );
  OBUF TmpSlct_OBUF_3155 (
    .I(TmpSlct_OBUF),
    .O(TmpSlct)
  );
  OBUF LED1_OBUF_3156 (
    .I(LED1_OBUF),
    .O(LED1)
  );
  OBUF LED2_OBUF_3157 (
    .I(LED2_OBUF),
    .O(LED2)
  );
  OBUF Enc05ctrl_OBUF_3158 (
    .I(Enc05ctrl_OBUF),
    .O(Enc05ctrl)
  );
  OBUF LED3_OBUF_3159 (
    .I(LED3_OBUF),
    .O(LED3)
  );
  OBUF LED4_OBUF_3160 (
    .I(LED4_OBUF),
    .O(LED4)
  );
  OBUF LED5_OBUF_3161 (
    .I(LED5_OBUF),
    .O(LED5)
  );
  OBUF TP10_OBUF_3162 (
    .I(TP10_OBUF),
    .O(TP10)
  );
  OBUF TP12_OBUF_3163 (
    .I(TP12_OBUF),
    .O(TP12)
  );
  OBUF PAH0_OBUF_3164 (
    .I(PAH0_OBUF),
    .O(PAH0)
  );
  OBUF PAH1_OBUF_3165 (
    .I(PAH1_OBUF),
    .O(PAH1)
  );
  OBUF Enc15ctrl_OBUF_3166 (
    .I(Enc15ctrl_OBUF),
    .O(Enc15ctrl)
  );
  OBUF MTXI_OBUF_3167 (
    .I(MTXI_OBUF),
    .O(MTXI)
  );
  OBUF GP_Motor0_1_OBUF_3168 (
    .I(GP_Motor0_1_OBUF),
    .O(GP_Motor0_1)
  );
  OBUF TmpEn_OBUF_3169 (
    .I(TmpEn_OBUF),
    .O(TmpEn)
  );
  OBUF PAL0_OBUF_3170 (
    .I(PAL0_OBUF),
    .O(PAL0)
  );
  OBUF PAL1_OBUF_3171 (
    .I(PAL1_OBUF),
    .O(PAL1)
  );
  OBUF Enc133ctrl_OBUF_3172 (
    .I(Enc133ctrl_OBUF),
    .O(Enc133ctrl)
  );
  OBUF PBH0_OBUF_3173 (
    .I(PBH0_OBUF),
    .O(PBH0)
  );
  OBUF PBH1_OBUF_3174 (
    .I(PBH1_OBUF),
    .O(PBH1)
  );
  OBUF Enc033ctrl_OBUF_3175 (
    .I(Enc033ctrl_OBUF),
    .O(Enc033ctrl)
  );
  OBUF PresEn_OBUF_3176 (
    .I(PresEn_OBUF),
    .O(PresEn)
  );
  OBUF GPIO8_OBUF_3177 (
    .I(GPIO8_OBUF),
    .O(GPIO8)
  );
  OBUF GPIO9_OBUF_3178 (
    .I(GPIO9_OBUF),
    .O(GPIO9)
  );
  OBUF GP_Motor1_1_OBUF_3179 (
    .I(GP_Motor1_1_OBUF),
    .O(GP_Motor1_1)
  );
  OBUF PBL0_OBUF_3180 (
    .I(PBL0_OBUF),
    .O(PBL0)
  );
  OBUF PBL1_OBUF_3181 (
    .I(PBL1_OBUF),
    .O(PBL1)
  );
  OBUF GPIO10_OBUF_3182 (
    .I(GPIO10_OBUF),
    .O(GPIO10)
  );
  OBUF MHSI_OBUF_3183 (
    .I(MHSI_OBUF),
    .O(MHSI)
  );
  OBUF PresSlct_OBUF_3184 (
    .I(PresSlct_OBUF),
    .O(PresSlct)
  );
  OBUF Home05ctrl_OBUF_3185 (
    .I(Home05ctrl_OBUF),
    .O(Home05ctrl)
  );
  OBUF HSO_OBUF_3186 (
    .I(HSO_OBUF),
    .O(HSO)
  );
  OBUF INT_OBUF_3187 (
    .I(INT_OBUF),
    .O(INT)
  );
  OBUF MTRpwr_OBUF_3188 (
    .I(MTRpwr_OBUF),
    .O(MTRpwr)
  );
  OBUF SCLout_OBUF_3189 (
    .I(SCLout_OBUF),
    .O(SCLout)
  );
  OBUF Home133ctrl_OBUF_3190 (
    .I(Home133ctrl_OBUF),
    .O(Home133ctrl)
  );
endmodule