//--------------------------------------------------------------------------------------------------
//
// Title       : MISCouts
// Design      : U4
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Core\U4\src\MISCouts.v
// Generated   : Wed Dec 24 10:50:17 2003
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {MISCouts}}
module MISCouts ( MReset ,inDATA ,Reset ,LED1 ,LightSense ,GP_Motor0_1 ,LED2 ,DCOROUTw ,Mclk ,GP_Motor1_1 ,LED3 ,LED4 ,MTRpwrn ,LED5 ,MTRpwr );

input MReset ;
wire MReset ;
input [7:0] inDATA ;
wire [7:0] inDATA ;
input Reset ;
wire Reset ;
input LightSense ;
wire LightSense ;
input DCOROUTw ;
wire DCOROUTw ;
input Mclk ;
wire Mclk ;

output GP_Motor1_1 ;
wire GP_Motor1_1 ;
output LED3 ;
wire LED3 ;
output LED4 ;
wire LED4 ;
output MTRpwrn ;
wire MTRpwrn ;
output LED5 ;
wire LED5 ;
output MTRpwr ;
wire MTRpwr ;
output LED1 ;
wire LED1 ;
output GP_Motor0_1 ;
wire GP_Motor0_1 ;
output LED2 ;
wire LED2 ;

//}} End of automatically maintained section

// -- Enter your statements here -- //



reg [7:0] MISCr;

assign LED1 = MISCr[0] | !LightSense;
assign LED2 = MISCr[1] | !LightSense;
assign LED3 = MISCr[2] | !LightSense;
assign LED4 = MISCr[3] | !LightSense;
assign LED5 = MISCr[4] | !LightSense;
assign GP_Motor0_1 = MISCr[6];
assign GP_Motor1_1 = MISCr[7];
assign MTRpwr = MISCr[5];
assign MTRpwrn = !MISCr[5];

always @ (negedge Mclk or posedge MReset)  //added reset to make async and will shut off when Reset high
	begin
		if (MReset) MISCr <= 8'b0;
		else if (Reset) MISCr <= 8'b0;
		else if (DCOROUTw) MISCr <= inDATA;
		else MISCr <= MISCr;
	end
endmodule
